Op - Amp (Compatibility Mode)

Analog Signal Processing Using
Operational Amplifiers (Op-amps)

Chew Chee Meng
Department of Mechanical Engineering
National University of Singapore
2
Introduction
General purpose of amplifier:
To deliver a larger signal to a load than is
available from the signal source
Op Amp
a high gain differential voltage amplifier
Used in 1950s to implement analog computers
Capable of realising many mathematical operations in
electrical domain, e.g. scaling, integration, addition of
voltage signals
Now commonly found in engineering instrumentation
and analog signal processing, e.g. differential
amplification, filters, etc.
3
Introduction
4
Introduction
Objectives:
Understand properties of operational amplifier and
concepts of gain, input impedance, and output
impedance
Understand difference between open-loop and
closed-loop op-amp configurations
Analyse op-amp circuits using ideal op-amp
analysis
Understand physical limitations of an op-amp
Know how to design basic op amp circuits for
analog signal processing
5
Introduction
Op-amp
consisting of transistors, resistors and capacitors fabricated on a
single IC (integrated circuit) chip.
Two inputs and one output
Internal circuit of 741* Op Amp
Output
Non-
inverting
input
Inverting
input
*a general purpose op amp
6
Introduction
Op-amp
Schematic representation
Non-inverting
input
Inverting
input
v
o
+
-
+V
S
(supply)
-V
S
(supply)
output
7
Ideal Op-amp Characteristics
Characteristics Ideal Typical (eg 741)
1. Open-loop gain, A
OL
10
5
2. Input impedances
2MO
3. Output impedance 0 75
O
4. Bandwidth, BW Limited
5. Obeys eqn (2-1) Yes Yes (within limits)
6. Common mode rejection ratio (CMRR) 90dB
Non-inverting
input
Inverting
input
v
o
+
-
+V
S
(supply)
-V
S
(supply)
output
( 2-1) V
o
= A
OL
(V
+
-V
-
)
8
Equivalent Circuit Model for Ideal Op-amp
A
OL
V
id
+
V
-
V
+
V
o
( 2-1)
+
V
id
Remark: Op-amp amplifies the difference between voltages at
noninverting and inverting terminals.
V
id
: differential input voltage (difference between the input voltages)
A
OL
: open-loop gain
I
0
= A
0L
I
d
= A
0L
(I
+
- I
-
)
9
Inverting Amplifier
v
1
v
o
+
R
1
R
f
How to analyse such a circuit?
1
1
f
o
R
v v
R
=
10
Negative Feedback
Open-loop (no feedback) vs closed-loop (with
feedback) gains
Closed-loop: positive vs negative feedback
Negative feedback results in stable behavior
+
negative feedback
11
Ideal Op-Amp Technique
Assumption 1: V
+
= V
-
(Since output is typically finite with
negative feedback and from Eq. (2-1)
which has high open loop gain, A)
Assumption 2: No currents flowing
into op-amps input terminals (Due to
high input impedance)
If negative feedback
is present
V
+
V
-
Non-inverting
input
Inverting
input
v
o
+
-
12
Ideal Op-Amp Technique
General procedure:
1. Check negative feedback is present
2. Apply Assumptions 1 & 2
3. Apply Kirchhoffs current law at non-inverting terminal, V
+
4. Apply Kirchhoffs current law at inverting terminal,V
-
5. Obtain expression for output
Limitations of ideal op-amp technique:
If result calculated is either infinity or 0, more precise op-amp
model may be needed (E.g., using circuit model in Slide 8).
13
Inverting Amplifier
To obtain input/output relationship expression (transfer
function) for inverting amplifier circuit.
v
1
v
o
+
X
R
1
R
f
1
1
0
o
f
v v v v
R R

+ =
Negative Feedback present, can apply
ideal op-amp technique
Apply Assumption 1, v
-
=v
+
=0
Apply KCL at V
-
(node X) =>
(*)
1
1
1
f
o
C
R
v v
R
A v
=
=
Hence
v
-
v
+
Remarks:
All voltages are referenced to the ground voltage.
In (*), we have applied Assumption 2, i.e. the
currents flowing into the input terminals are zero.
A
c
=R
f
/R
1
is the closed-loop gain
Circuit analysis:
14
Inverting Amplifier
Input impedance of inverting amplifier circuit
v
1
v
o
+
X
R
1
R
f
i
1
1 1
1
1 1
v v v
i
R R
= ~
Input impedance:
1
1
1
R
i
v
R
IN
= =
15
Inverting Amplifier
Remark:
- Typically, resistors used are in the range
between 500O and 1MO.
- Lower bound to ensure not putting too much load
on power supply (P = V
2
/R) (see pg 646, Hampbley,
3
rd
ed, & Example 5.1 of Alciatore & Histand)
- Upper bound (typically for feedback resistor) to
avoid problem due to bias current error (will discuss
later)
16
Inverting Summing Amplifier
V
1
R
f
R
1
R
2
V
2
X
-
+
V
o
V
n
V
-
R
n
0 1 2
1 2
0
n
n f
V V V V V V V V
R R R R

+ + + + =
f n
n
R
Vo
R
V
R
V
R
V
= + + +
2
2
1
1
) (
2
2
1
1
n
f f f
o
V
Rn
R
V
R
R
V
R
R
V + + + =
) (
2 1 n
f
o
V V V
R
R
V + + + =
) (
2 1 n o
V V V V + + + =
Applying KCL at node 'X and using Assumption 2:
Negative feedback is present,
can use ideal op-amp technique
From Assumption 1: V
-
=0
or
If R
1
= R
2
= = R
n
= R,
we have the summing amplifier:
If R
f
=R, we have the summer:
17
Non-inverting amplifier
V
1
R
f
R
1
X
-
+
V
o
o
f
V
R R
R
V
+
=
1
1
1
1
1
o
f
R
V V
R R
=
+
1 1
1
R
R
V
V
f
o
+ =
Considering Assumption 2 (i
b
=0)
and by voltage divider equation:
Since V
-
=V
1
,
=>
i
b
=0
Negative feedback is present,
can use ideal op-amp technique
From Assumption 1: V
-
= V
+
= V
1
Remark: Gain is positive => Non-inverting
V
-
R
f
R
1
X
V
o
18
Non-inverting amplifier (cont.)
Input impedance of non-inverting amplifier:
(Since i 0)
i
V
1
R
f
R
1
-
+
V
o
=
i
V
R
IN
1
19
Impedance buffer
i
V
+
R
TH
= 500K
V V
L i
=
+
~
50
50 500 000
0
,
i
R
L
= 50 V
L
+
-
By voltage divider:
How to achieve V
L
= V
i
?
20
Voltage follower/buffer amplifier (a special case of non-inverting
amplifier)
V
1
-
+
V
o
V
V
ie V V
0
1
0 1
1
0
1 = +
=
= .
Remarks:
High input resistance
Low output resistance
Power gain
Useful as a buffer to interface circuits
Here, R
f
= 0 and R
1
=
Hence,
21
Use of a Voltage Follower for impedance buffer problem
Since R
IN
(input impedance of the amplifier) is very large,
For the voltage follower (assume output current is within the limit),
R
TH
= 500K
R
L
= 50
V
o V
1
i ~ 0 and hence,
i ~ 0
V
i
-
+
Voltage
follower
1 L O
V V V = =
1 O
V V =
1 i
V V =
V
L
Hence,
22
Differential Amplifier
Amplification of small transducer signals
V
1
+V
n
V
o
+
X
R
1
R
2
V
1
Transducers output
) (
1
1
2
n o
V V
R
R
V + =
E.g.: Electrocardiogram (ECG) measurement
If inverting amplifier is used:
Leading wire susceptible to electromagnetic
wave interference (results in noise signal
added to original input signal)
23
Circuit analysis:
i
V
2
i
1
2
V
o
V
1
R
2
R
1
R
3
R
4
Ideal Op-Amp:
Assumption 1: V
+
= V
-
Assumption 2: i
1
=i
2
=0
Negative feedback is
present
Circuit to achieve
differential voltage
amplification
24
V
2
V
o
V
1
R
2
R
1
R
3
R
4
V V
R
V V
R
1
1
0
2
0
+

=

V V
R
V
R
2
3 4
0
0
+

=
+ +
) )( (
2 1
2 1
4 3
4 3
3
2
2 1
1
R R
R R
R R
R R
R
V
R
V
R
V
o
+
+
= +
KCL at node X
KCL at node Y
Therefore
25
V
2
V
o
V
1
R
2
R
1
R
3
R
4
) )( (
2 1
2 1
4 3
4 3
3
2
2 1
1
R R
R R
R R
R R
R
V
R
V
R
V
o
+
+
= +
V
R
R
V V
0
2
1
2 1
= ( )
Now set R
1
=R
3
, and R
2
=R
4
, then
Differential amplification
26
Amplification of small transducer signals (cont)
)) ( ) ((
2 1
1
2
n n o
V V V V
R
R
V + + =
) (
2 1
1
2
V V
R
R
V
o
=
i.e.
V
1
+V
n
V
1
V
2
V
2
+V
n
Twisted pair (noise will be
common to both wires)
V
o
R
2
R
1
R
3
R
4
If differential amplifier is used:
27
Integrators
How would you design an integrator circuit to integrate
voltage signals?
V
o
V
i
R
C
Integration
}
b
a
dx x f ) (
28
Integrators
Circuit analysis:
V V
R
C
d V V
dt
i

+

=

( )
0
0

+ =
V
R
C
dV
dt
i 0
0
}
= dt V
RC
V
i o
1
Ideal Op-amp:
I
b
= 0
KCL at node X:
V
o
V
i
R
I
b
C
Negative feedback is present
0 V V
+
= =
29
Integrators
Application Example
Design a circuit for an electronic camera shutter application to
generate a voltage signal proportional to the total amount of light
that has fallen on a detector during the time it is exposed to the light.
When the voltage reaches a desired voltage, the shutter will be
closed.
Thevenin equivalent circuit can be derived for the detector:
Open circuit voltage (Thevenin voltage), V
s
= oL (L is light density in
photons per second and o =10
-15
Vs/photon)
Thevenin resistance, R
s
= 10
6
O.
Design a circuit that produces an output voltage of 1V after 10
11
photons strike the detector.
Integrators
Example (cont)
30
V
o
V
s
-
+
R
1
R
+
-
s
C
}
+
=
t
s
s
o
dt V
C R R
t V
0
1
) (
1
) (
}
=
t
s
o
Ldt
C R
V
0
) (
o
Choose appropriate values for the
resistor and capacitor to satisfy design
specification:
Let choose R
1
=0 so that
t>0
Detectors
equivalent
circuit
A switch to short capacitor so that
output V
o
is zero. Switch is
opened just before start of
integration operation
Integration is required for the
application.
(*)
Integrators
Example (cont)
31
V
o
V
s
-
+
R
1
R
+
-
s
C
11
0
10 =
}
t
Ldt
11
10
) (
1 =
C R
s
o
pF C 100
10
10 10
6
15 11
=
=

We want V
o
= -1V when
Sub into (*),
Therefore,
What other application can you apply this integrator circuit?
Differentiator
Differentiation
32
V
o
V
i
R
C
dt
dv
i
How would you design a differentiator circuit to to obtain
the derivative of a voltage signal at current time t?
(t, v
i
)
Differentiator
Circuit analysis
33
KCL at node X:
+ =
=
V
R
C
dV
dt
V RC
dV
dt
i
i
0
0
0
Negative feedback is present
Ideal Op-amp: i
b
= 0,
V
o
V
i
R
C
0 V V
+
= =
i
b
34
Practical Op Amp circuit design considerations
Bandwidth limitations
Typical Op-Amp's open-loop gain vs frequency plot (frequency
response curve)
frequency (Hz)
Definition: Decibel (dB):
Gain A in dB, A dB =20 log
10
A
Open
loop
0
20
40
60
80
100
120
A
dB
1 10 100 1k 10k 100k 1M 10M 100M
-20dB/decade
35
Bandwidth limitations (cont)
Bandwidth of a system:
The range of frequencies where gain of the system does not
drop by 3 dB (corresponds to 70.7% of DC gain value).
Open
loop
frequency (Hz)
0
20
40
60
80
100
120
1
A
dB
3dB
Bandwidth=100Hz
-3dB => 0.707
10 100 1k 10k 100k 1M 10M 100M
Break
frequency
36
frequency (Hz)
Open loop
0
20
40
60
80
100
120
A
dB
Approximation of frequency response curve
1 10 100 1k 10k 100k1M 10M 100M
37
Gain-bandwidth product (GBP or
GBW) of an op amp = DC gain x
bandwidth
Remarks:
GBP is constant for a particular op-amp
(for both open loop and closed loop)
=> Trade-off between gain and
bandwidth
Closed-loop response
frequency (Hz)
Open loop
Closed-loop
0
20
40
60
80
100
120
A
dB
1 10 100 1k 10k 100k 1M 10M 100M
38
Bandwidth limitations
Example: Determine the GBP for the op-amp whose open-loop gain vs
frequency plot is given below:
A

d
B
Freq (Hz)
0
20
40
60
80
100
120
Solution:
GBP can be obtained by multiplying the frequency
and the gain values at any point on the curve to the
right of the break frequency.
Using 80 dB (A = 10,000) and 1kHz
GBP = 10,000 X 1 kHz
= 10MHz.
Using 0 dB (A = 1) and 10 MHz:
GBP = 1 X 10 MHz
= 10 MHz.
break
frequency
1 10 100 1k 10k 100k 1M 10M 100M
39
Voltage supply limits
Slope = A
v
+
- v
-
v
o
v
o
= A (v
+
- v
-
)
Ideally,
v
o
+
-
V
+
V
-
40
Voltage supply limits
-V
s
+V
s
V
s
/A
-V
s
/A
Slope = A
v
+
- v
-
v
o
Saturation (due
to negative
supply rail)
Saturation (due
to positive supply
rail)
Linear region
Actual V
o
is limited by the
voltage supplies (V
s
)
v
o
+
-
+V
S
(supply)
-V
S
(supply)
V
+
V
-
41
Output Current Limits
Limits to the current that an op amp can
supply to a load (mainly due to heat issue)
For 741 op amp, limits are 40 mA
If current being drawn from output exceeds
these limits, output (voltage) waveform
becomes clipped (deviate from theoretical
value)
v
o
+
-
i
o
43
Input bias current error
Small input bias currents (in the order of 100nA for
op amps with bipolar transistor input stages) are
present at inverting and noninverting terminals
Bias currents cause a small shift to output voltage
(input bias current error) in amplifier circuits (see
following example)
I
b+
I
b-
44
Input bias current error (cont)
Consider the following circuit where both inputs are
grounded and let V
o
be the error in the output voltage due to
the input bias currents:
+
-
R
f
R
i
V
o
I
b
45
0 = +
+

b
f
o
i
I
R
V V
R
V
) 0 (

= V A V
o
A
V
V
o
=
Let i
b
denote the input bias current
Applying KCL at node X,
(1)
=>
Sub (2) into (1),
(2)
( ) ( )
f i f i
o o o
b
f f i f f i
R R R R
V V V
I V
R R R R A R R
+ +
= = +
+
-
R
f
R
i
X
V
o
I
b
By op-amp equation,
46
f
o
b
R
V
I =
V I R
b f 0
=
As A ,
or,
Remark:
Input bias current error, V
o
, is directly proportional to R
f
. Hence, R
f
should not be too large (usually limited to 1 MO or less). Recall, the
resistors used in op amp circuits should be between 500 O to 1 M O
+
-
R
f
R
i
X
V
o
I
b
47
Bias current balancing:
Extra resistor R
b
added to reduce the input bias current error:
V
o
R
2
R
1
R
b
48
V
R
V V
R
I
x x
b
1
0
2
0 +

+ =
V
R
I
y
b
b
+ =
+
0
V
R
V V
R
V
R
x x
y
b 1
0
2
+

=
KCL at node X:
KCLat node Y:
From the above equations,
When V
0
=0,
V A V V
y x 0
= ( )
+
=
b b
I I
Assume:
V V
y x
=
=>
V
R
V
R
V
R
x x x
b 1 2
+ =
Hence the input bias current error can
be eliminated by choosing R
b
as above.
V
o
R
2
I
b-
R
1
R
b
I
b+
R R R
b 1 2
1 1 1
= +
R R R
b 1 2
= / /
Hence, or
Let i
b+
and i
b-
denote the input bias currents flowing into the
noninverting and inverting terminals, respectively
49
Common-mode rejection ratio (CMRR)
cm
d
A
A
CMRR =
Common-mode input voltage
Ideally, output should be zero
Common-mode voltage gain:
Common-mode rejection ratio,
differential-mode gain
common-mode gain
+
-
+
-
V
icm
+
V
ocm
icm
ocm
CM
V
V
A =
Measure ability of differential amplifier
to reject common-mode inputs
50
dB
A
A
CMRR
cm
d
10
log 20 =
CMRR typically expressed
in decibel:
Desirable to have CMRR as
high as possible - Typical values:
80 to 100 dB
51
Example:
A differential amplifier circuit with
R
1
=R
3
=10kO, R
2
=R
4
=270kO. Given
V
1
= 2.00 V and V
2
= 2.05 V,
determine V
0
for:
(a) CMRR = , (b) CMRR = 80 dB,
(c) CMRR = 40 dB.
27 10 / 270
1
2
= = =
R
R
A
d
Gain of differential amplifier,
V
2
V
o
V
1
R
2
R
1
R
3
R
4
52
Example (cont)
V
V
d 0
2 05 2 00 27
135
=
=
( . . )
.
(a) For CMRR = , no amplification of common mode input.
The output voltage is only given by amplification of differential input
voltage,
V
2
V
o
V
1
R
2
R
1
R
3
R
4
53
Example (cont)
A
A
cm
d
CMRR
=
=

10
2 7 10
20
3
( )
.
V
V
icm
=
+
=
( . . )
.
2 00 2 05
2
2 025
V A V
V
mV
cm cm icm 0
3
2 7 10 2 025
5 47
=
=
=

. .
.
V V V
mV
V
d cm 0 0 0
135 5 47
1355
= +
= +
=
. .
.
(b) With finite CMRR, output is composed of differential-mode output
Vod and common-mode output V
ocm
.
Total output of differential amplifier is
dB
A
A
CMRR
cm
d
10
log 20 =
where
Common-mode output,
54
Example (cont)
(c) For CMRR=40 dB, the overall voltage is found to be
V V
0
1897 = .
Remark:
Importance of CMRR in differential amplification application
A special class of differential amplifier used for transducer
conditioning is the instrumentation amplifier. Such
instrumentation amplifier has very high input impedance, low drift
and high CMRR
55
Specification sheets of 741 Op Amp
56
Specification sheets of 741 Op Amp
57
58
Design of Op-amp circuit (for Analog Computing)
To design op-amp circuit given a desired input/output relationship
Example: Obtain the voltage output
from two given voltage inputs V
1
and V
2
, using op-amps.
V V V
0 1 2
2 =
R
2
=2R
1
R
R
1
V
1
V
o
=2V
1
-V
2
R
R
R
4
3
5
6
7
R
where R
2
=2R
1
, and R
5
=R
6
=R
7
R
3
and R
4
are chosen for bias current balancing.
Note: In practice, the resistors used are usually between 500 O to 1 MO.
Solution:
-2V
1
V
2
59
Multiple-stage Op-Amp designs
Amplification requirements of many applications cannot be met
using single stage circuit.
For example:
Desired specifications: closed-loop gain = 200 and bandwidth =
100 kHz
Given Op-amps with GBP=10MHz
A single op-amp will not meet the specifications as 200x100kHz
= 20 MHz > GBP.
If closed-loop gain = 200, bandwidth = GBP/200 = 50kHz
Less than desired bandwidth
60
Need to reduce closed-loop gain to increase bandwidth
And to achieve overall gain requirement by cascading more than 1
op-amp amplifier circuit, e.g.:
Gain
14.14
Gain
14.14
Gain = 200
BW = GBP/gain
= 10 MHz / 14.14
= 707 kHz
BW = GBP/gain
= 10 MHz / 14.14
= 707 kHz
V
i
V
o
V
o
V
i
1/
1/2
2 1
707 2 1 455 100
n
overall s
BW BW
kHz kHz
=
= = >
n is the number of stages
BW
s
is the smallest BWalong the path
61
Procedure in design process:
Step 1: Determine maximum amount of gain per stage (=
GBP/required bandwidth) => number of required stages can be
estimated
Step 2: Determine whether input connections should be made to
inverting or non-inverting terminal of op-amp.
As a rule of thumb, if required input impedance > 1MO, first stage
should be a non-inverting amplifier which has large input impedance
Step 3: Draw a block diagram of circuit (each block represents an
inverting, noninverting, or summing amplifier circuit) so that target
output(s) vs input(s) relationship can be achieved.
Step 4: Check that overall bandwidth is indeed satisfied (for all
paths). If not, add one more stage to the path and go to Step 3.
Step 5: Select values for resistors to achieve the desired gain of
each block and add bias current balancing resistors
62
Example
Design an amplifier circuit that is composed of 741 op-amps in order to
obtain a gain of 800 with an input impedance of at least 1 MO . The
amplifier must respond to a signal with frequency up to 40 kHz. Given GBP
=1 MHz.
Solution:
Step 1: Determine the maximum amount of gain per stage.
Maximum gain per stage = GBP/ desired bandwidth =1 MHz / 40 kHz = 25
To achieve an overall gain of 800, need at least three stages of amplification (25
X 25 = 625 only).
Overall gain should be split among three stages, e.g. 8x10x10
63
Example (cont)
Step 2: To achieve high input impedance (>1MO), first stage must be a
non-inverting amplifier. Next 2 stages can be either inverting or non-
inverting as long as overall output is achieved.
Lets choose non-inverting amplifier circuit for all stages.
Step 3: Draw a block diagram of the circuit (each block represents an
inverting, noninverting, or summing amplifier circuits) so that target
output(s) vs input(s) relationship can be achieved.
8
10 10
v
i 8v
i
80v
i
800v
i
64
Example (cont)
Step 4: Check that the overall bandwidth is indeed satisfied
Since GBP = constant, smallest bandwidth, BW
s
, corresponds to highest gain.
Here, maximum gain = 10, hence,
kHz kHz BW BW
n
s overall
40 51 1 2 100 1 2
3 / 1 / 1
> = = =
Satisfy design requirement!
kHz
MHz
BW
s
100
10
1
= =
65
Example (cont)
Step 5: Select the values for the resistors to achieve the desired gain of each block
and add bias current balancing resistors (all resistors should have values between
500 O to 1 M O)
A possible set of resistor values for non-inverting amplifier with gain = 10 is
(R
1
= 90 kO, R
2
= 10 kO). Corresponding bias current balancing resistor, R
a
= 90
kO// 10kO = 9kO
For amplifier with gain = 8, R
1
= 70 kO, R
2
= 10 kO; bias current balancing resistor,
R
b
= 70kO // 10kO = 8.75kO
Hence, the overall circuit is as follows:
R
a
=9 kO
R
a
=9 kO
90 kO
90 kO
70 kO
10 kO
10 kO
10 kO
R
b
=8.75 kO

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