Introduction The Xilinx Embedded Development Kit (EDK) tool is used to generate and implement the Microblaze soft-core

processor system on Xilinx boards. The tool (version 13.1) is downloadable from the Xilinx Website at http://www.xilinx.com/support/download/index.htm . You can generate a 30 day evaluation license for this tool from the website. Alternatively, you can use the license server available at 2100@cnl-ece.nus.edu.sg from within NUS Network.

Setting up Xilinx floating license (screencast)

For a step-by-step video on how to setup your Xilinx floating license, especially when you are connected to the Internet off-campus, navigate to this hyperlink.
Requirements Working installation of Xilinx ISE Design Suite 13.1 Internet connectivity (with VPN connection if off-campus) for floating license Spartan-3E lab kit Thumbdrive Objectives In this lab you will learn:

 How to create a single core processor system with a single Microblaze processor core and the associated peripherals like UART, DDR memory and TFT controller. You will run some simple program and build two simple Helloworld programs on the Microblaze processor and verify that the system is working. You will also learn how to draw and write onto the TFT controller to display text and graphics on the monitor. You are strongly encouraged to generate the hardware bitstreams for Lab 1A and 1C before arriving at the lab as they require processing time. Bitstream generation does not require the setup of the FPGA board. Make full use of the lab period to develop and troubleshoot software. LAB 1A BASE SYSTEM BUILDER (Hardware Platform by Xilinx Platform Studio) Procedure Launch the Xilinx EDK by navigating to Xilinx ISE Design Suite 13.1 -> EDK -> Xilinx Platform Studio. After the software is launched, you will see the following screen. Make sure the Base System Builder is selected. Click OK.

Browse to an appropriate location where you would like to save your project file and give a name to your project. The project will be saved as an .xmp file. Next time, when you want to open your project, you can select "Open Recent Project" and point to your project file (.xmp file).

When you click OK, the Base System Builder will appear as shown below. Select the PLB (Processor Local Bus) system which is the legacy bus standard used for all current FPGA families.

Since we are creating a new design, there we will select the first option and click NEXT to continue (shown below).

Then, you will now see the following screen asking for the board details. The board we are using is Xilinx Spartan 3E Starter kit (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=S3EBOARD) manufactured by Digilent Inc. It contains Xilinx Spartan XC3S1600E FPGA. To understand more, you can download the details from the above website. It is important to understand more about the features of the FPGA and the board in terms of the available DDR memory, number of Logic Gates, Block RAM modules etc because this information is critical while creating a hardware design on the board.

Select the board Spartan 3E 1600E Microblaze Dev Board (which corresponds to the board we are using) and Board Revision as RevA. Click NEXT to continue.

You will be provided with an option to create a single processor system or dual processor system as shown. For this lab, we are developing a single Microblaze core based processor system. You can see this option selected by default. Click NEXT to continue.

 In the next screen as shown, you will configure the processor memory and speed. You can select the speed of 50 MHZ as system clock frequency and 32 KB memory as the local memory. Click NEXT to continue.

In this screen, you are given the option to add or remove external peripherals to/from the system. For this lab, you require only the peripherals as shown below. Make sure that the

interrupt of xps_timer_0 is enabled when you add the timer peripheral (xps_timer) to your system. Click NEXT to continue.

If want to speed up access to a particular memory device (perhaps DDR_SDRAM), then we can associate the cache to that memory. Since we do not require caches in this system, we will not enable caches in this system. Click NEXT to continue.

Finally, we are at the summary screen. We can see the names of various peripherals and the memory addresses to which each peripheral is mapped. Click FINISH to generate your system.

 Once the system is generated, you will see the above screen. Your hardware design is complete and now ready to use.

To generate the hardware, we can select the Generate Bitstream from the menu bar or the toolbar. This will take some time to complete. Congratulations. You have successfully completed your first hardware design on FPGA. LAB 1B SOFTWARE DEVELOPMENT (By Xilinx Software Development Kit) In this lab, we will try to create, compile, download and run software on the Microblaze processor. Now to develop the software platform by Xilinx Software Development Kit once we finish developing the hardware base system, first of all we need to export our hardware platform from

Xilinx Platform Studio to Xilinx Software Development Kit: Go the Project of menu bar, then select Export Hardware Design to SDK.

Then select Export & Launch SDK as shown below:

After the Workspace is launched, you will see the following screen. Choose the workspace folder to be same as where your hardware system is located for simplicity.

Once the SDK is launched, you can see the following screen.

To create a new board support package for software application development in SDK, do the following: 1. Click File > New > Xilinx Board Support Package. 2. In the Project name field, type a name for the board support package if you wish to override the default value, such as standalone_bsp_0. 3. Select the location for the board support project files. 4. From the Board Support Package OS drop-down list, select the type of board support package to create. A description of the platform types displays in the box below the dropdown list. 5. Click Finish. The wizard creates a new software platform and displays it in the SDK Navigator pane.

In the Overview page, you can configure basic settings for the OS Version and the Supported Libraries to be enabled in the platform.

You can see the option to configure the STDIN and STDOUT for the base system. Choose RS232 DCE for both STDIN and STDOUT, since we will use the UART terminal to communicate with the board.

Find and change the value of xmdstub_peripheral to "mdm_0".

Now we will compile the test applications and run it on the board to test its functionality. To create a software project: 1. Click File > New > Xilinx C Project. The New Xilinx C Project dialog box appears.

2. SDK provides useful sample applications listed in Select Project Template that you can use to create your project. The Description box displays a brief description of the selected sample application. When you use a sample application for your project, SDK creates the required source and header files and linker script. In this case, select the Memory Tests and click next. (To create a blank project later on you need to select the Empty Application. You can then add C files to the project.) 3. In the next page, New Xilinx C Project, you can choose to Create a new Board Support package or Target an existing Board Support Package for which you want to create the application from the list of available platforms. We will choose the second option here as shown below. Click Finish to create your application project.

To build an application, right click on it and select "Build Project". This will create an *.ELF file (executable and linkable format). This file can be run on the Microblaze just like *.EXE files on our PC. So build the memory_test_0 application project like below:

IMPORTANT!!! Before we download the bitstream to the FPGA (or program the FPGA), firstly, we need to connect out PC to the FPGA board using the programming cable. In this case, the programming cable is the USB cable given with the kit. Secondly, we need to connect the serial port of our PC to the RS232_DCE of the FPGA board so as to observe the results from the FPGA board. You are provided with a USB to Serial Port converter if your PC is NOT equipped with a serial port. If your laptop is unable to detect or install the RS232-to-USB cable drivers, use the RS232-to-RS232 cable (provided in your lab kit) to connect the FPGA board to a COM port residing on a desktop workstation. Most desktops would have a native COM port located at the back of the CPU tower.

Now download your program by selecting Program FPGA and then click Program as shown below:

Once the download completed, go the Run option from the menu bar and select Run Configurations. Now select the memory_tests_0 project and corresponding .elf file.

Now before run the program, to see the output on the console (as shown below), from the STDIO Connection tab of above window, select the option Connect STDIO to Console.

Set the drop down Port setting to the correct COM port ID. If there are multiple COM ports on your system, and if are unsure about how to check which COM port the FPGA board is communicating to your computer, check out the screencast at the following hyperlink. Finally ensure that BAUD Rate is set to the default communications speed of 9600. Click Run to enjoy the output as shown below:

Congratulations. You have successfully downloaded the bitstream and run the first program on the Microblaze Processor.

Similarly you can build, download and run another sample application peripheral_tests_0 to test the peripheral devices you selected while building the hardware base system in Lab 1A. To do that, Click File > New > Xilinx C Project. The New Xilinx C Project dialog box appears. Select Peripheral Tests and click Next to continue.

Then select the existing board support package to finish.

Now build the project peripheral_tests_0, then download to FPGA and at last run the program in a exactly similar way before (i.e. for memory_tests_0). Dont forget the select the option Connect

STDIO to Console before you run your program. If you follow these steps properly, then you are supposed to see the output on the Console as shown below:

You can similarly run another sample test program hello_world_0 which will output like below:

LAB 1C ADDING AND USING PERIPHERAL "TFT CONTROLLER" In this lab, we will try to add a new component to our previous design: A TFT controller IP that will help you to connect your FPGA board to the LCD monitor and enable you to do perform graphics functions on the monitor. Procedure Launch the Xilinx Platform Studio and then select "Open an Existing Project". Now browse to the folder where you have saved your earlier project and select the XMP file and click OPEN. You will see the various components of the design which you had added in the previous exercise.

Now we will add the TFT controller to the design. To the left side of your screen, you will see a tab called IP catalog. The IP catalog is a repository of all the various peripherals that can be added to our design. Each IP is basically a collection of files that describes the hardware function of the peripheral as described in its RTL code, the various pin connections, the driver libraries etc. From the IP catalog, go to the "IO Modules" subsection and expand it as shown in the picture above. You will see that it contains a peripheral called XPS TFT as shown below. Right click on this and select Add IP. Alternatively, you can drag and drop it onto the main window. You can see that this IP has been added to your design. Note the instance name of this IP ("xps_tft_0"). The peripheral will always be referred by this instance name throughout the design. However, the process is still not complete. We need to make the various connections between the pins of the IP to our main design manually. We will now connect the TFT controller to the Microblaze processor using the Processor Local Bus (PLB) interface as shown above. Under the tab Bus Interfaces, expand the controller IP and the select the mp_plb bus for both MPLB and SPLB.

The display controller requires a 25 MHz clock input. We will use the clock generator core to generate a 25 MHz clock. Go to Hardware->Launch Clock Wizard option to configure the clock sources to the design. You will now see the following window. Under the System Tab, configure the SYS_TFT_Clk to be 25 MHz. Now if you click on the Ports Overview tab, you will see that a 25 MHz clock is present in one of the clock generator outputs. The tool has automatically created the connection between the 25MHz clock source and the display controller clock pin as we will see next. Click OK to complete this step.

Now, click on the PORTS tab in the main window and expand the XPS_TFT_0 instance. You will see the various output ports of the controller. You can see that a 25 MHz clock signal is connected to the SYS_TFT_Clk port.

Now we will configure the VGA port signals of the TFT controller so as to interface the VGA port of the LCD monitor with the board. For this purpose, right click on the XPS_TFT_0 instance and select Configure IP. Now Unselect the Select TFT interface and click OK. We can now see that the various ports of the controller instance have changed the names. We need five signals from these ports to be routed to the VGA connector on the board to the LCD monitor. These signals are: TFT_VSYNC, TFT_HSYNC, TFT_VGA_R, TFT_VGA_G, and TFT_VGA_B. For each of these signals, configure the ports as "Make External". This will make the ports connect to the physical pins of the FPGA. However, the mapping of each port to a specific FPGA pin is still not decided yet.

Now if you move upwards and expand the External ports menu, you will see the above signals added to it. We will now map these ports to the VGA port on the board. For this purpose, we need to edit the UCF file of the system. The UCF file of the system contains the information that indicates which pins of the FPGA are routed to which ports of the design. For this, Go to the Project Tab on the left side of your screen and find a file <your_project_name>.ucf under the menu of Project Files. Double click on it to see the contents of this file. You can now copy the contents of the file "UCF-tft.txt" in the Lab1 folder and append to the end of the UCF file as shown in figure on the next page. Save the contents of the UCF file after copying.

 We will now configure the address of the new IP in the design. We need to define the memory mapping of the IP for the processor as well as specify the video memory location for the IP. Go to the Addresses tab in the System Assembly View. You can see an unmapped instance of the TFT controller. (OPTIONAL: Specify the size of the memory to be 8K.) Now click "Generate address" on the top right corner of your screen. The tool will now generate non conflicting addresses for each of the peripheral components you have added.

Since, the addresses have been generated now; we will specify the video memory to the TFT Controller. We will use the on board DDR memory for this purpose. Note the Base Address and Size of the DDR_SDRAM from the Addresses tab for this. The actual values on your project may vary from those shown in the screenshot below.

Now open the controller instance for configuration and for the field "Base address of PLB attached Video Memory", fill in the following hexadecimal value computed using the following formula: <DDR_SDRAM Base Address> + <DDR_SDRAM Size>.

To give an example, if <DDR_SDRAM Base Address> is 0x1234000 and <DDR_SDRAM Size> is 4 megabytes, the corresponding Base address of PLB attached Video Memory to be filled in is given by 0x12740000.

Since the program memory is shared with the video buffer on the DDR_SDRAM, the formula implies that the former resides in the first half of the SDRAM, whereas the video buffer resides in the second half. This is to ensure that both does not overwrite and corrupt the other. Now click generate bitstream from hardware menu which will take some time to complete and thus once done, the process for adding the TFT controller to your design is now complete. This time you need to export your hardware platform to SDK similarly as described at the initial points of Lab 1B by selecting Export Hardware Design to SDK and following the next steps as described earlier. We now will develop an application to test the display controller that we have in our system by creating a scrolling box on the monitor. Create a new Software application Project (Go to File > New > Xilinx C Project and then select Empty Application listed in Select Project Template to create a blank C project) as described earlier. Use the "display.c" program in the Lab1 folder as the source code and compile the project (Go to src folder of your new application project and by right clicking it add a new file and name it as display.c. Then copy & paste the code contents of display.c file from Lab1 folder and save it). Then build your project, program FPGA and Run before configuring it and dont forget to select the option Connect STDIO to Console from the STDIO Connection tab. See the output on your TFT monitor connected to the board. **(Note that you need to connect your monitor with FPGA board by the cable provided in the Spartan Kit before you build your project and also you need to select the input source of your TFT monitor as VGA)

IMPORTANT!!! Explore the APIs used in the Test and the TFT Controller applications. To find out more about the API offered by the drivers of a peripheral, we can click on the peripheral and select the View API under the driver submenu.

Probe the logic of XTft_DrawSolidBox(). How does a one dimensional video buffer mapped to a two dimensional video output? Any way to speed up the drawing of XTft_DrawSolidBox()? LAB 1D

XILKERNEL Xilkernel is a small, robust, and modular kernel. It is highly integrated with the Platform studio framework and is a free software library that you receive with the Xilinx EDK. You can read about Xilkernel in the OS and Libraries Document Collection PDF which can be obtained by going to Help -> EDK online Documentation.

Procedure We will now work on how to configure the Xilkernel OS in our system for Microblaze0. Click File > New > Xilinx Board Support Package. Then select Xilkernel from the tab Board Support Package OS and click finish.

We now will configure the Xilkernel OS for our system. Select "xilkernel" under Overview and then change the following parameters under the xilkernel subsection: systimer_spec: systmr_dev : xps_timer0 systmr_freq : 50000000 systmr_interval : 100 config_time : true stdin : RS232 DCE stdout : RS232 DCE sysintc_spec : xps_intc_0

Identify what did we change here and figure out why these settings for the above parameters. Make sure you select the correct timer device, interrupt controller and stdin/out terminals. Question: Can we set the stdin/out for Microblaze0 to be RS232_DTE? Why?

Now the OS configuration is partly complete. These settings would be required by default for our base system. We still have to configure the thread management and scheduling parameters of the OS as well. We will do that as per the Lab Exercise requirements. THREADS We will now try to execute some threads in one of the two Microblaze processors that we have to study about the various thread management features of Xilkernel. Round Robin Scheduling We will now run a program on a single Microblaze core that executes threads based on Round Robin scheduling. The program for Round Robin scheduling is "Players_RR.c" in the Lab1 folder. We will configure the Xilkernel to enable round robin scheduling.

 Create an Application called RoundRobin. Add the Players_RR.c program given in the folder Lab1 to the source code of the application. Next we will configure the scheduling policy and the thread management of the OS. Go to "Board Support Package Settings" and under the "Overview" tab for xilkernel, set the following configuration: config_pthread_support : true(default) config_sched : true (default) sched_type : SCHED_RR

In the program Players_RR.c, in the function main, you will see a call to the xilkernel called xilkernel_main(). When the CPU starts executing this kernel, the function "main_prog()" in the source code has to start execution. We need to configure a thread that starts this function in xilkernel. To do this, under the subsection config_pthread_support, select static_pthread_table and then do a single click on its Current Value space. A window opens up where you will add the thread calling function to be main_prog as shown below. Setting the priority to be 0 ensures that this thread gets the highest priority among all threads.

The OS configuration part is now complete. Now you can build the project and then Program the FPGA and run to see the output in the console as shown below. You can try to understand how the various threads created are getting executed in a Round Robin Manner.

HOMEWORK Develop a program using Xilkernel. This program will have two threads.

Thread 1: The first thread will generate a pair of random integer coordinates (x,y), where 0x639 and 0y479. The pair of coordinates will be sent over RS232_DTE at a rate of 1 update per second, and likewise will print the coordinates in text to the upper-left corner of the VGA display. Thread 2: The second thread will read in the coordinate pair from RS232_DCE and display a blue

colour filled circle, of radius 7 pixels, with its centre located at coordinate (x,y), against a white background on the VGA display.