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MC LC

A.C s l thuyt
I.Tng quan v cu trc v chc nng ca h MSP430 II.B bin i ADC10 III.Giao tip UART cho MSP430 IV.Tm hiu IC LM35 V.Tm hiu LCD 16x2

B.Thit k
I.S nguyn l II.Chc nng tng khi III.Nguyn l hot ng IV.Cc linh kin s dng trong mch V.S mch in VI.Kt qu

C.Kt Lun

A.C s l thuyt
I.Tng quan v cu trc v chc nng ca h MSP430 1.1.Cu trc ca MSP430 MSP430 cha 16 bt RISC CPU, cc ngoi vi v h thng b nh thi linh hot c kt ni vi nhau theo cu trc VON-NEUMANN, c cc Bus lin kt nh: Bus a ch b nh (MAB), Bus d liu b nh (MDB). y l mt b x l hin i vi cc m un b nh tng t nh nhng kt ni ngoi vi tn hiu s, MSP430 a ra c nhng gii php tt cho nhng nhu cu ng dng vi tn hiu hn tp. MSP430 c mt s phin bn nh MSP430x1xx, MSP430x2xx, MSP430x3xx,MSP430x4xx, MSP430x5xx. Di y l nhng c im tng qut ca h vi iu khin MSP430: Cu trc s dng ngun thp gip ko di tui th ca Pin - Duy tr 0.1uA dng nui RAM - Ch 0.8uA real-time clock. - 250uA/MIPS. B tng t hiu sut cao cho cc php o chnh xc: - 12 bit hoc 10 bit ADC-200ksbp, cm bin nhit - 12 bit ADC - B gim st in p ngun 16 bit RISC CPU cho php c nhiu ng dng, th hin mt phn kch thc Code lp trnh. - Thanh ghi ln nn loi tr trng hp tt nghn tp tin khi ang lm vic. - Thit k nh gn lm gim lng in tiu th v gim gi thnh. - Ti u ha cho nhng chng trnh ngn ng bc cao nh C, C++. - C 7 ch nh a ch - Kh nng ngt theo vc t ln Trong lp trnh c cc b nh Flash cho php thay i Code mt cch linh hot,phm vi rng, b nh Flash cn c th lu li nh nht k ca d liu.

1.2.H thng nh thi (Clock) linh hot H thng clock c thit k mt cch c bit cho nhng ng dng s dng ngun cung cp Pin. Mt b to xung nhp ph tn s thp (ACLK) c cung cp trc tip t mt b dao ng thch anh 32KHz. ACLK c s dng nh mt Real-time Clock nn kch hot cc tnh nng. Mt b dao ng k thut s tc cao (DCO) c th lm ngun xung ng h chnh (MCLK) s dng cho CPU v nhng kt ni ngoi vi tc cao. Bi thit k ny DCO c th hot ng n nh 1MHz trong thi gian t h 2uS. MSP430 c thit k da trn nhng gii php c hiu qu s dng mt RISC CPU 16 bt hiu sut cao. - B nh thi ph tn s thp: Hot ng ch sn sang s dng ngun cc thp. - B nh thi chnh (Master Clock) tc cao: Hot ng x l tn hiu hiu sut cao.

1.3.Cc vng a ch: MSP430 c thit k theo cu trc Von-Neumann c vng a ch c chia thnh nhiu vng nh l thanh ghi hm c bit (SFRs) nhng ngoi vi, RAM. B nh Flash/ROM.

1.3.1.Flash/ROM

a ch bt u ca Flash/ROM ph thuc vo ln ca Flash/ROM v cn ty thuc vo tng h vi iu khin. a ch kt thc ca Flash/ROM l 0x1FFFFh. Flash/ROM c th s dng cho c m chng trnh v d liu. Nhng bng Byte hoc Word c th c tn tr v s dng ngay trong Flash/ROM m khng cn copy vo RAM trc khi s dng chng. Nhng bng vecto c nh x n 16 Word pha trn ca vng a ch Flash/ROM vi nhng u tin ngt cao nht vng a ch cao nht ca Flash/ROM.
1.3.2.RAM

RAM bt u a ch 0200h v gii hn cui cng ty thuc vo kch thc ca RAM. RAM c th s dng cho c m chng trnh v d liu.

1.3.3.Cc module ngoi vi

Trong vng khng gian a ch ca MSP430 c 2 vng a ch dnh cho nhng m un ngoi vi. Vng a ch t 0100 n 01FFh s dng dnh ring cho nhng m un ngoi vi 16 bt. Vng a ch t 010 n 0FFh s dng dnh ring cho nhng m un ngoi vi 8 bt.
1.3.4.Thanh ghi hm c bit

SFRs lin quan nhiu n s cho php nhng tnh nng ca mt s m un ngoi vi v dng truyn nhng tn hiu ngt t ngoi vi. SFRs nm 16 Byte thp ca vng a ch v c t chc bng Byte. SFRs ch c th c truy nhp bi ch th Byte.
1.3.5.T chc b nh

Byte th dng nh v tr ca a ch l hoc chn, cn Word th ch s dng cho a ch chn. V vy khi s dng nhng ch lnh t th ch c a ch chn c s dng Byte thp ca mt Word lun l s chn, Byte cao th mt s l k tip.

II.B Bin i ADC10: 1.Gii thiu v ADC10: ADC10 l mt b bin i A-D 10Bit c hiu sut cao. M un ADC10 lp t 10 bit SAR core, b iu khin la chn mu, b sinh mu, b iu khin chuyn i d liu (DTC). DTC cung cp ADC10 nhng mu c chuyn i v lu tr bt k ni u trong b nh m khng c bt k s can thip no ca CPU. M un ADC10 c th c thit lp bi ngi s dng cho nhng ng dng a dng. ADC10 bao gm: T l chuyn i ln nht hn 200ksps. Ly mu v gi chu k ly mu c th lp trnh c. S chuyn i c khi to bi chng trnh hoc Time A. Chng trnh la chn s tham chiu bn trong hoc bn ngoi. C 8 knh nhp tn hiu t bn ngoi (12 i vi MSP430x22xx). C knh chuyn i cho cm bin nhit bn ngoi, Vcc, tham chiu bn ngoi. La chn ngun xung clock chuyn i. Nhn ADC v in p chun c cp xung mt cch ring r. B chuyn i d liu lu tr kt qu chuyn i mt cch t ng. 2.Hot ng ca ADC10
2.1.Nhn ADC10bit

Nhn ADC10 chuyn i mt tn hiu vo tng t sang s 10 bit v lu kt qu chuyn i trong thanh ghi ADC10MEM. Nhn ADC10 s dng chng trnh la chn mc in th ( v ) xc nh gii hn trn v gii hn di ca s chuyn i. Ng ra s ( ) c kch thc y (03FFh) khi tn hiu vo bng hoc nh hn v bng 0 khi tn hiu vo bng hoc nh hn . Knh tn hiu vo v mc in o chun ( v ) th c xc nh bi b nh iu khin chuyn i. Kt qu chuyn i ADC s dng nh dng nh phn l:

Nhn ADC10 c thit lp bi 2 thanh ghi iu khin l ADC10CTL0 v ADC10CTL1. Nhn ADC10 c cho php bi bit ADC10ON. C mt vi ngoi l l bit iu khin ADC10 c th b bin i khi ENC=0. ENC phi c set ln 1 trc khi c bt k s chuyn i bo c th xy ra. S chn lc xung clock chuyn i: ADC10CLK c s dng nh l xung clock chuyn i v b sinh chu k ly mu. Ngun xung clock ca ADC10 c chn bi vic s dng bit ADC10SSELx v c th c chia t 1-8 s dng bit ADC10DIVx. C th ngun ca ADC10CLK l SMCLK, MCLK, ACLK v mt b dao ng bn trong l ADC10OSC. Ngi s dng phi m bo rng ngun xung clock c chn cho ADC10CLK phi hot ng cho n khi s chuyn i kt thc. Khi ngun cp xung bt cht b mt khi ang trong qu trnh chuyn i th s chuyn i s khng hon thnh v kt qu th s b li.
2.2.Tn hiu vo ADC10 v b ghp knh

C 8 tn hiu bn trong v 4 tn hiu bn ngoi tng t c chn nh l mt knh ca s chuyn i bi b ghp knh tn hiu vo tng t. B ghp knh tn hiu vo l mt kiu ngt ri n lm gim tn hiu nhiu t nhng knh chuyn. B ghp knh tn hiu cng l mt T-switch lm gim ti thiu ha cc ghp ni gia cc knh. Nhng knh khng c chn th b c lp t A/D v im ni trung gian th c ni mass phn tn in dung nhm trnh s giao tip cho. ADC10 s dng ghp phn b in tch. Khi tn hiu vo c chuyn mch bn trong, s chuyn tip ny c th l nguyn nhn ca s qu trn tn hiu vo.

S la chn cng tng t:

Nhng tn hiu vo bn ngoi ca ADC10 l Ax, v th dng chung y ni vi cc Port I/O mc ch tng qut, l nhng cng CMOS k thut s. Khi nhng tn hiu tng t c t vo cc cng CMOS, dng nhiu i t Vcc n GND. Dng nhiu ny xut hin nu in th vo c gi tr gn mc chuyn tip ca cng. Bit ADC10AEx cung cp mt kh nng kha cc b m u vo v b m u ra.
2.3.B sinh in p qui chiu

ADC10 tch hp in p qui chiu bn trong vi 2 s la chn mc in p. Thit lp REFON=1 th cho php qui chiu bn trong. Khi REF2_5=1 th qui chiu bn trong l 2.5V. Khi REF2_5=0 th qui chiu bn trong l 1.5V. in p qui chiu bn ngoi c th cung cp cho v tng ng cc chn A4 v A3. Khi s dng in p bn ngoi hoc s dng Vcc qui chiu th nhng qui chiu bn trong c th c tt i bo v ngun.
2.4.Qu trnh bin i v ly mu:

Bin i A-D c bt u khi c xung cnh ln ca tn hiu vo SHI. SHI c la chn bi bit SHSx t cc ngun: ADC10SC Timer_A 1 Timer_A 0 Timer_A 2

Bit ISSH dng o chiu tn hiu SHI. Bit SHTx dng la chn chu k ly mu l 4, 8, 16 hoc 64 ADC10CLK. nh thi ly mu thit lp SAMPCON mc cao cho vic chn chu k ly mu sau khi ng b vi ADC10CLK. l thi gian ly mu. Khi SAMPCON t mc cao xung thp th qu trnh bin i A-D bt u. Khi SAMPCON =0 th tt c cc ng vo Ax c tng tr cao. Khi SAMPCON =1 th ng vo Ax ging nh mt b lc thng thp RC trong sut thi gian ly mu.

: in p vo chn Ax in p ngun bn ngoi. in tr ngoi. in dung ng vo. in p t in. in tr trong. nh hng n thi gian ly mu > (Rs+Ri).ln( ). :

Trong thc t th thi gian ly mu ln hn thi gian ly mu tnh ton v thi gian b m n nh .

Vi SR: tc qut b m (1us/V khi ADC10SR=0 v 2us/V khi ADC10SR=1) in p tham chiu ngoi.
2.5.B iu khin chuyn giao d liu ADC10

ADC10 c b iu khin chuyn giao d liu (DTC), n s t ng chuyn kt qu ca bin i A-D t thanh ghi ADC10MEM sang b nh ca chip. DTC c cho php khi thit lp thanh ghi ADC10DTC1 c gi tr khc 0. Khi DTC c cho php, mi khi ADC10 hon thnh vic bin i v lu kt qu vo thanh ghi ADC10MEM th vic chuyn giao d liu c kch hot. Mi DTC yu cu mt CPU MCLK. Trnh vic s dng cc Bus trong sut qu trnh chuyn giao d liu, CPU c tm ngng. S chuyn giao khng c kch hot trong khi ADC10 th bn.
2.5.1.Ch chuyn giao mt khi:

c kch hot khi bit ADC10TB Reset. Gi tr n trong ADC10TC1 xc nh s lng chuyn giao cho mt khi. a ch bt u ca khi l thanh ghi 16 bit ADC10SA. a ch kt thc l ADC10SA+2n-2.

a ch con tr bn trong c khi to bng ADC10SA v b m chuyn giao c khi to bng n. DTC chuyn giao gi tr t ADC10MEM sang a ch con tr ADC10SA. Sau mi ln chuyn giao th a ch con tr tng 2 v b m gim 1. DTC tip tc chuyn giao t ADC10MEM cho n khi b m gim

xung bng 0. Khi s dng DTC trong ch chuyn giao mt khi th c ADC10IFG c set sau mi khi c chuyn giao hon thnh.
2.5.2.Ch chuyn giao 2 khi

c chn khi bit ADC10TB c set. Gi tr n trong ADC10TC1 xc nh s chuyn giao trong mt khi. a ch u tin trong thanh ghi ADC10SA. a ch kt thc ca khi u tin l ADC10SA+2n-2. Dy a ch ca khi th 2 c xc nh t SA+2n n SA+4n-2. a ch con tr bn trong c khi to bng ADC10SA v b m chuyn giao c khi to bng n. DTC chuyn giao gi tr t ADC10MEM sang a ch con tr ADC10SA. Sau mi ln chuyn giao th a ch con tr tng 2 v b m gim 1. DTC tip tc chuyn giao t ADC10MEM cho n khi b m gim xung bng 0. thi im ny, khi th nht y, c ADC10IFG v bit ADC10B1 th c set. DTC tip tc vi khi 2. B m chuyn giao bn trong t ng np li gi tr n. DTC bt u chuyn kt qu bin i t ADC10MEM sang khi 2. Sau n ln chuyn giao hon thnh th khi 2 y. C ADC10IFG set, bit ADC10B1 c clear.

3.Cc thanh ghi ADC10 Cc thanh ghi ca ADC10 c trnh by bng sau:

3.1.ADC10CTL0, ADC10 control register 0

SREFx: la chn tham chiu

ADC10SHTx: thi gian gi v ly mu

ADC10SR: tc ly mu. Thit lp ADC10SR lm gim dng tiu th ca b m qui chiu. 0 b m qui chiu h tr trn 200ksps 1 b m qui chiu h tr trn 50ksps REFOUT: ng ra qui chiu 0 ng ra qui chiu tt 1 ng ra qui chiu m REFBURST: truyn tng khi qui chiu 0 b m qui chiu lin tc 1 b m qui chiu ch trong qu trnh ly mu v bin i. MSC: t hp ly mu v bin i 0 qu trnh ly mu yu cu mt xung cnh ln ca SHI kch hot mi ln ly mu v bin i. 1 Xung cnh ln u tin ca SHI s kch hot b nh thi ly mu. Nhng ngoi ra, ly mu v bin i c s dng nh mt cch t ng n khi chu k bin i c hon thnh. REF2_5V: b sinh in p qui chiu. REFON phi c set. 0 1.5V 1 2.5V REFON: iu khin tham chiu 0 tt tham chiu 1 m tham chiu ADC10ON: iu khin ADC10 0 Tt ADC10 1 Bt ADC10 ADC10IFG c ngt ADC10 0 khng ngt 1 ngt

ENC cho php bin i A-D 0 ADC10 khng c cho php 1 ADC10 c cho php ADC10SC bt u bin i A-D 0 Ly mu v bin i cha bt u 1 Bt u ly mu v bin i.
3.2.ADC10CTL1, ADC10 control register 1

INCHx La chn knh ng vo:

SHSx: La chn ngun thi gian gi v ly mu:

ADC10DF nh dng d liu ADC10 0 nh phn tiu chun 1 2 s b nhau ISH o tn hiu gi v ly mu 0 khng o tn hiu vo ly mu 1 o tn hiu vo ly mu ADC10DIVx b chia

ADC10SSELx la chn ngun xung clock ADC10 00 ADC10OSC 01 ACLK 10 MCLK 11 SMCLK CONSEQx la chn ch bin i A-D 00 Single channel single 01 Sequence-of-channels 10 Repeat single channel 11 Repeat sequence-of-channels ADC10BUSY ADC 10 bn 0 khng hot ng 1 tham chiu, ly mu, hoc bin i th hot ng.

3.3.ADC10MEM:

Thanh ghi lu tr kt qu ca bin i A-D v c nh dng nh phn. Bit 10 n 15 lun l 0.


3.4.ADC10DTC0:

ADC10TB la chn ch chuyn giao khi 0 chuyn giao 1 khi 1 chuyn giao 2 khi ADC10CT 0 Dng chuyn giao d liu khi mt khi hoc 2 khi c hon thnh. 1 D liu c chuyn lin tc, DTC ch c dng nu ADC10CT c clear hoc ADC10SA c ghi. ADC10B1 Bit ny xc nh khi c lm y bi kt qu ca bin i A-D ca 2 ch chuyn giao khi. ADC10B1 ch hp l khi c ADC10IFG c set ln u trong sut hot ng DTC. ADC10TB cung phi c set. 0 Khi 2 y 1 Khi 1 y ADC10FETCH bnh thng bit ny c reset.

3.5.ADC10DTC

Bit ny xc nh s chuyn giao trong mi khi. khi bit ny bng 0 th DTC khng c cho php.
3.6.ADC10SA

y l thanh ghi a ch bt u ca ADC10. Bit ny bt u a ch cho DTC. Bit 0 th khng c s dng v lun c gi tr l 0.

III.Giao tip UART cho MSP430 1.Giao tip UART UART vit tt ca Universal Asynchronous Receiver/Transmitter, ngha l b truyn nhn d liu ni tip bt ng b. UART cn phi kt hp vi mt thit b chuyn i mc in p to ra mt chun giao tip no . V d chun RS232 (Com) trn cc my tnh c nhn kaf s kt hp ca chip UART v chip chuyn i mc in p (MAX232)
1.1.Truyn thng ni tip bt ng b

Truyn thng ni tip bt ng b l phng thc truyn d liu ph bin hin nay. Tuy nhin vic truyn d liu ni tip d b mt hoc sai lch d liu, v vy d liu phi c x l trc khi c truyn i. Vic ng gi d liu thnh cc khung truyn m bo vic truyn nhn c m bo sai st n mc ti thiu. Mt khung truyn c m t nh sau:

trng thi ch th ng truyn c thng trc mc cao. Start bit (=0) l bt u tin trong khung truyn c chc nng bo cho thit b nhn chun b c d liu chuyn n. Data l d liu c gi i ngay sau Start bit. Ta c th quy nh s lng bit ca data. Parity bit l bt c them vo kim tra d liu sau khi truyn. Stop bit thng l 1 bit hoc 2 bit, dng bo kt thc mt khung truyn.
1.2.Tc Baud

c nh ngha l s bit truyn trong 1 giy. Tc Baud rt quan trng, hai bn thit b truyn nhn cn phi ging nhau v tc Baud th vic truyn nhn mi chnh xc. Vic tnh ton tc Baud s ni r hn. 2.Mode UART trong MSP430 H MSP430 thng cha mt hoc nhiu module truyn thng ni tip USCI. USCI thng c 2 knh A v B: USCI_A truyn nhn d liu ni tip bt ng b USCI_B truyn d liu ng b SPI v IC2 gia Slave v Mater.
2.1.USCI-UART Mode

ch UART, modules USCI_Ax kt ni MSP430 vi thit b bn ngoi qua chn UCAxRXD v UCAxTXD. Ch UART c chn khi bit UCSYNC c xa. Mode UART bao gm: 7 hoc 8 bit data vi bit kim tra chn l hoc khng. Thanh ghi truyn v nhn c lp B m truyn v nhn ring bit.

C th truyn LSB hoc MSB u tin. T ng pht hin tn hiu bt u khi ang ch LPMx. C th thit lp v thay i tc Baud. C trng thi pht hin li. C trng thi a ch. S dng ngt trong truyn nhn.

2.2.UART Baud Rate Generation

Module USCI_A bao gm 3 ngun xung clocks: BRCLK l cp cho module (SMCLK, ACLK, UCA0CLK); BITCLK iu khin tc bit truyn/ nhn. .

BITCLK16: sampling clock ch oversampling vi tn s . Oversampling Mode: UCOS16=1; BRBIT u tin s qua b chia to ra BITCLK16, BITCLK16 tip tc qua b chia 16 to ra BITCLK,BITCLK 16 dng iu khin ly mu. Low-frquency mode UCOS16=0: BRCLK dng ly mu trc tip v qua b chia to ta BITCLK. Thanh ghi iu khin b chia: UCA0BR0 v UCA0BR1: cng ng vai tr nh UCBRx. UCBRFx ch s ca b chia to ra BITCLK16 ch oversampling mode. UCBRSx ch s ca b chia to ra BITCLK cch tng t. Setting a Baud Rate:

- Low-frequency baud rate mode setting:

- Oversampling baud rate mode setting (


2.3.Ngt USCI

))

USCI transmit interrupt operation: C ngt UCAxRXIFG c set khi d liu c np vo UCAxTXBUF sn sng truyn. xy ra ngt th c UCAxTXIE v GIE cn c set. UCAxTXIFG t ng reset nu k t c vit ln UCAxTXBUF. USCI Receive Interrupt Operation

C ngt UCAxRXIFG c set nu d liu nhn c np vo UCAxRXBUF. xy ra ngt th c UCAxTXIE v GIE cn c set. UCAxRXIFG t ng reset nu UCAxRXBUF c c.
2.4.USCI Register UART mode

Kho st mt s thanh ghi quan trng. Cc thanh ghi ch UART nh bng 3 v 4:

IV.LM35(Cm bin nhit c chnh xc cao) LM35 l 1 dy cc sensors nhit c tch hp trong mch ca IC,m in p u ra ca n th t l tuyn tnh vi phn trm ca nhit . Do LM35 c u im l cc sensors nhit c ly chun theo Kelvin,cng nh ngi s

dng khng i hi 1 gi tr hng s in p ln t u ra ca n thun li cho vic xc nh thang o. LM35 hot ng di nhit -55 n 150 C.LM35 l 1 IC trong tch hp 46 transistor TO. Thang o chun +10mV/ . chnh xc 0.5 ti 25 . Thun li cho cc ng dng xa, hot g di in p 4-30V. Dng in cc mng D nh hn 60uA.

V.Tm hiu v LCD 16x2 1.Bng m t s chn ca LCD 16x2: Chn K hiu I/O M t 1 Vss Mass 2 Vcc Dng ngun 5v 3 VEE Cp ngun iu khin tng phn 4 RS I RS=0 chon thanh ghi lnh RS=1 chon thanh ghi d liu 5 R/W I R/W=1 c d liu, R/W=1 ghi 6 E I/O Cho php 7 DB0 I/O Bit d liu 8 DB1 I/O Nt 9 DB2 I/O Nt 10 DB3 I/O Nt 11 DB4 I/O Nt

12 13 14

DB5 DB6 DB7

I/O I/O I/O

Nt Nt Nt

Chn 15 v 16 l A v K. N c ni vi 2 chn ca 1 con Led dng sng LCD trong bng ti chng ta khng s dng. - S ghp ni LCD vi vi iu khin:

2.Nguyn l hot ng ca LCD: - Chn VCC, Vss, v VEE: cc chn VCC v VSS cp dng ngun 5v v mass tng ng. Chn VEE c dng iu khin tng phn. - Chn chn thanh ghi RS(Register Select): c 2 thanh ghi trong LCD chn RS c dng chn thanh ghi. nu RS=0 th thanh ghi m lnh c chn cho php ngi dng gi 1 lnh ln chng hn nh xo mn hnh, a con tr v u dng Nu RS=1 th thanh ghi d liu c chn cho php ngi dng gi d liu cn hin th ln LCD. - Chn c/ghi (R/W): u vo c/ghi cho php ngi dng c thng tin t LCD khi R/W=1 hoc ghi thng tin ln LCD. - Chn cho php E(Enable): chn cho php c s dng bi LCD cht d liu ca n. Khi d liu c cp n chn d liu th 1 xung mc cao

xung thp phi c p n chn ny LCD cht d liu trn cc chn d liu. Xung ny c rng ti thiu 450ns. - Chn DB0-DB7: y l ng d liu 8 bt, c dng gi thng tin ln LCD hoc c ni dung cc thanh ghi trong LCD. hin th cc ch ci v cc con s, chng ta gi m ASCII ca cc ch ci t A n Z , a n z v cc ch s t 0 n 9 n cc chn ny khi bt RS=1. - Bng m lnh ca LCD: M (HEX) Lnh n thanh ghi ca LCD 01 Xo mn hnh hin th 02 Tr v u dng 04 Gim con tr(dch con tr sang tri ) 06 Tng con tr(dch con tr sang phi) 05 Dch hin th sang phi 07 Dch hin th sang tri 08 Tt con tr, tt hin th 0a Tt hin th, bt con tr 0c Bt hin thi, tt con tr 0e Bt hin th, nhp nhy con tr 0f Tt con tr, nhp nhy con tr 10 Dch v tr con tr sang tri 14 Dch v tr con tr sang phi 18 Dch ton b hin th sang tri 1c Dch ton b hin th sang phi 80 p con tr v u dng th nht 0c0 p con tr v u dng th 2 38 Hai dng v ma tn 5x7.

B.Thit k
ti: Thit k mch o nhit mi trng s dng vi iu khin MSP430, hin th nhit ln LCD v giao tip UART vi my tnh v th s bin i nhit ln my tnh. I.S nguyn l ca mch:

II.Chc nng ca tng khi: 1.Khi ngun S dng LM1117 iu khin in p ra n nh 3.3V cung cp cho vi iu khin v led.

2.Khi LCD Nhn d liu t vi iu khin hin th ra nhit o c.

3.Khi Reset Reset li ton mch

4.Khi LM35 S dng IC LM35 (cm bin nhit ) o nhit ca mi trng.

5.Khi vi iu khin S dng MSP4302553 nhn d liu t LM35 bin i ADC gi gi tr hin th nhit ln LCD v thc hin giao tip UART vi my tnh v th bin i in p ln mn hnh my tnh bng C#.

III.Nguyn l hot ng ca mch Khi ngun cung cp in p n nh 3.3V cho vi iu khin MSP430,LM35,Led hot ng bnh thng. Cm bin nhit LM35 s o nhit v a d liu vo chn ADC0 ca vi iu khin (d liu l cc tn hiu in).Vi iu khin thc hin cc bin i ADC a cc tn hiu ny i ra nhit v a ln hin th ln LCD qua cc Port 2 ca vi iu khin v c ghi d liu vo LCD qua cc port 1.5 v 2.0 ca MSP430. Vi iu khin thc hin giao tip UART vi my tnh thng qua cc chn TX v RX a d liu ln my tnh v dng Visual v biu i bin i nhit ln mn hnh my tnh.

IV.Cc linh kin s dng trong mch

V.S mch in

VI.Kt qu

C.Kt Lun
Trong thi gian lm ti vi s hn ch v thi gian, ti liu, c s vt cht cng nh hn ch v kin thc i hi bn thn chng em phi c gng tm ti v nhit tnh trong cng vic nghin cu ti v cui cng ti hon thnh trn vn. l kt qu ca mt thi gian di n lc nghin cu ca chng em di s hng dn tn tnh ca gio vin hng dn nn ti hon thnh ng thi hn. Vi ti ny chng em va kim tra c kin thc ca mnh, va thu c mt s kin thc v lp trnh vi iu khin MSP430. Tuy thnh qu cng vic khng c g to ln nhng l qu trnh dn dt chng em lm quen vi vic ng dng kin thc hc vo thc t, to mt kh nng t lp khi nghin cu mt vn no . Tuy nhin trong qu trnh lm vic chng em khng th trnh khi sai st. Mong s ch bo ca thy v ng gp kin ca bn b ti ngy mt hon thin hn. Em chn thnh cm n thy

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