EECS 240 Analog Integrated Circuits Analog Scaling

S.Gambini Department of Electrical Engineering and Computer Sciences

EECS 240 Analog Scaling

2011 S.Gambini

What determines power/area consumption in analog?

Signal to Noise Ratio Linearity & Matching BW Vdd,nF,Cs Avt n,Cox

Design Methodology

Power,area How do these parameters change with technology scaling?

EECS 240 Analog Scaling

2011 S.Gambini

Scaling models(1)
Constant-field scaling (good old days)

L VDD Cox Avt fT,max fT,ss fK

!L !VDD Cox/! ~!Avt fT,max/! fT,ss/!2 fK/a2

EECS 240 Analog Scaling

2011 S.Gambini

SNR-limited design
typical example: A/D converter with >10 bits full scale input ~ VDD Fixed SNR specification S/N Psig=(VDD-kV*)2/2 Pnoise=nFKT/CLeff/f BW=f Gm/CLeff Psig CLeff (For same BW) Gm What happens to VDDID ?

ID

EECS 240 Analog Scaling

2011 S.Gambini

SNR-limited design
V*=100mV;f=1/3;SNR=80dB;BW=100MHz;k=2.5

Does not look so good....

EECS 240 Analog Scaling 2011 S.Gambini

Check our assumptions:

Are f,V* really unchanged? probably not A few tries: V* Vdd-kV* BAD! V* nF BAD!

f: L f This might help- but we are changing open-loop gain Can we find architectures that tolerate lower open loop gain? BW: is bandwidth really what matters? What if Slew Limited? Slew limited: Vdd Vstep Id Power goes down!
EECS 240 Analog Scaling 2011 S.Gambini

Noise-limited design
Input signal amplitude Vin fixed independent of Vdd Input noise fixed Example:(some) Sensor Interface,Radio Psig=Vin2/2 Pnoise=4KT/Gm BW nF+1/f noise Vdd Psig,Pnoise VddId V*

In addition: more fT fK Pnoise

Looks better
EECS 240 Analog Scaling 2011 S.Gambini

Matching limited design

Input signal amplitude Vin fixed independent of Vdd Noise ( to first order) negligible, matching important Example:low resolution A/D converter Psig=Vin2/2 !(Vio)= K Vin/2Nbits Vdd Avt Psig,!(Vio) Area,Ctot VddId

Also Looks Pretty good Also, scaling means lower comparator " for the same power, hence faster comparators possible
EECS 240 Analog Scaling 2011 S.Gambini

Power-limited scaling (today)

L VDD Cox Avt fT,max fT,ss fK !L ~1V Cox/!" ? fT,max/! fT,ss/!2 fK/a2

EECS 240 Analog Scaling

2011 S.Gambini

SNR-limited design
typical example: A/D converter with >10 bits full scale input ~ VDD Fixed SNR specification S/N Psig=(VDD-kV*)2/2 Pnoise=nFKT/CLeff/f BW=f Gm/CLeff Psig CLeff (For same BW) Gm

ID

Second order effects dominate-increased f, etc.

EECS 240 Analog Scaling

2011 S.Gambini

Noise-limited design
Input signal amplitude Vin fixed independent of Vdd Input noise fixed Example:(some) Sensor Interface,Radio Psig=Vin2/2 Pnoise=4KT/Gm BW nF+1/f noise Vdd Psig,Pnoise VddId V*

In addition: more fT fK Pnoise

Not so clear here either....

EECS 240 Analog Scaling 2011 S.Gambini

Digital Scaling

150X

More and more digital can be used for calibration

EECS 240 Analog Scaling

2011 S.Gambini

Dynamic Range
Analog power: quadratic in DR (for noise limited) Digital power: logarithmic in DR Digital computation always better? A/D #Bits=B1 fS Processing Processing A/D #Bits=B2 fS2

Analog advantageous for low dynamic range (<5-6 bits),simple computation or if ADC is very expensive and signifcant #bits/ speed reduction can be obtained. Or, when leakage power dominates digital power
EECS 240 Analog Scaling 2011 S.Gambini

Example analog-intensive systems

Chip1 Chip2

PCB trace

100001 TX

LPF

RX

EECS 240 Analog Scaling

2011 S.Gambini