CSE 577 Spring 2011

Current Source & Bias Circuits

Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Pennsylvania State University

Introduction
Required Features of Current Source
High Rout Wide Operation Range Constant Current Source Low PVT (Process, Voltage, Temperature) Sensitivity

Required Features of Bias Circuit

Low Rout Low PVT Sensitivity

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Current Source

Basic Current Source Wilson Current Mirror Cascode Current Mirror

Ideal vs. Actual Current Source

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Simple NMOS Current Source

Whats the bad feature of this?

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Cascode Current Source

Whats the bad feature of this?

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Basic Current Mirror

Whats the bad feature of this?

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Wilson Current Mirror

I out = I ref

g m1 (W / L)1 = I ref g m2 (W / L) 2

Whats the drawback of this circuit?

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Cascode Current Mirror

But, it still has limited output swing problem.

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Wide Swing Cascode Current Mirror

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Bias Circuits

Self Bias Circuits PTAT Bias Circuits Band gap Reference

Power Supply Dependency of Current Source

Consideration Factors
- VDD - Channel Length Modulation - Transistor Mismatch

How do we generate Iref independent of the supply voltage?

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Self Biasing Circuit

Whats role of Rs?

Whats the advantage of these circuits? Whats the problem of these circuits?
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Improved Self Biasing Circuit

Improved Circuit with Start-up Circuit Improved Circuit eliminating Body Effect * This Circuit is practical only if

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A Simple Temperature Compensation Concept

0
VDD VDD

M1(Ids)
Negative TC

90 Positive TC ZTC (Zero Temperature Coefficient)

vr0 M1 R1 M1(Vgs)

Self Bias Circuit

1. R1 is a conductor which has positive TC 2. M1 has negative TC below ZTC point (Semiconductor) 3. If we control Vr0 below ZTC point, Vr0 become less sensitive to temperature due to opposite TC of M1 and R1

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Case Study (I) Self Bias Circuit in DRAM

starter

For Temp. Compensation

Vext

pmos diode

vref
Whats the drawback of these circuits?
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Case Study (II) Self Bias Circuit in DRAM

Why does this circuit need the voltage buffer? Why are PMOS current mirrors stacked in the reference bias circuit? Voltage Buffer
starter For Temp. Compensation

vr1

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VBE Referenced CMOS SelfSelf-bias Circuit

How do we fabricate BJT in CMOS Process Technology?

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* Temperature Sensitivity ~ - 4000 ppm/C

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Realization of pnp BJT in CMOS Technology

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Vth Referenced CMOS SelfSelf-Bias Circuit

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Thermal Voltage Referenced CMOS SelfSelf-Bias Circuit

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Thermal Voltage Referenced CMOS SelfSelf-Bias Circuit

* Temp. Sensitivity ~ +3300 ppm/C 2/22/2011 Insoo Kim

CMOS Band gap Reference

Whats the problem?

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(contd) CMOS Band gap Reference

Actual Implementation of CMOS Band Gap Reference

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Actual Implementation of CMOS Band gap Reference

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Design Lab. Self Bias Circuit with Temp. Compensation Schematics

* AMIS 0.5um Tech

(a) Basic Schematic

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(b) actual implementation

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Design Lab. Self Bias Circuit with Temp. Compensation Simulation Results

VDD Vr0b

Vr0 (a)

Vr0 (b)

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Design Lab. Self Bias Circuit with Temp. Compensation Simulation Results Temp. Compensation
90C 25C 25C 90C

-10C

(a) (b)

(a) -10C (b)

Vr0
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Current
Insoo Kim

Design Lab. Self Bias Circuit with Temp. Compensation Zero Temperature Coefficient Point

90C

25C

-10C 0.82V

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References
Joongho Choi, CMOS analog IC Design, IDEC Lecture Note, Mar. 1999. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. Hongjun Park, CMOS Analog Integrated Circuits Design, Sigma Press, 1999.

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