Low-Noise Smart Sensor Based on Silicon Nanowire

for MEMS Resistive Microphone

J.Nebhen,E. Savary, W. Rahajandraibe, C. Dufaza, S.
Meillre, E. Kussener, H. Barthelmy

Aix Marseille University, CNRS, IM2NP UMR 7334, 13451,
Marseille, France.
jamel.nebhen@im2np.fr


J. Czarny, A. Walther
CEA-LETI
17 rue des Martyrs
38054 Grenoble, France
jaroslaw.czarny@cea.fr

AbstractThe design of CMOS integrated circuits dedicated to
hybrid integration of a MEMS resistive microphone with
readout interface is presented. Audio sensing is achieved with an
innovative low-cost technology that implements piezoresistive
detection in MEMS devices with single crystal silicon nanowires.
The complete circuit includes a custom designed analog front-
end consisting of a sensor conditioning and a fourth order single
bit continuous-time sigma-delta modulator (CT-!"M). The
complete interface circuit exhibits a current consumption of
2mA. The obtained smart-sensor features a reduced output data
rate that is suitable for a wireless sensor network with direct
transmission of the raw data to a remote base station.

I. INTRODUCTION
UDIO acquisition systems are among the fastest growing
consumer products such as smart phones, multimedia
portable PCs and video cameras. All these systems need the
development of new devices, both on the transducer and on
the front-end circuit to satisfy their demand for continuous
miniaturization and increase of their performances. Silicon
microphones are one of the rapidly maturing areas of MEMS
sensors owing to their improved aspects over the
conventional Electret-Condenser-Microphones (ECM) [1].
Silicon microphones exhibit improved aspects over ECMs
such as compatibility with standard fabrication and assembly
procedures, reduced size, low-power consumption, higher
immunity to mechanical shocks and low temperature
coefficient. For each reason, silicon microphones become a
viable candidate for applications where conventional ECMs
are applied. It opens-up the possibility of considering them in
novel applications such as microphone sensor for enhanced
acoustic performance [2]. However, interfacing to MEMS
microphones gives rise to a challenging necessity of
addressing the low-noise, low-power and high-performance
aspects of the interface at the same time. MEMS microphones
suffer from sensitivity deterioration owing to the inevitable
variation in gauge resistance. Since Microphones have a
relatively larger operational bandwidth (10Hz10kHz),
sensitivity is sometimes traded-off by employing specific
mechanical structures [3], to achieve a flat response in the
whole audio band. The large frequency band causes the
parasitic capacitances to suffer from dielectric-dispersion,
which can ultimately cause distortion in the readout.
We propose a smart-sensor design dedicated to auditive
sensor nodes based on a novel micro-sensor technology called
Micro- & Nano-Electromechanical Systems (M&NEMS) [4]
that uses silicon nanowires as strain gauges built inside
MEMS devices. This particular detection scheme makes these
sensors different from most of the low-cost microphones,
which are built with polysilicon and use a capacitive detection.
Therefore, the readout circuit driving the sensor formed by a
conditioning circuit and a low-noise analog-to-digital
converter (ADC) must be very accurate and robust in order to
handle the typically weak sensor output signals. The output
signals of the sensor are also affected by offset voltage. In
practice, offset is subject to temperature and manufacturing
process variations, thus causing a shift in the signal range
provided by the sensor.
In this paper, an ADC based on CT-!"M has been used
for several reasons [5]. On one hand, the noise-shaping
performed by CT-!"M allows high resolution in the band of
interest, with low noise and low power consumption, in
addition, the action of feedback renders CT-!"M very linear.
On the other hand, the principle of the current sensing devices
fits in with the topology of the CT-!"M, allowing total
integration of the sensor in the converter structure [6-7]. To
reduce noise, we have implemented a new architecture to
connect the sensor with readout interface. We propose to
replace the input resistors of the CT-!"M by the silicon
nanowire gauge with nominal resistance of 4k#.
The rest of the paper is organized as following: an
overview of the micro-sensor technology featuring silicon
nanowires as strain gauges, is described in section II. This
particular technology requires the design of a specific
conditioning and readout system, which is described in section
III. Section IV presents the architecture-level considerations of
the CT-!"M. CMOS implementation of the integrated circuit
(ASIC) is briefly described in section V and section VI
concludes the paper.

II. SENSING DEVICE
MEMS microphone was developed at CEA-LETI and it is
based on so-called M&NEMS technological platform that
allows integration of various sensors on one Silicon die [8].
This technology, which uses suspended Silicon piezo-resistive
nanogauges as detection means, has already been applied to
inertial sensors and has shown to be promising for size
reduction or performance improvement. Transducer presented
in Fig. 1 consists of four rigid micro beams placed between
the inlet vents that guide the sound waves and outlet vents that
enable pressure equilibration in a back cavity. Micro-slits
between the beams and top and bottom wafers enable the
motion of the beams while ensuring pressure drop from one to
the other side of the beam. Stress induced by the motion of a
A
978-1-4673-4642-9/13/$31.00 2013 IEEE

Figure 1. Cross-sectional scheme of the microphone with acoustic
configuration and sensing elements.

Figure 2. Top view of the micro-beams and the nanogauge.
beam inside suspended piezo-resistive Si gauges is transduced
into resistance variations and measured by use of Wheatstone
bridge architecture. The gauges are arranged into full
Wheatstone bridge in such manner that, on the occurrence of
sound pressure, two gauges will be compressed while the
other two will be stretched. Such sensor architecture ensures
self-cancelation of random accelerations.
The MEMS fabrication is carried out at CEA-LETI clean
room with typical micro-electronic process. Final shape of
MEMS part with zoom on nanogauge and rectangles
indicating inlet (blue) and outlet (green) vents is shown in Fig.
2. NEMS microphone exhibits 30 dB of Equivalent Input
Noise (EIN) with a resolution of 95 nV/bits. Analytical
calculation shows that 74 dB SNR (Signal to Noise Ratio)
could be achieved with biasing current of 100 A and readout
circuit featuring 6 nV/$Hz input referred noise.

III. M&NEMS SENSOR READOUT CIRCTUIT
Audio applications including hearing aids implant involve
large dynamic range and low power consumption. Acoustic
vibration lower than 30 dB SPL (Sound Pressure Level) must
be resolved while sound pressure over 110 dB SPL must not
generate harmonic distortion. Commercially available digital
output MEMS microphones feature 30 dB SPL of equivalent
input referred noise, power consumption lies in the mA range
with supply voltage of 2.5 V. The proposed M&NEMS
microphone targets input referred noise of 5 dB SPL lower
than commonly used MEMS microphones.
The M&NEMS analog front-end is depicted in Fig. 3. It is
composed of a sensor biasing circuit and a continuous time

Figure 3. M&NEMS Sensor analog front-end
sigma delta modulator used as read out circuit. The
Wheatstone bridge, composed by the nanowire gauges is
biased with a voltage controlled constant current sources.
Common mode voltage at modulator input is maintained at
Vdd/2 with a servo loop build around A1 that equate source
and sink current through the bridge. The differential current
Iin flowing through the modulator is proportional to the gauge
resistance imbalance induced by acoustic vibrations.
Note that a modulator (CT-!%M) follows directly the
Wheatstone bridge rather than an instrumentation amplifier
(IA). This proposed readout circuit exhibits improved aspects
over traditional architecture since the two voltage
preamplifiers used in classical IA topology have been omitted,
leading to simplest implementation and, a priori, lower noise
and power consumption. Single-bit modulator is well suited to
achieve high-resolution digital representation in spite of
impairment limitation of most advanced technological node.
Interfacing with standard audio processor will be
accomplished with the appropriate decimation filter.
Resolution is first limited by sensor self noise as well as
its biasing current. The noise from the sensor is composed of
i) Brownian motion acting on the mechanical structure causing
random resistance variations, ii) flicker noise due to
semiconductor biasing and iii) thermal noise. Increasing the
sensor current bias increases the useful signal level but also
the Brownian and Fliker noise, thus SNR improvement with
stronger biasing is limited. Next noise contribution comes
from the first amplifier where, once again, more power is
involved to rise signal to noise ratio.
For high sensitivity of the microphone, the system was
designed with a trade off between, noise performance, and
power consumption where an optimal repartition of the current
budget between the sensor bias and the modulators amplifier
building blocks has to be achieved. Cascaded continuous time
integrator feed-forward sigma delta seems to be the best ADC
topology to accomplish the involved trade off. First,
continuous time integrator provides intrinsic anti-aliasing
filtering [9] saving filter stage power consumption; second,
feed-forward implementation reduces integrators output swing
requirement [10] making amplifier design easier; third, unlike
switched capacitor integrator, amplifier settling time
requirement is relaxed, so as the saved power budget can be
allocated to input stage in favor of noise performance.
Modulator order was set to handle dynamic range of 10 dB
above sensor dynamic to allow for a software post-processing
compensation of the sensor drift caused by temperature
variations.
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IV. ANALOG-TO-DIGITAL CONVERSION
A. System design
The oversampling ratio (OSR) of the modulator was set to
64 to push quantization noise out of the 10 kHz bandwidth
whereas complying with standards digital audio clock
sampling frequency of 3.072 MHz. With a fourth order noise
shaping, theoretical signal to quantization noise ratio (SQNR)
of 127 dB is possible. In the current design, the circuit
resolution will be limited by electronic noise. Allowed SNR
degradation margin is estimated to be sufficient to incorporate
elements non-idealities loss in the whole system performance.
The coefficients of the modulator have been derived from [11]
and have been computed from Matlab sigma-delta ToolBox
based on the invariant impulse response theorem, they are
scaled to limit integrators output voltage swing to make low
voltage operation possible without rail-to-rail amplifier
topology. Modulator system topology is shown in Fig. 4,
where ci (i=2 to 4) represents the integrator coefficient, and ai
(i=1 to 4) represents the feed-forward coefficient. It was also
stated in the literature that this topology offers good stability
of the loop [12].
The finite gain and frequency bandwidth of real amplifier
used in integrators play important roles in the accuracy of the
integration stages. It has an impact on noise shaping and may
be responsible of SNR degradation. From simulation results it
was found that a DC gain of 60 dB with 6 MHz unity gain
bandwidth keeps time constant integration close to ideal value.
Finally, facing standard CMOS amplifier performance,
requirements for gain and bandwidth are rather relaxed.
Behavioral simulation performed with Simulink achieves 121


Figure 4. Sigma-delta topology

Figure 5. Modulator output spectrum
dB SQNR. The modulator output spectrum is shown in Fig. 5
with a 1 kHz test tone used as reference signal. The circuit has
been implemented on 65nm CMOS technology. However only
0.28 &m transistor (GO2) with 2.5-V supply voltage, offering
better noise performances compared to GO1 implementation
has been used. All the integrators are realized with active-RC
filter to guarantee linearity over full signal range. In addition,
its virtual ground relaxes the input range constraint on the
amplifier, which is in favor to low-voltage operation.
B. Noise calculation
As it was discussed upper, input stage noise performance is
critical. The main noise sources at the input stage come from
the equivalent input resistors of the nanowire gauge R1//R3,
the DAC resistors R
DAC
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of noise sources to the input-referred noise can be derived as
[13].


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A noise-efficient and gain-enhanced fully-differential two-
stage amplifier is developed for the modulator. The fully-
differential structure provides large output swing, even-order
harmonic suppression, and good PSRR/CMRR performance.
Two-stage amplifier is stabilized by the compensation
capacitors (CC). This topology isolates the gain and output
swing requirements [14]. To ensure that the output common-
mode level remains in the middle of supply voltage, a
common-mode-feedback circuit (CMFB) is necessary in the
active-load fully-differential amplifier to control its common-
mode voltage. CMOS operational amplifier exhibits Flicker
noise and thermal noise components. For typical bias
conditions and device geometries, the Flicker noise is
generally larger than the thermal noise for frequencies below
10Hz 10kHz.
An amplifier achieving an open-loop DC gain of 65 dB, a
phase margin of 62, and a unity-gain bandwidth of 16 MHz
has been implemented for the CT-!"M.


Figure 6. Layout of the CMOS ASIC in 0.28&m CMOS process: a) CT-
!"Modulator, b) Instrumentation Amplifier, c)M&NEMS sensor bias, d)
Compensation Cell, e) Decoupling capactor.
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Figure 7. Equivalent input-referred noise of the readout circuit.
The equivalent input referred noise of the fully-differential
two-stage amplifier exhibits 6 nV/$Hz density at 1 kHz with a
power consumption of 750 W.

V. OVERVIEW OF THE CMOS ASIC
A readout circuit related test chip has been fully integrated
and implemented on 0.28-&m CMOS technology. High-
resistive poly-silicon resistors and metalinsulatormetal
(MIM) capacitors has been adopted for passive devices due to
their high linearity. Fig. 6 shows the full layout of the chip
including the I/O pads. The active circuit is composed by the
CT-!"M, sensor bias, compensation cell, and decoupling
capacitor. An isolated instrumentation amplifier has been
implemented for comparison. The test chip occupies 1 mm
2
.
Post-layout simulation of the complete chip has been done for
verification. The total current consumption is 2 mA, the
additional power comes from the analog part of the
compensation cell required by the active pads. The equivalent
input referred noise is shown in Fig. 7. As we can state, a
noise density of 7 nV/$Hz is achieved within the frequency
range from 10 Hz to 10 kHz confirming the theoretical value.

VI. CONCLUSION
A new smart audio nano-sensor based on CEA-LETIs
M&NEMS technology has been presented. A custom-
designed electronic front-end performs amplification and
signal readout. Our main concerns were noise, flexibility and
power consumption. The front-end operation was verified and
a low noise level was simulated. An ADC system based on a
1-bit CT-!"M allows for a high resolution with no calibration.
To reduce noise, we have proposed to replace the input
resistors of the !"M by the silicon nanowire gauge. This
smart sensor is thus adequate for a hearing aids implant
monitoring system with remote processing of the raw sensor
data. The test chip has been sent to fabrication for validation
on Silicon.
ACKNOWLEDGMENT
This work has been supported by the French National
Research Agency (ANR) in the frame of its program P2N
(project nANR 2011 NANO 026).
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