Sigma Delta 1.2

Spring, 2011
FUNDAMENTALS OF FUNDAMENTALS OF SIGMA SIGMA-- FUNDAMENTALS OF FUNDAMENTALS OF SIGMA SIGMA

DELTA MODULATORS DELTA MODULATORS
J ose Silva-Martinez
Texas A&MUniversity Texas A&M University
Electrical and computer Engineering
(Amesp02.tamu.edu/~jsilva)
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J . Silva-Martinez
Part 1.2
Spring, 2011 Sigma Sigma- -Delta Oversampled A/ D Delta Oversampled A/ D
Conversion Conversion
There are several ways to implement the loop filter and DAC There are several ways to implement the loop filter and DAC
Switched Switched--capacitor technique capacitor technique
Switched Switched capacitor technique, capacitor technique,
Continuous Continuous- -time technique, time technique,
Most of the descriptions in the literature for sigma Most of the descriptions in the literature for sigma--delta ADC delta ADC
utilize switched utilize switched- -capacitor techniques because of capacitor techniques because of
The The quantizer quantizer anddelays can be easily accountedin discrete anddelays can be easily accountedin discrete The The quantizer quantizer and delays can be easily accounted in discrete and delays can be easily accounted in discrete
domain domain
The direct mapping from discrete The direct mapping from discrete- -time system level design time system level design
t t i t l l i l t ti t t i t l l i l t ti to transistor level implementation to transistor level implementation
Sampling, loop delay and stability can be easily analyzed in Sampling, loop delay and stability can be easily analyzed in
the Z the Z- -domain domain
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J . Silva-Martinez
Excellent properties of on Excellent properties of on- -chip capacitor, like accurate chip capacitor, like accurate
capacitor ratios, high linearity and programmability. capacitor ratios, high linearity and programmability.
S it h d S it h d it it
Vref+Vref-
Switched Switched--capacitor capacitor
(discrete (discrete--time) 1st time) 1st--
order 1 order 1- -bit sigma bit sigma- -delta delta
modulator modulator
C
I
u1
u2
Out+
Input+
modulator. modulator.
It is a fully differential It is a fully differential
structure to avoid structure to avoid
dd
C
S
C
u2
2
u1
Out+
u1
common common- -mode mode
interference. interference.
This architecture is This architecture is
C
S
C
I
u1
u2
u1
Out-
Input-
directly mapped from directly mapped from
the functional diagram. the functional diagram.
u2
Vref+Vref- u1
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J . Silva-Martinez
u2
Clock sequence
Conversion: Continuous Conversion: Continuous--Time Time
R li ti f R li ti f
Vref+Vref-
Conversion: Continuous Conversion: Continuous Time Time
Realization of a Realization of a
continuous continuous- -time 1 time 1
st st
order single order single- -bit sigma bit sigma- -
delta modulator delta modulator
C
I
Out+
R2
delta modulator. delta modulator.
It could be mapped from It could be mapped from
the functional diagram by the functional diagram by
i th I l i th I l
Out+
Input+
I
u1
R1
using the Impulse using the Impulse
Invariant Transform to Invariant Transform to
preserve the time domain preserve the time domain
properties of the discrete properties of the discrete
C
I
Out-
Input-
R1
R2
properties of the discrete properties of the discrete
prototype. prototype.
Vref+Vref- u1
Clock sequence
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J . Silva-Martinez
But switched But switched- -capacitor circuits capacitor circuits
need to settle to a certain accuracy within half clock period, need to settle to a certain accuracy within half clock period,
Limited operation speed and may result in high power Limited operation speed and may result in high power
consumption. consumption. pp
SC modulators barely achieve clock frequencies of 300 SC modulators barely achieve clock frequencies of 300 MHz. MHz.
For a continuous For a continuous--time implementation, there is no such time implementation, there is no such
t i t th hi h ti d l t i t th hi h ti d l constraint, thus higher operation speed or lower power constraint, thus higher operation speed or lower power
consumption could be expected. consumption could be expected.
Inherent anti Inherent anti- -alias mechanism that is very effective for alias mechanism that is very effective for
narrow narrow- -band applications band applications
Continuous Continuous- -time sigma time sigma--delta modulators operating up to delta modulators operating up to
several GHz have been reported several GHz have been reported
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J . Silva-Martinez
pp
Spring, 2011 Pros and Pros and conts conts of Continuous of Continuous- -
Time Noise Shaping Time Noise Shaping Time Noise Shaping Time Noise Shaping
Advantages of continuous-time sigma-delta noise shaping
d ith it h d it i l t ti compared with switched-capacitor implementation
Potential to work at higher frequencies
Intrinsic anti-alias filtering function (be careful with this statement) g ( )
Suitable for high speed bipolar integration
Easier to prototype with minimum discrete components
Disadvantages
Sensitive to clock jitter, and loop delay j , p y
Circuits need to be linear all the time
Tuning may be necessary due to PVT variations
Requires linear resistor option for CMOS technologies
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J . Silva-Martinez
Requires linear resistor option for CMOS technologies
More difficult to design and implement
Background required to understand Continuous Background required to understand Continuous- -time time
sigma sigma delta A/ Dconversion delta A/ Dconversion
sigma sigma--delta A/ D conversion delta A/ D conversion
Discrete-time sigma-delta modulation
Advantages and disadvantages of continuous-time implementation
Z-domain and S-domain transfer functions Z-domain and S-domain transfer functions
Impulse invariant transformations
Become familiar with mixed-mode loop analysis
Solid background on control theory Solid background on control theory
Solid background in Networks and feedback theory
Background in Matlab and Cadence
Understanding loop delay and its effects on loop stability
Understanding clock jitter
Tremendous intuition
But more important: BRAINPOWER is all about! BRAINPOWER is all about!
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J . Silva-Martinez
But more important: BRAIN POWER is all about! BRAIN POWER is all about!
Spring, 2011 EA EA Oversampled A/ D Conversion Oversampled A/ D Conversion
Architecture
Specifications and Matlab/Verilog-A simulations
Order and quantization levels
Feedback Feedforward Mixed-mode Feedback, Feedforward, Mixed-mode
Filter realization
Noise, Power, linearity
Quantizer (ADC)
Input impedance, Kickback noise, Power consumption, Delay
DAC
Speed, J itter performance, Linearity, Output impedance
Clocks Clocks
J itter, duty cycle and phase errors
System verification (Cadence)
SQNR, SJ NR, SNR, SDNR, stability, loop delay
Cl k Clocks
Calibration
Cover PVT variations, mismatch, add non-linearities
Extensive post-layout Simulations
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J . Silva-Martinez
p y
Metal delays, bondwire inductors, do not use ideal GND and ideal power supplies
Isolate as much as possible critical blocks from noisy digital.
Be careful with your assumptions; in many cases are not totally true!
Spring, 2011
Oversampled A/ D Conversion Oversampled A/ D Conversion
(Double check Masons rule) (Double check Masons rule) ( ) ( )
Ch k th i t t t t j t i
( )
| |
| |
|
|
.
|
\
|
= = =
+

1 1
2 2 2
1
T
e e e e Z z H
T
T
j
T
j
T
j
T j
e
e
e e e
e
Check the input-output trajectories
Original E(z) is shaped by NTF
O i i l E( ) i
Noise density Noise density
( )
|
|
.
|
\
|
|
.
|
\
|
=

2
2
2
T
sin j e z H
T
j
e
e
e
Original E(z) is
amplified here!
( )
( ) ( )
=
1
z H z E
Z z X
SQNR
e
Noise density Noise density
( )
|
.
|
\
|
=
2
2
T
sin z H
e
e
( ) ( )
( )
( ) | |
=
1
T
*
E
z X
SQNR
e
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J . Silva-Martinez
( )
|
.
|
\
|
2
2
T
sin
z E
e
Spring, 2011
( )
OSR
* * * . SQNR
N
3 1 2 5 1
2
3
2
|
|
.
|
\
|
~
t
Si l t Q ti ti
( )
( )
2
2
1
Z X
( ) dB OSR log * . N * . . SQNR 30 2 5 02 6 76 1 + + ~
. \
t
Signal to Quantization
Noise Ratio (SQNR)
( )
( ) ( ) ( )
( )
( ) ( ) ( )
= =
} }
0
2
2
0
2
1
df z H z E
z X
df z H z E
Z z X
SQNR
f
e
f
e
b b
N=number of bits in quantizer
OSR=fs/ 2fb
SQNR improves by 30dBwhen
( )
( )
|
.
|
\
|
|
.
|
\
|
=
}
0
2
2
2
2
1
e
df
T
sin
*
z E
z X
SQNR
f
b
SQNR improves by 30dB when
OSR increases by 10
Or 9dB SQNR improvement
( )
|
|
.
|
\
|
A
A
|
|
.
|
\
|
~
<<
2
3
2
2
2
6
2
2
1 2
2
1
t f *
f
f
*
*
*
V
V
SQNR
then , fs fb If
S
b
S
q
q
N
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J . Silva-Martinez
when doubling OSR
( )
|
|
.
|
\
|
~
2
3
2
3 1 2 5 1
2
12
t
OSR
* * * . SQNR
f
f
*
N
S
S
q
EA
EA
modulator
output
(digital)
H( )
Loop Filter
Quantizer
Sampler
Decimation
EA modulator
Anti-
Alias
H(z)
Input
(analog)
Filter
Nyquist
output
(digital)
Alias
Filter
(AAF)
DAC
High sample
rate, low
resolution
Low
sample
rate, high
resolution
Functional level diagram of a general discrete Functional level diagram of a general discrete--time time
ii d lt l d l d lt l d l tt di it l t di it l t
resolution
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J . Silva-Martinez
sigma sigma--delta oversampled analog delta oversampled analog--to to--digital converter digital converter
For an For an Lth Lth--order, oversampled low order, oversampled low- -pass SD modulator, dynamic pass SD modulator, dynamic
range (DR) can be expressedas, range (DR) can be expressedas,
range (DR) can be expressed as, range (DR) can be expressed as,
2 n 1 2L
2L
1) (2 SR O
1 2L
2
3
DR
+
=
+
OSR is the oversample ratio OSR is the oversample ratio
L is the order of the modulator (loopfilter) L is the order of the modulator (loopfilter)
2
L is the order of the modulator (loop filter) L is the order of the modulator (loop filter)
N is the number of bits of the N is the number of bits of the quantizer quantizer and DAC. and DAC.
Every time we double the oversample ratio, the equivalent Every time we double the oversample ratio, the equivalent
resolution increases by L+ resolution increases by L+0 0. .5 5 bits. bits.
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J . Silva-Martinez
( ) ( ) SR O log * 20 * . 0 L DR 5 + o
Spring, 2011
Top level decision: OSR, Top level decision: OSR, Filter Filter
order and bits in ADC/ DAC order and bits in ADC/ DAC //
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J . Silva-Martinez
|
.
|
\
|
|
|
|
|
.
|
\
|
|
.
|
\
|
+
+
+
= 1 N * 6. 02
2L
1 2L
OSR * 1 2L
2
3
10
l og * 10 dB
SQNR
i n
Spring, 2011 Continuous Continuous--Time Sigma Time Sigma- -Delta Delta
OversampledA/ DConversion OversampledA/ DConversion
The signal flow diagram of a sigma The signal flow diagram of a sigma--delta over delta over- -sampled sampled
analog analog--to to--digital converter andsignal spectrumplots at digital converter andsignal spectrumplots at
analog analog--to to--digital converter and signal spectrum plots at digital converter and signal spectrum plots at
different stages. different stages.
EA
Analog
input
Anti-alias
Filter
EA
Modulator
Decimation
Filter
Digital
output
g
n
a
l

F
l
o
w
S
i
g
Digital
e
c
t
r
u
m
Quantization
noise
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J . Silva-Martinez
S
p
e
Spring, 2011
Continuous Continuous- -Time Time
Sigma Sigma--Delta Modulation Delta Modulation Sigma Sigma Delta Modulation Delta Modulation
In the continuous In the continuous--time loop filter time loop filter Hc Hc(s) replaces the original (s) replaces the original
discrete discrete- -time loop filter H(z). time loop filter H(z).
Output
LoopFilter Quantizer
Discrete-time Continuous-time
Output
(digital)
Hc(s)
Input
Loop Filter Quantizer
x
c
(t)
u
c
(t)
p
(analog)
DAC
Y(n)
y
c
(t)
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J . Silva-Martinez
( )
Spring, 2011 Oversampled A/ D Conversion: Oversampled A/ D Conversion:
Feedforward Feedforwardarchitecture architecture
Eq stands for the quantization noise
Ed stands fo DAC non idealities (jitte +the mal noise)
Feedforward Feedforwardarchitecture architecture
Ed stands for DAC non-idealities (jitter + thermal noise)
Filters thermal noise is accounted in Eh
The modulators output becomes
( ) E * NTF E E X * STF Y
( ) ( ) s ZOH * s H
The error signal (Filters input) is
( )
q h d
E * NTF E E X * STF Y + + + =
( ) ( )
( ) ( )
1
1
1

+
=
Z * s ZOH * s H
STF
( ) { }
1
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J . Silva-Martinez
( ) ( )
1
1

+
=
Z * s ZOH * s H
NTF
( ) { }
q h d e
E * Z E E X ZOH ) s ( H * NTF V
1
+ + + =
Spring, 2011
Feed Feed--forward forwardconfiguration configuration Feed Feed--forward forwardconfiguration configuration
( ) ( )
( ) ( )
1
1

+
=
Z * s ZOH * s H
s ZOH * s H
STF
( ) ( )
( ) ( )
1
1
1
+
=
Z * s ZOH * s H
NTF
The system parameters are defined as
( )
|
|
|
=
=
S
T j
T
c sin * T z ZOH
e Z
S
e
e
( ) ( )
The lowpass transfer function H(s)
provides large loop gain (Noise shaping)
DC gain >>0 dB
( )
|
.
\
=
2
S
c sin * T z ZOH
DC gain >>0 dB
Enough phase margin at 0 dB gain
Z is a complex number (phase) Z is a complex number (phase)
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J . Silva-Martinez
Loop stability is fundamental Loop stability is fundamental
Spring, 2011
Feed Feed--forward forwardconfiguration configuration Feed Feed--forward forwardconfiguration configuration
( )
|
|
|
=
S
T j
T
i * T ZOH
e Z
S
e
e
Notice that
( )
|
.
|
\
|
=
2
S
S
c sin * T z ZOH
| |
| |
dB
0
5
0
f
i
|
|
|
( )
|
|
|
.
|
\
|
|
|
|
.
|
\
|
=
S
f
f
c sin f ZOH t
dB
15
10
5
20
15
10
S
S
f
f
sin
f
f
c sin
t
t
t
|
|
|
.
\
=
|
|
|
.
|
\
|
30
25
20
30
25
20
S
f
f
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J . Silva-Martinez
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.1 1
S
f
f
Spring, 2011
Use Masons rule again! Use Masons rule again! gg
( )
( ) f L
Z * f L
STF
+
=
1 ( )
( ) f L
NTF
f L
+
=
+
1
1
1
L(f) L(f) is defined as the
loop gain
( )
( ) ( )
( )
2
|
.
|
\
|
=
+ = =
T
c sin * T z ZOH
T sin * j T cos e Z
S
S
S S
T j
S
e
e e
e
Phase of L(f) L(f) is quite
important for stability
( ) ( )
1
2
=
. \
Z * z ZOH * z H ) f ( L
important for stability
Z is quite relevant for
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J . Silva-Martinez
phase of L(f)
Spring, 2011
Continuous Continuous--TTime ime EA EA Modulators Modulators
For in For in--band frequencies STF band frequencies STF
is determined by H(f) is determined by H(f)
At medium At medium- -high frequencies, high frequencies,
the blocker rejection is the blocker rejection is
limited( limited(WiMAX WiMAX)) limited ( limited (WiMAX WiMAX) )
Peaking if phase of L(f) Peaking if phase of L(f)
phase margin is not enough phase margin is not enough
A
DC
L(f)
At high At high- -frequencies, the frequencies, the
anti anti- -alias is mainly alias is mainly provided provided
by the by the sinc sinc function rather function rather
Freq
0 dB
( )
Fs
STF
NTF
( )
( ) f L
Z * f L
STF =
1
yy
than by the filter than by the filter
H(f)
ZOH(f)
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J . Silva-Martinez
( )
( ) f L
NTF
f L
+
=
+
1
1
1
Spring, 2011
Remarks on DAC non Remarks on DAC non- -idealities. Same analysis apply to the idealities. Same analysis apply to the
input referred filters noise input referred filters noise
E * STF Y =
d DAC
E * STF Y =
( ) ( )
( ) ( )
1
1

+
=
Z * s ZOH * s H
s ZOH * s H
STF
( ) ( ) 1 + Z s ZOH s H
DAC non DAC non--idealities are idealities are
reflected at the ADC output reflected at the ADC output
similarly to the signal similarly to the signal similarly to the signal similarly to the signal
Baseband noise can be directly Baseband noise can be directly
mapped to ADC input (Ed and Eh) mapped to ADC input (Ed and Eh)
Non Non linearities linearities in DAC that translate in DAC that translate Non Non--linearities linearities in DAC that translate in DAC that translate
HF noise into baseband affects HF noise into baseband affects
directly SQNR directly SQNR
DACis an extremely DACis an extremely
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J . Silva-Martinez
DAC is an extremely DAC is an extremely
critical component critical component
Spring, 2011
Remarks on Filters operation: Filters input Remarks on Filters operation: Filters input
E * Z E E X
q h d
+ + +
1
( ) s L
V
q h d
e
+
=
1
X(f)
F h i l f db k F h i l f db k l hi h l hi h i b d i b d
A
DC
H(f)
X(f)
For the single feedback For the single feedback loop architectures, the loop architectures, the inband inband
signal is usually very small: Nice property but signal is usually very small: Nice property but
Transition Transition band is more critical for filters linearity band is more critical for filters linearity
(neighbor channels); is this bad? Could be worse and it is! (neighbor channels); is this bad? Could be worse and it is!
0 dB
Fs
Freq
1/(1+L)
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J . Silva-Martinez
Mediu Medium and high frequency 1/ (1+L) gain could be around m and high frequency 1/ (1+L) gain could be around
22- -10 dB! 10 dB!
Filter must be designed for out Filter must be designed for out--of of--band blockers! band blockers!
ZOH(f)
Spring, 2011
Remarks on Filters operation: Filters input Remarks on Filters operation: Filters input
h d
E * Z * NTF
E E X
V
1
+ +
( )
q
h d
e
E * Z * NTF
s L
V
1
1
+
+
=
Ef Ef is an out is an out- -of of--phase replica of the phase replica of the X+Ef+Eh X+Ef+Eh if if
L(f)>>1 L(f)>>1
When loop gain reduces, the loop is less When loop gain reduces, the loop is less
effective andall HFinput signals appear at effective andall HFinput signals appear at effective and all HF input signals appear at effective and all HF input signals appear at
filter input filter input
Filter must be Filter must be very linear at HF to very linear at HF to
minimize signal minimize signal intermodulation intermodulation
di t ti di t ti distortions distortions
Filter must be designed for the Filter must be designed for the
blockers blockers
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J . Silva-Martinez
Blocker Blocker tolerance is a major issue in tolerance is a major issue in
broadband applications ( broadband applications (WiMAX WiMAX) )
Spring, 2011
Continuous Continuous--TTime ime EA EA Modulators Modulators
This is a realistic model This is a realistic model
Check the phase of the loop at Check the phase of the loop at Check the phase of the loop at Check the phase of the loop at
the unity gain frequency! the unity gain frequency!
( ) Z * f L ( )
( )
Z
f L
Z * f L
STF
/
+
=
1
2 1
( ) f L
Z
NTF
+
=
1
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J . Silva-Martinez
Spring, 2011
Stability Issues: Stability Issues: EA EA Modulators Modulators
A
DC
Freq
0
Fs
Check the phase contribution of Check the phase contribution of
the the filter filter and the and the delay delay
eq
L(f)
H(f)
( ) ( ) f H |
2
t
yy
element! element!
Check the Check the phase of the loop phase of the loop
at the unity gain frequency! at the unity gain frequency!
|
|
|
|
|
f
t 2
t
2
3 t
at the unity gain frequency! at the unity gain frequency!
Can you stabilize the loop Can you stabilize the loop
employing the conventional employing the conventional
filter design approach? filter design approach?
( )
( ) f L
Z * f L
STF
+
=
1
|
|
.
\ S
f
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J . Silva-Martinez
filter design approach? filter design approach?
Additional parasitic poles! Additional parasitic poles!
( )
( ) f L
Z
NTF
/
+
=

1
2 1
Spring, 2011
A
DC
With a filter with 2 zeros With a filter with 2 zeros
(finite gain at high frequency) (finite gain at high frequency)
Freq
0
Fs
( ) ( )
t
H(f)
( g g q y) ( g g q y)
Hard Hardto stabilize the loop if the to stabilize the loop if the
unity gain frequency is close to unity gain frequency is close to
Fs/ 2! Fs/ 2! (Very Low OSR) (Very Low OSR)
L(f)
( ) ( ) f H |
t
2
t
Notice Notice that the delay element add that the delay element add
--180 degrees at f=Fs/ 2 180 degrees at f=Fs/ 2
If the loop unity gain frequency is If the loop unity gain frequency is
not beyond not beyondf=Fs/ 4, then maximum f=Fs/ 4, then maximum
|
|
|
.
|
\
|
S
f
f
t 2
2
3 t
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J . Silva-Martinez
not beyond not beyondf Fs/ 4, then maximum f Fs/ 4, then maximum
phase contribution due to the phase contribution due to the
delay element is < delay element is <- -90 degrees 90 degrees
Spring, 2011
Not Not very difficult to stabilize the very difficult to stabilize the
loop if the unity gain frequency is loop if the unity gain frequency is
belowFs/ 4! belowFs/ 4! (not very LowOSR); (not very LowOSR); below Fs/ 4! below Fs/ 4! (not very Low OSR); (not very Low OSR);
e.g. around 100Mhz if clock e.g. around 100Mhz if clock
frequency is 400MHz frequency is 400MHz
Notice Notice that larger oversampling that larger oversampling
ratio allow you to reduce the filter ratio allow you to reduce the filter
gain at high gain at high- -frequency frequency
Out Out- -of of--Band noise is distributed Band noise is distributed in in
wider n=bandwidth, hence smaller wider n=bandwidth, hence smaller
A
DC
wider n bandwidth, hence smaller wider n bandwidth, hence smaller
noise density but same integrated noise density but same integrated
noise noise
Freq
0
( ) ( ) f H |
H(f)
L(f)
|
|
|
.
|
\
|
S
f
f
t 2
t
2
t
- 27 -
J . Silva-Martinez
2
3 t
Fs
Spring, 2011 Oversampled A/ D Conversion Oversampled A/ D Conversion
Multiple Feedback architecture Multiple Feedback architecture Multiple Feedback architecture Multiple Feedback architecture
This architecture presents This architecture presents
several several i te e ti i te e ti several several interesting interesting
properties, but be careful properties, but be careful
with its drawbacks! with its drawbacks!
Eq Eq stands for the stands for the
quantization noise quantization noise
( )
( ) ( )
1 1
2 + + + + =
ZOH * H * H
E * STF E * NTF E E X * STF Y
H q H d
Ed stands for DAC non Ed stands for DAC non- -
idealities (jitter + thermal idealities (jitter + thermal
noise) noise)
( ) ( )
( ) { } ( ) { }
1
2 1
2 1
2 1 1

+ +
=
ZOH
Z * ZOH * s H * D s H * D
ZOH * s H * s H
STF
noise) noise)
Filters thermal noise is Filters thermal noise is
accounted in EH1,2 accounted in EH1,2
D1 2 are the DAC D1 2 are the DAC
( ) { } ( ) { }
( )
( ) { } ( ) { }
2
1
2 1
2
2 1 1

=
+ +
=
ZOH * s H
STF
ZOH
NTF
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J . Silva-Martinez
D1,2 are the DAC D1,2 are the DAC
coefficients coefficients
( ) { } ( ) { }
1
2 1
2 1 1
2

+ + Z * ZOH * s H * D s H * D
STF
Feedback architecture Feedback architecture Feedback architecture Feedback architecture
( )
( ) ( )
( ) { } ( ) { }
1
2 1
2 1
2 1
2 1 1
2
+ +
=
+ + + + =
ZOH * s H * s H
STF
H q H d
( ) { } ( ) { }
( ) { } ( ) { }
( )
2
1
2 1
2 1
2
2 1 1
2 1 1
=
+ +
=
+ +
ZOH * s H
STF
ZOH
NTF
Z ZOH s H D s H D
Notice that in Notice that in- -band STF is still approximately unity (1/ D1 if band STF is still approximately unity (1/ D1 if
D1H1>>D2) upto the unity gain frequency D1H1>>D2) upto the unity gain frequency
( )
( ) { } ( ) { }
1
2 1
2 1 1
2

+ +
=
STF
D1H1>>D2) up to the unity gain frequency D1H1>>D2) up to the unity gain frequency
The error signal becomes: The error signal becomes:
( ) ( ) ( )
{ }
( ) ( )
H d
E E * s H * Z * NTF
Z * ZOH * s H * D E E X
V + +
+ + +
=

1
1
2 1
2 1
In In--band signal level at band signal level at Ve Ve is approximately obtained as is approximately obtained as
( ) { } ( ) { }
( ) ( )
q H e
E E s H Z NTF
V + +
+ +
=

2 2
1
2 1
2 1 1
( )
E
- 29 -
J . Silva-Martinez
( )
( ) ( ) { } ( ) { } s H * D s H * D
E
D s H * D
E D * E E X
V
q
H H d
e
2 1 1
2 1
2 1 2 1
2
+
+
+
+ + +
~
D1=1
( )
( ) ( )
( ) f L
ZOH * s H * s H
STF
H q H d
+
=
+ + + + =
1
2
2 1
2 1
( )
( ) ZOH * s H
STF
f L
ZOH
NTF
=
+
=
2
1
2
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
Out of band STF is quite small; excellent for blockers rejection Out of band STF is quite small; excellent for blockers rejection
NTF follows the ZOH at very high frequencies, Minimizing the alias issue NTF follows the ZOH at very high frequencies, Minimizing the alias issue
( ) f L
STF
+
=
1
2
{ }
- 30 -
J . Silva-Martinez
For STF2, again, the ZOH helps, but.. For STF2, again, the ZOH helps, but..
The ZOH is excellent filter around f= The ZOH is excellent filter around f=fs fs
The ZOH provides The ZOH provides --4 dB 4 dB
attenuation at f=0.5fs and attenuation at f=0.5fs and
--20 dB at f=0.9fs 20 dB at f=0.9fs
D1=1
( ) ( ) ( )
( ) f L
V
H d
e
+
+ + +
=

1
2 1
1
2 1
1
For in-band signals apparently is fine:
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( )
( )
1
1
2 1
2
H d
e
D H * D
D E E X
V
+ +
~
At the output of H1(s) we get
( )
( )
1
2
2 1
e
E E X
D
V
D s H * D
+ +
|
|
|
~
+
For out-band signals:
Most of the blockers and HF noise
( ) ( ) ( )
1
2 1 1
2 1

+ + + = Z * ZOH * s H * D E E X V
H d e
- 31 -
J . Silva-Martinez
This signal could be excessive for H2
( )
1 1
1
H d out H
E E X
D
V + +
|
.
\
~

sources are present at H1 input
D1=1
( ) ( ) ( )
( ) f L
V
H d
e
+
+ + +
=

1
2 1
1
2 1
1
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( )
( )
1
1
2 1
2
H d
e
D H * D
D E E X
V
+ +
~
( )
( )
1
2
2 1
e
E E X
D
V
D s H * D
+ +
|
|
|
~
+
( ) ( ) ( )
1
2 1 1
2 1

+ + + = Z * ZOH * s H * D E E X V
H d e
- 32 -
J . Silva-Martinez
( )
1 1
1
H d out H
E E X
D
V + +
|
.
\
~

D1=1
( ) ( )
( ) f L
E E * s H * Z * ZOH
V
q H
e
+
+
=

1
2 2
1
2
For in-band signals:
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( ) ( ) ( ) s H * s H
E
s H
E
V
q
H
e
2
2
+ =
At medium and HF only the ZOH helps
( ) ( ) ( ) s H * s H s H
2 1 1
- 33 -
J . Silva-Martinez
Looks like E Looks like EH2 H2 and and EEqq are not the main are not the main
issue in this topology issue in this topology
( ) ( )
q H e
E E * s H * ZOH V + =
2 2 2
Multiple Feedback architecture Multiple Feedback architecture Multiple Feedback architecture Multiple Feedback architecture
This linear This linear model is probably model is probably
more appropriated for the more appropriated for the
feedback architecture! feedback architecture!
ZOH does not affect the ZOH does not affect the
numerator of NTF numerator of NTF
Eq Eq stands for the stands for the
( )
( ) ( )
1 1
2 + + + + =
ZOH * s H * s H
H q H d
u e ato o u e ato o
Ed stands for DAC non Ed stands for DAC non- -
idealities (jitter + thermal idealities (jitter + thermal
noise) noise)
( ) ( )
( ) { } ( ) { }
1
2 1
2 1
1
2 1 1

=
+ +
=
NTF
ZOH * s H * s H
STF
noise) noise)
Filters thermal noise is Filters thermal noise is
accounted in EH1,2 accounted in EH1,2
D1 2 are the DAC D1 2 are the DAC
( ) { } ( ) { }
( )
( ) { } ( ) { }
1
2
1
2 1
2 1 1
2
2 1 1
+ +
=
+ +
=
ZOH * s H
STF
NTF
- 34 -
J . Silva-Martinez
D1,2 are the DAC D1,2 are the DAC
coefficients coefficients
( ) { } ( ) { }
2 1
2 1 1 + + Z ZOH s H D s H D
( )
( ) ( )
( ) { } ( ) { }
1
2 1
2 1
2 1 1
2
+ +
=
+ + + + =
ZOH * s H * s H
STF
H q H d
( ) { } ( ) { }
( ) { } ( ) { }
( )
{ }
1
2
1
2 1
2 1
2
2 1 1
1
2 1 1
=
+ +
=
+ +
ZOH * s H
STF
NTF
Z ZOH s H D s H D
Notice that in Notice that in- -band STF is still approximately unity (1/ D1 if band STF is still approximately unity (1/ D1 if
D1H1>>D2) upto the unity gain frequency D1H1>>D2) upto the unity gain frequency
( ) { } ( ) { }
1
2 1
2 1 1
2

+ +
=
STF
D1H1>>D2) up to the unity gain frequency D1H1>>D2) up to the unity gain frequency
The error signal becomes: The error signal becomes:
( ) ( ) ( )
{ }
( ) ( )
H d
E E * ZOH * s H * Z * NTF
V + +
+ + +
=

1
1
2 1
2 1
In In--band signal level at band signal level at Ve Ve is approximately obtained as is approximately obtained as
( ) { } ( ) { }
( ) ( )
q H e
E E ZOH s H Z NTF
V + +
+ +
=

2 2
1
2 1
2 1 1
( )
- 35 -
J . Silva-Martinez
( )
( ) ( ) { } ( ) { } ZOH * s H * D s H * D
E
D s H * D
E D * E E X
V
q
H H d
e
2 1 1
2 1
2 1 2 1
2
+
+
+
+ + +
~
D1=1
( )
( ) ( )
( ) { } ( ) { }
1
2 1
2 1
2 1
2 1 1
2
+ +
=
+ + + + =
ZOH * s H * s H
STF
H q H d
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( ) { } ( ) { }
( )
( ) { } ( ) { }
1
2 1
2
1
2 1
2 1 1
2
2 1 1
1
+ +
=
+ +
=
ZOH * s H
STF
NTF
Out of band STF is quite small; excellent for blockers rejection Out of band STF is quite small; excellent for blockers rejection
NTF does not follows the ZOH at very high frequencies NTF does not follows the ZOH at very high frequencies
{ }
( ) { } ( ) { }
2 1
- 36 -
J . Silva-Martinez
For STF2, again, the ZOH helps, but.. For STF2, again, the ZOH helps, but..
The ZOH is excellent around f= The ZOH is excellent around f=fs fs
The ZOH provides The ZOH provides --4 dB 4 dB
attenuation at f=0.5fs and attenuation at f=0.5fs and --20 dB 20 dB
at f=0.9fs at f=0.9fs
D1=1
( ) ( ) ( )
( ) f L
V
H d
e
+
+ + +
=

1
2 1
1
2 1
1
For in-band signals apparently is fine
if D2 is not very large
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( )
1
2
H d
D E E X
V
+ +
~
( )
1
1
2
2 1
e
D
D s H * D
V
| |
+
~
( ) ( ) ( )
1
2 1 1
2 1

+ + + ~ Z * ZOH * s H * D E E X V
H d e
- 37 -
J . Silva-Martinez
( )
1 1
1
2
H d out H
E E X
D
D
V + +
|
.
|
\
|
~

D1=1
( ) ( ) ( )
( ) f L
V
H d
e
+
+ + +
=

1
2 1
1
2 1
1
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( )
( )
1
1
2 1
2
H d
e
D H * D
D E E X
V
+ +
~
( )
( )
1
2
2 1
e
E E X
D
V
D s H * D
+ +
|
|
|
~
+
( ) ( ) ( )
1
2 1 1
2 1

+ + + = Z * ZOH * s H * D E E X V
H d e
- 38 -
J . Silva-Martinez
( )
1 1
1
H d out H
E E X
D
V + +
|
.
\
~

D1=1
( ) ( )
( ) f L
E E * ZOH * s H * Z
V
q H
e
+
+
=

1
2 2
1
2
For in-band signals:
( ) ( ) { } ( ) { }
1
2 1
2 1

+ = Z * ZOH * s H * D s H * D f L
( ) ( ) ( ) s H * s H
E
s H
E
V
q
H
e
2
2
+ =
At medium and HF only the ZOH helps
( ) ( ) { } ( ) { }
2 1
f
( ) ( ) ( ) s H * s H s H
2 1 1
- 39 -
J . Silva-Martinez
Looks like E Looks like EH2 H2 and and EEqq are not the main are not the main
issue in this topology issue in this topology
( )
q H e
E E * s H * ZOH V + =
2 2 2
Architecture
Order and quantization levels
Feedback Feedforward Mixed-mode Feedback, Feedforward, Mixed-mode
Filter realization
Quantizer (ADC)
DAC
Clocks Clocks
Cl k Clocks
Calibration
- 40 -
J . Silva-Martinez
p y
Spring, 2011
- 41 -
J . Silva-Martinez
Spring, 2011
Basic Continuous Basic Continuous--Time Time EA EA Modulator Modulator
H(s) 1
H(s)
in
V
out
D
STF
+
= =
Key Features Key Features
Bandwidth is traded with resolution
Suitable for high frequency applications
Suitable for low-voltage technologies
0
1
t
D
g g
Inherent anti-aliasing
Quantization noise is attenuated by high loop gain
Modest power consumption
- 42 -
J . Silva-Martinez
H(s) 1
1
noise
Q
out
D
NTF
+
= =
Good linearity, but must be improved to get better
resolution in ADC
Spring, 2011
System Design Considerations System Design Considerations
|
|
|
|
|
|
|
|
|
.
|
\
|
+
+
+
= 1 N * 6 02
1 2L
OSR * 1 2L
3
10
l og * 10 dB
SQNR
i n
Dynamic range
Order of filter, L L Becomes difficult to stabilize the system
|
.
|
\
|
|
|
.
\
+ = 1 N 6. 02
2L
2
10
l og 10 dB
SQNR
i n
Design parameters
Quantizer resolution, N N Linearity of the DACs limit the performance
Difficult to realize at high speeds
Over sampling ratio, OSR OSR Delay becomes critical
- 43 -
J . Silva-Martinez
For this project we use: L = 5, N = 3 and OSR = 8 SQNR = 74 dB
Clock Jitter limits the performance
43
Spring, 2011
- 44 -
J . Silva-Martinez
|
.
|
\
|
|
|
|
|
.
|
\
|
|
.
|
\
|
+
+
+
= 1 N * 6. 02
2L
1 2L
OSR * 1 2L
2
3
10
l og * 10 dB
SQNR
i n
Spring, 2011
System Design Considerations System Design Considerations (contd.) (contd.)
Third and fifth-order loop filters are popular for WiMAX
Loop filter H(z)
Chebyshev filter to get sharp roll-off with minimum group delay ripple in passband
High order filters affect more system stability: compensating zeros are critical
For instance, for a 5
th
order 20MHz modulator we have For instance, for a 5 order 20MHz modulator we have
Two complex conjugate poles at 16.7 MHz, 24.5 MHz
One real pole in LHP at 5.71MHz
- 45 -
J . Silva-Martinez
Two complex conjugate zeros at 37.5 MHz and 47.3 MHz
Architecture
Order and quantization levels q
Feedback, Feedforward, Mixed-mode
Filter realization
Quantizer (ADC) Q ( )
DAC
Clocks
Clocks
C lib i Calibration
I l t h ibl iti l bl k f i di it l
- 46 -
J . Silva-Martinez
Spring, 2011
Loop Filter Loop Filter
Linearity and Noise are important design considerations Linearity and Noise are important design considerations
Non-linearity in the filter gets reflected at the output of the ADC as distortion
Input referred-noise of the filter is not noise shaped p p
G
m
-C and Active-RC techniques could be used in CT filter implementation
Loop filter is realized as cascade of two second-order stages & a first-order stage
- 47 -
J . Silva-Martinez
First stage has high Q and wide bandwidth to minimize overall input referred noise
Active-RC implementation is chosen due to high linearity requirements
Spring, 2011
System Design Considerations System Design Considerations (contd.) (contd.)
System Stability
Bode plot of the Loop gain is shown Bode plot of the Loop gain is shown
below
System Design Parameters
Signal bandwidth (F ) 25 MHz
H(z)
Loop gain
Signal bandwidth (F
sig
) 25 MHz
Sampling frequency (F
s
) 400 MHz
Oversampling ratio (OSR) 8
f
th
Gain Margin ~ 18.5dB
Order of noise shaping (L) 5
th
Quantizer resolution (N) 3 bits
Supply voltage 1.8V
Phase Margin ~ 145
o
- 48 -
J . Silva-Martinez
Targeted resolution 12 bits
CMOS Technology 0.18m
Spring, 2011
Block Order DC-gain Cut-off frequency Quality factor IM3 SNR
First stage 2 15 5 dB 24 5 MH 7 51 < 72 dB > 72 dB First stage 2 15.5 dB 24.5 MHz 7.51 < -72 dB > 72 dB
Second stage 2 15.5 dB 16.7 MHz 1.54 < -60 dB > 60 dB
Third stage 1 17.7 dB 5.71 MHz - < -50 dB > 50 dB
- 49 -
J . Silva-Martinez
Summing stage 1 25.0 dB > 800MHz - < -60 dB > 60 dB
Complete filter 5 48.5 dB 25.0 MHz - < -72 dB > 72 dB
Spring, 2011
Feedforward FeedforwardArchitecture Architecture
Feed-forward architecture Higher linearity
5
th
order loop filter
3-bit quantizer
Delay compensation
Higher resolution, Wider bandwidth
Higher resolution (SQNR)
Ensure Stability
- 50 -
J . Silva-Martinez
Delay compensation
Time-variant single-bit NRZ DAC
Two-tone background calibration
Ensure Stability
Less sensitive to mismatches in DACs
Process and temperature variations
Spring, 2011
Loop Filter Implementation Loop Filter Implementation
First and second stages are implemented using two-integrator-loop biquadratic filter
- 51 -
J . Silva-Martinez
Spring, 2011
Loop Filter Implementation Loop Filter Implementation
Third stage is implemented using first Third stage is implemented using first- -order lossy integrator stage order lossy integrator stage
Capacitor tuning is implemented to compensate for process Capacitor tuning is implemented to compensate for process--and and- - p g p p p p g p p p
temperature variations of time constants up to temperature variations of time constants up to 30%
- 52 -
J . Silva-Martinez
Capacitor tuning, 30%
First-order integrator
Spring, 2011
Amplifier Implementation Amplifier Implementation
Amplifier needs to satisfy high gain and high bandwidth requirements Amplifier needs to satisfy high gain and high bandwidth requirements
Two Two--stage amplifier with feed stage amplifier with feed--forward compensation (NCFF) is used forward compensation (NCFF) is used g p g p p ( ) p ( )
Dominant pole is not pushed to low frequencies, still improvement in GBW Dominant pole is not pushed to low frequencies, still improvement in GBW
Feed Feed--forward path introduces a LHP zero which helps in frequency compensation forward path introduces a LHP zero which helps in frequency compensation
2 2
IN
OUT
M1 M2
1
1
2 2
M3
A
A
2
(1+ A
1
)
M3
Noise Noise GG
M1 M1
((inband inband) )
Li i Li i GG
F
r
e
q
u
e
n
c
y
A
1
A
2
- 53 -
J . Silva-Martinez
Linearity Linearity GG
M2 M2
Stability Stability GG
M3 M3
Magnitude
p1

p2
Spring, 2011
Amplifier Implementation Amplifier Implementation (contd.) (contd.)
Amplifier schematic level implementation using NCFF architecture Amplifier schematic level implementation using NCFF architecture
Performance parameter Performance parameter Value Value Performance parameter Performance parameter Value Value
DC DC--gain gain 52 dB 52 dB
Gain at 25MHz Gain at 25MHz 44 dB 44 dB
- 54 -
J . Silva-Martinez
Gain bandwidth product Gain bandwidth product 1.5 GHz 1.5 GHz
Input referred integrated noise (in 25 MHz) Input referred integrated noise (in 25 MHz) 19.02 V 19.02 V
Power consumption Power consumption 4.5 mW 4.5 mW
Spring, 2011
Summing Node in CT Summing Node in CT EA EA Modulator Modulator
Performs weighted addition of integrator outputs Performs weighted addition of integrator outputs
Injection of test inputs to perform back ground calibration Injection of test inputs to perform back ground calibration
Separates quiet analog and noisy digital circuitry Separates quiet analog and noisy digital circuitry
Provides a direct path around quantizer to compensate for Provides a direct path around quantizer to compensate for
excess loopdelay due to quantizer andDAC excess loopdelay due to quantizer andDAC excess loop delay due to quantizer and DAC excess loop delay due to quantizer and DAC
- 55 -
J . Silva-Martinez
Spring, 2011
Summing Stage Summing Stage
Quantizer + DAC introduce one cycle delay Quantizer + DAC introduce one cycle delay
Delay introduced by summing is Delay introduced by summing is undesired undesired
Excess loop delay GBW value
T
s
/2 400 MHz
y y g y y g
Digital (early clocks) Digital (early clocks) or Analog compensation? or Analog compensation?
Summing amplifier demands Summing amplifier demands high high bandwidth to bandwidth to
s
T
s
/4 800 MHz
T
s
/6 1.2 GHz
T
s
/8 1.6 GHz
minimize excess loop delay minimize excess loop delay
T
s
/10 2 .0 GHz
- 56 -
J . Silva-Martinez
Spring, 2011
Summing Stage Summing Stage (contd.) (contd.)
A A zero zero--pole pair pole pair is introduced in the feedback which adds negative delay is introduced in the feedback which adds negative delay
Tuning of C Tuning of C
TT
is provided to adjust the delay variations due to process and is provided to adjust the delay variations due to process and Tuning of C Tuning of C
TT
is provided to adjust the delay variations due to process and is provided to adjust the delay variations due to process and
temperature variations temperature variations
- 57 -
J . Silva-Martinez
Spring, 2011
Summing Stage Summing Stage (contd.) (contd.)
Group Group- -delay computed as derivate of phase delay computed as derivate of phase
The delay can be adjusted by tuning the capacitor C The delay can be adjusted by tuning the capacitor C
TT
y j y g p y j y g p
TT
The delay reduces as the size of the tuning capacitor is increased The delay reduces as the size of the tuning capacitor is increased
- 58 -
J . Silva-Martinez
Spring, 2011
Filter Transfer Characteristics Filter Transfer Characteristics
Si l d i d d h f h l fil Simulated magnitude and phase response of the open loop filter
DC gain DC gain 48 dB 48 dB IM3 (at 400mV IM3 (at 400mV
pp pp
)) - -73.5 dB 73.5 dB
Cut Cut--off frequency off frequency 24.5 MHz 24.5 MHz
Input referred integrated Input referred integrated
i i 25MH b d idth i i 25MH b d idth
42.2 V 42.2 V
- 59 -
J . Silva-Martinez
Cut Cut off frequency off frequency 24.5 MHz 24.5 MHz
noise in 25MHz bandwidth noise in 25MHz bandwidth
42.2 V 42.2 V
Power consumption Power consumption 21.3 mW 21.3 mW CMOS Technology CMOS Technology 0.18 m 0.18 m
Total area Total area 0.78 mm 0.78 mm
22
Power supply Power supply 1.8 V 1.8 V
Spring, 2011
Filter Filter (System) simulations (System) simulations
These simulations were obtained using ideal macromodel for other system blocks
SQNR =74dB with 25MHz bandwidth is achieved SQNR 74dB with 25MHz bandwidth is achieved
- 60 -
J . Silva-Martinez
ADC output spectrum from simulation with f
in
= 5.33MHz
Spring, 2011
Chip micrograph of CT LP Chip micrograph of CT LP EA EA ADC ADC
2.082 mm
5
th
order low-pass filter
S i
2
.
6
5
Summing
Multi-phase
DAC
Q ti
25 MHz bandwidth, 12-bit resolution
Active Area 2.66 mm X 2.08 mm
9

m
m
Digital logic
Quantizer
Fabricated in 0.18 m CMOS Technology
Thanks to J azz Semiconductors
Chi h b f ll t t d
VCO
Output
buffers
- 61 -
J . Silva-Martinez
Chip has been successfully tested
Spring, 2011
What about a Gm What about a Gm- -C Filter C Filter
Wide-band OTAs provide good Frequency Response
O l ti t bilit i Open-loop operation, no stability issues
Suitable for high frequency applications
OTAs connected back-to-back emulate a resonator
- 62 -
J . Silva-Martinez
Provide moderate linearity; OTA linearization techniques required
Spring, 2011 In In--band noise @ center frequency band noise @ center frequency
in a Gm in a Gm- -C C Bandpass Bandpass Filter Filter pp
For high Qfilters the total input referred noise power of biquad approximates
- 63 -
J . Silva-Martinez
For high-Q filters, the total input referred-noise power of biquad approximates
Spring, 2011
Nonlinearities in Gm-C Biquadratic Filter
Linearity is measured using two-tone test and expressed
as IM3 (in dB) as IM3 (in dB).
g
m1,1
g
o1,1
g
m3,1
g
o3,1
Nonlinearities arise from
T d t li it f OTA Transconductance nonlinearity of OTA
1
Output impedance nonlinearity of OTA
1
- 64 -
J . Silva-Martinez
Spring, 2011
Nonlinearities in resonator
g
m1,3
g
g
m1,1
g
m3,3
g
o1,1
g
m1,2
g
m3,2
Assuming that OTA
1
is ideal,
The third order nonlinearities produced by two OTAs are out-of-phase by 180
o
Magnitudes of third order harmonics become equal at resonant frequency
- 65 -
J . Silva-Martinez
Spring, 2011
OTA Implementation
Input G
m
-stage
Source degeneration for good linearity Source degeneration for good linearity
Non-linear source degeneration using
auxiliary NMOS differential pair further
improves linearity
Signal swing at the output is small
Output common-mode is fixed by R
D
Output OTA stage
Pseudo differential, better linearity
Nonlinearity due to output impedance is
lowbecause of high voltage head room
- 66 -
J . Silva-Martinez
low because of high voltage head room
Output common-mode is fixed by CMFB
Spring, 2011
Nonlinearities in resonator
Frequency of input tones Separation, f IM3 (V
amp
= 400mV
p-p
)
99.5 MHz, 100.5 MHz 1 MHz -79.7182 dB
99 MHz, 101 MHz 2 MHz -77.3634 dB
98.5 MHz, 101.5 MHz 3 MHz -76.2002 dB
98 MHz, 102 MHz 4 MHz -75.5994 dB
97 5 MH 102 5 MH 5 MH 75 4191 dB 97.5 MHz, 102.5 MHz 5 MHz -75.4191 dB
97 MHz, 103 MHz 6 MHz -75.1771 dB
96.5 MHz, 103.5 MHz 7 MHz -75.1465 dB
96 MHz, 104 MHz 8 MHz -75.1315 dB ,
95.5 MHz, 104.5 MHz 9 MHz -74.8356 dB
95 MHz, 105 MHz 10 MHz -74.7341 dB
90 MHz, 110 MHz 20 MHz -73.2794 dB
At the resonant frequency, harmonic distortion due to third
order nonlinearities in resonator becomes zero
- 67 -
J . Silva-Martinez
Linearity of the biquad depends on the separation between
input frequency tones used in IM3 measurement
Spring, 2011
Simulation Results
Parameter Value
OTA Simulation results Biquadratic filter simulation results
Parameter Value
Quality factor 10
Center frequency 100 MHz
IM3 63 dB @400 V
DC gain 53.96 dB
GBW 104.61 MHz
IM3 76 28 dB @400 V IM3 -63 dB @400mV
p-p
Noise density 18.74nV/Hz @ 100MHz
Integrating capacitor 2.8 pF
IM3 -76.28 dB @400mV
p-p
Noise density 10.68nV/Hz @ 100MHz
Phase Error +0.4
o
Power 28.8 mW
Power supply 1.8 V
Technology 0.18 m CMOS
Power 10.5 mW
Power supply 1.8 V
Technology 0.18 m CMOS gy
The input referred noise density of the biquad is 3times that of the OTA at
o
U f li d ti i th li it (IM3) b 10 dB
gy
- 68 -
J . Silva-Martinez
Use of non-linear source degeneration improves the linearity (IM3) by 10 dB
across process and temperature variations

Sigma Delta 1.2

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Sigma Delta 1.2

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Spring, 2011

FUNDAMENTALS OF FUNDAMENTALS OF SIGMA SIGMA-- FUNDAMENTALS OF FUNDAMENTALS OF SIGMA SIGMA

Most of the blockers and HF noise

Most of the blockers and HF noise

Most of the blockers and HF noise

Most of the blockers and HF noise

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