Simulation Lab Manual

1
PREPARED BY: APPROVED BY:

M.M.UNIVERSITY, SADOPUR (AMBALA) LABORATORY MANUAL
PRACTICAL EXPERIMENT INSTRUCTION SHEET
AIM: To simulate Half wave rectifier.
EXPERIMENT NO. : ECE-321-01 ISSUE DATE :
DEPTT.: ELECTRONICS AND COMMUNICATION ENGINEERING
LABORATORY : SEMESTER: V NO. OF PAGES: 02

AIM: - To simulate Half wave rectifier.
SOFTWARE USED:- OrCAD 9.2/10.6 Capture CIS

THEORY:-
In half wave rectification, either the positive or negative half of the AC wave is passed, while the other half
is blocked. Because only one half of the input waveform reaches the output, it is very inefficient if used for
power transfer. Half-wave rectification can be achieved with a single diode in a one-phase supply, or with
three diodes in a three-phase supply.

SIMULATION DIAGRAM:-

2

SIMULATED WAVEFORMS:-

RESULT: - Half wave rectifier has been simulated.

QUESTION-ANSWER:
Q1. What is rectifier?
ANS. Rectifier is basically a p-n junction diode which converts alternating current into unidirectional
current.

Q2. What is need of rectifier?
ANS. Most of the electronics components are operated with dc voltage. Therefore it is necessary to convert
alternating voltage into dc voltage.

Q3.What is the different type of rectifier?
ANS. There are mainly two types of rectifier,
3

1.Half wave rectifier 2. Full wave rectifier.

Q4.What is half wave rectifier?
ANS. When ac supply is applied at the input of rectifier it will suppress its one half and will give only one
half at output.

Q5. What do you mean by rectifier efficiency?
ANS. The ratio of DC power output to the AC power input is called rectifier efficiency.

Q6. What do you understand by ripple factor?
ANS. Ripple factor is defined as the ratio of the effective value of the AC component of voltage or current to
the average value.

Q7. What is the value of form factor in half wave rectifier?
ANS. It is defind as the ratio of rms value to the average value. The value of form factoe in half wave
rectifier is 1.57.

Q8. What do you mean by full wave rectifier?
ANS. In this type of circuits more than one diode is used. It enables the circuit to process both cycles of the
AC supply. During both the cycles, current flow through the load in the same direction.

Q9. What is Centre- tap rectifier?
ANS. In this type of circuit a transformer with the centre tapped secondary is used. Two diodes work
together in such a way that during the positive half cycle one diode is forward biased and the other is reverse
biased. For negative half cycle the second diode will be forward biased and 1
st
diode is reverse biased.

Q10.What is step- down transformers?
ANS. In step down transformer the number of turns in primary winding is greater than the number of turns in
secondary winding.
4

AIM: Simulation of Full wave center tap rectifier.

AIM: - Simulation of Full wave center tap rectifier.
SOFTWARE USED: - OrCAD 9.2/10.6 Capture CIS

THEORY: -
A full-wave rectifier converts the whole of the input waveform to one of constant polarity (positive or
negative) at its output. Full-wave rectification converts both polarities of the input waveform to DC (direct
current), and is more efficient. However, in a circuit with a non-center tapped transformer, four diodes are
required instead of the one needed for half-wave rectification. Four diodes arranged this way are called a
diode bridge or bridge rectifier:


5

SIMULATED WAVEFORMS:-

RESULT: - Full wave center tap rectifier has been simulated.

QUESTION-ANSWER:
Q1. What is Centre- tap rectifier?
ANS. In this type of circuit a transformer with the centre tapped secondary is used. Two diodes work
together in such a way that during the positive half cycle one diode is forward biased and the other is reverse
biased. For negative half cycle the second diode will be forward biased and 1
st
diode is reverse biased.

Q2.What is step- down transformers?
ANS. In step down transformer the number of turns in primary winding is greater than the number of turns in
secondary winding.
Q3.What is the different type of rectifier?
6


Q4.What is half wave rectifier?
ANS. When ac supply is applied at the input of rectifier it will suppress its one half and will give only one
half at output.


the average value.

Q7. What is the value of form factor in half wave rectifier?
ANS. It is defind as the ratio of rms value to the average value. The value of form factoe in half wave
rectifier is 1.57.


Q9. What is the value of PIV in case of half wave rectifier?
ANS. PIV= V
m

Q10. What is the value of PIV in case of Centre- tap wave rectifier?
ANS. PIV= 2V
m

7


AIM: Simulation of Full wave bridge type rectifier

AIM: - Simulation of Full wave bridge type rectifier
THEORY: -
The method to improve on this is to use every half-cycle of the input voltage instead of every other half-
cycle. The circuit which allows us to do this is called a Full Wave Rectifier.


8

SIMULATED OUTPUT: -

RESULT: - Full wave bridge type rectifier has been simulated successfully.

QUESTION-ANSWER:
Q1. Define Full wave rectifier?
ANS. In both the half cycles current flows through the load in the same direction.

Q2. What is need of rectifier?
ANS. Most of the electronics components are operated with dc voltage. Therefore it is necessary to convert
alternating voltage into dc voltage.

Q3. What is the different type of rectifier?

9



the average value.

Q7. What is the efficiency of FW rectifier?
ANS. Efficiency of full wave rectifier is 81.2%
Q8. Write one feature of Full wave rectifier?
ANS. The current drawn in both the primary & secondary of the supply transformer is Sinusoidal.

Q9. Define Transformer Utilization Factor?
ANS. Transformer Utilization Factor (TUF) is the ratio of d.c power to be delivered to the load to the a.c
rating of the Transformer secondary.

Q10. Write ripple factor for FW rectifier?
ANS. The ripple factor for Full wave rectifier is 0.48.

10

AIM:- To simulate logic gates.

AIM:- To simulate logic gates.
DIAGRAM:-

HI HI HI
HI HI HI HI
HI
HI HI HI
LO LO LO
LO
LO
LO
U4A
7432
1
2
3
U3A
7432
1
2
3
U2A
7432
1
2
3
U1A
7432
1
2
3
11

SIMULATION OUTPUT:-

DIAGRAM:-

Time Time
0s 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms 6.0ms 7.0ms 8.0ms
U1A:A
U1A:B
U1A:Y
U2A:A
U2A:B
U2A:Y
U2A:Y
U3A:A
U3A:B
U3A:B
U3A:Y
U4A:A
U4A:B
U4A:Y
LO
LO
LO
LO
HI
HI
HI HI
HI
U4A
7408
1
2
3
U3A
7408
1
2
3
U2A
7408
1
2
3
U1A
7408
1
2
3
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SIMULATION OUTPUT:-

DIAGRAM:-

Time Time
U1A:A
U1A:B
U1A:Y
U2A:A
U2A:B
U2A:Y
U3A:A
U3A:B
U3A:Y
U4A:A
U4A:B
U4A:Y
HI
HI
HI HI
HI
LO
LO
LO
LO
U4A
7402
2
3
1
U3A
7402
2
3
1
U2A
7402
2
3
1
U1A
7402
2
3
1
13

SIMULATION OUTPUT:-

DIAGRAM:-

SIMULATION OUTPUT:-

Time Time
U1A:A
U1A:B
U2A:A
U2A:B
U2A:Y
U3A:A
U3A:B
U3A:Y
U4A:A
U4A:B
U4A:Y
U1A:Y
HI
LO
U9A
7404
1 2
U8A
7404
1 2
Time Time
U8A:A
U8A:Y
U9A:A
U9A:Y
14

DIAGRAM:-

SIMULATION OUTPUT:-

RESULT: - Logic gates have been simulated successfully.

HI
HI
HI
HI
LO
LO
LO
LO
U11A
7400
1
2
3
U13A
7400
1
2
3
U12A
7400
1
2
3
U14A
7400
1
2
3
Time Time
U11A:A
U11A:B
U11A:Y
U12A:A
U12A:B
U12A:Y
U13A:A
U13A:B
U13A:Y
U14A:A
U14A:B
U14A:Y
15

QUESTION-ANSWER:
Q.1 Define Gates.
Ans. Gates are digital circuit, which perform a specific type of logical operation.

Q.2 Define IC?
Ans. IC means Integrated Circuit It is the integration of no. of components on a common substrate.

Q.3 (A+A) A=?
Ans. A.

Q.4. Define universal gates
Ans. We can design any type of logical expression by using universal gates.

Q.5 Will the output of a NAND Gate be 0.
Ans. When all the inputs are1.

Q.6 Which IC is used for NAND GATE?
Ans. IC 7400.

Q.7 Why NAND is called as universal gate?
Ans. Because all gates can be made using circuits.

Q.8 Name any other universal gate?
Ans. NOR Gate.

Q.9 Which type of TTL gates can drive CMOS Gate?
Ans. TTL with open collector can derive CMOS.

Q.10 What is meant by literal?
Ans. A logical variable in a complemented or Un-complemented form is called a literal

Q11. Give example of Demorgans theorem.
ANS. (AB)=A+B
(A+B)=A.B

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Q 12 (A+A) A =?
ANS. A.

Q 13 Define Universal gates.
ANS. Universal gates are those gates by using which we can design any type of logical expression.

Q 14 Write the logical equation for AND gate.
ANS. Y=A.B

Q 15 How many no. of input variables can a NOT Gate have?
ANS. One.

Q 16 .Under what conditions the output of a two input AND gate is one?
ANS. Both the inputs are one.

Q 17 1+0 =?
ANS. 1

Q 18 .When will the output of a NAND Gate be 0?
ANS. When all the inputs are 1.

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AIM: Simulation of J-K flip-flop.

AIM:- Simulation of J-K flip-flop.
SOFTWARE USED:- OrCAD 9.2/10.6 Capture CIS.
THEORY:-

(a) J-K Flip-Flop.:-
The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are two
outputs Q and Q' (where Q' is the reverse of Q).


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SIMULATED WAVEFORM:-

RESULT: - J-K flip-flop have been simulated successfully.

QUESTION-ANSWER:
Q 1.Flip flop is Astable or Bistable?
Ans. Bistable.

Q2.What are the I/Ps of JK flipflop where this race round condition occurs?
Ans. Both the inputs are 1.

Q3.When RS flip-flop is said to be in a SET state?
Ans. When the output is
19


Q4.When RS flip-flop is said to be in a RESET state?
Ans. When the output is 0.

Q5.What is the truth table of JK flip-flop?
Ans.

Q6.What is the function of clock signal in flip-flop?
Ans. To get the output at known time.

Q7.What is the advantage of JK flip-flop over RS flip-flop?
Ans. In RS flip-flop when both the inputs are 1 output is undetermined.

Q8.In D flip-flop I/P = 0 what is O/P?
Ans.0

Ans.1

Q10.In T flip-flop I/P = 1 what is O/P?
Ans. Qn

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AIM:- Simulation of D Flip-Flop and T Flip-Flop.

AIM:- Simulation of D Flip-Flop and T Flip-Flop.
SOFTWARE USED: - OrCAD 9.2/10.6 Capture CIS.
THEORY:-
(a) D-Flip-Flop:-
The D ip-op is widely used. It is also known as a data or delay flip-flop.The D flip-flop
captures the value of the D-input at a definite portion of the clock cycle (such as the rising
edge of the clock). That captured value becomes the Q output. At other times, the output Q
does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or
a delay line
(b) T-Flip-Flop:-
It is also known as Toggle flip-flop When the clock triggers, the value remembered by the
flip-flop either toggles or remains the same depending on whether the T input (Toggle) is 1 or
0.

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SIMULATED OUTPUT:-

RESULT: - D Flip-Flop and T Flip-Flop have been simulated successfully.

QUESTION-ANSWER:
Ans.0

Ans.1

Ans. Qn

Q4. What is D flip flop?
Ans: D flip flop also called data or delay flip flop it has one data input
D and one clocked input,

Q5. What is T flip flop?
Ans:T flip flop has one input and two outpus Q and inverse of Q

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Ans. To get the output at known time

Q6.Flip flop is Astable or Bistable?
Ans. Bistable.

Q7. What are the I/Ps of JK flipflop where this race round condition occurs?

Ans.1

Q9. In T flip-flop I/P = 1 what is O/P?
Ans. Qn

23

AIM: Simulation of Shift register.

AIM: - Simulation of Shift register.
SOFTWARE USED:- OrCAD 9.2/10.6 Capture CIS
THEORY:-
A shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is
connected to the "data" input of the next flip-flop in the chain, resulting in a circuit that shifts by one position
the "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, at
each transition of the clock input.

24

OUTPUT WAVEFORMS:-

RESULT: - Shift register has been simulated successfully.

QUESTION-ANSWER:
Q.1 Define K-map?
Ans. It is a method of simplifying Boolean Functions in a systematic mathematical way.

Q.2 Define SOP?
Ans. Sum of Product.

Q.3 Define POS ?
Ans. Product of Sum
25

Q.4 What are combinational circuits?
Ans. These are those circuits whose output depends upon the inputs present at that
instant of time.

Q.5 What are sequential circuits?
Ans. These are those circuits whose output depends upon the input present at that time
as well as the previous output.

Q.6 If there are four variables how many cells the K-map will have?
Ans. 16.

Q.6 If there are four variables how many cells the K-map will have?
Ans. 16.

Q.7 When two min-terms can be adjacent?
Ans. 2 to the power n.

Q.8 Which code is used for the identification of cells?
Ans8. Gray Code.

Q.9 Define Byte?
Ans. Byte is a combination of 8 bits.

Q.10 When simplified with Boolean Algebra (x + y)(x + z) simplifies to
Ans. x + yz

26

AIM: To simulate 3x8 decoder

AIM: - To simulate 3x8 decoder.
THEORY:-
A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the
original information can be retrieved. The same method used to encode is usually just reversed in order to
decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2
n

unique output lines.In digital electronics, a decoder can take the form of a multiple-input, multiple-output
logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.
e.g. n-to-2
n
, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise
its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only
when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the
NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is
called as "active low output". A slightly more complex decoder would be the n-to-2
n
type binary decoders.
These type of decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2
n
unique outputs. We say a maximum of 2
n
outputs because in case the 'n' bit coded
information has unused bit combinations, the decoder may have less than 2
n
outputs. We can have 2-to-4
decoder, 3-to-8 decoder or 4-to-16 decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with
enable signals).

27

3x8 decoder
TRUTH TABLE
Input

Output
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0


0
HI
LO
LO
LO
U3
74259
14
13
1
2
3
4
5
6
7
9
10
11
12
1
5
G
D
S0
S1
S2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
L
R
CLK
DSTM1
28

OUTPUT WAVEFORMS:-

Result: Truth table of 3x8 decoder is verified.
QUESTION-ANSWER:
Q. 1 What do you understand by decoder?
Ans. A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. Most IC decoders include one or more enable inputs to control the circuit
operation.

Q. 2 What is demultiplexer?
Ans. The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n address
inputs. It has 2n outputs. The address input determine which data output is going to have the same value as
the data input. The other data outputs will have the value 0.

Q. 3 What do you understand by encoder?
Ans. An encoder or multiplexer is therefore a digital IC that outputs a digital code based on which of its
several digital inputs is enabled.

Q. 4 What is the main difference between decoder and demultiplexer?
Ans. In decoder we have n input lines as in demultiplexer we have n select lines.

Time Time
0s 0.1us 0.2us 0.3us 0.4us 0.5us 0.6us 0.7us 0.8us 0.9us 1.0us 1.1us
U3:Q0
U3:Q1
U3:Q2
U3:Q3
U3:Q4
U3:Q5
U3:Q6
U3:Q7
29

Q. 5 Why Binary is different from Gray code?
Ans. Gray code has a unique property that any two adjacent gray codes differ by only a single bit.

Q. 6 Write down the method of Binary to Gray conversion.
Ans. Using the Ex-Or gates.

Q. 7 Convert 0101 to Decimal.
Ans. 5

Q. 8 Write the full form of ASCII Codes?
Ans. American Standard Code for Information Interchange.

Q.9. If a register containing 0.110011 is logically added to register containing 0.101010 what would be the
result?
Ans.111011

Q10.Binary code is a weighted code or not?
Ans. Yes

30

AIM: To design a RC Coupled Amplifier.

AIM: - To design a RC Coupled Amplifier.
THEORY: -
In RC coupled amplifier, the two transistors are identical and a common power supply is used. The input is
provided to the first stage of the amplifier where it is amplified and this output is used as input for the second
stage. This is amplied once again by the other transistor in the second stage and the final output is obtained.
There will be a 180 degree phase shift after the first stage amplification which is nullified by the 180 degree
phase shift of the second stage amplification. Thus, we obtain an output which is an amplified signal of the
input and is in phase with the input signal.

Simulated Diagram:-

31

Simulated Waveform:-

Result: Simulation result of RC Coupled Amplifier is verified.
QUESTION-ANSWER:
Q1. In RC coupled amplifier which component is responsible for reduction in voltage gain in the high
frequency range?
ANS. Shunt capacitance in the input circuit.

Q2. In RC coupled amplifier which components value is responsible for low 3-Db frequency?
ANS. Increasing the value of coupling capacitor Cb.

Q3. In RC coupled amplifier which components value is responsible for high 3-dB frequency?
ANS. By reducing the total effective shunt capacitance in the input circuit of hybrid pie model.

Q4. In a single stage RC coupled amplifier, what is the phase shift introduced in the true middle frequency?
ANS. 180

Q5. Which type of coupling capacitor is used in RC coupled amplifier?
ANS. 0.05 f paper capacitor.

Q6. What is the application of RC coupled amplifier?
ANS. It is widely used as a voltage amplifier.

Q7. In single stage RC coupled amplifier, what is the phase shift at low 3-dB frequency?
ANS. 225

Q8. In single stage RC coupled amplifier, what is the phase shift at high 3-dB frequency?
ANS. 135
32

Q9. In RC coupled amplifier what is the effect of low 3-dB frequency by increasing the value of coupling
capacitor C
b
?
ANS. Decreasing.

Q10. In RC coupled amplifier what is the effect of low 3-dB frequency by increasing the value of total
effective shunt capacitor?
ANS. Decreasing.

33

AIM: Simulation of S-R flip-flop.

AIM:- Simulation of J-K flip-flop.
SOFTWARE USED:- OrCAD 9.2/10.6 Capture CIS.
THEORY:-

(a) S-R Flip-Flop:-
This type of flip-flop has two inputs: Set and Reset. Two outputs: Q and Q' (Q' being the inverse of
Q). The SR flip-flop can also have a clock input for a level driven circuit as opposed to a pulse
driven circuit.


34

SIMULATED WAVEFORM:-

Result: - S-R flip-flop have been simulated successfully.

QUESTION-ANSWER:
Q 1.Flip flop is Astable or Bistable?
Ans. Bistable.

Q2.What are the I/Ps of JK flipflop where this race round condition occurs?

Q3.When RS flip-flop is said to be in a SET state?
Ans. When the output is

35


Q4.When RS flip-flop is said to be in a RESET state?
Ans. When the output is 0.

Q5.What is the truth table of JK flip-flop?
Ans.

Ans. To get the output at known time.

Q7.What is the advantage of JK flip-flop over RS flip-flop?
Ans. In RS flip-flop when both the inputs are 1 output is undetermined.

Ans.0

Ans.1

Ans. Qn

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