IEEE Verilog Coding Rules

3/28/14 1 IEEE Verilog Coding Rules
1/38 https://computing.ece.vt.edu/~athanas/4514/ledadoc/html/pol_ieee_verilog.html
1
IEEE Verilog Coding Rules
Introduction
This chapter provides detailed reference information for the Verilog
IEEE_RTL_SYNTH_SUBSET policy for the Leda Checker tool. This policy
contains the rules defining the most common synthesis subsets for
Register Transfer Level (RTL) synthesis. They are based on industrial
subsets and on the rules featured in the following document:
IEEE P1364.1 "Draft Standard for Verilog Register Transfer Level
Synthesis"
The rules are grouped into rulesets. Each ruleset imposes constraints
on the elements of the language for a given chapter of the Verilog
Language Reference Manual (LRM) and is derived from the
corresponding subsection in the IEEE P1364.1 draft document. Table 2
provides an overview of the different IEEE_RTL_SYNTH_SUBSET policy
rulesets for Verilog.
Table2:IEEE_VERILOGPolicyRulesets
Ruleset Descriptions
"Data Types
Ruleset"
This is a set of rules implementing the constraints
imposed by synthesis on elements of Chapter 3 of
the Verilog LRM.
"Expressions
Ruleset"
the Verilog LRM.
"Assignments
Ruleset" the Verilog LRM.
"Gate and Switch
Level Modeling
Ruleset"
the Verilog LRM.
"User Defined
Primitives
Ruleset"
the Verilog LRM.
"Behavioral
Modeling
Ruleset"
the Verilog LRM.
"Tasks and
Functions
Ruleset"
the Verilog LRM.
"Hierarchical
Structures
Ruleset"
the Verilog LRM.
"Specify Blocks
Ruleset"
the Verilog LRM.
"System Tasks
and Functions
Ruleset"
the Verilog LRM.
Data Types Ruleset
The following rules are from the data types ruleset:
SYN3_2_1_B
Message: trireg nets are not supported for synthesis
Description None
Policy IEEE_RTL_SYNTH_SUBSET
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_2
Message: Drive strengths in net declaration are
ignored
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_3
Message: Charge strengths in net declaration are
ignored
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_4
Message: Delays in net declaration are ignored
Description None
Ruleset DATA_TYPES
Language Verilog
Language Verilog
Type Block-level
Severity Warning
SYN3_2_5
Message: Delays (delay2) in net declaration are
ignored
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_6
Message: Delays (delay3) in net declaration are
ignored
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Warning
SYN3_2_7
Message: tri1 nets are not supported for synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_8
Message: triand nets are not supported for synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_9
Message: tri0 nets are not supported for synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_2_10
Message: trior nets are not supported for synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_9_1
Message: time declarations are not supported for
synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_9_2
Message: real declarations are not supported for
synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
SYN3_9_3
Message: realtime declarations are not supported for
synthesis
Description None
Ruleset DATA_TYPES
Language Verilog
Type Block-level
Severity Error
Expressions Ruleset
The following rules are from the expressions ruleset:
SYN4_1_1_B
Message: Expressions of type mintypmax are ignored
Description None
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Warning
SYN4_1_2
Message: The case equality operator '===' is not
supported in binary operations
Description None
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
SYN4_1_3
Message: The case inequality operator '!==' is not
supported in binary operations
Description None
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
SYN4_1_4
Message: Real numbers are not supported for
synthesis
Description This rule tests that real literals are not used.
Ruleset EXPRESSIONS
Language Verilog
Type Block-level
Severity Error
Assignments Ruleset
The following rules are from the assignments ruleset:
SYN6_1_1
Message: Do not use assignment in net declaration
Description None
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Error
SYN6_1_2
Message: Drive strengths in continuous assign
statements are ignored
Description None
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
SYN6_1_3
Message: Delay3 values in continuous assign
Description None
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
SYN6_1_4
Message: Delay2 values in continuous assign
Description None
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
SYN6_1_5
Message: Delay values in continuous assign
Description None
Ruleset ASSIGNMENTS
Language Verilog
Type Block-level
Severity Warning
Gate and Switch Level Modeling Ruleset
The following rules are from the gate and switch level modeling ruleset:
SYN7_1_1
Message: nmos switch instantiations are not
supported for synthesis
Description None
Ruleset GATE_AND_SWITCH_LEVEL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN7_1_2
Message: pmos switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_3
Message: rnmos switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_4
Message: rpmos switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_5
Message: tran switch instantiations are not supported
for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_6
Message: rtran switch instantiations are not supported
for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_7
Message: tranif0 switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_8
Message: tranif1 switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_9
Message: rtranif0 switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_10
Message: rtranif switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_11
Message: cmos switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_12
Message: rcmos switch instantiations are not
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_13
Message: pull (pullup and pulldown) gate
instantiations are not supported for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN7_1_14
Message: Drive strengths in n input gate
instantiations are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_15
Message: Drive strengths in n output gate
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_16
Message: Drive strengths in enable gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_17
Message: Delay2 values in n input gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_18
Message: Delay values in n input gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_19
Message: Delay2 values in n output gate
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_20
Message: Delay values in n_output gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_21
Message: Delay3 values in enable gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN7_1_22
Message: Delay2 values in enable gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
Severity Warning
SYN7_1_23
Message: Delay values in enable gate instantiations
are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
User Defined Primitives Ruleset
The following rules are from the user defined primitives ruleset:
SYN8_1_1_B
Message: UDP declarations are not supported for
synthesis
Description
User-defined primitive declarations are not supported for
synthesis.
Ruleset USER_DEFINED_PRIMITIVES
Language Verilog
Type Block-level
Severity Error
SYN8_6_1_A
Message: UDP instantiations are not supported for
synthesis
Description
User-defined primitive declaration instantiations are not
supported for synthesis.
Ruleset USER_DEFINED_PRIMITIVES
Language Verilog
Type Block-level
Severity Error
Behavioral Modeling Ruleset
The following rules are from the behavioral modeling ruleset:
SYN9_1
Message: Illegal always construct: Does not model any
combinational logic or sequential logic
Description
Combinational logic is modeled by an always statement if
its event list does not contain any edge event (posedge
or negedge). Sequential logic is modeled if the always
statement has one or more edge events in the event list
(that is, @(posedge clock)). One of the edge events
specified must represent the clock edge condition under
which the storage device stores the value (see Section 5
in IEEE P1364.1 /D1.4 Draft Standard for Verilog RTL). For
example:
always@(posedgeCLOCK)
if(RESET)//RESETmodelstheresetsignalof
//thestoragedevice
OUT=1'b0
else
OUT=1'b1
Ruleset BEHAVIORAL_MODELING
Language Verilog
Type Block-level
Severity Error
SYN9_2
Message: Missing or redundant signal in the
sensitivity list of an always block
Description
All the variables read in the always statement must be
included in the sensitivity list to avoid mismatches
between simulation and synthesized logic.Note:
unnecessary signals in the sensitivity list are also
detected.When modeling combinational logic and latches,
all the signals read in the always block must be in the
sensitivity list. All other signals must not be present in
the sensitivity list.When modeling sequential logic (flip-
flops) only the clock and asynchronous set-reset signals
must be in the sensitivity list.
Language Verilog
Type Block-level
Severity Error
SYN9_3
Message: Do not mix blocking and non-blocking
assignments in a combinational always block
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_4
Message: Do not use blocking assignments for
variables modeling level-sensitive storage devices
(latches)
Description Prevents race conditions in Verilog simulations.
Language Verilog
Type Block-level
Severity Error
SYN9_5
Message: A level-sensitive storage device (latch) may
be inferred for this variable
Description
This rule is intended to make sure that latch inferring
was not done accidentally. This rule only checks at the
module level. There is a similar rule in the Leda general
coding guidelines policy that you can use to check the
entire design.
Language Verilog
Type Block-level
Severity Warning
SYN9_6
Message: A sequential always block must have one
clock signal exactly
Description
When modeling edge-sensitive storage devices, the
following rules apply:
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
Language Verilog
Type Block-level
Severity Error
SYN9_7
Message: Do not use blocking assignments in
sequential always blocks
Description
Non-blocking assignments are recommended to avoid
race conditions in Verilog simulations. When modeling
edge-sensitive storage devices, the following rules apply:
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
This rule is flagged for unintentional latches also.
Language Verilog
Type Block-level
Severity Error
SYN9_8
Message: Only one edge event should be present in
the event list of a synchronous always block
Description
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
Language Verilog
Type Block-level
Severity Error
SYN9_9
Message: A clock expression should be of the form
'posedge <clock_name>'
Description
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
When modeling edge-sensitive storage devices with
asynchronous set-reset, the following rules apply:
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_10
Message: A falling-edge clock expression should be of
the form 'negedge <clock_name>'
Description
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_11
Message: Multiple event lists in an always statement
are not supported for synthesis
Description
SYN9_6
SYN9_7
SYN9_8
SYN9_9
SYN9_10
SYN9_11
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_12
Message: Polarity mismatch for asynchronous
reset/set/load <%context> : use 'if(<%context>)'
Description
If a variable modeling asynchronous reset/set/load has a
posedge event, then it should have positive polarity in
the corresponding if condition.When modeling edge-
sensitive storage devices with asynchronous
reset/set/load, the following rules apply:
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_13
Message: Polarity mismatch for asynchronous
reset/set/load <%context> : use 'if(!<%context>)',
'if(~<%context>' or 'if(<%context> == 1'b0)'
Description
If a variable modeling asynchronous reset/set/load has a
negedge event, then it should have negative polarity in
the corresponding if condition. When modeling edge-
sensitive storage devices with asynchronous
reset/set/load, the following rules apply:
SYN9_9
Description SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_14
Message: Level sensitive events are not allowed in a
sequential always block
Description
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_15
Message: An asynchronous sequential always block
must have one clock signal exactly
Description
SYN9_9
SYN9_10
SYN9_11
SYN9_12
SYN9_13
SYN9_14
SYN9_15
Language Verilog
Type Block-level
Severity Error
SYN9_16
Message: Initial constructs are ignored
Description None
Language Verilog
Type Block-level
Severity Warning
SYN9_17
Message: Procedural continuous assign statements are
not supported for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_18
Message: Procedural continuous deassign statements
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_19
Message: Procedural continuous force statements are
Description None
Language Verilog
Type Block-level
Severity Error
Severity Error
SYN9_20
Message: Procedural continuous release statements
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_21
Message: Repeat event controls in timing control
statements are not supported for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_22
Message: Delay values are ignored in synthesis
Description This rule tests delay values in assignment statements.
Language Verilog
Type Block-level
Severity Warning
SYN9_23
Message: Forever loop statements are not supported
for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_24
Message: Repeat loop statements are not supported
for synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_25
Message: While loop statements are not supported for
synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_26
Message: Expression bound in for loop statements
should be statically computable
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_27
Message: Initial reg assignment bound in for loop
statements should be statically computable
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_28
Message: Wait statements are not supported for
synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_29
Message: Event triggers are not supported for
synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_30
Message: Fork-join blocks are not supported for
synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_31
Message: Event declarations are not supported for
synthesis
Description None
Language Verilog
Type Block-level
Severity Error
SYN9_32
Message: The always statement must be followed by
an event control (@)
Description None
Language Verilog
Type Block-level
Severity Error
Tasks and Functions Ruleset
The following rules are from the tasks and functions ruleset:
SYN10_1
Message: Writing to global variables in functions is
Description
Use of variables (both reading the value of and writing a
value to) that are defined outside a function declaration
but not within the enclosing module declaration is not
supported. The Checker reports an error if a variable is
assigned a value in a function and defined elsewhere.
Ruleset TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error
SYN10_2
Message: Writing to global variables in tasks is not
Description
Use of variables (both reading the value of and writing a
value to) that are defined outside a task declaration but
not within the enclosing module declaration is not
supported. The Checker reports an error if a variable is
assigned a value in a task and defined elsewhere.
Ruleset TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error
Hierarchical Structures Ruleset
The following rules are from the hierarchical structures ruleset:
SYN12_1
Message: Macromodules are not supported for
synthesis
Description None
Ruleset HIERARCHICAL_STRUCTURES
Language Verilog
Type Block-level
Severity Error
SYN12_2
Message: Input ports must not be assigned a value
Description None
Ruleset HIERARCHICAL_STRUCTURES
Language Verilog
Type Block-level
Severity Error
Specify Blocks Ruleset
The following rule is from the specify blocks ruleset:
SYN13_1
Message: Specify blocks are ignored
Description None
Ruleset SPECIFY_BLOCKS
Language Verilog
Type Block-level
Severity Warning
System Tasks and Functions Ruleset
The following rules are from the system tasks and functions ruleset:
SYN14_1
Message: System task enables are ignored
Description None
Ruleset SYSTEM_TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Warning
SYN14_2
Message: System function calls are not supported for
synthesis
Description None
Ruleset SYSTEM_TASKS_AND_FUNCTIONS
Language Verilog
Type Block-level
Severity Error

IEEE Verilog Coding Rules

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3/28/14 1 IEEE Verilog Coding Rules

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