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VLSI FAQ

1. What is Intrinsic and Extrinsic Semiconductor?


The pure Silicon is known as Intrinsic Semiconductor.
When impurity is added with pure Silicon, its electrical properties are varied. This is known as
Extrinsic Semiconductor.
2. What is CMOS Technology?
The fabrication of an IC using CMOS transistors is known as CMOS Technology. CMOS
transistor is nothing but an inverter, made up of an n-MOS and p-MOS transistor connected in
series.
3. Give the advantages of CMOS IC?
Size is less
High Speed
Less Power Dissipation
4. What are four generations of Integration Circuits?
SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale Integration)
5. Give the variety of Integrated Circuits?
More Specialized Circuits
Application Specific Integrated Circuits (ASICs)
Systems-On-Chips
6. Why NMOS technology is preferred more than PMOS technology?
N-channel transistors have greater switching speed when compared to PMOS transistors.
Hence, NMOS is preferred than PMOS.
7. What are the different MOS layers?
n-diffusion
p-diffusion
Polysilicon
Metal

8. What are the different layers in MOS transistor?
The layers are Substrate, diffused Drain & Source, Insulator (SiO2) & Gate.

9. What are the different operating regions for an MOS transistor?
Cutoff Region
Non- Saturated (Linear) Region
Saturated Region
10. What is Enhancement mode transistor?
The device that is normally cut-off with zero gate bias is called Enhancement mode transistor.
11. What is Depletion mode device?
The Device that conducts with zero gate bias is called Depletion mode device.
12. When the channel is said to be pinched off?
If a large Vds is applied, this voltage will deplete the inversion layer. This Voltage effectively
pinches off the channel near the drain.
13. What are the steps involved in manufacturing of IC?
Silicon wafer Preparation
Epitaxial Growth
Oxidation
Photo-lithography
Diffusion
Ion Implantation
Isolation technique
Metallization
Assembly processing & Packaging
14. What is meant by Epitaxy?
Epitaxy means arranging atoms in single crystal fashion upon a single crystal substrate.
15. What are the processes involved in photo lithography?
(1) Masking process (2) Photo etching process.
These are important processes involved in photolithography.
16. What is the purpose of masking in fabrication of IC?
Masking is used to identify the location in which Ion-Implantation should not take place.
17. What lire the materials used for masking?
Photo resist, Si02, SiN, Poly Silicon.
18. What are the types of Photo etching?
Wet etching and dry etching are the types of photo etching.
19. What is diffusion process? What are doping impurities?
Diffusion is a process in which impurities are diffused into the Silicon chip at C
temperature. B203 and P205 are used as impurities used.
20. What is Ion-Implantation process?
It is process in which the Si material is doped with an impurity by making the accelerated
impurity atoms to strike the Si layer at high temperature.
21. What are the various Silicon wafer Preparation?
Crystal growth & doping
Ingot trimming & grinding
Ingot slicing
Wafer polishing & etching
Wafer cleaning.
22. What are the different types of oxidation?
The two types of oxidation are Dry & Wet Oxidation.
23. What is Isolation?
It is a process used to provide electrical isolation between different components and
interconnections.
24. Give the different types of CMOS process?
p-well process
n-well process
twin-tub process
SOI process
25. What is Channel-stop Implantation?
In n-well fabrication, n-well is protected with the resist material. (Because, it should not be
affected during Boron implantation). Then Boron is implanted except n-well. The above said
process is done using photo resist mask. This type of implantation is known as Channel-stop
implantation.
26. What is LOCOS?
LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
27. What is SWAMI?
SWAMI means Side Wall Masked Isolation. It is used to reduce bird's beak effect.
28. What is LDD?
LDD means Lightly Doped Drain Structures. It is used for implantation of n- region in n-well
process.
29. What is Twin-tub process? Why it is called so?
Twin-tub process is one of the CMOS technologies. Two wells (the other name for well is Tub)
are created in this process. So, because of these two tubs, this process is known as Twin-tub
process.
30. What are the steps involved in twin-tub process?
Tub Formation
Thin-oxide Construction
Source & Drain Implantation
Contact cut definition
Metallization.
31. What are the special features of Twin-tub process?
In Twin-tub process, Threshold voltage, body effects of n and p devices are independently
optimized.
32. What are the advantages of Twin-tub process?
Advantages of Twin-tub process are (1) Separate optimized wells are available. (2) Balanced
performance is obtained for n and p transistors.
33. What is SOI? What is the material used as Insulator?
SOI means Silicon-on-Insulator. In this process, a Silicon based transistor is built on an
insulating material like Sapphire or SiO
2
.
34. What are the advantages and disadvantages of SOI process?
Advantages of SOI process: 1. There is no well formation in this process. 2. There is no field-
Inversion problem. 3. There is no body effect problem.
Disadvantages of SOI process: 1. It is very difficult to protect inputs in this process. 2. Device
gain is low. 3. The coupling capacitance between wires always exists.
35. What are the advantages of CMOS process?
Low Input Impedance
Low delay Sensitivity to load.
36. What are the various etching processes used in SOI process?
Various etching processes used in SOI are,

(A. FULLY ANISTROPHIC ETCHING)

(B. PREFERENTIAL ETCHING)


(C. ISOTROPHIC ETCHING)

37. What is BiCMOS Technology?
It is the combination of Bipolar technology & CMOS technology.
38. What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
N Collector area
Buried Sub collector (SCCD)
Processing steps in CMOS process
39. What is meant by interconnect? What are the types are of interconnect?
Interconnect means connection between various components in an IC.
Types of Inter connect: 1. Metal Inter connect 2. PolySilicon Inter connect 3. Local Inter connect.
40. What is Silicide?
The combination of Silicon and tantaleum is known as Silicide. It is used as gate material in
Polysilicon Interconnect.
41. What is Polycide?
The combination of Silicide and Polysilicon is known as Polycide. It is used as gate material.
42. What is Stick diagram?
The diagram which conveys the layer information through the use of various colours is known
as Stick diagram. It is also the cartoon of a chip layout.
43. What are the uses of Stick diagram?
It can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large cells.
44. Give the various color coding used in stick diagram?
Green - n-diffusion
Red - polysilicon
Blue - metal
Yellow - implant
Black - contact areas.
45. Compare between CMOS and bipolar technologies.

CMOS Technology Bi-polar Technology
Low static power dissipation
High input impedance (low drive current)
Scalable threshold voltage
High noise margin
High packing density
High delay sensitivity to load (fanout limitations)
Low output drive current
Low gm (gm Vin)
Bidirectional capability
A near ideal switching device
High power dissipation
Low input impedance (high drive current)
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
High gm (gm a eVin)
High ft at low current
Essentially unidirectional
46. Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between
the gate and the source of the MOS transistor below which the drain to source current, IDS
effectively drops to zero.
47. What is Body effect?
The threshold voltage VTh is not a constant with respect to the voltage difference between the
substrate and the source of MOS transistor. This effect is called substrate-bias effect or body
effect.
48. What is Channel-length modulation?
The current between drain and source terminals is constant and independent of the applied
voltage over the terminals. This is not entirely correct. The effective length of the conductive
channel is actually modulated by the applied VDS , increasing VDS causes the depletion region
at the drain junction to grow, reducing the length of the effective channel.
49. What is Latch up?
Latch-up is a condition in which the parasitic components give rise to the establishment of low
resistance conducting paths between VDD and VSS with disastrous results. Careful control
during fabrication is necessary to avoid this problem.
50. What is demarcation line?
Demarcation line is an imaginary line used in stick diagram, to separate p-MOS and n-MOS
transistors.
All p-MOS transistors are placed above demarcation line and n-MOS below the demarcation
line

51. What are the two types of Layout design rules?
Lambda design rules and micron rules are major types of layout design rules.
52. What is Lay-out design rule?
The rules followed to prepare the photo mask are known as Layout design rules.
53. What are LVS and DRL tools?
LVS means Layout Versus Schematic. It checks layout against schematic diagram. It is very
important to verify layout.
DRC means Design Rule Checker. This tool checks every occurrence of design rule list on
layout. Width, spacing of every metal line in layout are checked with this tool.
54. What is instance? What is instancing?
To construct big complex circuit, the basic cells (small cells) can be copied. This process is
known as Instancing. The cell which is copied is known as Instance.
55. What is flat cell?
The cell which is independent and not related to other objects is known as flat cell.
56. What are the cells available in primitive library?

NOT, NAND, NOR, are the basic cells in primitive library.
57. What is Design Hierarchy?
When we want to design AND-4 input gate, we use NAND-2 and NOR-2 basic blocks. By
combining NAND-2 and NOR-2, we create AND-4 input gate. This is known as Design
Hierarchy.

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