You are on page 1of 95

13.

CAN Bus, an Efficient Approach for Monitoring and


Controlling Manufacturing Processes in Industries - (ieee!1!"


A#stract$

This paper shows a simple and effective approach to the design and implementation of
automated Industrial manufacturing Systems oriented to control the characteristics of each
individual product manufactured in a production line and also their manufacturing conditions.
The particular products considered in this work are steel sheets that undergo the galvanizing
processes. However, the approach can be modified to be applicable in other industries, like
paper, textile, aluminum, etc. The system makes use of sensor nodes placed at different places to
monitor and control various parameters of interest to guarantee and improve the uality of the
products manufactured in many industries. The proposed system uses !"# bus to send and
receive the data from the nodes to the central controller which provides many advantages over
the currently used distributed control system.
!"# $!ontroller "rea #etwork% was originally designed for robust use in
communicating among different control systems of a vehicle. It works efficiently in the noisy
and continuously moving circumstances in a vehicle. The robustness of this communication can
also be efficient for industries. In industries the sensors are essential components of closed&loop
control systems. They are used in all industries for different types of applications from
monitoring a machine tool in a manufacturing plant to control of a process in a chemical plant.
Traditionally, using sensors meant that long cables were needed to connect each sensor back to a
centralized monitoring or control station. 'ach cable may have contained multiple wires for both
power and sensor data. (hen working with a small number of sensors, this may not seem like a
daunting task to wire, but consider the number of sensors in some practical applications. )or
example, dozens of sensors may be used to monitor various thermal parameters in a
manufacturing facility* thousands of sensors monitor the heat shield tiles on the Space Shuttle*
tens of thousands of sensors monitor current naval vessel+s condition and performance. The
system can monitor different uantities like temperatures, speed, torue, pressure with the help
of set of hundreds of sensor nodes at distributed locations to sense different physical uantities
and send the data to a centralized place to monitor the processes going on. !urrently distributed

BLOCK DIAGRAM
1





C%AP&E'-1
IN&'()*C&I(N
!ontroller "rea #etwork $!"#% was initially created by ,erman automotive system supplier
-obert .osch in the mid&/012s for automotive applications as a method for enabling robust
serial communication. The goal was to make automobiles more reliable, safe and fuel&
efficient while decreasing wiring harness weight and complexity. Since its inception, the
!"# protocol has gained widespread popularity in industrial automation and
automotive3truck applications. 4ther markets where networked solutions can bring attractive
benefits like medical euipment, test euipment and mobile machines are also starting to
utilize the benefits of !"#. The goal of this application note is to explain some of the basics
2
ATMEGA32
Sensor-1
+1, -C)
Sensor-2
CAN
Control
CAN
Drive
Micro
controller
CAN
Drive
CAN
Control
2x1 LCD
of !"# and show the benefits of choosing !"# for embedded systems networked
applications.
The !ontroller "rea #etwork $the !"# bus% is a serial communications bus for real&time
control applications* operates at data rates of up to / 5egabits per second, and has excellent
error detection and confinement capabilities. !"# was originally developed by the ,erman
company, -obert .osch, for use in cars, to provide a cost&effective communications bus for
in&car electronics and as alternative to expensive, cumbersome and unreliable wiring looms
and connectors. The car industry continues to use !"# for an increasing number of
applications, but because of its proven reliability and robustness, !"# is now also being used
in many other control applications.
!"# is an international standard and is documented in IS4 //101 $for high&speed
applications% and IS4 //6/0 $for lower&speed applications%.
In this application !"# uses multiple transmitter nodes to acuire data from sensors and
transmit the data in packets over a !"# bus. 'ach transmitter consists of an "T 5ega78
micro controller. The !"# packets are received by a single receiver node and display
messages on the ,9!: display unit.
3
C%AP&E'-
P(.E' /*PP-0
"n "! powered linear power supply usually uses a transformer to convert the voltage from
the wall outlet $mains% to a different, usually a lower voltage. If it is used to produce :!, a
rectifier is used. " capacitor is used to smooth the pulsating current from the rectifier. Some
small periodic deviations from smooth direct current will remain, which is known as ripple.
These pulsations occur at a freuency related to the "! power freuency $for example, a
multiple of 62 or ;2 Hz%.
The voltage produced by an unregulated power supply will vary depending on the load and
on variations in the "! supply voltage. )or critical electronics applications a linear regulator
will be used to stabilize and ad<ust the voltage. This regulator will also greatly reduce the
ripple and noise in the output direct current. 9inear regulators often provide current limiting,
protecting the power supply and attached circuit from overcurrent.
"d<ustable linear power supplies are common laboratory and service shop test euipment,
allowing the output voltage to be set over a wide range. )or example, a bench power supply
used by circuit designers may be ad<ustable up to 72 volts and up to 6 amperes output. Some
can be driven by an external signal, for example, for applications reuiring a pulsed output.
The simplest :! power supply circuit consists of a single diode and resistor in series with the
"! supply. This circuit is common in rechargeable flashlights.
The power supply we get from the supply is 872= "! supply. .ut here we need 6=3/8= :!
power supply.So we have to convert it to 6= :! supply.)or this purpose we use step down
transformer,rectifier,regulator and filter circuits.The step down transformer here we are using
is 872=&/8= which is operated at 62Hz. "nd the rectifier we are using is full wave bridge
rectifier by using /#>22? diodes.The regulator we are using is ?1263?1/8. )or the filtering
purpose we are using capacitor as a filter.
4
5
C%AP&E'-3
A1' MIC'(C(N&'(--E'
3.1(1'1IE.
The "Tmega78 is a low&power !54S 1&bit microcontroller based on the "=- enhanced
-IS! architecture. .y executing powerful instructions in a single clock cycle, the "Tmega78
achieves throughputs approaching / 5I@S per 5Hz allowing the system designer to optimize
power consumption versus processing speed.
3.2eatures
High&performance, 9ow&power "=-A 1&bit 5icrocontroller
"dvanced -IS! "rchitecture
/7/ @owerful Instructions B 5ost Single&clock !ycle 'xecution
78 x 1 ,eneral @urpose (orking -egisters
)ully Static 4peration
Cp to /; 5I@S Throughput at /; 5Hz
4n&chip 8&cycle 5ultiplier
High 'ndurance #on&volatile 5emory segments
78D .ytes of In&System Self&programmable )lash program memory
/28> .ytes ''@-45
8D .yte Internal S-"5
(rite3'rase !yclesE /2,222 )lash3/22,222 ''@-45
:ata retentionE 82 years at 16F!3/22 years at 86F!$/%
4ptional .oot !ode Section with Independent 9ock .its In&System
@rogramming by 4n&chip .oot @rogram True -ead&(hile&(rite
4peration
@rogramming 9ock for Software Security
GT", $I''' std. //>0./ !ompliant% Interface
.oundary&scan !apabilities "ccording to the GT", Standard
'xtensive 4n&chip :ebug Support
6
@rogramming of )lash, ''@-45, )uses, and 9ock .its through the
GT", Interface
@eripheral )eatures
Two 1&bit Timer3!ounters with Separate @rescalers and !ompare
5odes
4ne /;&bit Timer3!ounter with Separate @rescaler, !ompare 5ode,
and !apture 5ode
-eal Time !ounter with Separate 4scillator
)our @(5 !hannels
1&channel, /2&bit ":! 1 Single&ended !hannels ? :ifferential
!hannels in TH)@ @ackage 4nly 8 :ifferential !hannels with
@rogrammable ,ain at /x, /2x, or 822x
.yte&oriented Two&wire Serial Interface
@rogrammable Serial CS"-T
5aster3Slave S@I Serial Interface
@rogrammable (atchdog Timer with Separate 4n&chip 4scillator
4n&chip "nalog !omparator
Special 5icrocontroller )eatures
@ower&on -eset and @rogrammable .rown&out :etection
Internal !alibrated -! 4scillator
'xternal and Internal Interrupt Sources
Six Sleep 5odesE Idle, ":! #oise -eduction, @ower&save, @ower&
down, Standby and 'xtended Standby
I34 and @ackages
78 @rogrammable I34 9ines
>2&pin @:I@, >>&lead TH)@, and >>&pad H)#359)
4perating =oltages
8.? & 6.6= for "Tmega789
>.6 & 6.6= for "Tmega78
Speed ,rades
2 & 1 5Hz for "Tmega789
7
2 & /; 5Hz for "Tmega78
@ower !onsumption at / 5Hz, 7=, 86F! for "Tmega789
"ctiveE /./ m"
Idle 5odeE 2.76 m"
@ower&down 5odeE I / J"
3.3Pin Configurations
Pin )escriptions
1CC :igital supply voltage.
3N) ,round.
Port A (PA4..PA!" @ort " serves as the analog inputs to the "3: !onverter.@ort " also
serves as an 1&bit bi&directional I34 port, if the "3: !onverter is not used. @ort pins can
provide internal pull&up resistors $selected for each bit%. The @ort " output buffers have
symmetrical drive characteristics with both high sink and source capability. (hen pins @"2
to @"? are used as inputs and are externally pulled low, they will source current if the
internal pull&up resistors are activated. The @ort " pins are tri&stated when a reset condition
becomes active,even if the clock is not running.
Port B (PB4..PB!" @ort . is an 1&bit bi&directional I34 port with internal pull&up resistors
$selected for each bit%. The @ort . output buffers have symmetrical drive characteristics with
both high sink and source capability. "s inputs, @ort . pins that are externally pulled low will
8
source current if the pull&up resistors are activated. The @ort . pins are tri&stated when a reset
condition becomes active,even if the clock is not running.
Port C (PC4..PC!" @ort ! is an 1&bit bi&directional I34 port with internal pull&up resistors
$selected for each bit%. The @ort ! output buffers have symmetrical drive characteristics with
both high sink and source capability. "s inputs, @ort ! pins that are externally pulled low will
source current if the pull&up resistors are activated. The @ort ! pins are tri&stated when a reset
condition becomes active,even if the clock is not running. If the GT", interface is enabled,
the pull&up resistors on pins @!6$T:I%, @!7$T5S% and @!8$T!D% will be activated even if a
reset occurs.
The T:2 pin is tri&stated unless T"@ states that shift out data are entered. @ort ! also serves
the functions of the GT", interface and other special features of the "Tmega78.
Port ) (P)4..P)!" @ort : is an 1&bit bi&directional I34 port with internal pull&up resistors
$selected for each bit%. The @ort : output buffers have symmetrical drive characteristics with
both high sink and source capability. "s inputs, @ort : pins that are externally pulled low will
source current if the pull&up resistors are activated. The @ort : pins are tri&stated when a reset
condition becomes active,even if the clock is not running.
'E/E& -eset Input. " low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running.
5&A-1 Input to the inverting 4scillator amplifier and input to the internal clock operating
circuit.
5&A- 4utput from the inverting 4scillator amplifier.
A1CC "=!! is the supply voltage pin for @ort " and the "3: !onverter. It should be
externally connected to =!!, even if the ":! is not used. If the ":! is used, it should be
connected to =!! through a low&pass filter.
A'E2 "-') is the analog reference pin for the "3: !onverter.
3.6MC* Control 'egister 7 MC*C'
The 5!C !ontrol -egister contains control bits for power management.
K Bit 4 7 /E$ /leep Ena#le
9
The S' bit must be written to logic one to make the 5!C enter the sleep mode when the
S9''@ instruction is executed. To avoid the 5!C entering the sleep mode unless it is the
programmers purpose, it is recommended to write the Sleep 'nable $S'% bit to one <ust before
the execution of the S9''@ instruction and to clear it immediately after waking up.
K .its ;...> B S58..2E Sleep 5ode Select .its 8, /, and 2 .These bits select between the six
available sleep modes as shown in below Table .
Idle Mode
(hen the S58..2 bits are written to 222, the S9''@ instruction makes the 5!C enter Idle
mode, stopping the !@C but allowing S@I, CS"-T, "nalog !omparator, ":!, Two&wire
Serial Interface, Timer3!ounters, (atchdog, and the interrupt system to continue operating.
This sleep mode basically halts clk!@C and clk)9"SH, while allowing the other clocks to
run. Idle mode enables the 5!C to wake up from external triggered interrupts as well as
internal ones like the Timer 4verflow and CS"-T Transmit !omplete interrupts. If wake&up
from the "nalog !omparator interrupt is not reuired, the "nalog !omparator can be
powered down by setting the "!: bit in the "nalog !omparator !ontrol and Status -egister
B "!S-. This will reduce power consumption in Idle mode. If the ":! is enabled, a
conversion starts automatically when this mode is entered.
A)C Noise 'eduction Mode
(hen the S58..2 bits are written to 22/, the S9''@ instruction makes the 5!C enter ":!
#oise -eduction mode, stopping the !@C but allowing the ":!, the 'xternal Interrupts, the
Two&wire Serial Interface address watch, Timer3!ounter8 and the (atchdog to continue
operating $if enabled%. This sleep mode basically halts clkI34, clk!@C, and clk)9"SH, while
allowing the other clocks to run.
This improves the noise environment for the ":!, enabling higher resolution measurements.
If the ":! is enabled, a conversion starts automatically when this mode is entered. "part
form the ":! !onversion !omplete interrupt, only an 'xternal -eset, a (atchdog -eset, a
.rown&out -eset, a Two&wire Serial Interface "ddress 5atch Interrupt, a Timer3!ounter8
interrupt, an S@53''@-45 ready interrupt, an 'xternal level interrupt on I#T2 or I#T/, or
an external interrupt on I#T8 can wake up the 5!C from ":! #oise -eduction mode.
Po8er-do8n Mode
10
(hen the S58..2 bits are written to 2/2, the S9''@ instruction makes the 5!C enter
@ower&down mode. In this mode, the 'xternal 4scillator is stopped, while the 'xternal
interrupts, the Two&wire Serial Interface address watch, and the (atchdog continue operating
$if enabled%.4nly an 'xternal -eset, a (atchdog -eset, a .rown&out -eset, a Two&wire
Serial Interface address match interrupt, an 'xternal level interrupt on I#T2 or I#T/, or an
'xternal interrupt on I#T8 can wake up the 5!C. This sleep mode basically halts all
generated clocks, allowing operation of asynchronous modules only.
#ote that if a level triggered interrupt is used for wake&up from @ower&down mode, the
changed level must be held for some time to wake up the 5!C.
(hen waking up from @ower&down mode, there is a delay from the wake&up condition
occurs until the wake&up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake&up period is defined by the same !DS'9 fuses
that define the reset time&out period.
Po8er-sa9e Mode
(hen the S58..2 bits are written to 2//, the S9''@ instruction makes the 5!C enter
@ower&save mode. This mode is identical to @ower&down, with one exceptionEIf
Timer3!ounter8 is clocked asynchronously, i.e., the "S8 bit in "SS- is set, Timer3!ounter8
will run during sleep. The device can wake up from either Timer 4verflow or 4utput
!ompare event from Timer3!ounter8 if the corresponding Timer3!ounter8 interrupt enable
bits are set in TI5SD, and the ,lobal Interrupt 'nable bit in S-', is set.
If the "synchronous Timer is #4T clocked asynchronously, @ower&down mode is
recommended instead of @ower&save mode because the contents of the registers in the
"synchronous Timer should be considered undefined after wake&up in @ower&save mode if
"S8 is 2.
This sleep mode basically halts all clocks except clk"SL, allowing operation only of
asynchronous modules, including Timer3!ounter8 if clocked asynchronously.
/tand#: Mode
(hen the S58..2 bits are //2 and an external crystal3resonator clock option is selected, the
S9''@ instruction makes the 5!C enter Standby mode. This mode is identical to @ower&
down with the exception that the 4scillator is kept running. )rom Standby mode, the device
wakes up in six clock cycles.
E+tended /tand#: Mode
(hen the S58..2 bits are /// and an external crystal3resonator clock option is selected, the
S9''@ instruction makes the 5!C enter 'xtended Standby mode. This mode is identical to
@ower&save mode with the exception that the 4scillator is kept running. )rom 'xtended
Standby mode, the device wakes up in six clock cycles..
11
Mini;i<ing Po8er Consu;ption
There are several issues to consider when trying to minimize the power consumption in an
"=- controlled system. In general, sleep modes should be used as much as possible, and the
sleep mode should be selected so that as few as possible of the device+s functions are
operating. "ll functions not needed should be disabled. In particular, the following modules
may need special consideration when trying to achieve the lowest possible power
consumption.
Analog to )igital Con9erter
If enabled, the ":! will be enabled in all sleep modes. To save power, the ":! should be
dis&abled before entering any sleep mode. (hen the ":! is turned off and on again, the next
conversion will be an extended conversion.
Analog Co;parator
(hen entering Idle mode, the "nalog !omparator should be disabled if not used. (hen
entering ":! #oise -eduction mode, the "nalog !omparator should be disabled. In the
other sleep modes, the "nalog !omparator is automatically disabled. However, if the "nalog
!omparator is set up to use the Internal =oltage -eference as input, the "nalog !omparator
should be disabled in all sleep modes. 4therwise, the Internal =oltage -eference will be
enabled,independent of sleep mode. -efer to M"nalog !omparatorN on page /01 for details
on how to configure the "nalog !omparator.
Bro8n-out )etector
If the .rown&out :etector is not needed in the application, this module should be turned off.
If the .rown&out :etector is enabled by the .4:'# )use, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute
12
significantly to the total current consumption. -efer to M.rown&out :etectionN on page 70 for
details on how to configure the .rown&out :etector.
Internal 1oltage 'eference
The Internal =oltage -eference will be enabled when needed by the .rown&out :etector, the
"nalog !omparator or the ":!. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power.
(hen turned on again, the user must allow the reference to start up before the output is used.
If the reference is kept on in sleep mode, the output can be used immediately. -efer to
MInternal =olt& age -eferenceN on page >/ for details on the start&up time.
.atchdog &i;er
If the (atchdog Timer is not needed in the application, this module should be turned off. If
the (atchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always
consume power. In the deeper sleep modes, this will contribute significantly to the total
current consump&tion. -efer to M(atchdog TimerN on page >/ for details on how to configure
the (atchdog Timer.
Port Pins
(hen entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
the both the I34 clock $clkI34% and the ":! clock $clk":!% are stopped, the input buffers of
the device will be disabled. This ensures that no power is consumed by the input logic when
not needed. In some cases, the input logic is needed for detecting wake&up conditions, and it
will then be enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to =!!38, the input buffer will use excessive power.
=&A3 Interface and (n-chip )e#ug /:ste;
If the 4n&chip debug system is enabled by the 4!:'# )use and the chip enter @ower down
or @ower save sleep mode, the main clock source remains enabled. In these sleep modes, this
will contribute significantly to the total current consumption. There are three alternative ways
to avoid thisE
K :isable 4!:'# )use.
K :isable GT",'# )use.
K (rite one to the GT: bit in 5!C!S-.
The T:4 pin is left floating when the GT", interface is enabled while the GT", T"@
controller is not shifting data. If the hardware connected to the T:4 pin does not pull up the
logic level, power consumption will increase. #ote that the T:I pin for the next device in the
scan chain contains a pull&up that avoids this problem. (riting the GT: bit in the 5!C!S-
register to one or leaving the GT", fuse unprogrammed disables the GT", interface.
13
C%AP&E'-6
C(N&'(--E' A'EA NE&.('>
6.1IN&'()*C&I(N
!ontroller "rea #etwork $!"#% was initially created by ,erman automotive system supplier
-obert .osch in the mid&/012s for automotive applications as a method for enabling robust
14
serial communication. The goal was to make automobiles more reliable, safe and fuel&
efficient while decreasing wiring harness weight and complexity. Since its inception, the
!"# protocol has gained widespread popularity in industrial automation and
automotive3truck applications. 4ther markets where networked solutions can bring attractive
benefits like medical euipment, test euipment and mobile machines are also starting to
utilize the benefits of !"#. The goal of this application note is to explain some of the basics
of !"# and show the benefits of choosing
!"# for embedded systems networked applications.
The !ontroller "rea #etwork $the !"# bus% is a serial communications bus for real&time
control applications* operates at data rates of up to / 5egabits per second, and has excellent
error detection and confinement capabilities. !"# was originally developed by the ,erman
company, -obert .osch, for use in cars, to provide a cost&effective communications bus for
in&car electronics and as alternative to expensive, cumbersome and unreliable wiring looms
and connectors. The car industry continues to use !"# for an increasing number of
applications, but because of its proven reliability and robustness, !"# is now also being used
in many other control applications.
!"# is an international standard and is documented in IS4 //101 $for high&speed
applications% and IS4 //6/0 $for lower&speed applications%.
9ow&cost !"# controllers and interface devices are available as off&the&shelf components
from several of the leading semiconductor manufacturers. !ustom built devices and popular
microcontrollers with embedded !"# controllers are also available. There are many !"#&
related system development packages, hardware interface cards and easy&to&use software
packages that provide system designers, builders and maintainers with a wide range of
design, monitoring, analysis, and test tools.
.hat is CAN?
!"# or !ontroller "rea #etwork is a robust industrial strength hardware and software
protocol used to communicate between microcontrollers. It is very popular in modern
automotive applications and is gaining popularity in industrial and home automation
applications.
%o8 CAN 8or@s
Principle
Data messages transmitted from any node on a CAN bus do not ontain addresses
of eit!er t!e transmitting node" or of any intended reei#ing node$
Instead, the content of the message $e.g. -evolutions @er 5inute, Hopper )ull, O&ray :osage,
etc.% is labeled by an identifier that is uniue throughout the network. "ll other nodes on the
network receive the message and each performs an acceptance test on the identifier to
determine if the message, and thus its content, is relevant to that particular node.
15
If the message is relevant, it will be processed* otherwise it is ignored. The uniue identifier
also determines the priority of the message. The lower the numerical value of the identifier,
the higher the priority.
In situations where two or more nodes attempt to transmit at the same time, a non&destructive
arbitration techniue guarantees that messages are sent in order of priority and that no
messages are lost.
Bit encoding
CAN uses Non %eturn to &ero 'N%&( enoding ')it! bit*stuffing( for data
ommuniation on a differentia+ t)o )ire bus$ ,!e use of N%& enoding ensures
om-at messages )it! a minimum number of transitions and !ig! resi+iene to
e.terna+ disturbane$
The physical bus
The two wire bus is usually a twisted pair $shielded or unshielded%. )lat pair $telephone type%
cable also performs well but generates more noise itself, and may be more susceptible to
external sources of noise.
Robustness
!"# will operate in extremely harsh environments and the extensive error checking
mechanisms ensure that any transmission errors are detected. See the P'rror HandlingP section
of this site for more details.
The IS4//101 standard Q-ecommendsQ that bus interface chips be designed so that
communication can still continue $but with reduced signal to noise ratio% even ifE
& 'ither of the two wires in the bus is broken
& 'ither wire is shorted to power
& 'ither wire is shorted to ground
Net8or@ 2le+i#ilit: and E+pansion
The content&oriented nature of the !"# messaging scheme delivers a high degree of
flexibility for system configuration.
#ew nodes that are purely receivers, and which need only existing transmitted data, can be
added to the network without the need to make any changes to existing hardware or software.
5easurements needed by several controllers can be transmitted via the bus, thereby removing
the need for each controller to have its own individual sensor
How Arbitration Works on the CAN Bus
In any system, some parameters will change more rapidly than others. )or example &
parameters that change uickly could be the -@5 of a car engine, or the current floor level of
an elevator $CS% & lift $CD%. Slower changing parameters may be the temperature of the
coolant of a car engine.
16
It is likely that the more rapidly changing parameters need to be transmitted more freuently
and, therefore, must be given a higher priority.
To determine the priority of messages, !"# uses the established method known as !arrier
Sense, 5ultiple "ccess with !ollision :etect $!S5"3!:% but with the enhanced capability
of non&destructive bitwise arbitration to provide collision resolution, and to deliver maximum
use of the available capacity of the bus.
Non-Destructive Bitwise Arbitration
The priority of a !"# message is determined by the numerical value of its identifier.
The numerical value of each message identifier $and thus the priority of the message% is
assigned during the initial phase of system design.
The identifier with the lowest numerical value has the highest priority. "ny potential bus
conflicts are resolved by bitwise arbitration in accordance with the wired&and mechanism, by
which a dominant state $logic 2% overwrites a recessive state $logic /%.
6.%igher la:er i;ple;entations
"s the !"# standard does not include tasks of application layer protocols, such as flow
control, device addressing, and transportation of data blocks larger than one message, many
implementations of higher layer protocols were created. "mong these
are :evice#et, !"#open, S:S $Smart :istributed System%, !"#aerospace, G/070,
Smart!raft, #5'" 8222, !"# Dingdom, Safety.CS p, 'nergy.us and 5il!"#.
"n "-I#! technical working group develops the "-I#! 186 standard with special
reuirements for the aviation industry.
17
.
.lock :iagram
6.3&:pes of CAN
There are two types of CAN implementations depending in the size of
the identifier field.
1) STANDARD: 11-bit wide identifier field
!) "#T"ND"D: !$-bit wide identifier field
The Standard !"# protocol $version 8.2"%, also now known as .ase )rame )ormat, supports
messages with // bit identifiers.
The 'xtended !"# protocol $version 8.2.%, also now known as 'xtended )rame )ormat,
supports both // bit and 80 bit identifiers.
5ost 8.2" controllers transmit and receive only Standard format messages, although some
$known as 8.2. passive% will receive 'xtended format messages & but then ignore them. 8.2.
controllers can send and receive messages in both formats.
.!A 2or;at
" Standard !"# $=ersion 8.2"% 5essage )rame consists of seven different bit fieldsE
" Start of )rame $S4)% field & which indicates the beginning of a message frame.
18
"n "rbitration field, containing a message identifier and the -emote Transmission
-euest $-T-% bit. The -T- bit is used to discriminate between a transmitted :ata
)rame and a reuest for data from a remote node.

5essage )rame
" !ontrol )ield containing six bitsE
R two reserved bits $r2 and r/% and
R a four bit :ata 9ength !ode $:9!%. The :9! indicates the number of bytes in the
:ata )ield that follows
" :ata )ield, containing from zero to eight bytes.
The !-! field, containing a fifteen bit cyclic redundancy check code and a recessive
delimiter bit
The "!Dnowledge field, consisting of two bits. The first is the Slot bit which is
transmitted as recessive, but is subseuently over written by dominant bits transmitted
from any node that successfully receives the transmitted message. The second bit is a
recessive delimiter bit
The 'nd of )rame field, consisting of seven recessive bits.
)ollowing the 'nd 4f )rame is the I#Termission field consisting of three recessive bits.
"fter the three bit I#Termission period the bus is recognised to be free. .us Idle time maybe
of any arbitrary length including zero.
.!B 2or;at
The !"# 8.2. format provides a twenty nine $80% bit identifier as opposed to the // bit
identifier in 8.2".
=ersion 8.2. evolved to provide compatibility with other serial communications protocols
used in automotive applications in the CS". To cater for this, and still provide compatibility
with the 8.2" format, the 5essage )rame in =ersion 8.2. has an extended format.
The differences areE
In =ersion 8.2. the "rbitration field contains two identifier bit fields. The first
$the base I:% is eleven $//% bits long for compatibility with =ersion 8.2". The
19
second field $the I: extension% is eighteen $/1% bits long, to give a total length
of twenty nine $80% bits.
The distinction between the two formats is made using an Identifier 'xtension
$I:'% bit.
" Substitute -emote -euest $S--% bit is also included in the "rbitration
)ield. The S-- bit is always transmitted as a recessive bit to ensure that, in
the case of arbitration between a Standard :ata )rame and an 'xtended :ata
)rame, the Standard :ata )rame will always have priority if both messages
have the same base $// bit% identifier.
"ll other fields in a 8.2. 5essage )rame are identical to those in the Standard format.
!"A and !"B Co#patibility
8.2. controllers are completely backward compatible with 8.2" controllers and can transmit
and receive messages in either format.
#ote, however, that there are two types of 8.2" controllersE
The first is capable of transmitting and receiving only messages in 8.2"
format. (ith this type of controller, reception of any 8.2. message will flag
an error.
The second $known as 8.2. passive% is capable of sending and receiving 8.2"
messages. They will also acknowledge receipt of 8.2. messages & but then
ignore them.
Therefore, within the above mentioned constraints it is possible to use both =ersion 8.2"
$with 8.2. passive capabilities% and 8.2. controllers on a single network.
The number of uniue identifiers available to users, on a single 8.2" network, is 8,278 $8 to
the power // & 8 to the power >%.
9eaving aside the use for compatibility purposes with "merican buses, the number of uniue
identifiers available on a 8.2. network is in excess of 622 millionS
/tandard Co;;on Na;e Baud 'ate Ma+ nodes
Ma+
-ength
Adapter for
PCAN
interfaces
IS4 //?17 IS4.CS 862 D.it3s 72 >2m #one
IS4 //101&
8
High speed&!"# max. / 5.it3s //2 ;622 m #one
IS4 //101&
7
)ault Tolerant !"# max. /86 D.it3s 78 622 m
@!"#
TG"/26>
20
IS4 //008
)5S or Truck3Trailer
!"#
max. /86 D.it3s
8 $@oint to
@oint%
>2 m
@!"#&
.:/22//S
IS4 /6?;6 :iagnostics 4n !"# max / 5.it3s //2
S"' G/070
862 D.it3s 72 >2m
S"' G881> max. / 5.it3s //2
S"' G8>//
Single (ire !"#
77,7 D.it3s
17,7D.it3s in
HS5ode
78 @!"#&"C6?0
6.6I;ple;entations of CAN
!ommunication is identical for all implementations of !"#. However, there are two
principal hardware implementations.
The two implementation are known as .asic !"# and )ull !"#.
The terms .asic !"# and )ull !"# must not be confused with the terms Standard !"# &
also known as .ase )rame )ormat $// bit identifier, =ersion 8.2" data format% and 'xtended
!"# & also known as 'xtended )rame )ormat$80 bit identifier, or =ersion 8.2. data format%.
Suitably configured, each implementation $.asic or )ull !"#% can handle both .ase and
'xtended data formats.
Basic CAN
In .asic !"# configurations there is a tight link between the !"# controller and the
associated microcontroller. The microcontroller, which will have other system related
functions to administer, will be interrupted to deal with every !"# message.
2ull CAN
)ull !"# devices contain additional hardware to provide a message QserverQ that
automatically receives and transmits !"# messages without interrupting the associated
microcontroller. )ull !"# devices carry out extensive acceptance filtering on incoming
messages, service simultaneous reuests, and generally reduce the load on the
microcontroller.
Net8or@ /i<es
The number of nodes that can exist on a single network is, theoretically, limited only by the
number of available identifiers. However, the drive capabilities of currently available devices
imposes greater restrictions. :epending on the device types, up to 78 or ;> nodes per network
is normal, but at least one manufacturer now provides devices that will allow networks of //2
nodes.
)ata 'ate 9s Bus -ength
The rate of data transmission depends on the total overall length of the bus and the delays
associated with the transceivers. )or all IS4//101 compliant devices running at /5bit3sec
speed, the maximum possible bus length is specified as >2 5etres, )or longer bus lengths it is
21
necessary to reduce the bit rate. To give some indication of this the following numbers are
from the :evice#et features listE
622 D bits per second at /22 metres $781 ft%
862 D bits per second at 822 metres $;6; ft%
/86 D bits per second at 622 metres $/;>2 ft%
/ignal Characteristics
!"# may be implemented over a number of physical media so long as the drivers are open&
collector and each node can hear itself and others while transmitting $this is necessary for its
message priority and error handling mechanisms%. The most common media is a twisted pair
6v differential signal which will allow operations in high noise environments and with the
right drivers will work even if one of the wires is open circuit. " number of transceiver chips
are available the most popular probably being the @hilips 18!86/ as well as the TG"/2>2.
(hen running )ull !"# $IS4 //101&8% at its higher speeds it is necessary to terminate the
bus at both ends with /82 4hms. The resistors are not only there to prevent reflections but
also to unload the open collector transceiver drivers.
6.A&he (/I ;odel
IS4?>01 defines a communications standard known as the 4pen Systems Interconnection
$4SI% model. This model describes how communications should occur between computers on
any network, and has been adopted as a general QopenQ network communication standard. In
principle & anything that conforms to the standard can communicate, electronically, with
anything else that conforms to the standard.
The 4SI model defines seven independent QlayersQ of a protocol stack. Strict compliance
with the standard reuires that each layer is insulated from the others by well&defined
interfaces. )ew, if any, networks comply absolutely with the 4SI model with regard to
provision of all seven layers as distinct entities.
22
/ig $ ,!e 0e#en 1ayer 203 mode+
.CAN and the (/I Model
The !"# specification $IS4//101% discusses only the @hysical and :ata&9ink layers for a
!"# network.
The :ata&9ink 9ayer & is the only layer that recognises and understands the format of
messages. This layer constructs the messages to be sent to the @hysical 9ayer, and
decodes messages received from the @hysical 9ayer. In !"# controllers, the :ata&
9ink 9ayer is usually implemented in hardware.
The @hysical 9ayer & specifies the physical and electrical characteristics of the bus, and
of the hardware that converts the characters of a message into electrical signals for
transmitted messages & and electrical signals into characters for received messages.
"lthough the other layers may be implemented in either hardware $as chip level
functions% or software, the @hysical 9ayer is always QrealQ hardware$
CAN Applications -a:ers
5any applications of !"# reuire services that are beyond the basic functionality specified
by the :ata&9ink 9ayer but which may be implemented at the "pplication 9ayer. )or
example, the transmission or reception of data units longer than eight bytes. To meet this
need several organisations have developed "pplication 9ayers. .rief details about <ust a few
of them and contact details are given below.
CA- (CAN Application -a:er"
"ptly named, and based on an existing and proven protocol originally developed by @hilips
5edical Systems, !"9 is an application&independent application layer that has been
specified and is now maintained by the !"# in "utomation $!i"% user group. "nyone who
implements !"9 may do so free of any licence royalty. The !"9 specification $document
reference !i" :S&82/...82?% may be purchased from !i". 9ogical 9ink !ontrol $99!%
K "cceptance )iltering
K 4verload #otification
K -ecovery 5anagement
5edium "ccess !ontrol $5"!%
K :ata 'ncapsulation3:ecapsulation
K )rame !oding $Stuffing3:estuffing%T
K 'rror :etection3Signalling
K Serialization3:eserialization
23
@hysical Signaling $@9S%
K .it 'ncoding3:ecoding
K .it Timing3Synchronization
@hysical 5edium "ttachment $@5"%
K :river3-eceiver !haracteristics
5edium :ependent Interface $5:I%
K !onnectors

CANopen
!"#open is an implementation of !"9 and is defined by the !"#open !ommunications
@rofile in !i" :S&72/. This document may also be purchased from !i". Information about
!"#open may be obtained from the !i" Cser ,roup
Lou might also want to get hold of a copy of Q'mbedded #etworking with !"# and
!"#openQ by 4laf @feiffer, "ndrew "yre and !hristian Deydel. @ublished by -T! .ooks.
IS.#E 2&080708&?1&?. @rice in the CS" U>0.06.
)e9iceNetB
:evice#et is a !i"&approved application layer based on !"# 8.2" and is widely used in
industrial automation applications. :evice#et $originally developed by -ockwell3"llen&
.radley% is now an Q4penQ fieldbus regulated by an independent organisation know as the
4pen :evice#et =endors "ssociation, from whom copies of the specification may be
purchased. @urchasers of the specification receive an unlimited, royalty&free licence to
develop :evice#et compatible products.
NMEA !!!
"n application layer used in the marine and pleasure craft sector.
/)/B (/;art )istri#uted /:ste;"
S:S is also a !i"&approved application layer. :eveloped by Honeywell, one of the main
uses of S:S is for machine control applications.
CAN >ingdo;B
"nother !i"&approved application layer, named !"# Dingdom, is provided by a Swedish
company named Dvaser "..
6.,&arget Applications
!"# is being designed into a widerange of applications that usecommand and control
networks.
Some of these applications includeE
Industrial control
5aritime electronics
"vionics3aerospace electronics
C@S $Cninterruptible @ower Supply%
Heavy machinery and earthmoving euipment
)actory automation
24
5edical euipment
'levator control
'xercise euipment
"utomotive passenger car
Trucks3buses
4ff&highway and off&road vehicles
C%AP&E'-A
MCPA1A /tand-Alone CAN Controller .ith /PI Interface
A.1)escription
5icrochip Technology+s 5!@86/6 is a stand&alone !ontroller "rea #etwork $!"#%
controller that implements the !"# specification, version 8.2.. It is capable of transmitting
and receiving both standard and extended data and remote frames. The 5!@86/6 has two
acceptance masks and six acceptance filters that are used to filter out unwanted messages,
thereby reducing the host 5!Cs overhead. The 5!@86/6 interfaces with microcontrollers
$5!Cs% via an industry standard Serial @eripheral Interface $S@I%.
A.2eatures
K Implements !"# =8.2. at / 5b3sE
& 2 B 1 byte length in the data field
& Standard and extended data and remote frames
K -eceive buffers, masks and filtersE
& Two receive buffers with prioritized message storage
& Six 80&bit filters
& Two 80&bit masks
K :ata byte filtering on the first two data bytes $applies to standard data frames%
K Three transmit buffers with prioritizaton and abort features
K High&speed S@I Interface $/2 5Hz%E
& S@I modes 2,2 and /,/
K 4ne&shot mode ensures message transmission is attempted only one time
25
K !lock out pin with programmable prescalerE
& !an be used as a clock source for other device$s%
K Start&of&)rame $S4)% signal is available for monitoring the S4) signalE
& !an be used for time&slot&based protocols and3or bus diagnostics to detect early bus
degredation
K Interrupt output pin with selectable enables
K .uffer )ull output pins configurable asE
& Interrupt output for each receive buffer
& ,eneral purpose output
K -euest&to&Send $-TS% input pins individually configurable asE
& !ontrol pins to reuest transmission for each transmit buffer
& ,eneral purpose inputs
K 9ow&power !54S technologyE
& 4perates from 8.?= B 6.6=
& 6 m" active current $typical%
& / J" standby current $typical% $Sleep mode%
K Temperature ranges supportedE
& Industrial $I%E &>2F! to V16F!
& 'xtended $'%E &>2F! to V/86F!
Pac@ages &:pes
26
(9er9ie8
The 5!@86/6 is a stand&alone !"# controller developed to simplify applications that
reuire interfacing with a !"# bus. " simple block diagram of the 5!@86/6 is shown in
)igure /&/. The device consists of three main blocksE
/. The !"# module, which includes the !"# protocol engine, masks, filters, transmit and
receive buffers.
8. The control logic and registers that are used to configure the device and its operation.
7. The S@I protocol block.
CAN Module
The !"# module handles all functions for receiving and transmitting messages on the !"#
bus. 5essages are transmitted by first loading the appropriate message buffer and control
registers. Transmission is initiated by using control register bits via the S@I interface or by
using the transmit enable pins. Status and errors can be checked by reading the appropriate
registers. "ny message detected on the !"# bus is checked for errors and then matched
against the user&defined filters to see if it should be moved into on of the two receive buffers.
A.3B-(C> )IA3'AM
27
28
A.6CAN ME//A3E 2'AME/
The 5!@86/6 supports standard data frames, extended data frames and remote frames
$standard and extended%, as defined in the !"# 8.2. specification.
/tandard )ata 2ra;e
The !"# standard data frame is shown in )igure 8&/."s with all other frames, the frame
begins with a Start&4f&)rame $S4)% bit, which is of the dominant state and allows hard
synchronization of all nodes.
The S4) is followed by the arbitration field, consisting of /8 bitsE the //&bit identifier and
the -emote Transmission -euest $-T-% bit. The -T- bit is used to distinguish a data frame
$-T- bit dominant% from a remote frame $-T- bit recessive%.
)ollowing the arbitration field is the control field, consisting of six bits. The first bit of this
field is the Identifier 'xtension $I:'% bit, which must be dominant to specify a standard
frame. The following bit, -eserved
29
.it Wero $-.2%, is reserved and is defined as a dominant bit by the !"# protocol. The
remaining four bits of the control field are the :ata 9ength !ode $:9!%, which specifies the
number of bytes of data $2 B 1 bytes%contained in the message.
"fter the control field is the data field, which contains any data bytes that are being sent, and
is of the length defined by the :9! $2 B 1 bytes%.
The !yclic -edundancy !heck $!-!% field follows the data field and is used to detect
transmission errors. The !-! field consists of a /6&bit !-! seuence, followed by the
recessive !-! :elimiter bit.
The final field is the two&bit "cknowledge $"!D% field.:uring the "!D Slot bit, the
transmitting node sends out a recessive bit. "ny node that has received an error&free frame
acknowledges the correct reception of the frame by sending back a dominant bit $regardless
of whether the node is configured to accept that specific message or not%. The recessive
acknowledge delimiter completes the acknowledge field and may not be overwritten by a
dominant bit.
E+tended )ata 2ra;e
In the extended !"# data frame, shown in )igure 8&8,the S4) bit is followed by the
arbitration field, which consists of 78 bits. The first // bits are the 5ost Significant bits
$5Sb% $.ase&l:% of the 80&bit identifier.
These // bits are followed by the Substitute -emote -euest $S--% bit, which is defined to
be recessive.
The S-- bit is followed by the l:' bit, which is recessive to denote an extended !"# frame.
It should be noted that if arbitration remains unresolved after transmission of the first // bits
of the identifier, and one of the nodes involved in the arbitration is sending a standard !"#
frame $//&bit identifier%, the standard !"# frame will win arbitration due to the assertion of a
dominant l:' bit. "lso, the S-- bit in an extended !"# frame must be recessive to allow
the assertion of a dominant -T- bit by a node that is sending a standard !"# remote frame.
The S-- and l:' bits are followed by the remaining/1 bits of the identifier $'xtended l:%
and the remote transmission reuest bit.To enable standard and extended frames to be sent
across a shared network, the 80&bit extended messageidentifier is split into //&bit $most
significant% and /1&bit $least significant% sections. This split ensures that thel:' bit can
remain at the same bit position in both the standard and extended frames.)ollowing the
arbitration field is the six&bit control field.The first two bits of this field are reserved and must
30
bedominant. The remaining four bits of the control field are the :9!, which specifies the
number of data bytescontained in the message.
The remaining portion of the frame $data field, !-! field, acknowledge field, end&of&frame
and intermission% is constructed in the same way as a standard data frame $see Section 8./
MStandard :ata )rameN%.
'e;ote 2ra;e
#ormally, data transmission is performed on an autonomous basis by the data source node
$e.g., a sensor sending out a data frame%. It is possible, however, for a destination node to
reuest data from the source. To accomplish this, the destination node sends a remote frame
with an identifier that matches the identifier of the reuired data frame. The appropriate data
source node will then send a data frame in response to the remote frame reuest.
There are two differences between a remote frame$shown in )igure 8&7% and a data frame.
)irst, the -T- bit is at the recessive state and, second, there is no data field. In the event of a
data frame and a remote frame with the same identifier being transmitted at the same time,
the data frame wins arbitration due to the dominant -T- bit following the identifier. In this
way,the node that transmitted the remote frame receives the desired data immediately.
Error 2ra;e
"n error frame is generated by any node that detects a bus error. "n error frame, shown in
)igure 8&>, consists of two fieldsE an error flag field followed by an error delimiter field.
There are two types of error flag fields.The type of error flag field sent depends upon the
error status of the node that detects and generates the error flag field.5
1.acti9e errors
31
If an error&active node detects a bus error, the node interrupts transmission of the current
message by generating an active error flag. The active error flag is composed of six
consecutive dominant bits. This bit seuence actively violates the bit&stuffing rule. "ll other
stations recognize the resulting bit&stuffing error and, in turn, generate error frames
themselves, called error echo flags.
The error flag field, therefore, consists of between six and twelve consecutive dominant bits
$generated by one or more nodes%. The error delimiter field $eight recessive bits% completes
the error frame. Cpon completion of the error frame, bus activity returns to normal and the
interrupted node attempts to resend the aborted message.
.passi9e errors
If an error&passive node detects a bus error, the node transmits an error&passive flag followed
by the error delimiter field. The error&passive flag consists of six consecutive recessive bits.
The error frame for an error&passive node consists of /> recessive bits. )rom this it follows
that, unless the bus error is detected by an error&active node or the transmitting node, the
message will continue transmission because the error&passive flag does not interfere with the
bus.If the transmitting node generates an error&passive flag,it will cause other nodes to
generate error frames due to the resulting bit&stuffing violation. "fter transmission of an error
frame, an error&passive node must wait for six consecutive recessive bits on the bus before
attempting to re<oin bus communications.
The error delimiter consists of eight recessive bits and allows the bus nodes to restart bus
communications cleanly after an error has occurred.
(9erload 2ra;e
"n overload frame, shown in )igure 8&6, has the same format as an active error frame. "n
overload frame,however, can only be generated during an interframe space. In this way, an
overload frame can be differentiated from an error frame $an error frame is sent during the
transmission of a message%. The overload frame consists of two fieldsE an overload flag
followed by an overload delimiter. The overload flag consists of six dominant bits followed
by overload flags generated by other nodes $and, as for an active error flag, giving a
maximum of twelve dominant bits%. The overload delimiter consists of eight recessive bits.
"n overload frame can be generated by a node as a result of two conditionsE
/. The node detects a dominant bit during the interframe space, an illegal condition.
'xceptionE The dominant bit is detected during the third bit of I)S. In this case, the receivers
will interpret this as a S4).
32
8. :ue to internal conditions, the node is not yet able to begin reception of the next message.
" node may generate a maximum of two seuential overload frames to delay the start of the
next message.
Interfra;e /pace
The interframe space separates a preceding frame $of any type% from a subseuent data or
remote frame.
The interframe space is composed of at least three recessive bits called the Intermission. This
allows nodes time for internal processing before the start of the next message frame. "fter the
intermission, the bus line remains in the recessive state $bus idle% until the next transmission
starts.
33
C%AP&E'-,
%igh-/peed CAN &ranscei9er(MCPAA1"
,.1(1E'1IE.
The 5!@866/ is a high&speed !"#, fault&tolerant device that serves as the interface between
a !"# protocol controller and the physical bus. The 5!@866/ provides differential transmit
and receive capability forX the !"# protocol controller and is fully compatible with the IS4&
//101 standard, including 8>= reuirements. It will operate at speeds of up to / 5b3s.
Typically, each node in a !"# system must have a device to convert the digital signals
generated by a !"# controller to signals suitable for transmission over the bus cabling
$differential output%. It also provides a buffer between the !"# controller and the high&
voltagespikes that can be generated on the !"# bus byoutside sources $'5I, 'S:, electrical
transients, etc.%.
&rans;itter 2unction
The !"# bus has two statesE :ominant and -ecessive. " dominant state occurs when the
differential voltage between !"#H and !"#9 is greater than a defined voltage $e.g.,/.8=%.
" recessive state occurs when the differential voltage is less than a defined voltage $typically
2=%. The dominant and recessive states correspond to the low and high state of the TO:
input pin, respectively. However, a dominant state initiated by another !"# node will
override arecessive state on the !"# bus.
Ma+i;u; nu;#er of nodes
The 5!@866/ !"# outputs will drive a minimum load of >6Y, allowing a maximum of //8
nodes to be connected $given a minimum differential input resistance of 82 kY and a nominal
termination resistor value of /82Y%.
'ecei9er 2unction
The -O: output pin reflects the differential bus voltage between !"#H and !"#9. The low
and high states of the -O: output pin correspond to the dominant and recessive states of the
!"# bus, respectively.
Internal Protection
!"#H and !"#9 are protected against battery shortcircuits and electrical transients that can
occur on the !"# bus. This feature prevents destruction of the transmitter output stage
during such a fault condition. The device is further protected from excessive current loading
by thermal shutdown circuitry that disables the output drivers when the <unction temperature
exceeds a nominal limit of /;6F!. "ll other parts of the chip remain operational and the chip
temperature is lowered due to the decreased power dissipation in the transmitter outputs. This
protection is essential to protect against bus line short&circuit&induced damage.
34
,. (perating Modes
The -S pin allows three modes of operation to beselectedE
K High&Speed
K Slope&!ontrol
K Standby
(hen in High&speed or Slope&control mode, the drivers for the !"#H and !"#9 signals are
internally regulated to provide controlled symmetry in order to minimize '5I emissions.
"dditionally, the slope of the signal transitions on !"#H and !"#9 can be controlled with a
resistor connected from pin 1 $-S% to ground, with the slope proportional to the current
output at -S, further reducing '5I emissions.
%I3%-/PEE)
High&speed mode is selected by connecting the -S pin to =SS. In this mode, the transmitter
output drivers have fast output rise and fall times to support high&speed!"# bus rates.
/-(PE-C(N&'(-
Slope&control mode further reduces '5I by limiting the rise and fall times of !"#H and
!"#9. The slope, or slew rate $S-%, is controlled by connecting an external resistor $-'OT%
between -S and =49 $usually ground%. The slope is proportional to the current output at the
-S pin. Since the current is primarily determined by the slope&control resistance value
-'OT, a certain slew rate is achieved by applying a respective resistance. llustrates typical
slew rate values as a
function of the slope&control resistance value.
/&AN)B0 M()E
The device may be placed in standby or MS9''@N mode by applying a high&level to -S. In
S9''@ mode, the transmitter is switched off and the receiver operates at a lower current. The
receive pin on the controller side $-O:% is still functional but will operate at a slower rate.
The attached microcontroller can monitor -O: for !"# bus activity and place the
transceiver into normal operation via the -S pin $at higher bus rates, the first !"# message
may be lost%.
&5) Per;anent )o;inant )etection
If the 5!@866/ detects an extended low state on the TO: input, it will disable the !"#H
and !"#9 output drivers in order to prevent the corruption of data on the !"# bus. The
drivers are disabled if TO: is low for more than /.86 ms $minimum%. This implies a
maximum bit time of ;8.6 Zs $/; kb3s bus rate%, allowing up to 82 consecutive transmitted
dominant bits during a multiple bit error and error frame scenario. The drivers remain
disabled as long as TO: remains low. " rising edge on TO: will reset the timer logic and
enable the !"#H and !"#9 output drivers.
35
Po8er-on 'eset
(hen the device is powered on, !"#H and !"#9 remain in a high&impedance state until
=:: reaches the voltage&level =@4-H. In addition, !"#H and !"#9 will remain in a high
impedance state if TO: is low when =:: reaches =@4-H. !"#H and !"#9 will become
active only after TO: is asserted high. 4nce powered on, !"#H and !"#9 will enter a
high&impedance state if the voltage level at =:: falls below =@4-9, providing voltage
brown&out protection during normal operation.
,.3Bloc@ )iagra;
,.6Pin )iagra;
36
Pins )escription
&'AN/MI&&E' )A&A INP*& (&5)"
TO: is a TT9&compatible input pin. The data on this pin is driven out on the !"#H and
!"#9 differential output pins. It is usually connected to the transmitter data output of the
!"# controller device. (hen TO: is low,!"#H and !"#9 are in the dominant state.
(hen TO: is high, !"#H and !"#9 are in the recessive state,provided that another !"#
node is not driving the !"# bus with a dominant state. TO: has an internal pull&up resistor
$nominal 86 k[ to =::%.
3'(*N) /*PP-0 (1//"
,round supply pin.
/*PP-0 1(-&A3E (1))"
@ositive supply voltage pin.
'ECEI1E' )A&A (*&P*& ('5)"
-O: is a !54S&compatible output that drives high or low depending on the differential
signals on the !"#H and !"#9 pins and is usually connected to the receiver data input of
the !"# controller device. -O: is high when the !"# bus is recessive and low in the
dominant
state.
37
'E2E'ENCE 1(-&A3E (1'E2"
-eference =oltage 4utput $:efined as =::38%.
CAN -(. (CAN-%
The !"#9 output drives the low side of the !"# differential bus. This pin is also tied
internally to the receive input comparator.
CAN %I3% (CAN%"
The !"#H output drives the high&side of the !"# differential bus. This pin is also tied
internally to the receive input comparator.
/-(PE 'E/I/&(' INP*& ('/"
The -S pin is used to select High&speed, Slope&control or Standby modes via an external
biasing resistor.
38
C%AP&E'-4
A1' /&*)I(
/tarting A1' /tudio
Start the "=- Studio program by clicking onE
Start&\@rograms&\"T5'9 "=- Tools&\"=- Studio >
4nce the program has started, you will be looking at a screen like thisE
Creating a Ne8 ProCect
In this tutorial we will make a simple program that increases the value of one of the @4-T
registers, making a binary counter.
To create a new pro<ect, click on Q#ew @ro<ectQ on the (elcome Screen or go to theQ@ro<ectQ
menu and select Q#ewQ.
In this dialog box you should select Q"tmel "=- "ssemblerQ and enter the pro<ect name. (e
choose the name QledQ here, but this could of course be an arbitrary name. #ext youPll have to
select the pro<ect location. This is the location where "=- Studio will store all files
associated with the pro<ect. (e have used the location HEXcsse/222XpracsX as the folder. If the
folder does not exist, "=- Studio will ask you whether to create it or not. !lick Q#ext \\Q
Select Q"=- SimulatorQ as the debug platform and Q"T02S16/6Q as the device to use, then
click Q)inishQ.
(e can now enter the "ssembly code of the program. $"=- Studio has opened an editor
window called led.asm%. "lternatively you can add or create other assembly language files by
right clicking on QSource )ilesQ in the @ro<ect window.
39
The led.asm file is automatically marked as Q"ssembler 'ntry )ileQ $the small red arrow on
the icon next to the filename shows this%. This indicates that the code from this file will be
assembled $and executed% first. 4nly one file can be marked as an entry file.
Editing the Asse;#ler file
(e have now added a new but empty file to our pro<ect. The next step is to fill this file with
our code. The file is initially empty and youPll have to manually enter the following codeE $or
you may !opy and @aste the code below directly into the editor window.%
Asse;#le the /ource Code
To assemble the code, we need to build the pro<ect. Select Q.uildQ from the .uild menu $or
press I)?\%E
The result of building the pro<ect will be shown in the Q.uildQ pane.
(e are now ready to advance to the next step, which is running the code in simulator mode.
/i;ulating the Code
"t this point we have generated the files needed to simulate the code. To start running the
code, select QStart :ebuggingQ from the Q:ebugQ menuE
Instruction Pointer
#ow take a look in the editor view, youPll see that a yellow right&arrow has appeared in the
left margin of the code. This arrow indicates the position of the program counter. In other
words, it points to the next instruction to be executed.
(e want to set the I34 =iew so that we can have a closer look at what is happening on the
@ort . registers during program execution. In the QI34 =iewQ (indow, click on the V symbol
next to Q@4-T.Q. Similarly, you can expand other views if desired.
This shows all registers associated with @ort ., these areE @ort . :ata register $@4-T.%,
:ata :irection $::-.% and Input @ins $@I#.%. "s shown each bit in the registers are
represented by a checkbox. " logical PzeroP $2% is represented by an empty checkbox and a
logical Pone$/% is represented by a filled&in checkbox. These checkboxes will be updated
during program execution, and show the current state of every bit. Lou may also set and clear
these bits by clicking on the appropriate checkbox at any time during the program execution.
Lou can also monitor the hexadecimal euivalent representation.
/ingle /tepping the Progra;
There are two commands to single step through the code. These are QStep 4verQ I)/2\ and
QStep IntoQ I)//\. The difference between these commands is that QStep 4verQ does not
trace into subroutines. Since our example does not contain any subroutines, there is no
difference between the operation of these commands in this example.
#ow single step down to the last line of code $r<mp loop% by repeatedly pressing the I)//\
key or by selecting QStep IntoQ from theQ:ebugQ menu. #otice how the colour changes from
black to red on the registers that change value. This makes it easier to identify which registers
change value on each instruction. !ontinue pressing the I)//\ key and see how the binary
value in @ort . is increased.
40
/etting Brea@points
.reakpoints are a method of halting execution flow. .y adding a breakpoint in the assembly
code we can run run the program at full speed, and it will be stopped at the line with the
breakpoint. .y now you have noticed that you have to press I)//\ three times to go through
the loop once. (e will add a breakpoint at the r<mp loop instruction to show how this can be
used to speed up the debug process.
@lace the cursor on the r<mp loop instruction in the source view window and press I)0\ $or
the QToggle .reakpointQ in the Q:ebugQ menu or right&click on the line of code and select
QToggle .reakpointQ%. " red circle will appear in the left margin of the source view . .y
pressing I)6\ or Q-unQ from the Q:ebugQ menu the program will start running and break
$stop% at the instruction with the breakpoint.
Modif:ing the Code
#ow we want the program to count down instead of up. To make this change wePll have to
edit the source code. @lace the cursor in the source view, and change the inc to a dec
instruction. If you now press I)6\ $-un% the following dialog box will appear. This box
indicates that one of the source files has been changed, and that the pro<ect should be rebuilt.
@ress QLesQ.
The @ro<ect will now be rebuilt, and the instruction pointer will start at the first line of code.
#otice how the breakpoint is remembered.
(pening the .atch 1ie8
4pen the (atch window by selecting Q(atchQ from the Q=iewQ menuE
=ariables that are defined $by the .def directive% can be placed in the (atch view. The only
defined variable in this code is the temp variable. -ight&click the Q(atchesQ window and
select Q"dd ItemQ. Type in the variable name temp at the cursor and then press the 'nter key.
"s we continue to run through the program the temp variable will constantly be updated
during program execution.
/etting up the Processor 1ie8
#ow we will examine the @rocessor view. 4pen this view by right clicking in the toolbar area
and select Q@rocessorQE
This view shows processor specific information like the value of the @rogram !ounter. In this
view you will also find a !ycle !ounter and a Stop(atch. These are very useful if you wish
to measure the length of a loop or how much time a specific subroutine uses. (e will not use
this view directly in this example, but it provides a lot of useful information during
debugging of a pro<ect. Lou can also view the contents of the individual registers.
/a9ing the ProCect
.efore exiting "=- Studio we will save our pro<ect. "=- Studio will remember where the
views are placed and will use this setting when opening the pro<ect later. To save the pro<ect
select QSave @ro<ectQ from the Q@ro<ectQ menu.
41
C%AP&E'-D
Code 1ision A1' (C1A1'"
"n I:' has following functionsE
K @reprocessing
K !ompilation
K "ssembly
K 9inking
K 4b<ect Translation
K Text 'ditor
If we <ust use compiler and linker independently we still need to get a text editor.
So combining everything will actually mess things up. So the best way is to get So f twa r e
which has it all. That+s called an Integrated :evelopment 'nvironment, in short I:'.
I consider !ode&=ision&"=- to be the best I:' for getting started with "=-
programming on (indows O@, =ista. It has a very good !ode (izard which generate codes
automatically S Lou need not mess with the assembly words. So in all my tutorials I will be
using !="=-. Lou can download evaluation version for free which has code size limitation
but good enough for our purpose.
)or all my examples I will be using "tmega&/; as default microcontroller because it
very easily available and is powerful enough with sufficient number of pins and peripherals
we use.
9et+s take a look on the software. The main window looks like following,
#ow click on )i le &&&\ #ew &&&\@ro<ect
42
" pop up window will come asking whether you want to use !ode (izard "=-, obviously
select yes because that is the reason we are using !="=- S
#ow have a look on this (izard. It has many tabs where we can configure @4-TS,
TI5'-S, 9!:, ":! etc. I am explaining some of them
!HI@E Select the chip for which you are going to write the program. Then select the
freuency at which !hip is running. .y default all chips are set on Internal 4scillator of /
5Hz so select / 5Hz if that is the case. If you want to change the running clock freuency of
the chip then you have to change its fuse bits $I will talk more about this in fuse bits section%.
P('&$
@4-T is usually a collection of 1 pins.
)rom this tab you can select which pin you want to configure as output and which as input. It
basically writes the ::- and @4-T register through this setting. -egisters are
basically -"5 locations which configure various peripherals of microcontroller and by
changing value of these registers we can change the function it is performing. I will talk more
about registers later. "ll the details are provided in the datasheet.
So you can configure any pin as output or input by clicking the box.
)or "tmega&/; which has > @orts we can see > tabs each corresponding to one @ort. Lou
can also set initial value of the @ins you want to assign. or if you are using a pin as input then
whether you want to make it as pull&up or tristated, again I will talk in details about these
functions later.
Similarly using this code wizard you can very easily configure all the peripherals on the
"tmega.
#ow for generating code <ust go to )i le &&&&\ ,enerate, Save and 'xit $of the code wizard%
#ow it will ask you name and location for saving three files. Two being pro<ect files and one
being the.! file which is your program. try to keep same names of all three files to avoid
confusion. .y default these files are generated in !EX!="=-Xbin
The generated program will open in the text editor. Have a look it has some declarations
like @4-T, ::-, T!!-2 and many more. These are all registers which configures various
functions of "tmega and by changing these value we make different functions. "ll the
details about the registers are commented <ust below them. #ow go down and find
following infinite while loop there. (e can start writing our part of program <ust before
the while loop. "nd as for most of the applications we want microcontroller to perform the
same task forever we put our part of code in the infinite while loop provided by the code
wizard S
while $/%
]
33 @lace your code here
^*
43
^
See how friendly this code wizard is, all the work $configuring registers% automatically
done and we don+t even need to understand and go to the details about registers too S
#ow we want to generate the hex file, so first compile the program. 'ither press )0 or go to
@ro<ect &&&\ !ompile.
It will show compilation errors if any. If program is error free we can proceed to making of
hex file. So either press ShiftV)0 or go to @ro<ect &&&&\ 5ake. " pop up window will come
with information about code size and flash usage etc.
So the machine file is ready now S It is in the same folder where we saved those 7 files.
44
C%AP&E'-E
A1' In-/:ste; Progra;;ing
E.1Introduction
In&System @rogramming allows programming and reprogramming of any "=-
microcontroller positioned inside the end system. Csing a simple Three&wire S@I interface,the
In&System @rogrammer communicates serially with the "=- microcontroller,reprogramming
all non&volatile memories on the chip.
In&System @rogramming eliminates the physical removal of chips from the system.This will
save time, and money, both during development in the lab, and when updating the software or
parameters in the field.
This application note shows how to design the system to support In&System @rogramming. It
also shows how a low&cost In&System @rogrammer can be made, that will allow the target
"=- microcontroller to be programmed from any @! euipped with a regular 0&pin serial
port. "lternatively, the entire In&System @rogrammer can be builtinto the system allowing it
to reprogram itself.
E.&he Progra;;ing Interface
)or In&System @rogramming, the programmer is connected to the target using as few wires as
possible. To program any "=- microcontroller in any target system, a simple Six&wire
interface is used to connect the programmer to the target @!.. )igure below shows the
connections needed.
The Serial @eripheral Interface $S@I% consists of three wiresE Serial !locD $S!D%, 5aster In B
Slave 4ut $5IS4% and 5aster 4ut B Slave In $54SI%. (hen programming the "=-, the In&
System @rogrammer always operate as the 5aster, and the target system always operate as
the Slave.
The In&System @rogrammer $5aster% provides the clock for the communication on the S!D
9ine. 'ach pulse on the S!D 9ine transfers one bit from the @rogrammer $5aster% to the
Target $Slave% on the 5aster 4ut B Slave In $54SI% line. Simultaneously,each pulse on the
S!D 9ine transfers one bit from the target $Slave% to the @rogrammer $5aster% on the 5aster
In B Slave 4ut $5IS4% line.
45
To assure proper communication on the three S@I lines, it is necessary to connect ground on
the programmer to ground on the target $,#:%.
To enter and stay in Serial @rogramming mode, the "=- microcontroller reset line has to be
kept active $low%. "lso, to perform a !hip 'rase, the -eset has to be pulsed to end the !hip
'rase cycle. To ease the programming task, it is preferred to let the programmer take control
of the tar&get microcontroller reset line to automate this process using a fourth control line
$-eset%.
To allow programming of targets running at any allowed voltage $8.? & ;.2 =%, the
programmer can draw power from the target system $=!!%. This eliminate the need for a
separate power sup&ply for the programmer. "lternatively, the target system can be supplied
from the programmer at programming time, eliminating the need to power the target system
through its regular power connector for the duration of the programming cycle.
)igure below shows the connector used by this In&System @rogrammer to connect to the
target system. The standard connector supplied is a 8 x 7 pin header contact, with pin spacing
of /22 mils
E.3%ard8are )esign Considerations
To allow In&System @rogramming of the "=- microcontroller, the In&System @rogrammer
must be able to override the pin functionality during programming. This section describes the
details of each pin used for the programming operation.
3N)
The In&System @rogrammer and target system need to operate with the same reference
voltage. This is done by connecting ground of the target to ground of the programmer. #o
special consid&erations apply to this pin.
'E/E&
The target "=- microcontroller will enter Serial @rogramming mode only when its reset line
is active $low%. (hen erasing the chip, the reset line has to be toggled to end the erase cycle.
To simplify this operation, it is recommended that the target reset can be controlled by the In&
Sys&tem @rogrammer.
Immediately after -eset has gone active, the In&System @rogrammer will start to
communicate on the three dedicated S@I wires S!D, 5IS4, and 54SI. To avoid driver
contention, a series resistor should be placed on each of the three dedicated lines if there is a
possibility that external circuitry could be driving these lines. The connection is shown in
)igure 7. The value of the resistors should be chosen depending on the circuitry connected to
46
the S@I bus. #ote that the "=- microcontroller will automatically set all its I34 pins to
inputs, with pull ups disabled, when -eset is active.
To avoid problems, the In&System @rogrammer should be able to keep the entire Target
System -eset for the duration of the programming cycle. The target system should never
attempt to drive the three S@I lines while -eset is active.
/C>
(hen programming the "=- in Serial mode, the In&System @rogrammer supplies clock
information on the S!D pin. This pin is always driven by the programmer, and the target
system should never attempt to drive this wire when target reset is active. Immediately after
the -eset goes active, this pin will be driven to zero by the programmer. :uring this first
phase of the programming cycle, keeping the S!D 9ine free from pulses is critical, as pulses
47
will cause the target "=- to loose synchronization with the programmer. (hen in
synchronization, the second byte $U67%,will echo back when issuing the third byte of the
programming enable instruction. If the U67 did not echo back, give -eset a positive pulse,
and issue a new @rogramming 'nable command.
#ote that all four bytes of the of the @rogramming 'nable command must be sent before
starting a new transmission.
The target "=- microcontroller will always set up its S!D pin to be an input with no pull up
whenever -eset is active. See also the description of the -eset wire.
The minimum low and high periods for the Serial !lock $S!D% input are defined in the
programming section of the datasheet. )or the "T02S/822 they are defined as followsE
9owE \/ OT"9/ clock cycle
HighE \> OT"9/ clock cycles
M(/I
(hen programming the "=- in Serial mode, the In&System @rogrammer supplies data to the
target on the 54SI pin. This pin is always driven by the programmer, and the target system
should never attempt to drive this wire when target reset is active.
The target "=- microcontroller will always set up its 54SI pin to be an input with no pull
up whenever -eset is active. See also the description of the -eset wire. 5IS4 (hen -eset is
applied to the target "=- microcontroller, the 5IS4 pin is set up to be an input with no pull
up. 4nly after the M@rogramming 'nableN command has been correctly transmitted to the
target will the target "=- microcontroller set its 5IS4 pin to become an output. :uring this
first time, the In&System programmer will apply its pull up to keep the 5IS4 line stable until
it is driven by the target microcontroller.
1CC
(hen programming the target microcontroller, the programmer outputs need to stay within
the ranges specified in the :! !haracteristics.
To easily adapt to any target voltage, the programmer can draw all power reuired from the
tar& get system. This is allowed as the In&System @rogrammer will draw very little power
from the target system, typically no more than 82 m". The programmer shown in this
application note operates in this mode.
"s an alternative, the target system can have its power supplied from the programmer
through the same connector used for the communication. This would allow the target to be
programmed without applying power to the target externally.
(CAN"
48
C%AP&E'-1!
C()E
1!.1&rans;itter1 code$
_include Iavr3io.h\
_include Iavr3interrupt.h\
_include Iutil3delay.h\
_include Istdio.h\
_include Iinttypes.h\
_include Istring.h\
_define @-I#T$string, ...% printf`@$@ST-$string%, __``="`"-,S``%
_define setbit$@ort,.it% ]@ort ab$/II.it%*^ 335acro to set a port bit
_define clrbit$@ort,.it% ]@ort cb d$/II.it%*^ 335acro to clear a port bit
_include Qlcd.hQ
_include Qmcp86/6.hQ
_include Qmcp86/6`defs.hQ
_include Qglobal.hQ
_include Qdefaults.hQ
_include Qadc.hQ
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR3
void spi`reset$void%*
void mcp86/6`write`register$char addr, char data%*
char mcp86/6`read`register$char addr%*
char spi`putc$char val%*
void :'9"L`7S'!$void%*
49
uint1`t mcp86/6`send`message7$t!"# Rmessage7%*
int Temperatute*
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR3
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR3
void mcp86/6`bit`modify$uint1`t adress, uint1`t mask, uint1`t data%
]
clrbit$@4-T.,>%*
spi`putc$S@I`.IT`54:I)L%*
spi`putc$address%*
spi`putc$mask%*
spi`putc$data%*
setbit$@4-T.,>%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
uint1`t mcp86/6`read`status$uint1`t type%
]
uint1`t data*
clrbit$@4-T.,>%*
spi`putc$type%*
data b spi`putc$2x22%*
setbit$@4-T.,>%*
return data*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
bool mcp86/6`init$void%
]
S'T`I#@CT$5!@86/6`I#T%*
S'T$5!@86/6`I#T%*
S@!- b 2b2/2/2222*
50
S@S-b/*
spi`reset$%*
mcp86/6`write`register$2x2f,2x12%*
tempbmcp86/6`read`register$2x2e%*
printf$QXncontrol regbeOQ,temp%*
33 wait a little bit until the 5!@86/6 has restarted
`delay`us$/2%*
33 load !#)/..7 -egister
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'%*
spi`putc$!#)7%*
spi`putc$$/II@HS',8/%%* 3
33 .itrate /86 kbps at /; 5Hz
spi`putc$$/II.T954:'%a$/II@HS',//%%*
spi`putc$$/II.-@8%a$/II.-@/%a$/II.-@2%%*
setbit$@4-T.,>%*
33 test if we could read back the value b\ is the chip accessiblef
if $mcp86/6`read`register$!#)/% Sb $$/II.-@8%a$/II.-@/%a$/II.-@2%%% ]
return false*
^
33 set TOn-TS as inputs
mcp86/6`write`register$TO-TS!T-9, 2%*
33 reset device to normal mode
mcp86/6`write`register$!"#!T-9, 2%*
`delay`ms$/2%*
tempbmcp86/6`read`register$2x2e%*
printf$QXnnormal modebeOQ,temp%*
return true*
^
51
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void spi`reset$%
]
clrbit$@4-T.,>%*
S@:- b 2b//222222*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S- b 2*
setbit$@4-T.,>%*

^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void mcp86/6`write`register$char addr, char data%
]
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222/2*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b data*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S-b 2*
setbit$@4-T.,>%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
char mcp86/6`read`register$char addr%
]
52
unsigned char data*
33 set chip select low
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222//*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b 2x22*
while$ S$ S@S- c $/IIS@I)% % % *
data b S@:-*
33 set chip select high
setbit$@4-T.,>%*
return data*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
char spi`putc$char val%
]
S@:- bval*
while$ S$ S@S- c $/IIS@I)% % % *
S@S- b2*
return S@:-*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
33 check if there are any new messages waiting
uint1`t mcp86/6`check`message$void% ]
tempbmcp86/6`read`register$2x72%*
printf$QXnTransmit control reg in check msgbeOXnQ,temp%*
return $SIS`S'T$5!@86/6`I#T%%*
53
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
33 check if there is a free buffer to send messages
bool mcp86/6`check`free`buffer$void%
]
uint1`t status b mcp86/6`read`status$S@I`-'":`ST"TCS%*
if $$status c 2x6>% bb 2x6>% ]
33 all buffers used
return false*
^
return true*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
uint1`t mcp86/6`send`message$t!"# Rmessage%
]
uint1`t status b mcp86/6`read`status$S@I`-'":`ST"TCS%*
printf$QdatabexQ,status%*
3R StatusbyteE
R .it )unction
R 8 TO.2!#T-9.TO-'H
R > TO./!#T-9.TO-'H
R ; TO.8!#T-9.TO-'H
R3uint1`t address*
33mcp86/6`write`register$TO.2!T-9,2x27%*
if $bit`is`clear$status, 8%%
]address b 2x22*
@-I#T$QIn Transmit .uffer 2 modeXnXnQ%*
^
else if $bit`is`clear$status, >%%
54
]
address b 2x28*
@-I#T$QIn Transmit .uffer / modeXnXnQ%*
^
else if $bit`is`clear$status, ;%%
]
address b 2x2>*
@-I#T$QIn Transmit .uffer 8 modeXnXnQ%*
^
else ]
33 all buffer used b\ could not send message
return 2*
^
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'`TO a address%*
spi`putc$message&\id \\ 7%*
spi`putc$message&\id II 6%*
spi`putc$2%*
spi`putc$2%*
uint1`t length b message&\header.length c 2x2f*
if $message&\header.rtr%
]
33 a rtr&frame has a length, but contains no data
spi`putc$$/II-T-% a length%*
^
33 set message length
spi`putc$length%*
33 data
for $uint1`t ib2*iIlength*iVV%
55
]
spi`putc$message&\datagiT%*
^
setbit$@4-T.,>%*
clrbit$@4-T.,>%*
33 send message
address b $address bb 2% f / E address*
spi`putc$S@I`-TS a address%*
setbit$@4-T.,>%*
return address*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
uint1`t mcp86/6`send`message/$t!"# Rmessage/%
]
uint1`t status b mcp86/6`read`status$S@I`-'":`ST"TCS%*
printf$QdatabexQ,status%*
3R StatusbyteE
R
R .it )unction
R 8 TO.2!#T-9.TO-'H
R > TO./!#T-9.TO-'H
R ; TO.8!#T-9.TO-'H
R33
uint1`t address*
mcp86/6`write`register$TO.2!T-9,2x27%*
if $bit`is`clear$status, 8%%
]
address b 2x22*
@-I#T$QIn Transmit .uffer 2 modeXnXnQ%*
56
^
else if $bit`is`clear$status, >%%
]
address b 2x28*
@-I#T$QIn Transmit .uffer / modeXnXnQ%*
^
else if $bit`is`clear$status, ;%%
]
address b 2x2>*
@-I#T$QIn Transmit .uffer 8 modeXnXnQ%*
^
else ]
33 all buffer used b\ could not send message
return 2*
^
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'`TO a address%*
spi`putc$message/&\id \\ 7%*
spi`putc$message/&\id II 6%*
spi`putc$2%*
spi`putc$2%*
uint1`t length b message/&\header.length c 2x2f*
if $message/&\header.rtr%
]
33 a rtr&frame has a length, but contains no data
spi`putc$$/II-T-% a length%*
^
33 set message length
57
spi`putc$length%*
33 data
for $uint1`t ib2*iIlength*iVV%
]
spi`putc$message/&\datagiT%*
^
setbit$@4-T.,>%*
clrbit$@4-T.,>%*
33 send message
address b $address bb 2% f / E address*
spi`putc$S@I`-TS a address%*
setbit$@4-T.,>%*
return address*
^
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR3
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void :'9"L`7S'!$void%
]
long int i*
for$ib&0000*iIb2x0000*iVV%*
^
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void hex8ascii$int T`d%
]
58
ones b T`de/2*
tensbT`d3/2*
lcd`data`out$tensV2x72%*
onesbonesV2x72*
lcd`data`out$ones%*
lcd`data`out$PcP%*
^
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
=oid welcome`message$void%
]
lcd`9ine/$%*
lcd`string$Q!"# Transmitter _/Q%*
lcd`9ine8$%*
lcd`string$Q T'5@'-"TC-' Q%*
`delay`ms$8222%*
^
unsigned char sb2,vb2*
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
33 Hauptprogram
int main$void%
]
::-" b 2xfe*
::-: b 2xff*
::-. b 2xff*
33::-!b2x))*
59
lcd`init$%*
33 ::-. b 2b/2///22/*
setbit$@4-T.,>%*
sei$%*
welcome`message$%*
3R&&&&&&mcp86/6 initilization&&&&&&&&R3
if $Smcp86/6`init$%%
]
33 @-I#T$QXn mcp 86/6 not initilizedXnQ%*
for $**%*
^
else
]
33 @-I#T$QXn 5!@86/6 is activeXnQ%*
lcd`clr$%*
^
t!"# message,message/,message7*
adc`init$%*
mcp86/6`bit`modify$!"#!T-9,$/II-'H4@8%a$/II-'H4@/%a$/II-'H4@2%, 2%*
message.id b 2xaa*
message.header.rtr b 2*
message.header.length b 8*
message/.id b 2xbb*
message/.header.rtr b 2*
message/.header.length b 1*
message7.id b 2xba*
message7.header.rtr b 2*
60
message7.header.length b 1*
3R&&&&&&&&&&&&&&&&&&&&&&&&&&R3
while$/%
]
Temperatutebadc`convert$%*
lcd`cmnd`out$2x12%*
lcd`string$QT'5@'-"TC-'E Q%*
hex8ascii$Temperatute%*
message.datag2T b Temperatute3/2*
message.datag/T b Temperatutee/2*
mcp86/6`send`message$cmessage%*
mcp86/6`check`message$%*
mcp86/6`send`message/$cmessage/%*
mcp86/6`check`message$%*
^
return 2*
^
61
1!. -C)
_include Iavr3io.h\
_include Iutil3delay.h\
_include Icompat3ina02.h\
3R_define -S 7 33port:
_define -( / 33port.
_define '# 8 33port.R3
3R
_define -S 7 33port:
_define -( / 33port.
_define '# 8 33port.R3
_define 9!: @4-T"
_define setbit$@ort,.it% ]@ort ab$/II.it%*^ 335acro to set a port bit
_define clrbit$@ort,.it% ]@ort cb d$/II.it%*^ 335acro to clear a port bit
void lcd`data`out$char%*
void lcd`cmnd`out$char%*
void lcd`init$void%*
void lcd`string$char Rptr%*
void lcd`char$char byte%*
void lcd`clr$void%*
void lcd`9ine/$void%*
void lcd`9ine8$void%*
void lcd`9ine7$void%*
void lcd`9ine>$void%*
void lcd`init$void%
]
lcd`cmnd`out$2x81%*
62
lcd`cmnd`out$2x81%*
lcd`cmnd`out$2x81%*
lcd`cmnd`out$2x2;%*
lcd`cmnd`out$2x2c%*
lcd`cmnd`out$2x2/%*
33 lcd`cmnd`out$2x12%*
^
void lcd`cmnd`out$char a%
]
9!: b $$a c 2x)2% a 2x2>%*
9!: b 2x22*
9!: b $$a II >% a 2x2>%*
9!: b 2x22*
`delay`ms$/2%*
^
void lcd`data`out$char val%
]
9!: b $$val c 2x)2% a 2x2!%*
9!: b 2x22*
9!: b $$val II >% a 2x2!%*
9!: b 2x22*
`delay`ms$/2%*
^
void lcd`string$char Rptr%
]
while$Rptr%
]
lcd`char$Rptr%*
ptrVV*
63
^
^
void lcd`char$char byte%
]
lcd`data`out$byte%*
^
void lcd`clr$void%
]
lcd`cmnd`out$2x2/%*
^
void lcd`9ine/$void%
]
lcd`cmnd`out$2x12%*
^
void lcd`9ine8$void%
]
lcd`cmnd`out$2xc2%*
^
void lcd`9ine7$void%
]
lcd`cmnd`out$2x0>%*
^
void lcd`9ine>$void%
]
lcd`cmnd`out$2x:>%*
^
64
1!.3&rans;itter code
_include Iavr3io.h\
_include Iavr3interrupt.h\
_include Iavr3pgmspace.h\
_include Iutil3delay.h\
_include Istdio.h\
_include Iinttypes.h\
_define @-I#T$string, ...% printf`@$@ST-$string%, __``="`"-,S``%
_define setbit$@ort,.it% ]@ort ab$/II.it%*^ 335acro to set a port bit
_define clrbit$@ort,.it% ]@ort cb d$/II.it%*^ 335acro to clear a port bit
_include Qlcd.hQ
_include Quart.cQ
_include Qmcp86/6.hQ
_include Qmcp86/6`defs.hQ
_include Qglobal.hQ
_include Qdefaults.hQ
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRR3
unsigned char tempb2*
unsigned char :temp*
void spi`reset$void%*
void mcp86/6`write`register$char addr, char data%*
char mcp86/6`read`register$char addr%*
char spi`putc$char val%*
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRR3
static int putchar``$char c, )I9' Rstream% ]
uart`putc$c%*
65
return 2*
^
static )I9' mystdout b ):'=`S'TC@`ST-'"5$putchar``, 2, `):'=`S'TC@`(-IT'%*
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRR3
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRR3
void mcp86/6`bit`modify$uint1`t adress, uint1`t mask, uint1`t data%
]
clrbit$@4-T.,>%*
spi`putc$S@I`.IT`54:I)L%*
spi`putc$adress%*
spi`putc$mask%*
spi`putc$data%*
setbit$@4-T.,>%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
uint1`t mcp86/6`read`status$uint1`t type%
]
uint1`t data*
clrbit$@4-T.,>%*
spi`putc$type%*
data b spi`putc$2x22%*
setbit$@4-T.,>%*
return data*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
bool mcp86/6`init$void%
]
66
S'T`I#@CT$5!@86/6`I#T%*
S'T$5!@86/6`I#T%*
S@!- b 2b2/2/2222*
S@S-b/*
spi`reset$%*
mcp86/6`write`register$2x2f,2x12%*
tempbmcp86/6`read`register$2x2e%*
printf$QXncontrol regbeOQ,temp%*
33 wait a little bit until the 5!@86/6 has restarted
`delay`us$/2%*
33 load !#)/..7 -egister
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'%*
spi`putc$!#)7%*
spi`putc$$/II@HS',8/%%* 33 .itrate /86 kbps at /; 5Hz
spi`putc$$/II.T954:'%a$/II@HS',//%%*
spi`putc$$/II.-@8%a$/II.-@/%a$/II.-@2%%*
setbit$@4-T.,>%*
33 test if we could read back the value b\ is the chip accessiblef
if $mcp86/6`read`register$!#)/% Sb $$/II.-@8%a$/II.-@/%a$/II.-@2%%% ]
return false*
^
33 set TOn-TS as inputs
mcp86/6`write`register$TO-TS!T-9, 2%*
33 reset device to normal mode
mcp86/6`write`register$!"#!T-9, 2%*
`delay`ms$/2%*
tempbmcp86/6`read`register$2x2e%*
printf$QXnnormal modebeOQ,temp%*
67
return true*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void spi`reset$%
]
clrbit$@4-T.,>%*
S@:- b 2b//222222*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S- b 2*
setbit$@4-T.,>%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void mcp86/6`write`register$char addr, char data%
]
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222/2*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b data*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S-b 2*
setbit$@4-T.,>%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
char mcp86/6`read`register$char addr%
68
]
unsigned char data*
33 set chip select low
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222//*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b 2x22*
while$ S$ S@S- c $/IIS@I)% % % *
data b S@:-*
33 set chip select high
setbit$@4-T.,>%*
return data*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
char spi`putc$char val%
]
S@:- bval*
while$ S$ S@S- c $/IIS@I)% % % *
S@S- b2*
return S@:-*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
33 check if there are any new messages waiting
uint1`t mcp86/6`check`message$void% ]
tempbmcp86/6`read`register$2x72%*
printf$QXnTransmit control reg in check msgbeOXnQ,temp%*
69
return $SIS`S'T$5!@86/6`I#T%%*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
33 check if there is a free buffer to send messages
bool mcp86/6`check`free`buffer$void%
]
uint1`t status b mcp86/6`read`status$S@I`-'":`ST"TCS%*
if $$status c 2x6>% bb 2x6>% ]
33 all buffers used
return false*
^
return true*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
uint1`t mcp86/6`send`message8$t!"# Rmessage8%
]
uint1`t status b mcp86/6`read`status$S@I`-'":`ST"TCS%*
printf$QdatabexQ,status%*
3R StatusbyteE
R
R .it )unction
R 8 TO.2!#T-9.TO-'H
R > TO./!#T-9.TO-'H
R ; TO.8!#T-9.TO-'H
R3
uint1`t address*
33 mcp86/6`write`register$TO.2!T-9,2x27%*
if $bit`is`clear$status, 8%%
]
70
address b 2x22*
@-I#T$QIn Transmit .uffer 2 modeXnXnQ%*
^
else if $bit`is`clear$status, >%%
]
address b 2x28*
@-I#T$QIn Transmit .uffer / modeXnXnQ%*
^
else if $bit`is`clear$status, ;%%
]
address b 2x2>*
@-I#T$QIn Transmit .uffer 8 modeXnXnQ%*
^
else ]
33 all buffer used b\ could not send message
return 2*
^
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'`TO a address%*
spi`putc$message8&\id \\ 7%*
spi`putc$message8&\id II 6%*
spi`putc$2%*
spi`putc$2%*
uint1`t length b message8&\header.length c 2x2f*
if $message8&\header.rtr%
]
33 a rtr&frame has a length, but contains no data
spi`putc$$/II-T-% a length%*
^
71
33 set message length
spi`putc$length%*
33 data
for $uint1`t ib2*iIlength*iVV%
]
spi`putc$message8&\datagiT%*
^
setbit$@4-T.,>%*
clrbit$@4-T.,>%*
33 send message
address b $address bb 2% f / E address*
spi`putc$S@I`-TS a address%*
setbit$@4-T.,>%*
return address*
^
void :oorStatus$void%
]
:temp b @I#!*
:temp b :temp c 2x2f*
switch$:temp%
]
case 2x22E
lcd`9ine/$%*
lcd`string$Q"ll :oors 4pen Q%*
break*
case 2x2/E
lcd`9ine/$%*
lcd`string$Q)r )l .l 4pen Q%*
break*
72
case 2x28E
lcd`9ine/$%*
lcd`string$Q)l .l )r open Q%*
break*
case 2x27E
lcd`9ine/$%*
lcd`string$Q)l .l open Q%*
break*
case 2x2>E
lcd`9ine/$%*
lcd`string$Q)l .r )r open Q%*
break*
case 2x26E
lcd`9ine/$%*
lcd`string$Q)l .r open Q%*
break*
case 2x2;E
lcd`9ine/$%*
lcd`string$Q)l )r open Q%*
break*
case 2x2?E
lcd`9ine/$%*
lcd`string$Q)l open Q%*
break*
case 2x21E
lcd`9ine/$%*
lcd`string$Q.l .r )r open Q%*
break*
case 2x20E
73
lcd`9ine/$%*
lcd`string$Q.l .r open Q%*
break*
case 2x2"E
lcd`9ine/$%*
lcd`string$Q.l )r open Q%*
break*
case 2x2.E
lcd`9ine/$%*
lcd`string$Q.l open Q%*
break*
case 2x2!E
lcd`9ine/$%*
lcd`string$Q.r )r open Q%*
break*
case 2x2:E
lcd`9ine/$%*
lcd`string$Q.r open Q%*
break*
case 2x2'E
lcd`9ine/$%*
lcd`string$Q)r open Q%*
break*
case 2x2)E
lcd`9ine/$%*
lcd`string$Q"ll :oors !lose Q%*
break*
^
74
^
void welcome`message$void%
]
lcd`9ine/$%*
lcd`string$Q!"# Transmitter_8Q%*
lcd`9ine8$%*
lcd`string$Q :oor Status Q%*
`delay`ms$6222%*
^
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRR3
3
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
RRRR3
int main$void%
]
::-! b 2x22*
::-" b 2xff*
::-: b 2xff*
::-. b 2xff*
lcd`init$%*
t!"# message8*
33 Initialisiere die C"-T Schnittstelle
uart`init$C"-T`."C:`S'9'!T$0;22C9, )`!@C%%*
setbit$@4-T.,>%*
sei$%*
33 Cmleiten der Standardausgabe b\ ab <etzt koennen wir printf$% verwenden
stdout b cmystdout*
welcome`message$%*
33 =ersuche den 5!@86/6 zu initilaisieren
75
if $Smcp86/6`init$%%
]
@-I#T$QXn mcp 86/6 not initilizedXnQ%*
for $**%*
^
else ]
@-I#T$QXn 5!@86/6 is activeXnQ%*
lcd`clr$%*
^
@-I#T$Q!an @ro<ectXnQ%*
33 einige Testwerte
message8.id b 2xcc*
message8.header.rtr b 2*
message8.header.length b 1*
@-I#T$Q#ormal 5odeXnXnQ%*
mcp86/6`bit`modify$!"#!T-9, $/II-'H4@8%a$/II-'H4@/%a$/II-'H4@2%, 2%*
while$/%
]
:oorStatus$%*
message8.datag2T b :temp*
if $mcp86/6`send`message8$cmessage8%%
]
@-I#T$Qmessage sendXnQ%*
^
else
]
@-I#T$Qmessage failedXnQ%*
^
if $mcp86/6`check`message$%%
76
]
^
^
return 2*
^z
1!.6'ecei9er Code
_include Iavr3io.h\
_include Iavr3interrupt.h\
_include Iavr3pgmspace.h\
_include Icompat3deprecated.h\
_include Iutil3delay.h\
_include Istdio.h\
_include Iinttypes.h\
_define @-I#T$string, ...% printf`@$@ST-$string%, __``="`"-,S``%
_define setbit$@ort,.it% ]@ort ab$/II.it%*^ 335acro to set a port bit
_define clrbit$@ort,.it% ]@ort cb d$/II.it%*^ 335acro to clear a port bit
_include Qlcd.hQ
_include Quart.cQ
_include Qmcp86/6.hQ
_include Qmcp86/6`defs.hQ
_include Qglobal.hQ
_include Qdefaults.hQ
unsigned char tempb2,:temp*
void spi`reset$void%*
void mcp86/6`write`register$char addr, char data%*
char mcp86/6`read`register$char addr%*
char spi`putc$char val%*
void delay`7sec$void%*
77
uint1`t mcp86/6`get`message/$t!"# R%*
void print`can`message/$t!"# R%*
void :isplay`names$void%
]
lcd`9ine/$%*
lcd`string$Q !"# -eciver Q%*
lcd`9ine8$%*
lcd`string$Q Section Q%*
^
void print`can`message$t!"# Rmessage%
]
uint1`t length b message&\header.length*
@-I#T$QidE 2xe7xXnQ, message&\id%*
@-I#T$QlengthE edXnQ, length%*
@-I#T$QrtrE edXnQ, message&\header.rtr%*
if $Smessage&\header.rtr%
]
@-I#T$QTimeE Q%*
for $uint1`t i b 2* i I length* iVV%
]
@-I#T$Qec Q, message&\datagiT%*
^
^
^
void print`can`message8$t!"# Rmessage%
]
uint1`t length b message&\header.length*
@-I#T$QidE 2xe7xXnQ, message&\id%*
@-I#T$QlengthE edXnQ, length%*
78
@-I#T$QrtrE edXnQ, message&\header.rtr%*
if $Smessage&\header.rtr%
@-I#T$Q:oorE Q%*
for $uint1`t i b 2* i I length* iVV%
]
@-I#T$Qex Q, message&\datagiT%*
^
:tempbmessage&\datag2T*
switch$:temp%
]
case 2x22E
lcd`9ine8$%*
lcd`string$Q"ll :oors 4pen Q%*
break*
case 2x2/E
lcd`9ine8$%*
lcd`string$Q)r )l .l 4pen Q%*
break*
case 2x28E
lcd`9ine8$%*
lcd`string$Q)l .l )r open Q%*
break*
case 2x27E
lcd`9ine8$%*
lcd`string$Q)l .l open Q%*
break*
case 2x2>E
lcd`9ine8$%*
lcd`string$Q)l .r )r open Q%*
79
break*
case 2x26E
lcd`9ine8$%*
lcd`string$Q)l .r open Q%*
break*
case 2x2;E
lcd`9ine8$%*
lcd`string$Q)l )r open Q%*
break*
case 2x2?E
lcd`9ine8$%*
lcd`string$Q)l open Q%*
break*
case 2x21E
lcd`9ine8$%*
lcd`string$Q.l .r )r open Q%*
break*
case 2x20E
lcd`9ine8$%*
lcd`string$Q.l .r open Q%*
break*
case 2x2"E
lcd`9ine8$%*
lcd`string$Q.l )r open Q%*
break*
case 2x2.E
lcd`9ine8$%*
lcd`string$Q.l open Q%*
break*
80
case 2x2!E
lcd`9ine8$%*
lcd`string$Q.r )r open Q%*
break*
case 2x2:E
lcd`9ine8$%*
lcd`string$Q.r open Q%*
break*
case 2x2'E
lcd`9ine8$%*
lcd`string$Q)r open Q%*
break*
case 2x2)E
lcd`9ine8$%*
lcd`string$Q"ll :oor !lose Q%*
break*
^
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void print`can`message/$t!"# Rmessage%
]
uint1`t length b message&\header.length*
@-I#T$QidE 2xe7xXnQ, message&\id%*
@-I#T$QlengthE edXnQ, length%*
@-I#T$QrtrE edXnQ, message&\header.rtr%*
@-I#T$QXnQ%*
@-I#T$Q:ateE Q%*
for $uint1`t i b 2* iIlength*iVV% ]
@-I#T$Qec Q, message&\datag$i%T%*
81
^
^
void print`can`message7$t!"# Rmessage%
]
uint1`t length b message&\header.length*
@-I#T$QidE 2xe7xXnQ, message&\id%*
@-I#T$QlengthE edXnQ, length%*
@-I#T$QrtrE edXnQ, message&\header.rtr%*
@-I#T$QXnQ%*
@-I#T$QTempE Q%*
for $uint1`t i b 2* iIlength*iVV% ]
@-I#T$Qec Q, message&\datag$i%T%*
^
^
static int putchar``$char c, )I9' Rstream% ]
uart`putc$c%*
return 2*
^
static )I9' mystdout b ):'=`S'TC@`ST-'"5$putchar``, 2, `):'=`S'TC@`(-IT'%*
3RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR3
void mcp86/6`bit`modify$uint1`t adress, uint1`t mask, uint1`t data%
]
clrbit$@4-T.,>%*
spi`putc$S@I`.IT`54:I)L%*
spi`putc$adress%*
spi`putc$mask%*
spi`putc$data%*
setbit$@4-T.,>%*
^
82
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
uint1`t mcp86/6`read`status$uint1`t type%
]
uint1`t data*
clrbit$@4-T.,>%*
spi`putc$type%*
data b spi`putc$2x22%*
setbit$@4-T.,>%*
return data*
^
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
bool mcp86/6`init$void%
]
S'T`I#@CT$5!@86/6`I#T%*
S'T$5!@86/6`I#T%*
S@!- b 2b2/2/2222*
S@S-b/*
spi`reset$%*
mcp86/6`write`register$2x2f,2x12%*
tempbmcp86/6`read`register$2x2e%*
printf$QXncontrol regbeOQ,temp%*
33 wait a little bit until the 5!@86/6 has restarted
`delay`us$/2%*
33 load !#)/..7 -egister
clrbit$@4-T.,>%*
spi`putc$S@I`(-IT'%*
spi`putc$!#)7%*
spi`putc$$/II@HS',8/%%* 33 .itrate /86 kbps at /; 5Hz
spi`putc$$/II.T954:'%a$/II@HS',//%%*
83
spi`putc$$/II.-@8%a$/II.-@/%a$/II.-@2%%*
33 activate interrupts
spi`putc$$/II-O/I'%a$/II-O2I'%%*
setbit$@4-T.,>%*
33 test if we could read back the value b\ is the chip accessiblef
if $mcp86/6`read`register$!#)/% Sb $$/II.-@8%a$/II.-@/%a$/II.-@2%%% ]
return false*
^
33 deaktivate the -On.) @ins $High Impedance State%
mcp86/6`write`register$.)@!T-9, 2%*
33 set TOn-TS as inputs
33 mcp86/6`write`register$TO-TS!T-9, 2%*
33 turn off filters b\ receive any message
mcp86/6`write`register$-O.2!T-9, $/II-O5/%a$/II-O52%%*
mcp86/6`write`register$-O./!T-9, $/II-O5/%a$/II-O52%%*
33 reset device to normal mode
mcp86/6`write`register$!"#!T-9, 2%*
`delay`ms$/2%*
tempbmcp86/6`read`register$2x2e%*
printf$QXnnormal modebeOQ,temp%*
return true*
^3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void spi`reset$%
]
clrbit$@4-T.,>%*
S@:- b 2b//222222*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S- b 2*
84
setbit$@4-T.,>%*
^
void mcp86/6`write`register$char addr, char data%
]
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222/2*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b data*
while$ S$ S@S- c $/IIS@I)% % % *
33 clear S@I) flag
S@S-b 2*
setbit$@4-T.,>%*
^
char mcp86/6`read`register$char addr%
]
unsigned char data*
33 set chip select low
S@!- b 2b2/2/2222*
clrbit$@4-T.,>%*
S@:- b 2b222222//*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b addr*
while$ S$ S@S- c $/IIS@I)% % % *
S@:- b 2x22*
while$ S$ S@S- c $/IIS@I)% % % *
data b S@:-*
85
33 set chip select high
setbit$@4-T.,>%*
return data*
^
char spi`putc$char val%
]
S@:- bval*
while$ S$ S@S- c $/IIS@I)% % % *
S@S- b2*
return S@:-*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
33 check if there are any new messages waiting
uint1`t mcp86/6`check`message$void% ]
tempbmcp86/6`read`register$2x72%*
printf$QXnTransmit control reg in check msgbeOXnQ,temp%*
return $SIS`S'T$5!@86/6`I#T%%*
^
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
uint1`t mcp86/6`get`message$t!"# Rmessage%
]
33 read status
uint1`t status b mcp86/6`read`status$S@I`-O`ST"TCS%*
uint1`t addr*
33 printf$QXn satus regbeOQ,status%*
if $bit`is`set$status,;%%
]
33 message in buffer 2
86
addr b S@I`-'":`-O*
printf$QXnmessage in buffer 2Q%*
^
else if $bit`is`set$status,?%%
]
33 message in buffer /
addr b S@I`-'":`-O a 2x2>*
printf$QXnmessage in buffer /Q%*
^
else
]
33 'rrorE no message available
printf$QXn'rrorE no message availableQ%*
return 2*
^
clrbit$@4-T.,>%*
spi`putc$addr%*
33 read id
message&\id b $uint/;`t% spi`putc$2xff% II 7*
message&\id ab spi`putc$2xff% \\ 6*
spi`putc$2xff%*
spi`putc$2xff%*
33 read :9!
uint1`t length b spi`putc$2xff% c 2x2f*
message&\header.length b length*
message&\header.rtr b $bit`is`set$status, 7%% f / E 2*
33 read data
for $uint1`t ib2*iIlength*iVV% ]
87
message&\datagiT b spi`putc$2xff%*
^
setbit$@4-T.,>%*
33 clear interrupt flag
if $bit`is`set$status, ;%%
]
mcp86/6`bit`modify$!"#I#T), $/II-O2I)%, 2%*
^
else
]
mcp86/6`bit`modify$!"#I#T), $/II-O/I)%, 2%*
^
return $status c 2x2?% V /*
^
3R&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&R3
void delay`7sec$void%
]
long int i*
for$ib2*iIb2x0000*iVV%*
^
33 &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
33 Hauptprogram
int main$void%
]
33 Initialisiere die C"-T Schnittstelle
uart`init$C"-T`."C:`S'9'!T$0;22C9, )`!@C%%*
::-" b 2x))*
::-. b 2xff*
88
::-!b2xff*
3R sbi$@4-T",reset%*
`#4@$%*
`#4@$%*
cbi$@4-T",reset%*
`#4@$%*
`#4@$%*
sbi$@4-T",reset%*R3
lcd`init$%*
33 lcd`!lr$%*
:isplay`names$%*
`delay`ms$622%*
33 lcd`!lr$%*
33 disp`string$Q!"# -eceiverQ%*
33 "ktiviere Interrupts
33 ::-. b 2b/2///22/*
setbit$@4-T.,>%*
sei$%*
33 Cmleiten der Standardausgabe b\ ab <etzt koennen wir printf$% verwenden
stdout b cmystdout*
33 =ersuche den 5!@86/6 zu initilaisieren
if $Smcp86/6`init$%%
]
@-I#T$QXn mcp 86/6 not initilizedXnQ%*
lcd`9ine/$%*
lcd`string$Qnot initilizedQ%*
for $**%*
^
else ]
89
@-I#T$QXn 5!@86/6 is activeXnQ%*
lcd`9ine/$%*
lcd`string$Q initilizedQ%*
^
t!"# message*
mcp86/6`bit`modify$!"#!T-9, $/II-'H4@8%a$/II-'H4@/%a$/II-'H4@2%, 2%*
lcd`clr$%*
while $/%
]
if $mcp86/6`check`message$%%
]
if $mcp86/6`get`message$cmessage%%
]
uint1`t length b message.header.length*
33print`can`message$cmessage%*
if$message.idbb2xaa%
]
print`can`message$cmessage%*
lcd`9ine/$%*
lcd`string$QTemperatureE Q%*
for $uint1`t i b 2* i I length* iVV%
]
lcd`data`out$message.datagiTV2x72%*
^
lcd`data`out$PcP%*
^
^
if$message.idbb2xcc%
90
]
print`can`message8$cmessage%*
^
^
^
return 2*
^
91
/C%EMA&IC
% T & ' R ( ) A * A + A + ( 1
M E S S A G E S T R E A M W I T H C A N
C
1 1 T h , r s d a y - . e b r , a r y 1 / - ! 0 1 0
T i t l e
S i z e D o 1 , m e n t N , m b e r R e 2
D a t e : S h e e t o f
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C 3 C C 3 C C 3 C C
3 C C
3 C C
3 C C
3 C C
3 C C 3 C C
3 C C 1 ! 3
1 ! 3
1 ! 3
1 ! 3
1 ! 3
3 C C
1 ! 3
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
3 C C
T # D
R # D
T " ) 4 5 D A T A
T " ) 4 5 C * 6
C A N 5 S C 6
C A N 5 C S
C A N 5 ' N T
C A N 5 ) 7 S '
C A N 5 ) ' S 7
. ( A * 0
. ( A * !
. ( A * 1
A D C 5 C & 1
A D C 5 C & 0
C A N 5 ) 7 S '
C A N 5 ) ' S 7
C A N 5 ) 7 S '
C A N 5 ) ' S 7
C A N 5 S C 6
C A N 5 S C 6
C A N 5 C S
S D 5 C S
S D 5 ) 7 S '
S D 5 C * 6
S D 5 ) ' S 7
T " ) 4 5 C * 6
T " ) 4 5 D A T A
D 8
D 9
D :
D !
D 0
D ;
D 1
D <
A D C 5 C & 0
A D C 5 C & 1
T # D
R # D
R T C 5 D A T A
R T C 5 C * 6
C A N 5 ' N T
' N T " R R ( 4 T
T # D
R # D
S D 5 C S
S D 5 ) 7 S '
S D 5 C * 6
S D 5 ) ' S 7
T " ) 4 5 C * 6
T " ) 4 5 D A T A
D ;
D <
D :
D 9
D 8
D !
D 1
D 0
' N T " R R ( 4 T
C A N 5 ' N T
R T C 5 D A T A
R T C 5 C * 6
C A N 5 C S
C A N 5 S C 6
C A N 5 ) ' S 7
C A N 5 ) 7 S '
' N T " R R ( 4 T
R T C 5 C * 6
R T C 5 D A T A
' N T " R R ( 4 T
A D C 5 C & 9
A D C 5 C & :
A D C 5 C & <
A D C 5 C & ;
A D C 5 C & 8
A D C 5 C & !
S D 5 ) ' S 7
S D 5 C S
S D 5 ) 7 S '
S D 5 C * 6
A D C 5 C & 0
A D C 5 C & 1
A D C 5 C & !
A D C 5 C & 8
A D C 5 C & 9
A D C 5 C & :
A D C 5 C & <
A D C 5 C & ;
D 0
D 1
D 8
D !
D 0
D 1
D !
D 8
7 4 5 A ) 4 1
7 4 5 A ) 4 !
7 4 5 A ) 4 8
7 4 5 A ) 4 9
7 4 5 A ) 4 1
7 4 5 A ) 4 !
7 4 5 A ) 4 8
7 4 5 A ) 4 9
R S T
R S T
( !
A T M E G A 3 2
$
1 /
1 $
! 0
! $
8
0
8
1
9 0
1
!
8
9
:
<
;
/
! 1 ! !
! 8
! 9
! :
! <
! ;
! /
1
0
1
1
1 !
1 8
1 9
1 :
1 <
1 ;
8 $
8 /
8 ;
8 <
8 :
8 9
8 8
8
!
R S T
4 D 9 = 7 C 1 + )
4 D : = 7 C 1 A )
4 D < = ' C 4 1 )
4 C ; = T 7 S C ! )
A
3
C
C
>
N
D
4 A 0 ? A D C 0
4 + 0 = # C 6 ? T 0 )
4 + 1 = T 1 )
4 + ! = ' N T ! ? A ' N 0 )
4 + 8 = 7 C 0 ? A ' N 1 )
4 + 9 = S S )
4 + : = ) 7 S ' )
4 + < = ) ' S 7 )
4 + ; = S C 6 )
4 D ; = 7 C ! ) 4 C 0 = S C * )
4 C 1 = S D A )
4 C ! = T C 6 )
4 C 8 = T ) S )
4 C 9 = T D 7 )
4 C : = T D ' )
4 C < = T 7 S C 1 )
3
C
C
>
N
D
# T A * !
# T A * 1
4 D 0 = R # D )
4 D 1 = T # D )
4 D ! = ' N T 0 )
4 D 8 = ' N T 1 )
4 A 1 ? A D C 1
4 A ! ? A D C !
4 A 8 ? A D C 8
4 A 9 ? A D C 9
4 A : ? A D C :
4 A < ? A D C <
4 A ; ? A D C ;
A
R
"
.
+
-
( 1 A
* ) 8 ! 9
8
!
1
9
1
1
C
R 1 $
1 0 6
1
! 8 9 : < ; / $
C 1 $
1 0 , . ? ! : 3
C 1 1
1 0 0 4 .
C ! 1 ! ! 4 .
C 1 / ! ! 4 .
% 8
8 ! ; < / @ A
( 8
L 2 9 3 D
!
;
1 0
1 :
1 $
8
<
1 1
1 9
1
<
/
9:1
8
1
!
1 A
! A
8 A
9 A
1
-!
"
N
8
-9
"
N
1 %
! %
8 %
9 %
3
C
C
1
3
C
C
!
>
N
D
>
N
D
>
N
D
>
N
D
C !
0 1 , .
B 1
M O T O R 3
1
!
B 8
M O T O R 4
1
!
B 4 8
B ( ) 4 " R
1 !
R ! 1 1 6
D !
1 N 9 0 0 ;
1 !
B 1 /
C 7 N 1 0 A 4
1
8
:
;
$
!
9
<
/
1 0
1
8
:
;
$
!
9
<
/
1 0
( ;
M A X 2 3 2
1 8
/
1 1
1 0
1
8
9
:
!
<
1 !
$
1 9
;
1
<
1
:
R 1 ' N
R ! ' N
T 1 ' N
T ! ' N
C C
C 1 -
C ! C
C ! -
3
C
3
-
R 1 7 ( T
R ! 7 ( T
T 1 7 ( T
T ! 7 ( T 3
C
C
>
N
D
C ! <
1 0 , . ? ! : 3
C ! !
0 1 , .
C ! ;
1 0 , . ? ! : 3
+
-
( 1 +
* ) 8 ! 9
:
<
;
9
1
1
B 9
P O R T A
1
!
8
9
:
<
;
/
( 1 0
L M 7 8 0 5
1
!
8
3 ' N
>
N
D
3 7 ( T
C
R :
1 0 6
1
! 8 9 : < ; / $
+ T 1
8 8 3
1
!
B 1 1
C 7 N !
1
!
R 9
1 0 6
1
8
!
C ! :
0 1 , .
( <
S H T 1 x
9
1
8
!
:
<
;
/
3
D
D
>
N
D
C * 6
D A T A
N C
N C
N C
N C
B 1 ;
C 7 N !
1
!
( $
L M 7 8 1 2
1
!
8
3 ' N
>
N
D
3 7 ( T
B $
P O R T B
1
!
8
9
:
<
;
/
C
R 1 ;
1 0 6
1
! 8 9 : < ; / $
( /
D S 1 8 0 ; 9
;
:
1
!
<
8
/
>
N
D
S D E ? 7 ( T
S D A
# 1
# !
S C * 6
3 + A T
3
C
C
B ;
C 7 N 8
1
!
8
R 1 <
1 0 6
R 1 9
1 0 6
C 1 ;
0 1 , .
C <
0 1 , .
+
-
( 1 D
* ) 8 ! 9
1 !
1 8
1 9
9
1
1
C $
0 1 , .
( 1 1
A T ! 9 C ! : <
1
!
8
9
:
<
;
/
A 0
A 1
A !
> N D
S D A
S C * 6
E 4
3
C
C
-
+
D :
+ R ' D > "
!
1
8
9
S E 8
7 N ? 7 . . S E ' T C &
1 !
B ! 1
C 7 N !
1
!
R 8
1 0 6
B 1 8
C & A N N " * 1
1
!
8
D 9
8 ) )
B ! 8
C 7 N !
1
!
D <
* " D
R ! 8
8 8 0 "
B 1 9
I / O P I N
1
!
8
R 1
1 0 6
1
8
!
R ! 9
! ! 0 &
+
-
( 1 C
* ) 8 ! 9
1 0
$
/
9
1
1
C ! 8
1 0 , . ? ! : 3
B ! 9
C 7 N !
1
!
B 1 <
C 7 N !
1
!
C ! /
0 1 , .
4 1
D - T % 4 " . e m a l e
:
$
9
/
8
;
!
<
1
B ! :
C 7 N !
1
!
C ! 9
0 1 , .
D 8
8 ) )
R ! ! 9 ; 6
B ! <
C 7 N !
1
!
C 1 :
1 0 , . ? ! : 3
C : ! ! 4 .
C 9 ! ! 4 .
% 1
1 < ) h z
B 1 :
S D C A R D
1
!
8
9
:
<
;
/
$
B 4 :
B ( ) 4 " R
1 !
B ! !
C 7 N !
1
!
B ! 0
C 7 N !
1
!
B !
L C D
1
!
8
$
:
1 0
1 1
1 !
1 8
1 9
9
<
;
/
1 :
1 <
R 1 0
1 0 @
R $
1 0 @
B 1 $
C 7 N !
1
!
C 8
1 0 , . ? ! : 3
S E 1 R S T S E
1 !
R <
1 0 6
C 1 <
0 1 , .
S E ! R S T S E
1 !
B 1 !
P O R T C
1
!
8
9
:
<
;
/
R !
1 0 6
1
8
!
R 1 8
1 0 @
R 1 1
1 0 @
R 1 !
1 0 @
B <
P O R T D
1
!
8
9
:
<
;
/
C
R /
1 0 6
1
! 8 9 : < ; / $
R ! 0
1 0 0 "
D 1
8 ) )
C ! 0
1 0 , . ? ! : 3
( 9
M C P 2 5 1 5
1
!
8
9
:
<
;
/
$
1 0
1 1
1 !
1 8
1 9
1 :
1 <
1 ;
1
/
T # C A N
R # C A N
C * 6 7 ( T ? S 7 .
T # 0 R T S
T # 1 R T S
T # ! R T S
7 S C !
7 S C 1
3
S
S
R # 1 + .
R # 0 + .
' N T
S C 6
S '
S 7
C S
R " S " T
3
D
D
B :
C 7 N 9
1
!
8
9
( :
M C P 2 5 5 1
1
!
8
9
:
<
;
/
T # D
3
S
S
3
D
D
R # D
3 R " .
C A N *
C A N &
R S
R 1 /
< 0 "
B 4 ! 1 !
B 4 1 1 !
B /
C & A N N " * !
1
!
8
B 4 9 1 !
B 1 0
C 7 N !
1
!
R ! : 1 6
R ! < 1 6
C /
1 0 , . ? ! : 3
R 1 :
/ ! 6
C 1 9
0 1 , .
C 1 0
0 1 , .
C ;
0 1 , .
C 1 8 ! ! 4 .
C 1 ! ! ! 4 .
% !
! : ) h z
C 1
0 1 , .
R ;
1 0 6
1
8
!
P O W E R S U P P L Y
C A N C O N T R O L L E R & T R N S C E I V E R
S E R I A L C O M M U N I C A T I O N
F U A L I N D I C A T O R
A D C C H A N N E L S
T E M P R A T U R E & H U M I D I T Y S E N S O R
S P I I N S Y S T E M P R O G R A M M I N G
92
93
C(NC-*/I(N
In this pro<ect we had measured the temperature and door status of the car by using !"#
$!ontroller "rea #etwork%protocol. It can also extended to -T!$-eal Time !ontrol%,
window status of the car,5@7 player status etc.
!"# $!ontroller "rea #etwork% is a serial bus system. !"# was originally designed for
automotive applications and it is a serial bus system especially suited for networking
QintelligentQ devices as well as sensors and actuators within a machine or plant. :ue to its
excellent technical and commercial properties !"# is used today in a wide range of
applications, eg. 5obile systems, machine and auto mobiles.
94
BIB-I(3'AP%0
'effered Boo@s
/."=- 5I!-4!4#T-499'-
& "T5'9
8.!"#
&54T4-49"
7.!"#
&.4S!H
>. !"#open
&H. .oterenbrood
6.!"# TCT4-I"9
&"T5'9
'effered -in@s
/.(((.(IDI@':I".!45
8.(((.,44,9'.!45
7.(((."T5'9.!45
95

You might also like