Coa New1

QUESTION BANK II - CSE
Ms.B.NIRMALA ASST.PROFESSOR/CSE
Dr. NAVALAR NEDUNCHEZHIYAN COLLEGE OF ENGINEERING
THOLUDUR 606 303, CUDDALORE DIST
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
ANNA UNIVERSITY CHENNAI
YEAR: II / SEM IV
CS2253 COMPUTER ORGANIZATION AND ARCHITECTURE
(Common to CSE and IT)
UNIT I BASIC STRUCTURE OF COMPUTERS 9
Functional units Basic operational concepts Bus structures Performance and metrics Instructions and
instruction sequencing Hardware Software interface Instruction set architecture Addressing modes
RISC CISC ALU design Fixed point and floating point operations.
UNIT II BASIC PROCESSING UNIT 9
Fundamental concepts Execution of a complete instruction Multiple bus organization Hardwired control
Micro programmed control Nano programming.
UNIT III PIPELINING 9
Basic concepts Data hazards Instruction hazards Influence on instruction sets
Data path and control considerations Performance considerations Exception
handling.
UNIT IV MEMORY SYSTEM 9
Basic concepts Semiconductor RAM ROM Speed Size and cost Cache memories Improving cache
performance Virtual memory Memory management requirements Associative memories Secondary
storage devices.
UNIT V I/O ORGANIZATION 9
Accessing I/O devices Programmed I/O Interrupts Direct memory access Buses Interface Circuits
Standard I/O interfaces (PCI, SCSI, and USB) I/O Devices and processors.
L: 45 T: 15 Total: 60
TEXT BOOKS
1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization, 5th Edition, Tata Mc-Graw
Hill, 2002.
2. Heuring, V.P. and Jordan, H.F., Computer Systems Design and Architecture, 2nd Edition, Pearson
Education, 2004.
REFERENCES
1.Patterson, D. A., and Hennessy, J.L., Computer Organization and Design: The Hardware/Software
Interface, 3rd Edition, Elsevier, 2005.
2. William Stallings, Computer Organization and Architecture Designing for Performance, 6th Edition,
Pearson Education, 2003.
3. Hayes, J.P., Computer Architecture and Organization, 3rd Edition, Tata Mc-Graw Hill, 1998.


SUBJECT CODE: CS2253
SUBJECT NAME: COMPUTER ORGANIZATION AND ARCHITECTURE

UNIT 1 -BASIC STRUCTURE OF COMPUTERS
PART-A (1 MARKS)
1. A collection of 8 bits is called
a. byte b. word c. record d. file
2. The ascending order or a data Hierarchy is
a. bit - bytes - fields - record - file database b. bit - bytes - record - field - file - database
c. bytes - bit- field - record - file database d. bytes -bit - record - field - file - database
3. How many address lines are needed to address each memory locations in a 2048 x 4 memory
chip?
a. 10 b. 11 c. 8 d. 12
4.A computer program that converts an entire program into machine language at one time is called
a/an
a. interpreter b. simulator c. compiler d. commander
5.In immediate addressing the operand is placed
a. in the CPU register b. after OP code in the instruction c. in memory d. in stack
6.Microprocessor 8085 can address location upto
a. 32K b. 128K c. 64K d. 1M
7.The ALU and control unit of most of the microcomputers are combined and manufacture on a
single silicon chip. What is it called?
a. monochip b. microprocessor c. ALU d. control unit
8.What does ICMP stand for?
1) Internet Connection Modem Protocol 2) Intranet Control Message Program
3) Internal Conflict Management Program 4) Internet Control Message Protocol
9.A microporgram is sequencer perform the operation
a. read b. write c. execute d. read and write e. read and execute
10.Interrupts which are initiated by an I/O drive are
a. internal b. external c. software d. all of above
11.Processors of all computers, whether micro, mini or mainframe must have
a. ALU b. Primary Storage c. Control unit d. All of above
12.What is the control unit's function in the CPU?
a. To transfer data to primary storage b. to store program instruction
c. to perform logic operations d. to decode program instruction
13.What is meant by a dedicated computer?
a. which is used by one person only b. which is assigned to one and only one task
c. which does one kind of software d. which is meant for application software only
14.The most common addressing techiniques employed by a CPU is
a. immediate b. direct c. indirect d. register e. all of the above
15.Pipeline implement
a. fetch instruction b. decode instruction c. fetch operand d. calculate operand
e. execute instruction f. all of abve
16.Which of the following code is used in present day computing was developed by IBM
corporation?
a. ASCII b. Hollerith Code c. Baudot code d. EBCDIC code
17.When a subroutine is called, the address of the instruction following the
CALL instructions stored in/on the
a. stack pointer b. accumulator c. program counter d. stack

18.A microprogram written as string of 0's and 1's is a
a. symbolic microinstruction b. binary microinstruction c. symbolic microprogram
d. binary microprogram
19.Interrupts which are initiated by an instruction are
a. internal b. external c. hardware d. software
20.Memory access in RISC architecture is limited to instructions
a. CALL and RET b. PUSH and POP c. STA and LDA d. MOV and JMP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
a a b c b c b c e b d d b e f d d d b c

PART B (2 MARKS)
21. Write the basic functional units of computer? [A.U.APR/MAY10]
The basic functional units of a computer are input unit, output unit, memory unit, ALU unit and control unit.
22. Define ALU. What are the various operations performed in ALU? [A.U.APR/MAY 06]
ALU is a part of computer that performs all arithmetic and logical operations. It is a component of central
processing unit. Arithmetic operations: Addition, subtraction, multiplication, division, increment and decrement;
Logical operations: AND, OR, XOR, NOT, compare, shift, rotate.-
23. Compute the effective CPI for a processor, for the following instruction mix: [A.U.APR/MAY 07][A.U.
APR/MAY 2012]
Instruction type Clock cycle count Frequency
ALU operations 140
Loads 320
Stores 210
Branches taken 320
Branches untaken 210
An enhancement to the processor is made by adding a branch prediction unit. This decreases the number of Cycles
taken to execute a branch from 3 to 2.
24. What is a bus? What are the different buses in a CPU? [A.U.APR/MAY O8] [A.U. APR/MAY 2011]
A group of lines that serve as a connecting path for several devices is called bus .The different buses in a CPU are
1] Data bus 2] Address bus 3] Control bus
25. Why data bus is bidirectional and address bus is unidirectional in most microprocessor?
Data bus: The data bus consists of 8, 16, 32 or more parallel signal lines. These lines are used to send data to
Memory and output ports, and to receive data from memory and input port. Therefore, data bus lines are
bidirectional. This means that CPU can read data on these lines from memory or from a port, as well as send data
out of these lines to a memory location or to a port. The data bus is connected in parallel to all peripherals. The
communication between peripherals and CPU is activated by giving output enable pulse to the peripherals. Outputs
of peripherals are floated when they are not in use.
Address bus: It is a unidirectional bus. The address bus consists of 16, 20, 24 or more parallel signal lines. On these
lines the CPU sends out the address of the memory location or IO port that is to be written to or read from. Here, the
Communication is one-way, the address is send from CPU to memory and IO port and hence these lines are
unidirectional.
26. What is meant by stored program concepts? Discuss. [A.U.APR/MAY O9]
Stored program concept is an idea of storing the program and data in the memory.
27. Define multiprogramming?(A.U.APR/MAY 2013)
Multiprogramming is a technique in several jobs are in main memory at once and the processor is switched from job
as needed to keep several jobs advancing while keeping the peripheral devices in use.
28. Define multiprocessing? [A.U.APR/MAY O8]
Multiprocessing is the ability of an operating system to support more than one process at the same time.
29. Define time sharing?
Time sharing is the process in which the system is designed to allow many users to use the CPU simultaneously.
30. What is a super computer? [A.U.NOV/DEC 2007]
A computer with high computational speed, very large memory and expansive parallel structured hardware is
Known as a super computer.

EX: CDC 6600
31. What is meant by VLSI technology? [A.U.APR/MAY 07]
VLSI is the abbreviation for Very Large Scale Integration. In this technology millions of transistors are put inside a
single chip as tiny components. The VLSI chips do the function of millions of transistors. These are Used to
implement parallel algorithms directly in hardware.
32. What are the characteristics of Von Neumann computers? [A.U.APR/MAY09]
* The program can data were represented in digital form and stored in the memory.
* The architecture has 5 basic parts -> the memory, the ALU, Control Unit, Input unit and output unit.
* It uses binary arithmetic.
* There were only fixed point arithmetic and no floating point arithmetic.
* used a special general purpose register called Accumulator.
* The first general purpose machine.
33. Define parallel processing. [A.U.APR/MAY O8] (A.U.APR/MAY 2013)
It is an efficient form of information processing to exploit the concurrent events in the computing process.
34. Define pipelining. [A.U. APR/MAY 2012]
Pipelining is technique of decomposing a sequential process in to number of sub operations and each of these Sub
operations are carried out independently in dedicated segments concurrently.
35. Mention some applications of parallel processing. [A.U.APR/MAY 07]
* In simulation and Modeling -> weather forecasting, oceanography, socio economy
* Engineering design and automation -> Aerodynamics, finite element analysis AI
* Medical, military and research -> computer assisted topography genetic engineering etc
* Energy resource explosion.
36. In what way hardware and software are equivalent? Not equivalent. [A.U.APR/MAY O9]
Software and hardware are logically equivalent. Any operation done by software could be done by hardware. Any
instruction executed by hardware can be simulated by software. They are not equivalent in the sense that, minimum
hardware required to execute software cannot be simulated by software. In other words with out the hardware
software cannot function, whereas with NIL software the hardware function perfectly.
37. Distinguish between hardware and firmware. [A.U.NOV/DEC 2007]
The hardware deals with all electronics and electrical components of a computer.
EX: ICs, diodes, resistors, power supplies, tapes etc
The firmware is embedded software of certain electronic circuits.
EX: ROMBIOS.
38. What is an operating system? [A.U.APR/MAY 07]
System software which acts as an interface between the user and the machine.
39. Define system throughput.
It is defined as the number of instructions executed per unit time (sec).
40. What is mainframe computer?
It is the large computer system containing thousands of ICs. It is a room- sized machine placed in special computer
centers and not directly accessible to average users. It serves as a central computing facility for an organization such
as university, factory or bank.
41. What is mini computer? [A.U.APR/MAY O8]
Minicomputers are small and low cost computers are characterized by
Short word size i.e. CPU word sizes of 8 or 16 bits.
Limited hardware and software facilities.
Physically smaller in size.
42. Define micro computer. [A.U.APR/MAY 06]
Microcomputer is a smaller, slower and cheaper computer packing all the electronics of the computer in to a handful
of ICs, including the CPU and memory and IO chips.
43. What is workstation?
The more powerful desktop computers intended for scientific and engineering applications are referred as
workstations.
44. Write the features of the third generation computers? [A.U.APR/MAY 07]
Pipelining concept was introduced.
Cache memory concept was introduced to close the speed gap between the CPU and main memory

Multiprogramming was introduced.
Time sharing concept was introduced.
Virtual memory concept was introduced to close the speed gap between the CPU and main memory.
Multiprogramming was introduced.
Time sharing concept was introduced.
Virtual memory concept was introduced.
Ex: IBM 360/370, CDC 6600/7600, Texas Instruments ASC (Advanced Scientific Computer), Digital
Equipments PDP-8.
45. What is load store architecture? [A.U.APR/MAY O8]
In a load / store architecture, operands must be in registers before they can be processed. The instructions that refer
to memory Locations are load, store and jump / branch .It supports limited set of addressing modes and use
hardware
To execute instructions.
46. Explain the absolute and auto increment addressing modes with an example instruction.
Absolute or direct addressing: To fetch an operand, the address of the operand in the memory is given in the
instruction. This form is called direct addressing. This type of addressing mode is used for handling STATIC data
Add B=> A = A + M [B] Auto-increment addressing mode: It is similar to register indirect mode except that register
is incremented after its value is used to access memory.
Add R1, (R2) +; R1 <- R1 + M [R2]
R2 <- R2 +d
This type of addressing mode is useful for stepping through arrays in a loop.
R2 start of array d size of an element
47. List out the different computer instruction formats. [A.U.APR/MAY 07]
4 address instruction
Opcode Source opera
Address 1
Source opera
Address 2
Destination opera
Address
Next instructi
address
Opcode Source operand address Source operand address Destination opera
address
Opcode Source destination opera
address
Source operand address 2
Opcode Source operand address
Opcode
48. Explain the following addressing modes with an example: [A.U.APR/MAY O8]
a) Register indirect addressing
b) Relative addressing
Register indirect addressing:
The effective address of the operand is the contents of the register or memory location, whose address appears in the
instruction.
Add R1, R2 [R3] R1 = R2+ [R3] Contents of memory pointed by R3.
Application:
1. used in pointers
R3
Memory

Relative addressing:
The effective address is obtained by adding contents of program counter with displacement.
Effective address = [PC] + displacement
Ex: near, far, short, jump instructions
1. Mem address instruction displacement
1000 near 10
EA for next instruction = [PC] + 10
= 1001 + 10
= 1011
2. Mem address instruction displacement
4000 JC 50
EA = 4001 + 50
= 4051
49. Define index mode. [A.U.NOV/DEC 2007]
In this mode the contents of the index register is added to the address part of the instruction to get the EA of the
operand. The index register is a special purpose CPU register that contains the index value. The address part of the
instruction determines the starting address of the data array in the memory. Each operand in the array is stored in the
memory relative to the starting address of the array. The distance between the starting address of the array and the
location of the operand in the array is the index value present in the index register. Any operand in the array can be
accessed with the same instruction provided that the index register contains thecorrect index value. The index
register can be incremented to facilitate access to the consecutive operands. Some computers dictate one CPU
register to function as index register. This register is involved implicitly when the index mode instruction is used.
USE: The indexed mode is used to access the array type data structure.
50.What is the role of program counter in addressing? [A.U.APR/MAY 07]
In this addressing mode the contents of program counter is added to the address part of the instruction in order to
obtain the EA. When the address part of the instruction is added to the contents of the PC the result produces the EA
whose position is relative to the next instruction.
51. What are the different addressing modes? [A.U.APR/MAY O8]
Direct addressing, indirect addressing, immediate addressing, base addressing, Index addressing, based index
addressing, based indexed with displacement addressing, relative addressing.
52. Compare the stack based architecture with GPR based architecture. [A.U.APR/MAY O9]
Stack based Vs GPR based
Reading a register in GPR architecture does not affect its contents but reading in stack architecture
removes the data form top of the stack.
Lot of over head involved in maintaining temporary variables in the stack.
In stack based architecture the register file stack is invisible to the programmer. Only the top of the
stack is visible. Hence easier to maintain compatibility with future versions.
Instruction lengths are smaller in stack based because the source and destination specifies are not
required. Hence the code length may be smaller
Add R1, R2, [R3] .Operand
53.Consider a two level indirection instruction such as Mov A, [ind], where ind points to the memory
location that contains the address of the operand that needs to be moved to register A. give an application of such
two level indirection.Pointer implementation is made easy with indirection. With two level indirection it is easier to
handle pointer of pointer.
54.What are condition codes? Can a processor be designed without any condition codes? )
[A.U.APR/MAY10]
Condition codes are 1- bit flag that store information regarding the result of various operations.These are used in
conditional branch instructions. They give elegant way of handling the conditional control flow.A processor may be
designed without condition codes, but it must have some other means of handling change in flow control may be
instructions like compare and branch if equal to zero.
55. Which data structures can be best supported using (a) indirect addressing mode (b) indexed addressing
mode? [A.U.APR/MAY O8]
(a) indirect addressing mode pointer data structure.
(b) indexed addressing mode array data structure.

56. What are the four basic types of operations that need to be supported by an instruction set?
Data transfer between memory and the processor register.
Arithmetic and logic operations on data.
Program sequencing and control.
i/o transfer
57. What are the limitations of assembly languages? [A.U.APR/MAY 06]
Limitations of assembly language:
1. Assembly language is processor dependent hence requires knowledge of internal details of processor to write a
program.
2. It is less user friendly than higher level languages.
3. program development is slower than the program development using high level languages.
58. The memory unit of a computer has 256 K words of 32 bits each. The computer has an instruction
format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a memory
address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word.
Total memory size = 256 K * 32 bits= 1024 Kbytes
Address bits = 20
Mode field = 3 bit 2^3 = 8 >7
Register address field = 6 bits 2^6 = 64> 60
Opcode field = 32 - 20 3 6=3 bits.
59. List the steps involved in the instruction execution. [A.U.NOV/DEC 2007]
Fetch the instruction from the memory. Decode the instruction.
Fetch the operands from the memory for executing the instruction Execute the instruction.
Store the results.
60. Explain the various instruction types? [A.U.APR/MAY O9]
Instructions are of many types
Data movement instruction Dyadic operations Monadic operations
Comparisons and conditional jumps Procedure call instruction Loop control
Input / output
61. Explain the various addressing modes. [A.U.APR/MAY O8] (A.U.NOV/DEC 2012)
The general subject of specifying where the operands are is called addressing.
Immediate addressing Direct addressing Register addressing
Relative addressing Indirect addressing Register indirect mode
Multilevel indirect addressing Indexed address mode Base register addressing mode
Auto increment or auto decrement mode Implied addressing Stack addressing
63.What is the improvement in performance ? [A.U.APR/MAY 07]
Speed up =execution time old /execution time new
Execution time old or CPU time=I.C.* Clk Cycles * cycle time
Execution time old =[40*1+20*3+10*2+20*2+10*2]
Cycles*cycles time
The enhancement decreases the number of cycles taken for branch instruction from 3 to 2.
Execution time new =[40*1+20*3+10*2+20*2+10*2] =180 cycles *cycle time
Speed up = (200*cycles time)/(180 cycles *cycles time) =1.1
64.List the basic functional units of a computer?(A.U.MAY/JUNE11) (A.U.NOV/DEC 2012)
The basic functional units of a computer are input unit, output unit, memory unit, ALU unit and control unit.
65.What is meant by MAR and MDR? A.U.MAY/JUNE11)
Memory Address Register (MAR) is a register that either stores the memory address from which data will be
fetched to the CPU or the address to which data will be sent and stored. MAR holds the memory location of data
that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR Used by the
CPU.
PART C (16 -Marks)
66. Explain the basic functional units of a simple computer. (8) [A.U.APR/MAY09] [A.U. APR/MAY 2012]
(A.U.APR/MAY 2013)

67. With a neat diagram explain Von Neumann computer architecture (16) [A.U.NOV/DEC07]
68. Explain various addressing modes found in modern processors (16) ) [A.U.APR/MAY10] [A.U.
APR/MAY 2012]
69. Explain various assembler directives used in assembly language program (8)
[A.U.APR/MAY 07] (A.U.APR/MAY 2013)
70. What are stack and queues? Explain its use and give its differences (10)
71. What are the various types of ISAs possible? Discuss. (8)[ A.U.APR/MAY O8]
72. (i) Explain instruction formats in detail (10) (A.U.NOV/DEC 2012)
(ii) What is a stack and what are the operations on stack? Give any three applications of stack (6)
[A.U.NOV/DEC 2007].
73.Describe how the floating point number are represented and used in digital arithmetic
operations.given example. (A.U.MAY/JUNE11).
74.Write the different between CISC and RISC architecture. (A.U.MAY/JUNE11). (A.U.NOV/DEC 2012)
75.What are the techniques used to measure the performance of a computer .explain each one of them with
necessary formulae. (A.U.MAY/JUNE11).

UNIT 2 --BASIC PROCESSING UNIT
PART-A (1 MARKS)
76.Where does a computer add and compare data?
a. Hard disk b. Floppy disk c. CPU chip d. Memory chip
77.Which of the following registers is used to keep track of address of the memory location where
the next instruction is located?
a. Memory Address Register b. Memory Data Register c. Instruction Register
d. Program Register
78.A complete microcomputer system consists of
a. microprocessor b. memory c. peripheral equipment d. all of above
79.CPU does not perform the operation
a. data transfer b. logic operation c. arithmetic operation d. all of above
80.Pipelining strategy is called implement
a. instruction execution b. instruction prefetch c. instruction decoding d. instruction manipulation
81.A stack is
a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor
c. a set of memory locations in R/WM reserved for storing information temporarily during the
execution of computerd. a 16-bit memory address stored in the program counter
82.A stack pointer is
a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.
b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location
where a subroutine address is stored. d. a register in which flag bits are stored
83.The branch logic that provides decision making capabilities in the control unit is known
a. controlled transfer b. conditional transfer c. unconditional transfer d. none of above
84.Interrupts which are initiated by an instruction are
a. internal b. external c. hardware d. software
85.A time sharing system imply
a. more than one processor in the system b. more than one program in memory c. more than
one memory in the system d. None of above
86. The sampling rate, (how many samples per second are stored) for a CD is...?

a. 48.4 kHz b. 22,050 Hz c. 44.1 kHz d. 48 kHz
87. Compact discs, (according to the original CD specifications) hold how many minutes of music?
a. 74 mins b. 56 mins c. 60 mins d. 90 mins
88. The base 10 (or decimal - our normal way of counting) number 65535 is represented in
hexadecimal as...?
a. 0xFFFFF b. 0xFFFF c. 0xFFF d. 0xFFFFFF
89.Where is the headquarters of Microsoft located?
a. Santa Clara, California b. Tucson, Arizona c. Richmond,Virginia d. Redmond, Washington
90. In what year was the "@" chosen for its use in e-mail addresses?
a. 1976 b. 1972 c. 1980 d. 1984
91. What was the first ARPANET message?
a. "lo" b. "hello world" c. "mary had a little lamb" d. "cyberspace, the final frontier"
92. Where is the headquarters of Intel located?
a. Redmond, Washington b. Tucson, Arizona c. Santa Clara, alifornia d. Richmond, Virginia
93. In which year was MIDI introduced?
a. 1987 b. 1983 c. 1973 d. 197
94. '.BAK' extension refers usually to what kind of file?
a. Backup file b. Audio file c. Animation/movie file d. MS Encarta document
95. '.MPG' extension refers usually to what kind of file?
a. WordPerfect Document file b. MS Office document c. Animation/movie file d. Image file

PART B (2 Marks)
96. In conforming to the IEEE standard mention any four situations under which a process sets exception
flag.
1. Under flow 2. Over flow 3. Divide by Zero 4. Invalid.
97. Why floating point number is more difficult to represent and process than integer? [APR/MAY O9]
In floating point numbers we have to represent any number in three fields sign, exponent and mantissa. The IEEE
754 standard gibes the format for these fields and according to format the numbers are to be represented. In case of
any process we have to consider mantissa and exponent separately. Therefore, floating point numbers are more
difficult to represent and process than integer.
98. What are the advantages and disadvantages of hardwired and micro-programmed control?
[A.U.APR/MAY 06]
Hardwired control Advantages
1. It is implemented using the gates, Flip Flops and hardware circuits. High speed operation and hence execution is
faster
2. Smaller implementation (component counts)
3. Favored approach in RISC style designs.
Disadvantages
1. Complex sequencing and micro operation logic.
2. Difficult to design and test
3. Inflexible design
4. Difficult to add new instructions
Micro-programmed control Advantages
1. It stores the control signals in the sequence in control memory.
2. Modification is simple by modifying the micro program in the control memory.
3. Just read from the control memory every clock cycle
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
c D d d b c a c d b c a b a b a c b a c

4. Favored approach in CISC style designs.
Disadvantages
1. Execution is slow
2. Separate Control memory is used
99. Define hard-wired control? [A.U.APR/MAY 07] [A.U. APR/MAY 2012]
Hard Wired control is a implemented with gates, f-flips decoders and other digital circuits. The goal in hard-wired
design control is to minimize the number of components and maximize the speed of operation.
100. What are the relative advantages and disadvantages of micro-programmed control over
hardwired control? [A.U.APR/MAY09]
Advantages of micro programmed control over hardware control
1. It provides considerable flexibility in implementing instruction sets.
2. It facilitates adding new instructions.
Disadvantages
1. Execution is slower
2. Control memory is needed
101. Define Microinstruction[A.U.APR/MAY O9] [A.U. APR/MAY 2012]
The individual control words in the micro program are usually referred to as microinstruction
102. Faster operations can be achieved by pre-fetching the next micro-instruction, while the current one
being executed. What are the complexities involved in per-fetching the micro instruction.
Whenever the status flags need to e checked to determine the next address of the micro instruction. Complex
hardware is needed to handle such cases.
103. State the differences between hardwired and micro-programmed control unit.
[A.U.APR/MAY O8]
control Micro programmed control
It is implemented using the gates,
Flip Flop and hardwired circuits.
No control memory is used.
Execution is faster.
Modification is difficult.
RISC Machines.
It will be implemented using the micro program stored in the control memory.
Control memory is used.
Execution is slower.
Modification is simple by modifying the micro program in the control memory.
CISC Machines.
104. Why is the Wait-For-memory-Function-Completed step needed when reading from or writing to the
main memory? [A.U.NOV/DEC 2007]
WMFC (Wait-For-memory-Function-Completed) step is required for the write control signal/read control single
cause the memory bus interface hardware to issue a write command / read command on the memory bus. The
processor wait in this process until the memory operation is completed and an WMFC response is received.
105. What are the address sequencing capabilities required in a control memory? (A.U.APR/MAY 2013)
1. Incrementing of the control address register.
2. Unconditional branch as specified by address field of the microinstruction.
3. Conditional branch depending on status bits in register of computer.
4. A facility for sub-routines calls and returns.
106. Discuss the principle of operation of a micro programmed control unit? [A.U.APR/MAY O8]
Microprogramming is a second alternative for designing the control unit of a digital computer. The principle of
microprogramming is an elegant and systematic method for controlling the micro-operation sequences in a digital
computer.
107. What are the types of control organizations we have?
There are two types of control organizations
1. Hardwired control organizations
2. Micro programmed control organization.
108. What is a control word? [A.U.APR/MAY O9] (A.U.APR/MAY 2013)

A control variable which can be represented by a string of 1s and 0s is called a control word.
109. What is micro programmed control unit?
A control unit whose binary control variables are stored in the memory is called a micro programmed control unit.
110. What is a micro instruction? [A.U.APR/MAY 07]
A set of micro operations constitute a micro instruction,
111. What is a micro program? [A.U. APR/MAY 2012]
A set of micro instructions constitute a micro program.
112. What are the differences between the main memory and control memory?
Main Memory Control Memory It is used storing OS routine and user Program. Ordinary user can access the main
memory do modifications.This is larger in size.It is used to store the micro program. Ordinary user can not access
the control memory. Only the designers can do the same. This is smaller in size.
113. What is micro program sequencer? [A.U.APR/MAY09]
The next address generator is also called the micro program sequencer. This will generate the address of the next
microinstruction in the sequence.
114. What is meant by mapping process?
The transformation from the instruction code bits to an address in the control memory where the routine is located is
referenced to as a mapping process.
115. Give the micro instruction format. [A.U.NOV/DEC 2007]
F1 F2 F3 CD BR AD Where
F1, F2, F3 Micro operation fields (3 bits each)
CD Condition for branching (2 bits)
BR Branch field (2 bits)
AD Address field (7 bits).
116. What is a hard wired logic? [A.U.APR/MAY O8]
If a computer is designed to operate based on the control gates, and other hard ware circuitry then it is called hard
wired control logic.
117. What is micro programming? [A.U.APR/MAY 07]
A technique for implementing the control function of the processor in a systematic and a flexible manner is called as
micro programming.
118. What are the advantages and disadvantages of the microprogramming? ) [A.U.APR/MAY10]
Advantages
1. An instruction set can be changed by changing the micro program.
2. Any up gradation to the existing system require only to modify the micro programs.
3. Less costly compared to hard wired logic.
Disadvantages
1. Comparatively slow.
119.define hardware control? A.U.MAY/JUNE11).
Hardware control is a operating system. OS is used to control the elctronic devices(hardware) via user. because user
can't control hardware directly so, OS is used to interface computer & user
120.What is micro programmed control unit? A.U.MAY/JUNE11).
A control unit whose binary control variables are stored in the memory is called a micro programmed control unit.
PART C (16 -Marks)
121. Describe how the floating-point numbers are represented and used in digital arithmetic operations. Give
an example. (16) [A.U.APR/MAY09] [A.U. APR/MAY 2012]
122. Explain the representations of floating point numbers in detail. (6) [A.U.NOV/DEC 07]
123. Give the organization of typical hardwired control unit and explain the functions performed by the
various blocks. (16)[ A.U.NOV/DEC08] (A.U.NOV/DEC 2012) (A.U.APR/MAY 2013)
124. Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to
overcome/minimize these hazards. (16)
125. Explain in detail about instruction execution characteristics. (16) [A.U.APR/MAY09] [A.U. APR/MAY
2012]
126. with a neat block diagram, explain in detail about micro programmed control unit and explain its
operations. (16)[ A.U.NOV/DEC07] (A.U.NOV/DEC 2012)
127. Explain the execution of an instruction with diagram. (8)

128. Explain the multiple bus organization in detail. (8)[ A.U.APR/MAY08] (A.U.APR/MAY 2013)
129. Explain the function of a six segment pipeline showing the time it takes to process eight tasks.
130. Highlight the solutions of instruction hazards. (6)[APR/MAY07]
131. Explain the instruction cycle highlighting the sub-cycles and sequence of steps to be followed.
(8)
132.What are the steps involved in execution of an instruction ?explain the execution of a complete
instruction with diagram. A.U.MAY/JUNE11).
133. Explain the multiple bus organization in detail.(8) A.U.MAY/JUNE11).
UNIT 3-PIPLINING
PART A (1 Marks)
134. '.INI' extension refers usually to what kind of file?
a. Image file b. System file c. Hypertext related file d. Image Color Matching Profile file
135. '.BAT' extension refers usually to what kind of file?
a. Compressed Archive file b. System file c. Audio file d. Backup file
136. '.JPG' extension refers usually to what kind of file?
a. System file b. Animation/movie file c. MS Encarta document d. Image file
137. '.MOV' extension refers usually to what kind of file?
a. Image file b. Animation/movie file c. Audio file d. MS Office document
138. '.TXT' extension refers usually to what kind of file?
a. Text File b. Image file c. Audio file d. Adobe Acrobat file
139. '.TMP' extension refers usually to what kind of file?
a. Compressed Archive file b. Image file c. Temporary file d. Audio file
140. Who created Pretty Good Privacy (PGP)?
a. Paul Zimmerman b. Tim Berners-Lee c. Marc Andreessen d. Ken Thompson
141. Who co-founded Hotmail in 1996 and then sold the company to Microsoft?
a. Shawn Fanning b. Ada Byron Lovelace c. Sabeer Bhatia d. Ray Tomlinson
142. Who co-created the UNIX operating system in 1969 with Dennis Ritchie?
a. Bjarne Stroustrup b. Steve Wozniak c. Ken Thompson d. Niklaus Wirth
143. Who is largely responsible for breaking the German Enigma codes, created a test that provided
a foundation for artificial intelligence?
a. Alan Turing b. Jeff Bezos c. George Boole d. Charles Babbage
144. Who built the world's first binary digit computer: Z1...?
a.Konrad Zuse b. Ken Thompson c. Alan Turing d. George Boole
145. Who developed Yahoo?
a. Dennis Ritchie & Ken Thompson b. David Filo & Jerry Yang c. Vint Cerf & Robert Kahn
d. Steve Case & Jeff Bezos
146. 'DB' computer abbreviation usually means ?
a. Database b. Double Byte c. Data Block d. Driver Boot
147. 'OS' computer abbreviation usually means ?
a. Order of Significance b. Open Software c. Operating System d. Optical Sensor
148. 'DTP' computer abbreviation usually means ?
a. Digital Transmission Protocol b. DeskTop Publishing c. Data Type Programming
d. Document Type Processing
149. 'CD' computer abbreviation usually means ?
a. Command Description b. Change Data c. Copy Density d. Compact Disc
150. What is the term to ask the computer to put information in order numerically or
alphabetically?
a. Crop b. Report c. Record d. Sort
151. What do we call a network whose elements may be separated by some distance? It usually
involves two or more small networks and dedicated high-speed telephone lines.

a. URL (Universal Resource Locator) b. LAN (Local Area Network) c. WAN (Wide
Area Network) d. World Wide Web
152. What do we call a collection of two or more computers that are located within a limited
distance of each other and that are connected to each other directly or indirectly?
a. Inernet b. Interanet c. Local Area Network d. Wide Area Network
153. What is part of a database that holds only one type of information?
a. Report b. Field c. Record d. File

PART-B (2 MARKS)
154. What is the ideal up expected in a pipelined architecture with n stages? Justify your answer.
Ideal Speedup Pipelining
No. of segments k Clock cycle time tp Tasks n
First task T1 requires ktp to complete its operations.
(n-1) tasks (n-1) tp
Total time = [k + (n-1)] tp
Speedup S = ntn /(k + (n-1))tp
If n is large, k + (n-1) becomes n. Therefore
S = ntn/ntp = tn/tp = k = No. of Stages (Since)
155. What is parallel processing? [A.U.APR/MAY O8]
Parallel processing refers to the concept of speeding-up the execution of a program, by dividing the program into
multiple fragments that can execute simultaneously, each on its own processor. A program being executed across n-
processor might execute n-times faster than it would be using a single processor.
156. State the different types of hazard that can occur in a pipeline. [A.U.APR/MAY 06]
Types of hazards in pipeline
Structural hazards:It arises from resource conflicts when the hardware cannot support all possible combination of
instructions in simultaneous overlapped execution.
Data hazards:It arises when an instruction depends on the result of a previous instruction.
Control hazards:It arises from pipelining of branches and other instructions that change the program counter.
157. Define nanoprogramming. [A.U. APR/MAY 2012] (A.U.NOV/DEC 2012)
Micro instructions are stored in the micro memory (control memory). There is a chance that a group of micro
instructions may occur several times in a micro program. As a result the more memory space isneeded.By making
use of the nano memory we can have significant saving in the memory when a group of micro operations occur
several times in a micro program.
158. What is pipelining? [A.U.APR/MAY O9] [A.U.MAY/JUNE 11]
Pipelining is a technique of decomposing a sequential process in to sub processes with each sub process being
executed in a special dedicated segment that operates concurrently with all other programs.
159. How do control instructions like branch, cause problems in a pipelined processor?
Pipelined processor gives the best throughput for sequenced line instruction. In branch instruction, as it has to
calculate the target address, whether the instruction jump from one memory location to other. In the meantime,
before calculating the larger, the next sequence instructions are got into the pipelines, which are rolled back, when
target is calculated.
160. What is meant by super scalar processor? [A.U.APR/MAY 07]
Super scalar processors are designed to exploit more instruction level parallelism in user programs. This means that
multiple functional units are used. With such an arrangement it is possible to start the execution of several
instructions in every clock cycle. This mode of operation is called super scalar execution.
161. Define pipeline speedup. [A.U. APR/MAY 2012] (A.U.NOV/DEC 2012)
Speed up is the ratio of the average instruction time without pipelining to the average instruction time with
pipelining.
Average instruction time without pipelining Speedup= Average instruction time with pipelining
162. What is pipelined computer? [A.U.APR/MAY09]
134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
B b d b a c a c c a a b a c b d d c c b

When hardware is divided in to a number of sub units so as to perform the sub operations in an overlapped fashion
is called as a pipelined computer.
163. List the various pipelined processors.
8086, 8088, 80286, 80386. STAR 100, CRAY 1 and CYBER 205 etc.
164. Classify the pipeline computers. [A.U.APR/MAY O8]
1. Based on level of processing processor pipeline, instruction pipeline, arithmetic pipelines
2. Based on number of functions Uni-functional and multi functional pipelines.
3. Based on the configuration Static and Dynamic pipelines and linear and non linear pipelines
4. Based on type of input Scalar and vector pipelines.
165. Define efficiency of a linear pipeline? [A.U.APR/MAY 06]
Efficiency of a linear pipeline can be defined as percentage of busy time space plan over the total time
-space span. This is equal to sum of all busy and idle time-space spans.
N = [bkT/K[kn + (n-1) T] = n/K + (n-1) Where
N number of tasks. K number of pipeline stages. T clock period of linear pipeline.
166. Define reservation table of a pipeline processor. [A.U.APR/MAY09]
Reservation table represents the flow of data through pipeline for one complete evaluation of a given function.
167. Explain the need of an instruction buffer in a pipelined CPU. [A.U.APR/MAY O8]
R1
S1
R2
S2
R3
Sn
RN
In order to increase the computational speed of the pipeline processor the instructions are fetched in advance and
will be placed in the instruction buffer.
168. Define arithmetic pipeline? Where it is used? [A.U.APR/MAY10] (A.U.APR/MAY 2013)
A pipeline processor which is designed to perform arithmetic operations (fixed point or floating point arithmetic
pipeline) is called arithmetic pipeline. An arithmetic pipeline receives multiple data as inputs and performs the
designated operation on the data. Arithmetic pipelines are used in the high-speed computers where a same type of
operation has to be performed repeatedly on a set of data items.
169. What is Vectorizer? [A.U.APR/MAY 07]
The process to replace a block of sequential code by vector instructions is called vectorization. The system software,
which generates parallelism, is called as vectorizing compiler.
170. Write down the expression for speedup factor in a pipelined architecture.
[A.U.MAY/JUNE 11]
The speedup for a pipeline computer is
S = (k + n -1) tp Where,
K number of segments in a pipeline
N number of instructions to be executed.
Tp cycle time
171. Explain the delayed branch concept. [A.U.APR/MAY O8]
When a branch instruction is encountered it delays the pipeline operation until the instruction at the branch address
is fetched. The method used in most RISC processors is to rely on the compilers to redefine the branches so that
they take at proper time in the pipeline. This method is called delayed branch.
172. What are the problems faced in instruction pipeline. [A.U.APR/MAY O9]
Resource conflicts Caused by access to the memory by two at the same time. Most of the conflicts can be
resolved by using separate instruction and data memories.
Data dependency Arises when an instruction depends on the results of the previous instruction but this result is
not yet available.
Branch difficulties Arises from branch and other instruction that change the value of PC (Program Counter).

P Pa ar rt t C C ( (1 16 6 - -M Ma ar rk ks s) )

173. Explain the multiple bus organization structure with neat diagram. [A.U.APR/MAY09] [A.U.
APR/MAY 2012]
174. Describe the Hardwired control method for generating the control signals.
Describe the micro programmed control unit in detail. [A.U.NOV/DEC 07] (A.U.NOV/DEC 2012)
175.Give the organization of the internal data path of a processor that supports a
4-stage pipeline for instructions and uses a 3- bus structure and discuss the same.
[ A.U.NOV/DEC08] (A.U.NOV/DEC 2012) (A.U.APR/MAY 2013)
176.What is pipelining? What are the various hazards encountered in pipelining? [A.U.APR/MAY10]
(A.U.APR/MAY 2013)
177. Describe the three mapping techniques used in cache memories with suitableExample. [A.U.APR/MAY 07]
[A.U. APR/MAY 2012]
178. Explain with neat diagram the internal organization of bit cells in a memory [A.U.MAY/JUNE 11]
UNIT 4 ---MEMORY SYSTEM
PART A (1 Marks)

179.The window which shows icons for things like the mouse, sound, and display is...?
a. My Computer b. Explorer c. Control Panel d. Taskbar
180.On the Task bar the time is shown in the...?
a. Start menu b. Scrollbar c. Desktop d. Notification area or Tray
181.Experts say the healthiest way to view a computer monitor is by...
a. Placing it 18 to 30 inches away from your eyes b. Viewing from a darkened room
c. Adjusting the screen for maximum contrast d. Using special glasses that filter out UV rays
182.A dual-layer DVD is valued because it:
a. Can hold more data b. Contains a backup of the data stored c. Uses a second layer to offer a
speed increase d. Creates alternative sound tracks
183.A JPG is...
a. A Jumper Programmed Graphic b. Formats for an image file c. A type of hard disk
d. A unit of measure for memory
184.Windows Vista, the eventual replacement for Windows XP, will demand more from a computer.
Which of the following statements is correct?
a. You'll need at least 512 megabytes of RAM b. A separate graphics card, rather than
onboard graphics, will be required c. A DVD drive is needed d. All the above
185.Your computer has gradually slowed down. What's the most likely cause?
a. Overheating b. Your processor chip is just getting old c. Adware/spyware is
infecting your PC d. You dropped a sandwich in your computer
186.The letters, "DOS" stand for...
a. Data Out System b. Disk Out System c. Disk Operating System d. Data Operating System
187.Changing computer language of 1's and 0's to characters that a person can understand is...
a. Highlight b. Clip art c. Decode d. Execute
188.Hardware devices that are not part of the main computer system and are often added later to the system.
a. Peripheral b. Clip art c. Highlight d. Execute
189.The main computer that stores the files that can be sent to computers that are networked together is...

a. Clip art b. Mother board c. Peripheral d. File server
190.To select text by shading as you drag the mouse arrow over the text is known as...
a. Clip art b. To highlight c. To fetch d. To decode
191.Another word for the CPU is...
a. Execute b. Microprocessor c. Micro chip d. Decode
192.Which of these is not a computer?
a. Aptiva b. Macintosh c. Acorn d. Paseo
193. Which was an early mainframe computer?
a. ENIAC b. UNIC c. BRAINIA d. FUNTRIA
194. Which of the following is not a programming language?
a. Basic b. Java c. Turing d. C#
195. RAM stands for...
a. Random Access Memory b. Really Annoying Machine c. Read A Manual ) Real Absolute
Memory
196. How many bits is a byte?
a. 4 b. 8 c. 16 d. 32
197. Which of the following is NOT a type of expansion slot or bus design used in Advanced-Technology class
systems?
a. PCMCIA b. ISA c. PROM d. EISA
198. Which company created the most used networking software in the 1980's
a. Microsoft b. Sun c. IBM d. Novell
PART B (2 Marks)
199. Distinguish between the write-through and write-back policies pointing out their merits and
Demerits.
When the CPU finds a word in the cache during a read operation the main memory is not involved in the transfer
however if the operation is a write, there are two ways that the system can proceed. The simplest and most
commonly used procedure is to update main memory with every memory write operation with cache memory being
updated in parallel if it contains the word at the specified address. This is called write-through method. This method
has an advantage that main memory always contains the same data as the cache. This care is important in systems
with DMA transfers. This method is simple to implement. This disadvantage is that it requires time to write data in
main memory resulting in traffic. The 2nd procedure is called write-back method. In this method only the cache
location is updated during a write operation. The location is then marked by a flag so that later when the block is
removed from the cache, the changes are copied in to main memory. The disadvantage is that main memory may
contain inconsistent data.
200. What is the necessary of virtual memory? [A.U.APR/MAY09]
Virtual memory is an important concept related to memory management. It is used to increase the apparent size of
main memory at a very low cost. Data are addressed in a virtual address space that can be as large as the addressing
capability of CPU.
201. Define hit ratio. [A.U.APR/MAY 07] (A.U.APR/MAY 2013)
When a processor refers a data item from a cache, if the referenced item is in the cache, then such a reference is
called Hit. If the referenced data is not in the cache, then it is called Miss Hit ratio is defined as the ratio of number
of Hits to number of references. Number of Hits
Hit ratio =Total Number of references
Number of Hits=Hits + Misses
202. What is meant by memory interleaving? Show the distribution of addresses for a memory system
179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198
c d a a b d c c c a d b b d a c a b c d

Consisting of two banks of four 1k memory modules to form an 8k memory system. Give the man memory address
format. The memory interleaving is a more effective way to address memory modules. The low order k bits of the
memory address select a module, and high order m bits name a location within module. Here consecutive addresses
are located in consecutive modules.
M bits K bits MM Address
Total memory = 8k
No. of address lines = 13
Memory Bank 0 Memory Bank 1
(Capacity 1K) (Capacity 1K)
Since we have 2 banks
K bit = 1 (To differentiate bank 0 and bank 1)k bits
For bank selection address in Module
203. What is TLB? What is its significance?
Translation look aside buffer is a small cache incorporated in memory management unit. It consists of page table
entries that correspond to most recently accessed pages. Significance The TLB enables faster address computing
It contains 64 to 256 entries
204. What is virtual memory? [A.U.APR/MAY O8] (A.U.APR/MAY 2013)
Virtual memory is an important concept related to memory management. It is used to increase the apparent size of
main memory at a very low cost. Data are addressed in a virtual address space that can be as large as the addressing
capability of CPU.
205. What is the necessary for memory hierarchy?
Memory hierarchy The major objective of designing memory hierarchy system is to provide adequate storage
capacity with acceptable level of performance at a reasonable cost. Address in Module Module
Module1
ABR
Module 0
Module2k - 1
1k
1k
1k
1k
1k
1k
1k
1k
12 bits 1 bit
206. How cache memory is used to reduce the execution time. ) [A.U.APR/MAY10]
If active portions of the program and data are placed in a fast small memory, the average memory access time can
be reduced, thus reducing the total execution time of the program. Such a fast small memory is called as cache
memory.
207. Define memory interleaving. [A.U.APR/MAY 07] [A.U.MAY/JUNE 11]
In order to carry out two or more simultaneous access to memory, the memory must be partitioned in to separate
modules. The advantage of a modular memory is that it allows the interleaving i.e. consecutive addresses are
assigned to different memory module.
208. In many computers the cache block size is in the range 32 to 128 bytes. What would be the main
Advantages and disadvantages of making the size of the cache blocks larger or smaller?
Larger the size of the cache fewer be the cache misses if most of the data in the block are actually used. It will be
wasteful if much of the data are not used before the cache block is moved from cache. Smaller size means more
misses.
209. What is the function of a TLB? (Translation Look-aside Buffer) [A.U.APR/MAY O9]
A small cache, called the Translation Look aside Buffer (TLB) is interpolated into the memory management unit,
which consists of the page table entries that corresponding to the most recently accessed paper.
210. An eight-way set-associative cache consists of a total of 256 blocks.
The main memory contains

8192 blocks, each consisting of 128 words.
1. How many bits are there in the main memory address?
2. How many bits are there in the TAG, SET and WORD fields?
The main memory contains of 256 blocks, and each block consists of 128 words.
Total words in MM = 8192 X 128 = 1048576
To address 32768 words we required (220 = 1048576) 20 bits
211. What do you understand by Hit ratio? [A.U.APR/MAY 06]
Hit ratio is a concept defined for any two adjacent level of a memory hierarchy. When information is found in cache
we call it a hit, otherwise miss. This hit and miss ratio is used to measure the performance of cache.
212. Define locality of reference. What are its types? [A.U.APR/MAY O9]
During the course of execution of a program memory references by the processor for both the instruction and the
data tends to cluster. There are two types:
1. Spatial Locality 2. Temporal Locality
213. List the factors that determine the storage device performance. [A.U.APR/MAY 07]
The storage device performance based on the following factors:
Address reference statistics
Access time storage capacity
Block size
Allocation algorithm
214. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?
2 (128 x 8) RAM Chips
215. What is memory system? [A.U.MAY/JUNE 11] [A.U. APR/MAY 2012]
Every computer contains several types of devices to store the instructions and data required for its operation. These
storage devices plus the algorithm-implemented by hardware and/or software-needed to manage the stored
information form the memory system of computer.
216. Give the classification of memory. [A.U.APR/MAY O8]
They can be placed into 4 groups.
CPU registers Main memory
Secondary memory Cache
217. Define CPU register, Main memory, Secondary memory, Cache.
CPU registers: These high speed registers in the CPU serve as the working memory for temporary storage of
Instruction and data.
Main memory: This large, fairly fast external memory stores programs and data that are in active use.
Storagelocations
In main memory are addressed directly by CPUs load and store instruction.
Secondary memory: This is larger in capacity but much slower than main memory. Secondary memory stores
systems
Programs, larger data files that are not continuously required by CPU.Cache: Most computers have another level of
IC memory-sometimes several such levels called cache memory,which is positioned logically between the CPU
registers and main memory.
218. Give the multilevel hierarchy of storage devices.
The goal of every memory system is to provide adequate storage capacity with an acceptable level ofperformance
and cost. We can achieve these goals by employing several memory types with differentcost/performance ratios-that
are organized to provide a high average performance at a low average cost per bit. The individual memory units
form a multilevel hierarchy of storage devices.
219. What is Read Access Time? [A.U.APR/MAY O9] [A.U. APR/MAY 2012]
A basic performance measure is the average time to read a fixed amount of information, for instance, one word,
from the memory. This parameter is called the read access time.
220. Define Random Access Memory. [A.U.NOV/DEC 2007]
It storage locations can be accessed in any order and access time is independent of the location being accessed, the
memory is termed a random-access memory.
221. What is Serial Access Memory?
Memories whose storage locations can be accessed only in a certain predetermined sequence called serial access
time.

222. What is Semi Random Access? [A.U.APR/MAY O8]
Memory devices such as magnetic hard disks and CD-ROMs contain many rotating storage tracks. If each track has
its own read write head, the tracks can be accessed randomly, but access within each track is serial. In such cases
the access mode is semi random.
223. What is ROM? [A.U.APR/MAY O9]
Memories whose contents cannot be altered online if they can be altered at all are read only memories.
224. What are PROMs?
Semi conductor ROMs whose contents can be changed offline with some difficulties is called PROMs.
225. What is destructive readout?
In some memories the method of reading the memories destroys the stored information, this phenomenon is called
destructive read out memory.
226. What do you mean by NDRO.
Memories in which reading does not affect the stored data have non destructive read out data.
227. Define memory refreshing. [A.U.APR/MAY 07]
Memory refreshing is defined as the process of regaining the lost charge for this continuous refreshing is needed.
228. What is SRAM and DRAM?
SRAM:Static random access memory. It tends to be faster. They require no refreshing.
DRAM:Dynamic random access memory. Data is stored in the form of charges. So continuous refreshing is needed.
229. What is volatile memory?
A memory is volatile if the loss of power destroys the stored information. Information can be stored indefinitely in a
volatile memory by providing battery backup or other means to maintain a continuous supply of power.
230. What is cycle time of memory? [A.U.APR/MAY09]
The minimum time that must elapse between the start of two consecutive access operations can be greater than Ta.
this elapsed time is called the cycle time.
231. What is MTBF?
Mean Time Before Failure. It is used to measure reliability. Memories with no moving parts have much higher
reliability than memories such as magnetic disks.
232. Give the categories of semiconductor memories. ) [A.U.APR/MAY10]
The semi conductor memories fall into two categories. They are
1. SRAM 2. DRAM
233. What is flash memory? [A.U.APR/MAY 06]
A recent semiconductor technology called flash memory of a same non-volatility as a PROM, but it can be done a
bit at a time.
234. Mention the causes of access a block of data in serial access memory. [A.U.APR/MAY O8]
Long access time is due to several factors.
The read-write head positioning time.
The relatively slow speed at which the tracks move.
The fact that the data transfer to and from the memory is serial rather than parallel.
235. How will you calculate time Tb to access a block of data in serial access memory?
The time Tb taken to access the block of data is Tb = Ts + 1/2r + n/rN
236. What is a multilevel memory? [A.U.APR/MAY O8]
A computers memory unit form a hierarchy of different memory type in which each member is in some sense
subordinate to next highest member of hierarchy.
237. What is split cache?
A cache which has two separate areas for storing instructions ( I- cache) and data ( d- cache) is called
split cache.
238. Give the basic structure of cache and what is its use?
Cache and main memory form a district sub hierarchy whose design objective is to support CPU access with a
minimum of delay. Hence hardware controllers that are transparent to both user and system programs usually
manage this sub hierarchy.
239. What is cache data memory? [A.U.APR/MAY O9] (A.U.NOV/DEC 2012)
Memory words are stored in cache data memory and are grouped into small pages called cache blocks or lines. The
contents of the caches data memory are thus copies of a set of main memory blocks.
240. Mention two system organizations for caches. [A.U.APR/MAY09]

Two system organizations for caches are
Look aside Look through
241. What is associate memory? [A.U.APR/MAY 07] (A.U.NOV/DEC 2012)
In associative memory each unit of stored information is fixed length word. Any sub field of the word can be chosen
as the key. The desired key is specified by a mask register, whose contents identify the bit positions that define the
key. It has a select circuit which enables the data field to be accessed.
242. Define seek time and latency time. [A.U.NOV/DEC 2007]
The average time to move a head from one track is seek time (Ts) of the memory. Once the head is in position, the
desired cell may be in the wrong part of the moving track. Some time is required for the cell to reach the read/write
head so that data transfer can begin. The average time for this movement to take place is the latency time (T1).
243. Mention two kinds of address locality to achieve their goal.
Two kinds address locality to achieve their goals are
Associative addressing or content addressing. Direct mapping.
244. What is the use of magnetic tape memories in todays usage?
The magnetic tape unit is one of the oldest and cheapest forms of mass memory. Its main use today is to provide
backup storage for a computer system in the event of failure of its hard disk sub system.
245. What is DVD? [A.U.APR/MAY O8]
A much denser type of CD digital video has recently been introduced in both read-only and read-write forms. With
two recording surfaces and two storage layers per surface, a DVD can have a capacity as high as 16GB.
246. Define magneto optical disk.
A magneto-optical disk memory uses rotating disks that store information in magnetic form but are accessed by a
laser beam similar to that in a CD-ROM drive. Like a magnetic disk, a magneto optical disk has a magnetizable
surface coating whose direction of magnetization can be polarized

247. Discuss the various mapping techniques used in cache memories. (8)[ A.U.APR/MAY07] [A.U.
APR/MAY 2012] (A.U.APR/MAY 2013)
248. A computer system has a main memory consisting of 16 M words. It also has a 32Kword cache
organized in the block-set-associative manner, with 4 blocks per set and 128 words per block.
(i) Calculate the number of bits in each of the TAG, SET and WORD fields of the main memory address
format. [A.U.MAY/JUNE 11]
(ii) How will the main memory address look like for a fully associative mapped cache? (8)
[ A.U.APR/MAY07] (A.U.APR/MAY 2013)
249. Explain the concept of virtual memory with any one virtual memory management technique.
250. Give the basic cell of an associative memory and explain its operation. Show how associative memories
can be constructed using this basic cell. (8) [A.U.MAY/JUNE 11]
251. Give the structure of semiconductor RAM memories. Explain the read and write operations in detail.
(16)[ A.U.NOV/DEC07] [A.U. APR/MAY 2012]
252. Explain the organization of magnetic disks in detail. (8) (A.U.APR/MAY 2013)
253 A digital computer has a memory unit of 64K*16 and a cache memory of 1K words. The cache uses
direct mapping with a block size of four words. How many bits are therein the tag, index, block and word
fields of the address format? How many blocks can the caches accommodate? (10)[ A.U.APR/MAY06]
254. Explain the concept of memory hierarchy. (6)

UNIT 5-INPUT OUTPUT ORGANIZATION

PART A (1 Marks)
255.Which Intel chip was the first to support a 32-bit bus architecture?
a. 486SI b. Pentium c. 286 d. 386DX
256.Which of the following operating systems is produced by IBM?
a. OS-2 b. Windows c. DOS d. UNIX
257. What was the clock speed of the original IBM PC?

a. Less than 5 MHz b. 10 MHz c. 8 MHz d. Just over 16 MHz
258. The IBM PC-XT was the first to include a hard drive. What was the capacity of this disk?
a. 20 MB b. 1.44 MB c. 10 MB 4) 750 KB
259. Which of the following word processors came first?
a. WordPerfect b. Lotus Notes c. MS Word d. WordStar
260. On what date was the debut of the first IBM Personal Computer?
a. August 12, 1981 b. January 21 1979 c. August 21, 1980 d. January 12, 1982
261. The Central Processing Unit is an embedded chip that acts as the 'brains' of a computer. What Intel chip
was used in the Altair (the first real personal computer)?
a. 6502 b. 8080 c. 6400 d. 8286
262. The invention of the transistor, or semiconductor, was one of the most important developments leading to
the personal computer revolution. What company invented the transistor in 1947?
a. International Business Machines b. MITS c. Xerox d. Bell Laboratories
263. This virus activated every Friday the 13th, affects both .EXE and .COM files and deletes any programs run
on that day. What is the name of that virus?
a. Chernobyl b. Jerusalem c. Melissa d. I Love You
264. In what year did the Symantec Corporation first release Norton Antivirus?
a. 1990 b. 1995 c. 1988 d. 1997
265. A computer virus that actively attacks an anti-virus program or programs in an effort to prevent
detection is...
a. Worm b. Retrovirus c. Trojan d. Ghost virus
266. A program that neither replicates or copies itself, but does damage or compromises the security of the
computer. Which 'Computer Virus' it is?
a. Joke Program b. Worm c. Trojan d. Hoax
267. Which of these is a documented hoax virus?
a. McDonalds screensaver b. Alien.worm c. Merry Xmas d. Adolph
268. In 1983, which person was the first to offer a definition of the term 'computer virus'?
a. McAfee b. Smith c. Cohen d. Norton
269. What is RISC?
a. Remodeled Interface System Computer b. Remote Intranet Secured Connection
c. Runtime Instruction Set Compiler d. Reduced Instruction Set Computer
270. What is a GPU?
a. Grouped Processing Unit b. Graphics Processing Unit c. Graphical Performance Utility
d. Graphical Portable Unit
271. What does ECP stand for?
a. Extended Capabilities Port b. Extra Compatible Part c. Extended Connection Port
d. External Cordless Peripheral
272. What is TTL?
a. Technical Talk Language b. Transparent Transfer Layer c. Time To Live d. True
Technology Lives
273. What is FMD?
a. Fast Ethernet Measuring Device b. Flashing Media Diode c. Fluorescent Multi-Layer
Disc d. Flash Media Driver
274. What does DOCSIS stand for?
a. Data Over Cable Service Interface Specification b. Data Over Cable Security Internet Std
c. Data Over Cable Secure International Stds d. Data Over Cable Service Internet Standard

PART B (2 Marks)
255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
d a a c d a b d b a b c a c d b a c c a

275.Distinguish between memory mapped I/O and I/O mapped I/O. ) [A.U.APR/MAY10]
Memory mapped I/O:
When I/O devices and the memory share the same address space, the arrangement is called memorymapped I/O.
The machine instructions that can access memory is used to transfer data to or from an I/Odevice.
Bus

Single-Bus Structure: For example, if DATAIN is the address of the input buffer of keyboard, the
instruction.MOVE DATAIN, R0 Reads the data from DATAIN and stores them into processor register
R0.Similarly if DATAOUT is the address of the output buffer of a display unit or printer, the instruction.MOVE R0,
DATAOUT sends the data from R0 to location DATAOUT.I/O mapped I/O:Here the I/O devices the memories
have different address space. It has special I/Instructions. Theadvantage of a separate I/O address space is that I/O
devices deals with fewer address lines.
276. Consider a computer in which several devices are to be serviced interrupts. How do you handle
This it the processor has only one request line?
Daisy Chain: Consider the problem of simultaneous request from two or more devices. The processor has to decide
Which request to be serviced first. Polling the status register of the I/O devices is the simplest scheme.Priority is
determined by the order in which devices are polled. In daisy chain scheme, interrupt request lineINTR is common
to all devices. The interrupt acknowledgement INTA, propagates serially through thedevices.When several devices
raise an interrupt request, the processor responds by setting INTA line to 1. The signal is received by device 1.
Device 1 passes the signal on to device 2 only if it does not require any service. If device 1 has a pending request for
interrupt, it blocks the INTA signal and proceeds to put its device identifying code on the data lines. Therefore, in
daisy chain arrangement, the device that is closest to the processor has the highest priority.
INTR
INTA
DAISY CHAIN
Processor
I/O Device1
Memory
I/O Device n
Processor
Device 1 Device 2 Device n
277. What is DMA? [A.U.APR/MAY O8] [A.U. APR/MAY 2012] (A.U.APR/MAY 2013)
DMA (Direct Memory Access) provides I/O transfer of data directly to and from the memory unit and the
peripheral.
278. Define Peripherals? [A.U.APR/MAY 07]
Peripheral refers to any external devices connected to a computer. Computer peripherals can be divided into two
categories according to their functions.
I/O peripherals: Keyboard, Mouse, Video Display Unit, Printer.
Storage Function: Secondary Memories, Mass Storage Device.
Eg: CD, Hard disk, Magnetic disk, Magnetic tape.
279. Distinguish between a synchronous bus and an asynchronous bus.
In synchronous bus both the transmitting and receiving devices use same clock for interpretation of individual bits.
Synchronous buses can operate with lower latency and higher bandwidth. In an asynchronous bus, the sender and
the receiver generate their clock signals independently. It uses start stop bit for data transmission
1
0
Start bit 1 bit 1 or 2 Time stop bit
280. How does a processor handle an interrupt? [A.U.APR/MAY O9]
Assume that an interrupt request arises during execution of instruction i. steps to handle interrupt by the
Processor is as follow:
1. Processor completes execution of instruction i
2. Processor saves the PC value, program status on to stack.
3. It loads the PC with starting address of ISR

4. After ISR is executed, the processor resumes the main program execution by reloading PC with (i+1)th
instruction address.
281. Define dumb terminal.[A.U.APR/MAY10]
0
LSB
1 2 3 4 5 6 7
Early CRT terminals were relatively simple in their functional capability, being able to perform primitive I/O
operations. Such terminals are some times called dumb terminals.
282. Why are interrupt masks provided in any processor?
Interrupt masks enable the higher priority devices come first and there for lower priority devices comelast. This
interrupt enable bits as a bit vector is called as interrupt mark which enables/disables the devices according to the
correct configuration of the mask.
283. How does bus arbitration typically work? [A.U.APR/MAY O8]
1. A bus master waiting to use the bus asserts the bus request
2. A bus master cannot the bus until its request is granted.
3. A bus master must signal to the arbiter the end of the bus utilization.
284. How is DMA operation? State its advantages.
DMA stands for Direct Memory Access. In order to transfer bulk amount of data between memory and I/O device
without involvement of CPU, this technique is used. The advantage is fast data transfer.
285. What is the necessity of an interface? [A.U.APR/MAY 07] [A.U. APR/MAY 2012]
Any device that has to be connected to a CPU requires an interface, which takes care of the mismatch in speed, data
and electrical characteristics between the CPU to the device.
286. Why does DMA have priority over the CPU when both request a memory transfer?
Since the data transfer rate using DMA is quite higher than the CPU and memory transfer rate, the DMA have
priority over the CPU when both request a memory transfer.
287. Define intra segment and inter segment communication. [A.U.APR/MAY O9]
Intra segment communication: Communication through a single computer. It can communicate through a distance
of a meter only. Inter segment communication: Communication through long distance. A set of computers and
connections called buses are involved.
288. Mention the group of lines in the system bus.
1. Address lines. 2. Data lines. 3. Control lines.
289. What is bus master and slave master?
Input output operations involve data transfers between IO device and Memory. In all the preceding operations
Memory is passive or slave device with respect to system bus transactions. Where as the CPU can control the
system bus, i.e. serve as a bus master?
290. What is the use of IO controller? [A.U.NOV/DEC 2007]
The magnetic disks and other secondary memory need to be connected to the system bus via interface circuits called
Io controllers. That performs series to parallel and parallel to series format conversions and other control functions.
It can interface many IO devices to system bus.
291. Differentiate synchronous and asynchronous communication).[A.U.APR/MAY10]
In synchronous communication each item is transferred during the time slot know to both the source and
destination. Data transfer is slow. In asynchronous communication data transfer is faster and can be used for long
distance communication. Each item being transferred is accompanied by the control signals.
292. What is strobe signal?
The data ready / request signals are used to load data from the source unit to the bus of from the bus to the
destination unit. Such control signals are called strobe signals.
293. What is bus arbitration? (A.U.NOV/DEC 2012) (A.U.APR/MAY 2013)
The possibility exists that several master or slave units connected to a shared bus will request access to the bus at
the same time. A selection mechanism called bus arbitration is therefore required to enable the current master,
which we still refer to as bus controller to decide among such competing requests.
294. Mention the types of bus arbitration. [A.U.APR/MAY O8]
Daisy chaining, Polling and Independent requesting
295. What is IO control method?
It refers the data transfer between the IO device and the memory or between the IO device and the CPU.

Ex: Testing the status of the device and to determine if they require service by the CPU.
296. What is DMA? [A.U.APR/MAY 07] (A.U.NOV/DEC 2012)
The CPU and IO controller interact only when the CPU yield the control of the memory bus to the IO controller in
response to the request from the latter. This level of IO control is called direct memory access and the IO device
interface control circuit is called as DMA controller.
297. Why the DMA does gets priority over CPU when both request memory transfer.
The CPU can wait to fetch instruction and data from the memory with out any damage occurring except that the loss
of time. DMA usually transfers data from a device that cant be stopped since information continues to flow so loss
of data may occur.
298.Specify the types of the DMA transfer techniques. [A.U.MAY/JUNE 11]
The CPU and IO controller interact only when the CPU yield the control of the memory bus to the IO controller in
response to the request from the latter. This level of IO control is called direct memory access and the IO device
interface control circuit is called as DMA controller.
299. Why are interrupt masks provided in any processor? [A.U.MAY/JUNE 11]
Interrupt masks enable the higher priority devices come first and there for lower priority devices come last. This
interrupt enable bits as a bit vector is called as interrupt mark which enables/disables the devices according to the
correct configuration of the mask.

300. Explain the functions to be performed by a typical I/O interface with a typical input output interface.
(16)[ A.U.APR/MAY08]
301. Discuss the DMA driven data transfer technique. (8) ) [A.U.APR/MAY10]
302. Discuss the operation of any two input devices (8) [A.U.NOV/DEC06]
303. Explain in detail about interrupt handling. (16)(A.U.NOV/DEC 2012) (A.U.APR/MAY 2013)
304. Explain in detail about standard I/O interface. (16)[ A.U.APR/MAY07] [A.U. APR/MAY 2012]
(A.U.APR/MAY 2013)
305. Describe the functions of SCSI with a neat diagram. (16) [A.U. APR/MAY 2012]
306 What is the importance of I/O interface? Compare the features of SCSI and PCI interfaces. (8)[
A.U.NOV/DEC06]
307. Write short notes on the following.
(i) Bus arbitration
(ii) Printer process communication
(iii) USB
(iv) DMA (16) [A.U.APR/MAY06] (A.U.APR/MAY 2013)
308. Explain the use of vectored interrupts in processes. Why is priority handling desired in interrupt
controllers? How does the different priority scheme work? (8) [A.U.MAY/JUNE 11]
309.List the standard I/O interface. explain in detail about their features stating their advantage and
disadvantage. [A.U.MAY/JUNE 11] (A.U.NOV/DEC 2012)

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