Chn Chn K K M t M t

Gii thiu c bn v LCD 16x2 Gii thiu c bn v LCD 16x2

3/02/2012 09:09:00 CH 3/02/2012 09:09:00 CH Gii thiu c bn Gii thiu c bn, , LCD 16x2 LCD 16x2, , Linh Kin C Bn Linh Kin C Bn, , in t c bn in t c bn No comments No comments
* Gii thiu : * Gii thiu :
Ngy nay, thit b hin th LCD (Liquid Crystal Display) c s dng trong rt nhiu cc ng dng ca VK. Ngy nay, thit b hin th LCD (Liquid Crystal Display) c s dng trong rt nhiu cc ng dng ca VK.
LCD c rt nhiu u im so vi cc dng hin th khc: N c kh nng hin th k t a dng, trc quan (ch, LCD c rt nhiu u im so vi cc dng hin th khc: N c kh nng hin th k t a dng, trc quan (ch,
s v k t ha), d dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau, tn rt t ti s v k t ha), d dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau, tn rt t ti
nguyn h thng v gi thnh r nguyn h thng v gi thnh r
Tng Qut V LCD HD44780 Tng Qut V LCD HD44780
1> Hnh dng v kch thc: 1> Hnh dng v kch thc:
C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn hnh 1 l loi LCD thng C rt nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, trn hnh 1 l loi LCD thng
dng. dng.
Hnh 1 : Hnh dng ca loi LCD thng dng Hnh 1 : Hnh dng ca loi LCD thng dng
Khi sn xut LCD, nh sn xut tch hp chp iu khin (HD44780) bn trong lp v v ch a cc chn giao Khi sn xut LCD, nh sn xut tch hp chp iu khin (HD44780) bn trong lp v v ch a cc chn giao
tip cn thit. Cc chn ny c nh s th t v t tn nh hnh 2 : tip cn thit. Cc chn ny c nh s th t v t tn nh hnh 2 :
Hnh 2 : S chn ca LCD Hnh 2 : S chn ca LCD
2> Chc nng cc chn : 2> Chc nng cc chn :
Top10 Top10 Danh Mc Ch Danh Mc Ch
Tng Hp Tng Hp
LIN H LIN H
ThGviTKhavEnter
13
BNG XP HNG TUN BNG XP HNG TUN
Download Proteus 7.8 SP2 FULL Download Proteus 7.8 SP2 FULL
IC 555 - Nguyn l, Cu to IC 555 - Nguyn l, Cu to
[Hc Lp trnh 8051] Bi 2: [Hc Lp trnh 8051] Bi 2:
Hng Dn S Dng Keil C Lp Hng Dn S Dng Keil C Lp
Trnh 8051 Trnh 8051
[Hng Dn] Ci t - S Dng [Hng Dn] Ci t - S Dng
Trnh Bin Dch Dev-C++ Trnh Bin Dch Dev-C++
[Hc lp trnh 8051] Bi 7: Ngt [Hc lp trnh 8051] Bi 7: Ngt
trong 8051 trong 8051
Gii thiu c bn v LCD 16x2 Gii thiu c bn v LCD 16x2
Code mu cho PIC - Kt hp: Code mu cho PIC - Kt hp:
ADC o nhit , in p, hin th ADC o nhit , in p, hin th
LCD v giao tip vi my tnh LCD v giao tip vi my tnh
TRANG CH TRANG CH BN TIN BN TIN
IN T C BN IN T C BN
LP TRNH LP TRNH
VI IU KHIN VI IU KHIN
CHIP KH TRNH CHIP KH TRNH
PHN MM PHN MM
GII THUT GII THUT
MUSIC MUSIC
DIENTUMAYTINH.COM DIENTUMAYTINH.COM
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hiu hiu
11 Vss Vss Chn ni t cho LCD, khi thit k mch ta ni chn ny Chn ni t cho LCD, khi thit k mch ta ni chn ny
vi GND ca mch iu khin vi GND ca mch iu khin
22 VDD VDD Chn cp ngun cho LCD, khi thit k mch ta ni chn Chn cp ngun cho LCD, khi thit k mch ta ni chn
ny vi VCC=5V ca mch iu khin ny vi VCC=5V ca mch iu khin
33 VEE VEE iu chnh tng phn ca LCD. iu chnh tng phn ca LCD.
44 RS RS Chn chn thanh ghi (Register select). Ni chn RS vi Chn chn thanh ghi (Register select). Ni chn RS vi
logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi. logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi.
+ Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR + Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR
ca LCD ( ch ghi - write) hoc ni vi b m a ca LCD ( ch ghi - write) hoc ni vi b m a
ch ca LCD ( ch c - read) ch ca LCD ( ch c - read)
+ Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu + Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu
DR bn trong LCD. DR bn trong LCD.
55 R/W R/W Chn chn ch c/ghi (Read/Write). Ni chn R/W Chn chn ch c/ghi (Read/Write). Ni chn R/W
vi logic 0 LCD hot ng ch ghi, hoc ni vi logic 0 LCD hot ng ch ghi, hoc ni
vi logic 1 LCD ch c. vi logic 1 LCD ch c.
66 EE Chn cho php (Enable). Sau khi cc tn hiu c t Chn cho php (Enable). Sau khi cc tn hiu c t
ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1 ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1
xung cho php ca chn E. xung cho php ca chn E.
+ ch ghi: D liu bus s c LCD chuyn + ch ghi: D liu bus s c LCD chuyn
vo(chp nhn) thanh ghi bn trong n khi pht hin mt vo(chp nhn) thanh ghi bn trong n khi pht hin mt
xung (high-to-low transition) ca tn hiu chn E. xung (high-to-low transition) ca tn hiu chn E.
+ ch c: D liu s c LCD xut ra DB0-DB7 + ch c: D liu s c LCD xut ra DB0-DB7
khi pht hin cnh ln (low-to-high transition) chn E khi pht hin cnh ln (low-to-high transition) chn E
v c LCD gi bus n khi no chn E xung mc v c LCD gi bus n khi no chn E xung mc
thp. thp.
7 - 14 7 - 14 DB0 - DB0 -
DB7 DB7
Tm ng ca bus d liu dng trao i thng tin Tm ng ca bus d liu dng trao i thng tin
vi MPU. C 2 ch s dng 8 ng bus ny : vi MPU. C 2 ch s dng 8 ng bus ny :
+ Ch 8 bit : D liu c truyn trn c 8 ng, vi + Ch 8 bit : D liu c truyn trn c 8 ng, vi
bit MSB l bit DB7. bit MSB l bit DB7.
+ Ch 4 bit : D liu c truyn trn 4 ng t + Ch 4 bit : D liu c truyn trn 4 ng t
DB4 ti DB7, bit MSB l DB7 DB4 ti DB7, bit MSB l DB7
15 15 -- Ngun dng cho n nn Ngun dng cho n nn
16 16 -- GND cho n nn GND cho n nn
[Hng Dn] Download - Ci t [Hng Dn] Download - Ci t
Phn Mm Altium Designer FULL Phn Mm Altium Designer FULL
[Hc lp trnh 8051] Bi 6: Truyn [Hc lp trnh 8051] Bi 6: Truyn
thng ni tip vi 8051 thng ni tip vi 8051
in Tr - Cch c Gi Tr in in Tr - Cch c Gi Tr in
Tr Tr
Chng ti ang trn
NHN LM N IN T TI HN NHN LM N IN T TI HN
Nhm qun tr website Nhm qun tr website www.linhkiendientu.co/ www.linhkiendientu.co/
chng ti quyt nh cung cp cc chng ti quyt nh cung cp cc sn phm in sn phm in
t t theo yu cu, nhn thit k theo yu cu, nhn thit k mach in t mach in t v v
n in t n in t. . Chi tit ti y Chi tit ti y: : Nhn lm n, Nhn lm n,
thit k mach in t theo yu cu tai H Ni. thit k mach in t theo yu cu tai H Ni.
LIN KT LIN KT
Kim Tin Trn Mng Kim Tin Trn Mng
Qung Co LED Qung Co LED
Truong Chuyen Truong Chuyen
Pho Thong Pho Thong
NG NHP NG NHP
vi Kt ni Bn b ca Google
Thnh vin (35) Thm
Bn l thnh vin ri? ng nhp
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Bng 1 : Chc nng cc chn ca LCD Bng 1 : Chc nng cc chn ca LCD
* Ghi ch : ch c, ngha l MPU s c thng tin t LCD thng qua cc chn DBx. * Ghi ch : ch c, ngha l MPU s c thng tin t LCD thng qua cc chn DBx.
Cn khi ch ghi, ngha l MPU xut thng tin iu khin cho LCD thng qua cc chn DBx. Cn khi ch ghi, ngha l MPU xut thng tin iu khin cho LCD thng qua cc chn DBx.
3> S khi ca HD44780: 3> S khi ca HD44780:
hiu r hn chc nng cc chn v hot ng ca chng, ta tm hiu s qua chp HD44780 thng qua cc hiu r hn chc nng cc chn v hot ng ca chng, ta tm hiu s qua chp HD44780 thng qua cc
khi c bn ca n. khi c bn ca n.
Hnh 3 : S khi ca HD44780 Hnh 3 : S khi ca HD44780
TRUY CP TRUY CP
FOLLOW BY EMAIL FOLLOW BY EMAIL
Email address...
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a> Cc thanh ghi : a> Cc thanh ghi :
Chp HD44780 c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor Register) v thanh ghi d liu Chp HD44780 c 2 thanh ghi 8 bit quan trng : Thanh ghi lnh IR (Instructor Register) v thanh ghi d liu
DR (Data Register) DR (Data Register)
- Thanh ghi IR : iu khin LCD, ngi dng phi ra lnh thng qua tm ng bus DB0-DB7. Mi lnh - Thanh ghi IR : iu khin LCD, ngi dng phi ra lnh thng qua tm ng bus DB0-DB7. Mi lnh
c nh sn xut LCD nh a ch r rng. Ngi dng ch vic cung cp a ch lnh bng cch np vo thanh c nh sn xut LCD nh a ch r rng. Ngi dng ch vic cung cp a ch lnh bng cch np vo thanh
ghi IR. Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m lnh ti a ch m IR ghi IR. Ngha l, khi ta np vo thanh ghi IR mt chui 8 bit, chp HD44780 s tra bng m lnh ti a ch m IR
cung cp v thc hin lnh . cung cp v thc hin lnh .
VD : VD : Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0) Lnh hin th mn hnh c a ch lnh l 00001100 (DB7DB0)
Lnh hin th mn hnh v con tr c m lnh l 00001110 Lnh hin th mn hnh v con tr c m lnh l 00001110
- Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM DDRAM hoc CGRAM - Thanh ghi DR : Thanh ghi DR dng cha d liu 8 bit ghi vo vng RAM DDRAM hoc CGRAM
( ch ghi) hoc dng cha d liu t 2 vng RAM ny gi ra cho MPU ( ch c). Ngha l, khi MPU ( ch ghi) hoc dng cha d liu t 2 vng RAM ny gi ra cho MPU ( ch c). Ngha l, khi MPU
ghi thng tin vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi ghi thng tin vo DR, mch ni bn trong chp s t ng ghi thng tin ny vo DDRAM hoc CGRAM. Hoc khi
thng tin v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni ca HD44780 s c chuyn ra thng tin v a ch c ghi vo IR, d liu a ch ny trong vng RAM ni ca HD44780 s c chuyn ra
DR truyn cho MPU. DR truyn cho MPU.
=> Bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2 thanh ghi ny khi giao tip vi => Bng cch iu khin chn RS v R/W chng ta c th chuyn qua li gi 2 thanh ghi ny khi giao tip vi
MPU. Bng sau y tm tt li cc thit lp i vi hai chn RS v R/W theo mc ch giao tip. MPU. Bng sau y tm tt li cc thit lp i vi hai chn RS v R/W theo mc ch giao tip.
RS RS R/W R/W Chc nng Chc nng
00 00 Ghi vo thanh ghi IR ra lnh cho LCD Ghi vo thanh ghi IR ra lnh cho LCD
00 11 c c bn DB7 v gi tr ca b m a ch DB0-DB6 c c bn DB7 v gi tr ca b m a ch DB0-DB6
11 00 Ghi vo thanh ghi DR Ghi vo thanh ghi DR
11 11 c d liu t DR c d liu t DR
Bng 2 : Chc nng chn RS v R/W theo mc ch s dng Bng 2 : Chc nng chn RS v R/W theo mc ch s dng
b> C bo bn BF: (Busy Flag) b> C bo bn BF: (Busy Flag)
Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong thi gian hon tt. Khi Khi thc hin cc hot ng bn trong chp, mch ni bn trong cn mt khong thi gian hon tt. Khi
ang thc thi cc hot ng bn trong chip nh th, LCD b qua mi giao tip vi bn ngoi v bt c BF (thng ang thc thi cc hot ng bn trong chip nh th, LCD b qua mi giao tip vi bn ngoi v bt c BF (thng
qua chn DB7 khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin, khi xong vic, n qua chn DB7 khi c thit lp RS=0, R/W=1) ln bo cho MPU bit n ang bn. D nhin, khi xong vic, n
s t c BF li mc 0. s t c BF li mc 0.
c> B m a ch AC : (Address Counter) c> B m a ch AC : (Address Counter)
Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM (DDRAM v CGRAM) m thng qua b Nh trong s khi, thanh ghi IR khng trc tip kt ni vi vng RAM (DDRAM v CGRAM) m thng qua b
m a ch AC. B m ny li ni vi 2 vng RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh m a ch AC. B m ny li ni vi 2 vng RAM theo kiu r nhnh. Khi mt a ch lnh c np vo thanh
ghi IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng RAM tng tc c bao hm ghi IR, thng tin c ni trc tip cho 2 vng RAM nhng vic chn la vng RAM tng tc c bao hm
trong m lnh. trong m lnh.
Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v ni dung ca AC c xut ra Sau khi ghi vo (c t) RAM, b m AC t ng tng ln (gim i) 1 n v v ni dung ca AC c xut ra
cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1 (xem bng tm tt RS - R/W). cho MPU thng qua DB0-DB6 khi c thit lp RS=0 v R/W=1 (xem bng tm tt RS - R/W).
Lu : Lu : Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp nht sau khi c BF ln Thi gian cp nht AC khng c tnh vo thi gian thc thi lnh m c cp nht sau khi c BF ln
mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay mt khong tADD khong 4uS-5uS (ngay sau mc cao (not busy), cho nn khi lp trnh hin th, bn phi delay mt khong tADD khong 4uS-5uS (ngay sau
khi BF=1) trc khi np d liu mi. Xem thm hnh bn di. khi BF=1) trc khi np d liu mi. Xem thm hnh bn di.
Hnh 4 : Gin xung cp nht AC Hnh 4 : Gin xung cp nht AC
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d> Vng RAM hin th DDRAM : (Display Data RAM) d> Vng RAM hin th DDRAM : (Display Data RAM)
y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt k t trn mn hnh v khi bn y l vng RAM dng hin th, ngha l ng vi mt a ch ca RAM l mt k t trn mn hnh v khi bn
ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti v tr tng ng trn mn hnh mt k t c m 8 bit m ghi vo vng RAM ny mt m 8 bit, LCD s hin th ti v tr tng ng trn mn hnh mt k t c m 8 bit m
bn cung cp. Hnh sau y s trnh by r hn mi lin h ny : bn cung cp. Hnh sau y s trnh by r hn mi lin h ny :
Hnh 4 : Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD Hnh 4 : Mi lin h gia a ch ca DDRAM v v tr hin th ca LCD
Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng RAM cn li khng dng cho Vng RAM ny c 80x8 bit nh, ngha l cha c 80 k t m 8 bit. Nhng vng RAM cn li khng dng cho
hin th c th dng nh vng RAM a mc ch. hin th c th dng nh vng RAM a mc ch.
Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX Lu l truy cp vo DDRAM, ta phi cung cp a ch cho AC theo m HEX
e> Vng ROM cha k t CGROM: Character Generator ROM e> Vng ROM cha k t CGROM: Character Generator ROM
Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v nh a ch bng 8 bit. Tuy Vng ROM ny dng cha cc mu k t loi 5x8 hoc 5x10 im nh/k t, v nh a ch bng 8 bit. Tuy
nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu 5x10 (tng cng l 240 thay v 2^8 = 256 mu k t). nhin, n ch c 208 mu k t 5x8 v 32 mu k t kiu 5x10 (tng cng l 240 thay v 2^8 = 256 mu k t).
Ngi dng khng th thay i vng ROM ny. Ngi dng khng th thay i vng ROM ny.
Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t. Hnh 5 : Mi lin h gia a ch ca ROM v d liu to mu k t.
Nh vy, c th ghi vo v tr th x trn mn hnh mt k t y no , ngi dng phi ghi vo vng DDRAM ti Nh vy, c th ghi vo v tr th x trn mn hnh mt k t y no , ngi dng phi ghi vo vng DDRAM ti
a ch x (xem bng mi lin h gia DDRAM v v tr hin th) mt chui m k t 8 bit trn CGROM. Ch l a ch x (xem bng mi lin h gia DDRAM v v tr hin th) mt chui m k t 8 bit trn CGROM. Ch l
trong bng m k t trong CGROM hnh bn di c m ROM A00. trong bng m k t trong CGROM hnh bn di c m ROM A00.
V d : V d : Ghi vo DDRAM ti a ch 01 mt chui 8 bit 01100010 th trn LCD ti th 2 t tri sang (dng Ghi vo DDRAM ti a ch 01 mt chui 8 bit 01100010 th trn LCD ti th 2 t tri sang (dng
trn) s hin th k t b. trn) s hin th k t b.
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Bng 3 : Bng m k t (ROM code A00) Bng 3 : Bng m k t (ROM code A00)
f> Vng RAM cha k t ha CGRAM : (Character Generator RAM) f> Vng RAM cha k t ha CGRAM : (Character Generator RAM)
Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000 ngi dng c th to cc mu k Nh trn bng m k t, nh sn xut dnh vng c a ch byte cao l 0000 ngi dng c th to cc mu k
t ha ring. Tuy nhin dung lng vng ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k t ha ring. Tuy nhin dung lng vng ny rt hn ch: Ta ch c th to 8 k t loi 5x8 im nh, hoc 4 k
t loi 5x10 im nh. t loi 5x10 im nh.
ghi vo CGRAM, hy xem hnh 6 bn di. ghi vo CGRAM, hy xem hnh 6 bn di.
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Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t. Hnh 6 : Mi lin h gia a ch ca CGRAM, d liu ca CGRAM, v m k t.
4> Tp lnh ca LCD : 4> Tp lnh ca LCD :
Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip vi LCD : Trc khi tm hiu tp lnh ca LCD, sau y l mt vi ch khi giao tip vi LCD :
* Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp trnh iu khin LCD ta ch c th tc * Tuy trong s khi ca LCD c nhiu khi khc nhau, nhng khi lp trnh iu khin LCD ta ch c th tc
ng trc tip c vo 2 thanh ghi DR v IR thng qua cc chn DBx, v ta phi thit lp chn RS, R/W ph ng trc tip c vo 2 thanh ghi DR v IR thng qua cc chn DBx, v ta phi thit lp chn RS, R/W ph
hp chuyn qua li gi 2 thanh ghi ny. (xem bng 2) hp chuyn qua li gi 2 thanh ghi ny. (xem bng 2)
* Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh lu i vi tc ca MPU, * Vi mi lnh, LCD cn mt khong thi gian hon tt, thi gian ny c th kh lu i vi tc ca MPU,
nn ta cn kim tra c BF hoc i (delay) cho LCD thc thi xong lnh hin hnh mi c th ra lnh tip theo. nn ta cn kim tra c BF hoc i (delay) cho LCD thc thi xong lnh hin hnh mi c th ra lnh tip theo.
* a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh ghi vo RAM. (iu ny gip chng * a ch ca RAM (AC) s t ng tng (gim) 1 n v, mi khi c lnh ghi vo RAM. (iu ny gip chng
trnh gn hn) trnh gn hn)
* Cc lnh ca LCD c th chia thnh 4 nhm nh sau : * Cc lnh ca LCD c th chia thnh 4 nhm nh sau :
Cc lnh v kiu hin th. VD : Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit / 4 bit), Cc lnh v kiu hin th. VD : Kiu hin th (1 hng / 2 hng), chiu di d liu (8 bit / 4 bit),
Ch nh a ch RAM ni. Ch nh a ch RAM ni.
Nhm lnh truyn d liu trong RAM ni. Nhm lnh truyn d liu trong RAM ni.
Cc lnh cn li . Cc lnh cn li .
Bng 4 : Tp lnh ca LCD Bng 4 : Tp lnh ca LCD
Tn lnh Tn lnh Hot ng Hot ng
Clear Clear
Display Display
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 0 0 0 0 1 DBx = 0 0 0 0 0 0 0 1
Lnh Clear Display (xa hin th) s ghi mt khong trng-blank (m Lnh Clear Display (xa hin th) s ghi mt khong trng-blank (m
hin k t 20H) vo tt c nh trong DDRAM, sau tr b m a hin k t 20H) vo tt c nh trong DDRAM, sau tr b m a
AC=0, tr li kiu hin th gc nu n b thay i. Ngha l : Tt hin AC=0, tr li kiu hin th gc nu n b thay i. Ngha l : Tt hin
th, con tr di v gc tri (hng u tin), ch tng AC. th, con tr di v gc tri (hng u tin), ch tng AC.
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home home
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 0 0 0 1 * DBx = 0 0 0 0 0 0 1 *
Lnh Return home tr b m a ch AC v 0, tr li kiu hin th gc Lnh Return home tr b m a ch AC v 0, tr li kiu hin th gc
nu n b thay i. Ni dung ca DDRAM khng thay i. nu n b thay i. Ni dung ca DDRAM khng thay i.
Entry Entry
mode mode
set set
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 0 0 1 [I/D] [S] DBx = 0 0 0 0 0 1 [I/D] [S]
I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th AC 1 n I/D : Tng (I/D=1) hoc gim (I/D=0) b m a ch hin th AC 1 n
v mi khi c hnh ng ghi hoc c vng DDRAM. V tr con tr v mi khi c hnh ng ghi hoc c vng DDRAM. V tr con tr
cng di chuyn theo s tng gim ny. cng di chuyn theo s tng gim ny.
S : Khi S=1 ton b ni dung hin th b dch sang phi (I/D=0) hoc S : Khi S=1 ton b ni dung hin th b dch sang phi (I/D=0) hoc
sang tri (I/D=1) mi khi c hnh ng ghi vng DDRAM. Khi S=0: sang tri (I/D=1) mi khi c hnh ng ghi vng DDRAM. Khi S=0:
khng dch ni dung hin th. Ni dung hin th khng dch khi c khng dch ni dung hin th. Ni dung hin th khng dch khi c
DDRAM hoc c/ghi vng CGRAM. DDRAM hoc c/ghi vng CGRAM.
Display Display
on/off on/off
control control
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 0 1 [D] [C] [B] DBx = 0 0 0 0 1 [D] [C] [B]
D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th, ni dung D: Hin th mn hnh khi D=1 v ngc li. Khi tt hin th, ni dung
DDRAM khng thay i. DDRAM khng thay i.
C: Hin th con tr khi C=1 v ngc li. C: Hin th con tr khi C=1 v ngc li.
B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li. B: Nhp nhy k t ti v tr con tr khi B=1 v ngc li.
Chu k nhp nhy khong 409,6ms khi mch dao ng ni LCD l Chu k nhp nhy khong 409,6ms khi mch dao ng ni LCD l
250kHz. 250kHz.
Cursor Cursor
or or
display display
shift shift
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 0 1 [S/C] [R/L] * * DBx = 0 0 0 1 [S/C] [R/L] * *
Lnh Cursor or display shift dch chuyn con tr hay d liu hin th Lnh Cursor or display shift dch chuyn con tr hay d liu hin th
sang tri m khng cn hnh ng ghi/c d liu. Khi hin th kiu 2 sang tri m khng cn hnh ng ghi/c d liu. Khi hin th kiu 2
dng, con tr s nhy xung dng di khi dch qua v tr th 40 ca dng, con tr s nhy xung dng di khi dch qua v tr th 40 ca
hng u tin. D liu hng u v hng 2 dch cng mt lc. Chi tit hng u tin. D liu hng u v hng 2 dch cng mt lc. Chi tit
s dng xem bng bn di: s dng xem bng bn di:
S/C S/C R/L R/L Hot ng Hot ng
00 00 Dch v tr con tr sang tri (Ngha l gim AC mt Dch v tr con tr sang tri (Ngha l gim AC mt
n v). n v).
00 11 Dch v tr con tr sang phi (Tng AC ln 1 n Dch v tr con tr sang phi (Tng AC ln 1 n
v). v).
11 00 Dch ton b ni dung hin th sang tri, con tr Dch ton b ni dung hin th sang tri, con tr
cng dch theo. cng dch theo.
11 11 Dch ton b ni dung hin th sang phi, con tr Dch ton b ni dung hin th sang phi, con tr
cng dch theo. cng dch theo.
Function Function
set set
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 0 1 [DL] [N] [F] * * DBx = 0 0 1 [DL] [N] [F] * *
DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit (t bit DL: Khi DL=1, LCD giao tip vi MPU bng giao thc 8 bit (t bit
DB7 n DB0). Ngc li, giao thc giao tip l 4 bit (t bit DB7 n DB7 n DB0). Ngc li, giao thc giao tip l 4 bit (t bit DB7 n
bit DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2 ln lin bit DB0). Khi chn giao thc 4 bit, d liu c truyn/nhn 2 ln lin
tip. vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn sau. tip. vi 4 bit cao gi/nhn trc, 4 bit thp gi/nhn sau.
N : Thit lp s hng hin th. Khi N=0 : hin th 1 hng, N=1: hin th N : Thit lp s hng hin th. Khi N=0 : hin th 1 hng, N=1: hin th
2 hng. 2 hng.
F : Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1: kiu k F : Thit lp kiu k t. Khi F=0: kiu k t 5x8 im nh, F=1: kiu k
t 5x10 im nh. t 5x10 im nh.
Set Set
CGRAM CGRAM
address address
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 0 1 [ACG][ACG][ACG][ACG][ACG][ACG] DBx = 0 1 [ACG][ACG][ACG][ACG][ACG][ACG]
Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch 1 bit ca Lnh ny ghi vo AC a ch ca CGRAM. K hiu [ACG] ch 1 bit ca
chui d liu 6 bit. Ngay sau lnh ny l lnh c/ghi d liu t chui d liu 6 bit. Ngay sau lnh ny l lnh c/ghi d liu t
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Chn cp ngun (Vcc-GND) Chn cp ngun (Vcc-GND) Min:-0.3V , Max+7V Min:-0.3V , Max+7V
Cc chn ng vo (DBx,E,) Cc chn ng vo (DBx,E,) Min:-0.3V , Max:(Vcc+0.3V) Min:-0.3V , Max:(Vcc+0.3V)
Nhit hot ng Nhit hot ng Min:-30C , Max:+75C Min:-30C , Max:+75C
Nhit bo qun Nhit bo qun Min:-55C , Max:+125C Min:-55C , Max:+125C
CGRAM ti a ch c ch nh. CGRAM ti a ch c ch nh.
Set Set
DDRAM DDRAM
address address
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD] DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD] [AD]
Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit lp ta Lnh ny ghi vo AC a ch ca DDRAM, dng khi cn thit lp ta
hin th hin th
mong mun. Ngay sau lnh ny l lnh c/ghi d liu t DDRAM mong mun. Ngay sau lnh ny l lnh c/ghi d liu t DDRAM
ti a ch c ch nh. ti a ch c ch nh.
Khi ch hin th 1 hng: a ch c th t 00H n 4FH. Khi Khi ch hin th 1 hng: a ch c th t 00H n 4FH. Khi
ch hin th 2 hng, a ch t 00h n 27H cho hng th nht, v ch hin th 2 hng, a ch t 00h n 27H cho hng th nht, v
t 40h n 67h cho hng th 2. t 40h n 67h cho hng th 2.
Read BF Read BF
and and
address address
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx =[BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC] DBx =[BF] [AC] [AC] [AC] [AC] [AC] [AC] [AC]
(RS=0,R/W=1) (RS=0,R/W=1)
Nh cp trc y, khi c BF bt, LCD ang lm vic v lnh Nh cp trc y, khi c BF bt, LCD ang lm vic v lnh
tip theo (nu c) s b b qua nu c BF cha v mc thp. Cho tip theo (nu c) s b b qua nu c BF cha v mc thp. Cho
nn, khi lp trnh iu khin, phi kim tra c BF trc khi ghi d liu nn, khi lp trnh iu khin, phi kim tra c BF trc khi ghi d liu
vo LCD. vo LCD.
Khi c c BF, gi tr ca AC cng c xut ra cc bit [AC]. N l Khi c c BF, gi tr ca AC cng c xut ra cc bit [AC]. N l
a ch ca a ch ca
CG hay DDRAM l ty thuc vo lnh trc . CG hay DDRAM l ty thuc vo lnh trc .
Write Write
data to data to
CG or CG or
DDRAM DDRAM
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = [Write data] DBx = [Write data]
(RS=1, R/W=0) (RS=1, R/W=0)
Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo cc chn Khi thit lp RS=1, R/W=0, d liu cn ghi c a vo cc chn
DBx t mch DBx t mch
ngoi s c LCD chuyn vo trong LCD ti a ch c xc nh ngoi s c LCD chuyn vo trong LCD ti a ch c xc nh
t lnh ghi a ch trc (lnh ghi a ch cng xc nh lun vng t lnh ghi a ch trc (lnh ghi a ch cng xc nh lun vng
RAM cn ghi) RAM cn ghi)
Sau khi ghi, b m a ch AC t ng tng/gim 1 ty theo thit lp Sau khi ghi, b m a ch AC t ng tng/gim 1 ty theo thit lp
Entry mode. Entry mode.
Read Read
data data
from CG from CG
or or
DDRAM DDRAM
M lnh : M lnh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DBx = [Read data] DBx = [Read data]
(RS=1, R/W=1) (RS=1, R/W=1)
Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c chuyn ra Khi thit lp RS=1, R/W=1,d liu t CG/DDRAM c chuyn ra
MPU thng qua cc chn DBx (a ch v vng RAM c xc MPU thng qua cc chn DBx (a ch v vng RAM c xc
nh bng lnh ghi a ch trc ). nh bng lnh ghi a ch trc ).
Sau khi c, AC t ng tng/gim 1 ty theo thit lp Entry mode, Sau khi c, AC t ng tng/gim 1 ty theo thit lp Entry mode,
tuy nhin ni dung hin th khng b dch bt chp ch Entry tuy nhin ni dung hin th khng b dch bt chp ch Entry
mode. mode.
5> Giao tip gia LCD v MPU : 5> Giao tip gia LCD v MPU :
a> c tnh in ca cc chn giao tip : a> c tnh in ca cc chn giao tip :
LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong c tnh in sau y: LCD s b hng nghim trng, hoc hot ng sai lch nu bn vi phm khong c tnh in sau y:
Bng 6 : Maximun Rating Bng 6 : Maximun Rating
c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V n 5.5V, T = -30 n +75C) c tnh in lm vic in hnh: (o trong iu kin hot ng Vcc = 4.5V n 5.5V, T = -30 n +75C)
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Chn cp ngun Vcc-GND Chn cp ngun Vcc-GND 2.7V n 5.5V 2.7V n 5.5V
in p vo mc cao VIH in p vo mc cao VIH 2.2V n Vcc 2.2V n Vcc
in p vo mc thp VIL in p vo mc thp VIL -0.3V n 0.6V -0.3V n 0.6V
in p ra mc cao (DB0-DB7) in p ra mc cao (DB0-DB7) Min 2.4V (khi IOH = -0.205mA) Min 2.4V (khi IOH = -0.205mA)
in p ra mc thp (DB0-DB7) in p ra mc thp (DB0-DB7) Max 0.4V (khi IOL = 1.2mA) Max 0.4V (khi IOL = 1.2mA)
Dng in ng vo (input leakage current) ILI Dng in ng vo (input leakage current) ILI -1uA n 1uA (khi VIN = 0 n Vcc) -1uA n 1uA (khi VIN = 0 n Vcc)
Dng in cp ngun ICC Dng in cp ngun ICC 350uA(typ.) n 600uA 350uA(typ.) n 600uA
Tn s dao ng ni fOSC Tn s dao ng ni fOSC 190kHz n 350kHz (in hnh l 270kHz) 190kHz n 350kHz (in hnh l 270kHz)
Bng 7: Min lm vic bnh thng Bng 7: Min lm vic bnh thng
b> S ni mch in hnh: b> S ni mch in hnh:
- S mch kt ni gia m un LCD v VK 89S52 (8 bit). - S mch kt ni gia m un LCD v VK 89S52 (8 bit).
- S mch kt ni gia mun LCD v VK (4 bit). - S mch kt ni gia mun LCD v VK (4 bit).
c> Bus Timing: c> Bus Timing:
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6> Khi to LCD: 6> Khi to LCD:
Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to gip ta thit lp cc giao thc lm Khi to l vic thit lp cc thng s lm vic ban u. i vi LCD, khi to gip ta thit lp cc giao thc lm
vic gia LCD v MPU. Vic khi to ch c thc hin 1 ln duy nht u chng trnh iu khin LCD v vic gia LCD v MPU. Vic khi to ch c thc hin 1 ln duy nht u chng trnh iu khin LCD v
bao gm cc thit lp sau : bao gm cc thit lp sau :
Display clear : Xa/khng xa ton b ni dung hin th trc . Display clear : Xa/khng xa ton b ni dung hin th trc .
Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t 5x8/5x10. Function set : Kiu giao tip 8bit/4bit, s hng hin th 1hng/2hng, kiu k t 5x8/5x10.
Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng nhp nhy. Display on/off control: Hin th/tt mn hnh, hin th/tt con tr, nhp nhy/khng nhp nhy.
Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim (Increment). Entry mode set : cc thit lp kiu nhp k t nh: Dch/khng dch, t tng/gim (Increment).
a> Mch khi to bn trong chp HD44780: a> Mch khi to bn trong chp HD44780:
Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n. V trong thi gian khi to Mi khi c cp ngun, mch khi to bn trong LCD s t ng khi to cho n. V trong thi gian khi to
ny c BF bt ln 1, n khi vic khi to hon tt c BF cn gi trong khong 10ms sau khi Vcc t n 4.5V (v ny c BF bt ln 1, n khi vic khi to hon tt c BF cn gi trong khong 10ms sau khi Vcc t n 4.5V (v
2.7V th LCD hot ng). Mch khi to ni s thit lp cc thng s lm vic ca LCD nh sau: 2.7V th LCD hot ng). Mch khi to ni s thit lp cc thng s lm vic ca LCD nh sau:
Display clear : Xa ton b ni dung hin th trc . Display clear : Xa ton b ni dung hin th trc .
Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8 Function set: DL=1 : 8bit; N=0 : 1 hng; F=0 : 5x8
Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off. Display on/off control: D=0 : Display off; C=0 : Cursor off; B=0 : Blinking off.
Entry mode set: I/D =1 : Tng; S=0 : Khng dch. Entry mode set: I/D =1 : Tng; S=0 : Khng dch.
Nh vy sau khi m ngun, bn s thy mn hnh LCD ging nh cha m ngun do ton b hin th tt. Do , Nh vy sau khi m ngun, bn s thy mn hnh LCD ging nh cha m ngun do ton b hin th tt. Do ,
ta phi khi to LCD bng lnh. ta phi khi to LCD bng lnh.
b> Khi to bng lnh: (chui lnh) b> Khi to bng lnh: (chui lnh)
Vic khi to bng lnh phi tun theo lu sau ca nh sn xut : Vic khi to bng lnh phi tun theo lu sau ca nh sn xut :
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Bi ng Mi hn Bi ng Mi hn Bi ng C hn Bi ng C hn
Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc mi bt in ln). V khi kt ni Nh cp trn, ch giao tip mc nh ca LCD l 8bit (t khi to lc mi bt in ln). V khi kt ni
mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng c kt ni n LCD, nn lnh khi to ban u (lnh mch theo giao thc 4bit, 4 bit thp t DB0-DB3 khng c kt ni n LCD, nn lnh khi to ban u (lnh
chn giao thc giao tip function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua chn giao thc giao tip function set 0010****) phi giao tip theo ch 8 bit (ch gi 4 bit cao mt ln, b qua
4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble. 4 bit thp). T lnh sau tr i, phi gi/nhn lnh theo 2 nibble.
Lu l sau khi thit lp function set, bn khng th thay i function set ngoi tr thay i giao thc giao tip Lu l sau khi thit lp function set, bn khng th thay i function set ngoi tr thay i giao thc giao tip
(4bit/8bit). (4bit/8bit).
(ngun: trietnguyen) (ngun: trietnguyen)
Trang ch Trang ch
0 nhn xt: 0 nhn xt:
ng mt Nhn xt ng mt Nhn xt
+2 xut url ny trn Google
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Nhn xt vi t cch:
Cc lin kt vi bi ny Cc lin kt vi bi ny
To mt Lin kt To mt Lin kt

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