ACOP

bq24751A
28 LD QFN
TOP VIEW
LEARN
SRN
BAT
CELLS
SRP
SRSET
IADAPT
ACDRV
ACSET
CHGEN
ACN
ACP
ACDET
P
V
C
C
B
T
S
T
H
I
D
R
V
R
E
G
N
P
H
L
O
D
R
V
P
G
N
D
O
V
P
S
E
T
A
G
N
D
V
R
E
F
V
A
D
J
V
D
A
C
A
C
G
O
O
D
B
A
T
D
R
V
1
2
3
4
5
6
7
8 9 10 11 12 13 14
15
16
17
18
19
20
21
27 26 25 24 23 22 28

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VREF
RAC
RSR
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers .
Q2 (ACFET)
SI4435
Q3(BATFET)
SI4435
N
P P
ACN
ACP
ACDRV
ACDET
ACGOOD
SRSET
ACSET
VREF
DAC
CELLS
CHGEN
VDAC
VADJ
DAC
ADC
IADAPT
HOST
PVCC
BATDRV
HIDRV
N
PH
BTST
REGN
LODRV
PGND
SRP
SRN
P
PACK+
PACK-
SYSTEM ADAPTER+
ADAPTER-
ACGOOD
AGND
bq24751A
R1
R2
66.5
kW
10 kW R4
C4
100 pH C5
C8
Q4
FDS6680A
Q5
FDS6680A
C9
L1
D1 BAT54
1 F m C10
C4
BAT
OVPSET
LEARN
ACOP
Q1 (ACFET)
SI4435
R3 422 kW
C3
C2
0.1 F m
0.1 F m
0.010 W
1 F m
C6
10 F m
C7
10 F m
0.010 W
C12
10 F m
0.1 F m
C13
0.1 F m
C11
10 F m
0.1 F m
C15
0.1 F m
C16
0.47 F m
1 F m
432 k 1% W
8.2 H m
PowerPad
C19
10 F m
C18
10 F m
C17
10 F m
R5 71 kW
R6 100 kW

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VREF
R1 432 kW
R2
66.5
kW
10 kW R4
R3 422 kW
R5 71 kW
RAC
RSR
(1) Pull-up rail could be either VREF or other system rail .
(2) SRSET/ACSET could come from either DAC or resistor dividers .
Q2 (ACFET)
SI4435
Q3(BATFET)
SI4435
N
P P
ACN
ACP
ACDRV
ACDET
ACGOOD
PVCC
BATDRV
HIDRV
N
PH
BTST
REGN
LODRV
PGND
SRP
SRN
P
PACK+
PACK-
SYSTEM ADAPTER+
ADAPTER-
ACGOOD
AGND
bq24751A
C8
Q4
FDS6680A
Q5
FDS6680A
C9
L1
D1 BAT54
C4
BAT
OVPSET
LEARN
ACOP
Q1 (ACFET)
SI4435
C3
C2
0.1 F m
0.1 F m
0.010 W
1 F m
C6
10 F m
C7
10 F m
0.010 W
C12
10 F m
0.1 F m
C13
0.1 F m
C11
10 F m
0.1 F m
C15
0.1 F m
C16
0.47 F m
8.2 H m
PowerPad
SRSET
ACSET
VREF
CELLS
CHGEN
VDAC
VADJ
GPIO
ADC IADAPT
HOST
C4
1 F m
C5
100 pF
66.5 kW
R9
R8 100 kW
43 kW
R7
R6
100 kW
C19
10 F m
C1
10 F m
C18
10 F m
C17
10 F m
R10 100 kW
C10
1 F m

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-0.20
-0.10
0
0.10
0.20
0.30
0.40
0.50
0 10 20 30 40 50
VREF - Load Current - mA
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
PVCC = 10 V
PVCC = 20 V
-3
-2.50
-2
-1.50
-1
-0.50
0
0 10 20 30 40 50 60 70 80
REGN - Load Current - mA
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
PVCC = 10 V
PVCC = 20 V
0
1
2
3
4
5
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
SRSET/VDAC Ratio
C
h
a
r
g
e

C
u
r
r
e
n
t

R
e
g
u
l
a
t
i
o
n

-
A
SRSET Varied,
4-Cell,
Vbat = 16 V
16
16.2
16.4
16.6
16.8
17
17.2
17.4
17.6
17.8
18
18.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VADJ/VDAC Ratio
V
o
l
t
a
g
e

R
e
g
u
l
a
t
i
o
n

-

V
VADJ = 0 -VDAC,
4-Cell,
No Load
V = 16.8 V
reg
-0.2
-0.1
0
0.1
0.2
0
2000 4000
6000 8000
Charge Current - mA
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
0
1
2
3
4
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ACSET/VDAC Ratio
I
n
p
u
t

C
u
r
r
e
n
t

R
e
g
u
l
a
t
i
o
n

-
A
ACSET Varied,
4-Cell,
Vbat = 16 V
5

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SRSET Varied
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
0 2 4 6 8
I Setpoint - A
(CHRG)
-
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
4-Cell, VBAT = 16 V
VADJ = 0 -VDAC
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
16.5 17 17.5 18 18.5 19
V - Setpoint - V
(BAT)
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
4-Cell, no load
ACSET Varied
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0 1 2 3 4 5 6
Input Current Regulation Setpoint - A
R
e
g
u
l
a
t
i
o
n

E
r
r
o
r

-

%
4-Cell, VBAT = 16 V
Iadapt Amplifier Gain
-25
-20
-15
-10
-5
0
5
0 1 2 3 4 5 6 7 8 9 10
I - A
(ACPWR)
P
e
r
c
e
n
t

E
r
r
o
r
V = 20 V, CHG = EN
I
V = 20 V, CHG = DIS
I
V = 20 V,
4-Cell,
V = 16 V
I
bat
0
1
2
3
4
5
0 1 2 3 4
System Current - A
I
c
h
r
g

a
n
d

I
i
n

-
A
Input Current
Charge Current

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V = 20 V,
Ichrg_set = 4 A,
T = 20 C
in
A

0
1
2
3
4
5
0 2 4 6 8 10 12 14 16 18
Battery Voltage - V
C
h
a
r
g
e

C
u
r
r
e
n
t

-
A
70
80
90
100
0 2000 4000 6000 8000
Battery Charge Current - mA
E
f
f
i
c
i
e
n
c
y

-

%
V = 12.6 V
reg
V = 16.8 V
(BAT)
V = 8.4 V
reg
C
h
2
2
0
V
/
d
i
v
t Time = 400 s/div m
C
h
1
2
0
V
/
d
i
v
C
h
4
1
0
V
/
d
i
v
C
h
3
1
0
V
/
d
i
v
V
BAT
V
SYS
V
ACDRV
V
BATDRV

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C
h
2
2
0
V
/
d
i
v
t Time = 2 ms/div
C
h
1
2
0
V
/
d
i
v
C
h
4
1
0
V
/
d
i
v
C
h
3
1
0
V
/
d
i
v
V
BAT
V
SYS
V
ACDRV
V
BATDRV

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IADAPT
ACGOOD
PVCC
ACDRV
BATDRV
BTST
HIDRV
PH
REGN
LODRV
PGND
LEARN
bq24751A
ACDET
ACP
ACN
BAT
SRP
AGND
6V LDO
V(ACP-ACN)
+
-
V(SRP-SRN)
ADAPTER DETECTED
COMP
ERROR
AMPLIFIER
V(ACN-BAT)
V(IADAPT)
+
-
20x
ACP
ACN
ENA_BIAS
20uA
IIN_ER
BAT_ER
ICH_ER
1V
20uA
285 mV
+ _
IIN_REG
VBAT_REG
IBAT_ REG
SRN
10mA
ACN-6V
PVCC-6V
PVCC
PVCC-6V PVCC-6V
LDO
DC-DC
CONVERTER
PWM LOGIC
PVCC
PH
4 V
+
_
BTST REFRESH
CBTST
SYSTEM
POWER
SELECTOR
LOGIC
/CHGEN
CHG_OCP
BAT_OVP
155C
IC Tj TSHUT
185 mV
+ _
PVCC
PVCC- BAT
LEVEL
SHIFTER
ACN
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
BAT_SHORT
ACOP
SYNCH
BAT
BAT_SHORT
+
-
2.9 V/cell
+
-
V(SRP-SRN)
CHG_OCP
+
-
145% X IBAT_REG
SYNCH
+
-
V(SRP - SRN)
SRSET
VADJ
VDAC
ACSET
VBAT_REG
IBAT_REG
IIN_REG
VBATSET
IBATSET
IINSET
RATIO
PROGRAM
+
-
13mV
20X
BAT
BAT_OVP
+
-
104% X VBAT_REG
CHRG_ON
SUSPEND
3.1 V
ACOV
+
-
UVLO
+
-
OVPSET
PVCC
+
-
4 V
VREF
3.3V
LDO
PVCC
FBO
EAI EAO
ENA_BIAS
ENA_BIAS
2.4V
+
-
ENA_BIAS
0.6V
+
-
OVPSET
CHGEN
ACOPS
5uA
VREF
Isrc=K*V(PVCC-ACP)
K=18uA/V
ACOPDET
-
+
2V
-
+
ENA_SRC
ENA_SNK
S
R Q
Q
ACDET
PVCC_UVLO
ACOP_LATCH
Delay
Rising
700 ms
CELLS
2, 3, 4
BAT

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V
BATT
+ cell count 4V )0.5
V
VADJ
V
VDAC

I
CHARGE
+
V
SRSET
V
VDAC

0.10
R
SR

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I
ADAPTER
+
V
ACSET
V
VDAC

0.10
R
AC

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f
o
+
1
2p L
o
C
o

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I
RIPPLE_MAX
2
vI
SYN
vI
RIPPLE_MAX
and I
RIPPLE_MAX
+

V
IN_MAX
*V
BAT_MIN

V
BAT_MIN
V
IN_MAX

1
f
s

L
MIN

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) ACP PVCC ( V I V I Power

LIM _ ACOC sd d
- = =

) ACP PVCC ( V 18mA/V

V 2 C
i
V C
t
ACOP
ACOP
ACOP ACOP
-

=
D
= D

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700ms
2ms
A
C
O
C
,
N
o
L
a
t
c
h
-
o
f
f
ACOC, with ACOP Latch-off,
Latch-off time accumulates
only when in current limit
regulation, ACOC. The time
before latch-off is
programmable with Cacop,
and is inversely proportional to
source-drain voltage of
ACFET (power). Cacop
charge/discharge per time
also provides memory for
power averaging over time.
700ms delay after
ACDET, before allow
ACDRV to turn-on
In all cases, after 700ms
delay, have input over-
current protection,
ACOC, by linearly limiting
input current.
Threshold is equal to the
lower of Idpm*1.5, or
10A.
8ms
Allow Charge to Turn-on
After Latch-Off, Latch
can only clear by:
1) bringing ACDET below
2.4V, then above 2. 4V; or
2) bringing PVCC below
UVLO, then above
UVLO.
Vin
ACDET
ACGOOD
BATDRV
ACDRV
Vsystem
Input Current
Vadapter
0V
Vadapter
Vbattery
Allow Charge
Charge Current
Ilim= 1.5xIdpm
(100 mV max
Across ACP_ACN)
V(ACOP)

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ACOC_REG
V(PVCC-ACP)
Iacop_pin
2V
V(ACOP)
ON
OFF
ACDRV_ON
LATCH-OFF
LATCH-OFF
Ilim= 1.5xIdpm
Iin
LATCH-OFF
Memory Effect
Averages Power

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5uA
REF=3.3V
Isrc=K*V(PVCC- ACP)
18 A/V m
ACOP
Cacop
ACOP Adaptor
Over Power
Comparator
ACOPDET
-
+
S
R Q
Q
ACDET
Deglitch
1 s m
ACOPDETDG
2V
-
+
ACP
PVCC
ACDRV
ACN
ENA_SRC
ENA_SNK
+
-
+
-
+
-
IIN
Differential Amp
CSA
V(ACP-ACN)
VDS
Differential Amp
V(PVCC-ACP)
Regulation
Reference
Lowest of
1.5xIDPM_PRG
or
10A (100mV)
IDPM_PRG
(100 mV_max)
ACOCREG =
REGULATING
ACOC ERROR
AMPLIFIER &
DRIVER
IADAPT
IDPM
Ratio-
metric
Program
ACSET
To Clear LATCH User must remove adapter
and reinsert, or PVCC brough below then
above input UVLO threshold in order to clear
latched fault
PVCC_UVLO
Turn-off ACDRV
ACDET
700 ms
Delay
ACDRV &
BATDRV
break-
before-make
logic
ACDRV_ON
RAC
0.010
Q2 (ACFET)
SI4435
P P
ADAPTER+
ADAPTER-
10uF
10 F m
C1
0.1uF C2
0.1uF
C3
Q1 (ACFET)
SI4435
0.47uF
10 F m 10 F m

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C1 C8
Ri Li
Ci
Vi Vc
Ii
C1 C8
Ri Li
Ci
Vi
Ii

w w - w -
w
+
w
w
+ =
-
t cos t sin
L 2
R
e
C Z
V
C Z
V
) 0 ( V ) t ( V
i
i
t
L 2
R
2
0 i 0
i
2
0 i 0
i
C C
i
i

i
i
0
C
L
Z =

2
i
i
i i
L 2
R
C L
1

- = w

i i
0
C L
1
= w

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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
Ci = 20 F m
Ci = 40 F m
Ri = 0.21 ,
Li = 9.3 H
W
m
(a) Vc with various Ci values
I
n
p
u
t

C
a
p
a
c
i
t
o
r

V
o
l
t
a
g
e

-

V
Time - ms
Li = 12 F m
Ri = 0.15 ,
Ci = 40 F
W
m
(b) Vc with various Li values
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
I
n
p
u
t

C
a
p
a
c
i
t
o
r

V
o
l
t
a
g
e

-

V
Li = 5 F m
Time - ms
Ri = 0.50 W
Li = 9.3 H,
Ci = 40 F
m
m
(c) Vc with various Ri values
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
5
10
15
20
25
30
35
I
n
p
u
t

C
a
p
a
c
i
t
o
r

V
o
l
t
a
g
e

-

V
Ri = 0.15 W
Time - ms

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Ci = 20 F m Ci = 40 F m
( c) Ci =49 ( 47 el ect rol yt i c and 2x ceramic) m m m F F F

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(a) Top Layer

(b) Bottom Layer

PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
BQ24751ARHDR PREVIEW QFN RHD 28 3000 TBD Call TI Call TI
BQ24751ARHDT PREVIEW QFN RHD 28 250 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2007
Addendum-Page 1