2512 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO.

8, AUGUST 2013
Sub-60-nm Extremely Thin Body
In
x
Ga
1x
As-On-Insulator MOSFETs on Si With
Ni-InGaAs Metal S/D and MOS Interface Buffer
Engineering and Its Scalability
Sanghyeon Kim, Student Member, IEEE, Masafumi Yokoyama, Member, IEEE, Noriyuki Taoka, Ryosho Nakane,
Tetsuji Yasuda, Osamu Ichikawa, Noboru Fukuhara, Masahiko Hata, Member, IEEE,
Mitsuru Takenaka, Member, IEEE, and Shinichi Takagi, Member, IEEE
AbstractWe report the operation of sub-60-nm deeply
scaled InGaAs- and InAs-on-insulator (-OI) MOSFETs on
Si substrates with MOS interface buffer engineering and Ni-
InGaAs metal source/drain (S/D). InAs-OI MOSFETs provide
400% I
on
enhancement, compared with an In
0.53
Ga
0.47
As
control device with the same drain-induced-barrier-lowering
(DIBL) of 100 mV/V, which is attributable to the mobility
enhancement and the S/D parasitic resistance (R
SD
) reduction.
In addition, InAs-OI MOSFETs with the MOS interface buffers
show excellent electrostatic characteristics. InAs-OI MOSFETs
with a channel length (L
ch
) of 55 nm shows small DIBL of
84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both
of which do not signicantly degrade with a decrease of L
ch
,
thanks to the extremely thin channel thickness. In addition,
from the simulation study, we have found that further vertical
scaling and back biasing techniques can improve the control of
short channel effect in InAs-OI MOSFETs.
Index TermsExtremely thin body (ETB) MOSFETs,
InGaAs MOSFETs, metal source/drain (S/D), Ni-InGaAs S/D,
Schottky S/D.
I. INTRODUCTION
III
V MATERIALS are actively studied as channel
alternatives for n-FET in the future CMOS technology
[1][20]. This is because they have high electron mobility and
low electron effective mass. In order to apply those channel
Manuscript received March 18, 2013; revised May 12, 2013; accepted
June 12, 2013. Date of publication July 9, 2013; date of current version
July 19, 2013. This work was supported in part by the Research and
Development Program for the Innovative Energy Efciency Technology, the
Innovation Research Project on Nano electronics Materials and Structures,
and the New Energy and Industrial Technology Development Organization,
Japan. The review of this paper was arranged by Editor H. S. Momose.
S. Kim, M. Yokoyama, N. Taoka, R. Nakane, M. Takenaka, and
S. Takagi are with the Department of Electrical Engineering and
Information Systems, The University of Tokyo, Tokyo 113-003, Japan
(e-mail: dadembyora@mosfet.t.u-tokyo.ac.jp; yokoyama@mosfet.t.u-tokyo.
ac.jp; ntaoka@alice.xtal.nagoya-u.ac.jp; nakane@cryst.t.u-tokyo.ac.jp;
takenaka@mosfet.t.u-tokyo.ac.jp; takagi@ee.t.u-tokyo.ac.jp).
T. Yasuda is with the National Institute of Advanced Industrial Science and
Technology, Ibaraki 305-8568, Japan (e-mail: yasuda-t@aist.go.jp).
O. Ichikawa, N. Fukuhara, and M. Hata are with Sumitomo Chemical Co.
Ltd., Ibaraki 300-3294, Japan (e-mail: ichikawao2@sc.sumitomo-chem.co.jp;
fukuharan1@sc.sumitomo-chem.co.jp; hatam1@sc.sumitomo-chem.co.jp).
Color versions of one or more of the gures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TED.2013.2270558
materials to future ultimately scaled CMOS, the control of
short channel effects (SCEs) is a key issue. Therefore, many
recent related studies have focused on IIIV channel MOS-
FETs employing 3-D structures, such as FinFETs, nanowires,
etc., which are promising structures for suppressing SCEs
[1], [2], and [5][9]. We have also developed an extremely
thin body (ETB) IIIV-on-insulator (IIIV-OI) structures using
direct wafer bonding (DWB) techniques in order to avoid
SCEs and have already demonstrated 3-nm-thick InGaAs-OI
MOSFETs [10][15]. In ETB MOSFETs, however, mobility
degradation with a decrease of body thickness (T
body
) <10 nm
is a limiting factor to achieve both high mobility and good
controllability of SCEs at the same time [12][18]. Therefore,
we have proposed the channel engineering, which introduces
the In
x
Ga
1x
As channel with higher indium content and MOS
interface buffer layers with higher conduction band edge [14],
[15]. As a result, we have achieved high peak mobility of 3180
cm
2
/Vs even in 3-nm-thick InAs-OI MOSFETs with 3-nm-
thick In
0.3
Ga
0.7
As MOS interface buffer layers at the top and
bottom of the channel. Moreover, the indium content increase
is also effective in the reduction of source/drain (S/D) parasitic
resistance (R
SD
) for the metal S/D structure used in the MOS-
FETs. This is because the increase of indium content results in
the reduction of the Schottky barrier height (SBH) [19], [20].
However, the immunity against SCEs and the current drive of
the InAs-OI MOSFETs using this channel engineering have
not been experimentally examined yet with L
ch
<100 nm.
Therefore, in this paper, we have demonstrated the deeply
scaled InAs-OI MOSFETs with the MOS interface buffer
layers on a Si substrate with the Ni-InGaAs metal S/D
structures and extremely thin T
body
. Reduction in gate lengths
due to encroachment of Ni silicides has been reported for Si
nanowire FETs [21], [22]. We have fabricated deeply scaled
MOSFETs with L
ch
of down to 55 nm by using the similar
approach. Furthermore, we have investigated the scalability
of the InAs-OI MOSFETs using technology computer aided
design (TCAD) simulation [23]. We have found that further
vertical scaling, such as EOT, EOT of BOX and T
body
scaling,
and a back biasing technique can give us better electrostatic
control in the present device structure, allowing us the further
device scaling.
0018-9383/$31.00 2013 IEEE
KIM et al.: SUB-60-nm EXTREMELY THIN BODY InxGa
1x
As-On-INSULATOR MOSFETs ON Si 2513
Fig. 1. Fabrication process of scaled In
x
Ga
1x
As-OI MOSFET with lateral
Ni encroachment.
II. FABRICATION OF DEEPLY SCALED
In
x
Ga
1x
As-OI MOSFETs
The IIIV-OI structures were fabricated by DWB [10][15].
The IIIV-OI structures are formed on the Si sub-
strates by using a p-type In
0.53
Ga
0.47
As control channel
(N
A
10
16
cm
3
, 10-nm thickness) without any MOS
interface buffer layers and unintentionally doped InAs
channels with MOS interface buffer In
0.3
Ga
0.7
As layers
(In
0.3
Ga
0.7
As/InAs/In
0.3
Ga
0.7
As structure with the thick-
ness of 3/3/3 nm). Using these wafers, MOSFETs with
Ni-InGaAs metal S/D are fabricated on the IIIV-OI sub-
strates. Fabrication process of MOSFETs with Ni-InGaAs
metal S/D [19], [20] is shown in Fig. 1. The IIIV-OI
wafers are cleaned by acetone, NH
4
OH, and (NH
4
)
2
S
x
, and
6- and 12-nm Al
2
O
3
is deposited by atomic layer deposition.
Subsequently, Ta gate is formed by sputtering, followed by
rapid thermal annealing (RTA) at 350 C. The gate patterning
is done by electron beam lithography. Then, 20-nm Ni for
S/D formation is deposited and RTA is carried out at 250 C
for 1 min in N
2
ambient to form the Ni-InGaAs S/D for all
the devices. During this RTA, Ni diffused toward the lateral
direction of the channels by a diffusion length of around
50 nm. This encroachment allows us to fabricate the deeply
scaled MOSFETs under several hundred nanometer gate pat-
terns. It has been reported in [24] that the diffusion length
of Ni into InGaAs can be controlled by RTA temperature,
RTA time, and Ni thickness. Finally, unreacted Ni is removed
by HCl. The cross-sectional transmission electron microscope
(TEM) images of a fabricated MOSFET with the buffer layer
(3/3/3 nm) are shown in Fig. 2. It is found that ETB InAs-OI
MOSFETs are fabricated on a Si substrate with the metal S/D
structures. The large area TEM image shows that the formed
InGaAs-OI and the buried oxide (BOX) layer have good
uniformity. It is observed that the Ni-InGaAs regions diffused
laterally along the thin body InGaAs-OI channel layers. As
result, it is evaluated directly from this TEM analysis that the
effective L
ch
is 55 nm with the dened gate length of 160 nm.
L
ch
for the other devices is estimated under an assumption
that the diffusion length of Ni into InGaAs is same for all the
devices.
Fig. 2. Cross-sectional TEM images of the fabricated InAs-OI MOSFETs
with a L
ch
of 55 nm, T
body
of 3/3/3 nm.
Fig. 3. (a) I
D
V
G
and (b) I
D
V
D
characteristics of InAs-OI MOSFETs with
a T
body
of 3/3/3 nm, T
ox
= 6 nm.
Fig. 4. (a) S.S. and (b) DIBL characteristics of In
0.53
Ga
0.47
As MOSFET
with different T
ox
of 12 nm (red symbol) and 6 nm (blue symbol).
III. ELECTRICAL PROPERTIES OF In
x
Ga
1x
As-OI
N-MOSFET
The I
D
V
G
and I
D
V
D
characteristics of the InAs-OI MOS-
FET with L
ch
of 55 nm, T
body
of 3/3/3 nm and Al
2
O
3
gate
dielectric thickness (T
ox
) of 6 nm are shown in Fig. 3(a) and
(b), respectively. The device shows good transfer and out-
put characteristics with small drain-induced-barrier-lowering
(DIBL) in spite of quite thick EOT of around 3.5 nm. This
result demonstrates the operation of ETB InAs-OI MOSFETs
on Si substrates with a sub-100-nm L
ch
region.
2514 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 8, AUGUST 2013
Fig. 5. V
th
of In
0.53
Ga
0.47
As MOSFET without buffers (blue symbol) and
InAs MOSFET with buffer (red symbol).
The S.S. and DIBL characteristics of the In
0.53
Ga
0.47
As-OI
MOSFETs (T
body
= 10 nm) with T
ox
of 6 and 12 nm are
shown in Fig. 4(a) and (b), respectively. The MOSFETs with
thinner T
ox
exhibit the lower S.S. and DIBL. These results
show that EOT scaling is effective to achieve good electrostatic
characteristics. V
th
characteristics of In
0.53
Ga
0.47
As-OI (with-
out buffers, T
body
= 10 nm) and InAs-OI MOSFETs (with
buffers, T
body
= 3/3/3 nm) at the V
D
of 0.5 V is shown in
Fig. 5. Both devices did not show the signicant V
th
roll-off
characteristics, indicating the good controllability of SCEs in
ETB InGaAs-OI structures. On the other hand, more positive
V
th
is obtained in In
0.53
Ga
0.47
As-OI MOSFETs than in InAs-
OI MOSFETs. This more positive V
th
of In
0.53
Ga
0.47
As is
attributable to the energy difference of the conduction band
minimum (CBM) [25]. CBM of In
0.53
Ga
0.47
As is higher
than that of InAs can cause the more positive V
th
shift in
In
0.53
Ga
0.47
As-OI MOSFETs.
Comparison in S.S. and DIBL between In
0.53
Ga
0.47
As-OI
MOSFETs (without buffers, T
body
= 10 nm, T
ox
= 6 nm)
and InAs-OI MOSFETs (with buffers, T
body
= 3/3/3 nm,
T
ox
= 6 nm) is shown in Fig. 6(a) and (b). The lower
S.S. is obtained in the In
0.53
Ga
0.47
As channel, because of
the closer distance between the MOS interface and the
channel and resulting higher gate capacitance. On the other
hand, the InAs-OI MOSFETs show the lower DIBL than
that of the In
0.53
Ga
0.47
As-OI ones. This fact is attributable
to the extremely thin channel thickness of 3 nm which is
much smaller than that of In
0.53
Ga
0.47
As (T
body
= 10 nm).
I
on
I
off
characteristics of the In
0.53
Ga
0.47
As-OI MOSFETs
and the InAs-OI MOSFETs are shown in Fig. 7(a). Note here
that the devices for data points in I
on
I
off
characteristics are
the same as in Fig. 6. The signicant I
on
enhancement of
around 400% is observed for the InAs-OI MOSFETs at same
I
off
of 1 nA/m. The I
on
characteristics of both devices are
also shown in Fig. 7(b) as a function of DIBL. The InAs-
OI MOSFETs (with buffers) also shows higher I
on
at the
same DIBL. To examine the reason of the I
on
enhancement,
we have plotted the total resistance (R
tot
) between source
and drain as a function of L
ch
, which is shown in Fig. 8.
The lower slope and lower R
SD
are obtained in the InAs-OI
MOSFETs (with buffers). The lower slope and the lower R
SD
are attributable to the higher mobility of the InAs channel with
buffer and the lower SBH due to the lower CBM of InAs than
that of In
0.53
Ga
0.47
As, respectively [8]. The S.S. and DIBL
Fig. 6. (a) S.S. and (b) DIBL characteristics of In
0.53
Ga
0.47
As MOSFET
without buffers (blue symbol) and InAs MOSFET with buffers (red symbol).
T
ox
for both devices is 6 nm.
Fig. 7. (a) I
on
I
off
and (b) I
on
-DIBL characteristics of In
0.53
Ga
0.47
As MOS-
FET w/o buffers (blue symbol) and InAs MOSFET with buffers (red symbol).
400% I
on
enhancement is obtained. T
ox
for both devices is 6 nm.
Fig. 8. R
tot
L
ch
characteristics of In
0.53
Ga
0.47
As-OI MOSFETs without
buffers (blue symbol) and InAs-OI MOSFETs with buffers (red symbol). T
ox
for both devices is 6 nm.
benchmark comparing among the recent results of the IIIV
3-D FETs are shown in Fig. 9(a) and (b). The comparison of
the electrical properties in the present MOSFETs with those
of IIIV 3-D FETs is summarized in Table I. The present
In
x
Ga
1x
As-OI MOSFETs show the comparable or better
electrostatic characteristics against the 3-D trigate FET or gate-
all-around FETs [2], [5][8], even though quite thick EOT
and the planar structure are used. It is also found that I
on
of the present device is comparable with that of the trigate
MOSFETs in spite of the ETB planar structure. Further EOT
scaling and process optimization allows us to provide the better
SCEs control and the higher performance.
KIM et al.: SUB-60-nm EXTREMELY THIN BODY InxGa
1x
As-On-INSULATOR MOSFETs ON Si 2515
TABLE I
COMPARISON OF ELECTRICAL PROPERTIES OF THIS PAPER TO MOST
RECENT RESULTS OF IIIV FETS WITH 3-D STRUCTURES
Fig. 9. Benchmark of (a) S.S. and (b) DIBL characteristics between several
3-D FETs and this paper.
IV. SIMULATION
To investigate the scalability of InGaAs-OI MOSFETs, we
performed device simulation by using a TCAD simulator,
Sentaurus [23], which solves the Poissons equation and the
hydrodynamic transport equations in a self-consistent manner.
The device structure used in the simulation is basically the
same as the experimental one, shown in Fig. 1. An InAs chan-
nel with MOS interface buffer layers (3/3/3 nm) is assumed.
At rst, simulation results are tted to the experimental
I
D
V
G
characteristics by adjusting values of D
it
and R
SD
as
tting parameters. Estimated D
it
and R
SD
are 1 10
13
cm
2
and 900 m, respectively. Experimental and simulated
I
D
V
G
curves of InAs-OI MOSFETs with the buffer layer
(3/3/3 nm) are shown in Fig. 10. These results show the
excellent agreement with the experimental results, meaning
that the carrier transport model assumed in this simulation is
proper.
Experimental and simulated results in S.S. and DIBL char-
acteristics are shown in Fig. 11(a) and (b), respectively. The
good agreement is obtained for L
ch
down to around 50 nm. On
the other hand, sudden increase of S.S. and DIBL is observed
in the simulation results around L
ch
of 40 nm. As a result, the
simulation predicts that SCEs affects the electrical properties
of MOSFETs more signicantly and, thereby the off-current
characteristics of MOSFETs become worse in this L
ch
region.
Fig. 10. Experimental and simulated I
D
V
G
curves of InAs-OI MOSFET
with buffer layers.
Fig. 11. Experimental and simulated (a) S.S. and (b) DIBL charateristics of
InAs-OI MOSFET with buffer layers.
Fig. 12. Simulated DIBL characteristics of InAs-OI MOSFET with buffer
layers as a parameter of T
ox
of 6 nm (red symbol) and 2 nm (blue symbol).
To achieve better scalability in this device structure, further
vertical scaling is one of the promising methods. Therefore,
T
ox
scaling and BOX thickness (T
BOX
) scaling effects are
simulated. DIBL-L
ch
characteristics of InAs-OI MOSFETs as
a parameter of T
ox
are shown in Fig. 12. It is clearly seen
that T
ox
scaling gives the better SCEs control in deeply scaled
L
ch
regions. T
BOX
scaling effects on DIBL is also shown in
Fig. 13. It is found that T
BOX
scaling also lead to improvement
in SCEs control.
Moreover, a back biasing technique can be used in our
device structure to suppress SCEs, as in SOI MOSFETs [26].
I
D
V
G
characteristics of InAs-OI MOSFETs at L
ch
of 10 nm
as a parameter of the back bias voltage (V
BG
) are shown
in Fig. 14. Signicant I
off
decrease and reduction in DIBL
2516 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 8, AUGUST 2013
Fig. 13. Simulated DIBL characteristics of InAs-OI MOSFET with buffer
layer as a parameter of T
BOX
of 40, 20, 10, and 5 nm (red, blue, green, and
black, respectively).
Fig. 14. Simulated I
D
V
G
characteristics of InAs-OI MOSFETs at L
ch
of
10 nm as a parameter of the back bias voltage (V
BG
) of 3, 1.5, and 0 V.
are observed by applying V
BG
even at L
ch
of 10 nm. Note
here that the contact resistance in the present simulation is
represented by inserting a contact resistance value (R
C
) at
metalsemiconductor interfaces as a given parameter. In the
present simulation, R
C
is set to be 900 m as the tting
parameter. As a result, an effect of possible change of R
C
due to increase in carrier concentration caused by V
BG
is not
included in the present simulations.
These simulated results strongly suggest that further vertical
scaling and the back biasing technique lead to signicant
improvement of SCEs control in the present InAs-OI MOS-
FETs even under the similar channel thickness.
From the viewpoint of the scalability of IIIV-OI MOS-
FETs, the effect of T
body
on SCE is a critical issue. Thus,
the effects of the thickness of the MOS interface buffer layers
and the channel thickness is also examined using simulation.
I
D
V
G
characteristics of InAs-OI MOSFETs at L
ch
of 10 nm
as a parameter of the thickness of the MOS interface buffer
layers are shown in Fig. 15. It is found that barrier thickness
scaling can suppress the SCEs to some extent, as similar to
the T
ox
scaling. However, the off-current is still high and,
thus, the SCEs need to be improved more. One possible way
to improve the off-current characteristics is to further scale
T
channel
. The T
channel
dependence of the I
D
V
G
characteristics
is simulated. The results are shown in Fig. 16. The off-current
characteristics are signicantly improved by further scaling
Fig. 15. Simulated I
D
V
G
characteristics of InAs-OI MOSFETs at L
ch
of
10 nm as a parameter of the thickness of MOS interface buffer layers.
Fig. 16. Simulated I
D
V
G
characteristics of InAs-OI MOSFETs at L
ch
of
10 nm as a parameter of the T
channel
.
T
channel
, due to tight electron connement in the extremely thin
channel layer. The S.S. and DIBL values are estimated to be
128 mV/dec and 46 mV/V at T
body
of 1/1/1 nm, respectively,
even under extremely short L
ch
of 10 nm. However, it should
be noticed that T
channel
scaling can be limited by mobility
reduction due to channel thickness uctuation scattering [15],
suggesting the existence of the tradeoff in T
channel
. Therefore,
a quantitative examination on the mobility characteristics with
a decrease of T
channel
is required.
V. CONCLUSION
We demonstrated the operation of the deeply scaled
InAs-OI MOSFETs with the Ni-InGaAs metal S/D structures
and L
ch
of 55 nm. It was found that the indium content
increase and the MOS interface buffer engineering provided
the 400% I
on
enhancement at the same DIBL of 100 mV/V
against the In
0.53
Ga
0.47
As-OI MOSFETs without any buffer
layers because of the mobility increase and the R
SD
reduc-
tion. Also, InAs-OI MOSFET with the MOS interface buffer
showed excellent SCEs control. These results showed that
the ETB IIIV-OI structure with the MOS interface buffer
engineering is a promising way to realize the ultimately scaled
future IIIV MOSFETs. Moreover, 2-D TCAD simulation
KIM et al.: SUB-60-nm EXTREMELY THIN BODY InxGa
1x
As-On-INSULATOR MOSFETs ON Si 2517
predicted that further vertical scaling, such as EOT, EOT of
BOX and T
body
scaling, and the back biasing technique can
improve the SCEs control in InAs-OI MOSFETs.
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Authors biographies and photographs not available at the time of publication.