IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

7, JULY 2013 3395

Reduced-Order Model and Control Approach for the
Boost Converter With a Voltage Multiplier Cell
Fabrcio Hoff Dupont, Student Member, IEEE, Cassiano Rech, Member, IEEE, Roger Gules, Member, IEEE,
and Jos e Renes Pinheiro, Member, IEEE
AbstractThe boost converter with a voltage multiplier cell al-
lows the static gain extension by means of the switching capacitor
technique, reducing the duty cycle needed to achieve the same
voltage gain when compared to the conventional boost converter.
However, the modeling of this converter is complex and requires
the use of advanced techniques due to the resonant inductor. Thus,
this paper aims to present a reduced-order model of this converter
without the resonant energy exchange between the capacitors, so
that the state-space averaging technique can be applied assuming
small ripple in the state variables. In addition, this paper presents
the design of a control system for the boost converter with a volt-
age multiplier cell. The adopted strategy employs an inner loop
to control the input current and an outer loop for the output
voltage regulation. Extensive analysis based on simulations and
an experimental prototype demonstrate that the proposed model-
ing, although simplied, is sufcient for an adequate control sys-
tem design, ensuring good voltage regulation, and fast transient
responses.
Index TermsHigh step-up converters, reduced-order model,
voltage multiplier cell.
I. INTRODUCTION
G
ROWING needs for electrical power generation and
global environmental concerns have increased the search
for renewable power sources. However, most of these renewable
sources present low output voltage and require converters with
high static gain, usually greater than ten. Also, it is important
to harvest all available energy, which calls for high-efciency
converters. These two features have been focus of several re-
searches, and a huge number of topologies have been proposed
lately for this end.
In high step-up isolated dcdc converters [1][6], the static
gain can be easily changed by the turn ratio of the trans-
formers. However, losses associated with the leakage energy
must be taken into account and properly handled to improve
the efciency of the converter. On the other hand, noniso-
Manuscript received January 5, 2012; revised September 7, 2012; accepted
September 26, 2012. Date of current version December 24, 2012. This work was
supported in part by PROCAD (Academic Cooperation Program) from CAPES
(Brazilian Commission for Higher Education), and in part by Conselho Nacional
de Desenvolvimento Cientcoe Tecnol ogico. Recommended for publication by
Associate Editor F. L. Luo.
F. H. Dupont, C. Rech, and J. R. Pinheiro are with the Power Electronics and
Control Research Group, Federal University of Santa Maria, Santa Maria, RS
97105-900, Brazil (e-mail: fhdupont@gmail.com; rech.cassiano@gmail.com;
jrenespinheiro@gmail.com).
R. Gules is with the Federal University of Technology, Curitiba, PR 80230-
901, Brazil (e-mail: rgules@gmail.com).
Digital Object Identier 10.1109/TPEL.2012.2224672
v
i
S
L
i
L
r
D
1
D
2
D
o
C
1
C
2
C
o
R
L
r
Li
r
C1
r
C2
r
Co
x
Li
x
C1
x
C2
x
Co
Fig. 1. Boost converter with a voltage multiplier cell employed to increase the
output voltage gain.
lated topologies require more elaborated strategies such as
switched capacitor [7], [8], magnetic coupling [9][12] or hy-
brid strategies [13][16], among others [17]. In [18], one can
nd other promising topologies for dcdc converters applied to
photovoltaic-based systems.
Although a great effort has been devoted to dcdc converter
topologies fed by renewable sources, modeling these converters
has a long way to go and only a few works have been found
until now in this area. The dynamic model of a six-phase in-
terleaved double dual boost and a control design is presented
in [19]. For switched capacitor converters, the investigation of
the dynamic model of a boost converter based on the three-state
switching cell is shown in [20], and the small signal model of
an improved current-fed converter is presented in [21], both ap-
plying the circuit averaging technique [22]. Also, a full-order
and a reduced-order model for the dcdc multilevel boost con-
verter based on the state-space averaging technique are proposed
in [23]. One of the reasons for this reduced number of studies
is due to the fact that several topologies cited before have res-
onant stages or ripples that cannot be neglected in one or more
state variables, which is a basic requirement to the applica-
tion of a conventional technique as the state-space averaging
[22], [24].
Among these topologies, one that still does not have a dy-
namic model is the boost converter with a voltage multiplier
cell [8], which employs a switching capacitor circuit to obtain a
high static gain without the need of extreme duty cycles. The cir-
cuit of this converter is shown in Fig. 1, in which it is possible to
observe the presence of a resonant inductor L
r
. The inclusion of
this inductor allows the operation with zero-current-switching
throughout the turn on of the power switch. Furthermore, the
reverse recovery problem of all diodes is minimized. These fea-
tures allow the increase of the converter efciency as desired in
renewable energy applications.
0885-8993/$31.00 2012 IEEE
3396 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013
Inspecting the waveform of the resonant inductor, one can
notice that its average current is zero. This brings a serious
problem to the purpose of obtaining a dynamic model of the
converter with the use of the well-known state-space averaging
technique. For this reason, the main objective of this paper is
to propose a reduced-order model, without the inclusion of the
resonant inductor L
r
, which can be effectively employed in
the design of controllers for the boost converter with a voltage
multiplier cell.
II. OPERATION PRINCIPLE
To obtain the dynamic model of the boost converter with a
voltage multiplier cell, the following assumptions have been
adopted:
1) the resonant inductor L
r
is neglected to allow the attain-
ment of an average model;
2) capacitors C
1
and C
2
behave as constant voltage sources,
i.e., high capacitance values are adopted;
3) the model must be nonconservative, i.e., the parasitic re-
sistance of the capacitors and inductors are considered
(at least the series resistance of C
2
must be considered).
Without them, the capacitors C
1
and C
2
behave as a single
state in stage 2, making impossible to obtain the model;
4) capacitors C
1
and C
2
have the same capacitance
(C
1
= C
2
);
5) semiconductor losses are neglected;
6) D
1
and D
o
start conducting simultaneously.
For the conguration analyzed in this paper, three operation
stages are observed as shown by Fig. 2. The theoretical wave-
forms for the main variables are presented by Fig. 3.
A. Stage 1 (t
0
to t
1
)
In the beginning of this stage, the switch S is turned OFFcaus-
ing the energy stored in the inductor to be partially transferred
to C
1
and partially to C
2
and the output branch. The induc-
tor current decreases while charging the multiplier capacitors,
whose voltage across their terminals increase approximately lin-
ear. The period of this stage is complimentary to the duty cycle
D, i.e., (1 D)T
s
, being T
s
the switching period, the inverse
of switching frequency F
s
. From Fig. 2(a), one can obtain the
following rst-order differential equations:
x
L
i
=
_
r
C
1
R
L
(r
C
2
+r
C
o
) +r
C
1
r
C
2
r
C
o
L
i
+
r
L
i
L
i
_
x
L
i

r
C
1
R
L
L
i
x
C
o

r
C
2
(r
C
o
+R
L
) +r
C
o
R
L
L
i
x
C
1

r
C
1
(R
L
+r
C
o
)
L
i
x
C
2
+
1
L
i
v
i
(1)
x
C
o
=
r
C
1
R
L
C
o
x
L
i

r
C
1
+r
C
2
+R
L
C
o
x
C
o
+
R
L
C
o
x
C
1

R
L
C
o
x
C
2
(2)
(c)
(b)
(a)
v
i
v
i
v
i
S
S
S
L
i
L
i
L
i
D
1
D
1
D
1
D
2
D
2
D
2
D
o
D
o
D
o
C
1
C
1
C
1
C
2
C
2
C
2
C
o
C
o
C
o
R
L
R
L
R
L
r
Li
r
Li
r
Li
r
C1
r
C1
r
C1
r
C2
r
C2
r
C2
r
Co
r
Co
r
Co
Fig. 2. Operation stages of the converter throughout a switching period:
(a) stage 1, (b) stage 2, and (c) stage 3.
t
0
t
1
t
2
t
3
vivC
1
Li
vi
Li
i
pk
i
L
(
A
)
v
C
1
,

v
C
2
(
V
)
i
C
1
,
i
C
2
(
A
)
v
o
(
V
)
v
C1
v
C2
i
C1
i
C2
(1 D)T
S
DT
s
Fig. 3. Theoretical waveforms of the main variables for the analyzed converter.
DUPONT et al.: REDUCED-ORDER MODEL AND CONTROL APPROACH FOR THE BOOST CONVERTER WITH A VOLTAGE MULTIPLIER CELL 3397
x
C
1
=
r
C
2
(r
C
o
+R
L
) +r
C
o
R
L
C
1
x
L
i
+
R
L
C
1
x
C
o

R
L
+r
C
o
C
1
x
C
1
+
r
C
o
+R
L
C
1
x
C
2
(3)
x
C
2
=
r
C
1
(r
C
o
+R
L
)
C
2
x
L
i

R
L
C
2
x
C
o
+
r
C
o
+R
L
C
2
x
C
1

R
L
+r
C
o
C
2
x
C
2
(4)
where
= r
C
o
(r
C
1
+r
C
2
) +R
L
(r
C
1
+r
C
2
+r
C
o
) (5)
x
L
i
is the inductor current, and x
C
1
, x
C
2
, and x
C
o
are the
voltages across capacitors C
1
, C
2
, and C
o
, respectively.
The output variables to be analyzed here are the input current
i
i
and the output voltage v
o
. Once the input current is the same
as the inductor current, one can directly use the state x
L
i
i
i
= x
L
i
. (6)
The output voltage is obtained by
v
o
= R
L
(C
o
x
C
o
+C
2
x
C
2
) (7)
and substituting (2) and (4) in (7), one has
v
o
=
r
C
1
r
C
o
R
L

x
L
i
+
(r
C
1
+r
C
2
)R
L

x
C
o
+
r
C
o
R
L

x
C
1

r
C
o
R
L

x
C
2
. (8)
Collecting (1)(4) in matrices A
1
and B
1
, and (6) and (8) in
matrix C
1
, one obtains the state equations
_
x(t) = A
1
x(t) +B
1
v
i
y(t) = C
1
x(t)
(9)
where x = [x
L
i
x
C
o
x
C
1
x
C
2
]
T
and y = [i
i
v
o
]
T
. Matrix A
1
is given in (29) at the bottom of next page, B
1
and C
1
are given
by
B
1
=
_
1
L
i
0 0 0
_
T
(10)
C
1
=
_
_
1 0 0 0
r
C
1
r
C
o
R
L

(r
C
1
+r
C
2
)R
L

r
C
o
R
L

r
C
o
R
L

_
_
.
(11)
B. Stage 2 (t
1
to t
2
)
At instant t
1
, the switch S is turned ON, diodes D
1
and D
o
are
turned OFF, and D
2
starts conducting allowing the energy to be
transferred from C
1
to C
2
. The voltages across these capacitors
tend to equalize, and the discharge current is only limited by the
internal resistance of the components implying in a peak current
through the diode D
2
. The period of this stage is determined by
the time required to equalize the voltages across the multiplier
capacitors and the turning off of diode D
2
.
From Fig. 2(b), the following differential equations can be
obtained:
x
L
i
=
r
L
i
L
i
x
L
i
+
1
L
i
v
i
(12)
x
C
o
=
1
C
o
(r
C
o
+R
L
)
x
C
o
(13)
x
C
1
=
x
C
1
+x
C
2
C
1
(r
C
1
+r
C
2
)
(14)
x
C
2
= x
C
1
. (15)
The output voltage is obtained by
v
o
=
R
L
R
L
+r
C
o
x
C
o
. (16)
As done in stage 1, (12)(15) are collected into matrices A
2
and B
2
. The input current (6) and the output voltage (16) into
C
2
result in the state-space description for the stage 2
_
x(t) = A
2
x(t) +B
2
v
i
y(t) = C
2
x(t).
(17)
Matrix A
2
is given in (30) at the bottom of the next page, B
2
and C
2
are given by
B
2
=
_
1
L
i
0 0 0
_
T
(18)
C
2
=
_
_
1 0 0 0
0
R
L
r
C
o
+R
L
0 0
_
_
(19)
C. Stage 3 (t
2
to t
3
)
At instant t
2
, the voltages across the terminals of the capaci-
tors C
1
and C
2
become equal, the diode D
2
is turned OFF, and
the third stage begins. The inductor current continues to rise
linearly, while the capacitor C
o
discharges providing energy to
the load. One can verify that the equations for x
L
i
and x
C
o
are
exactly the same obtained for stage 2. Moreover, once D
2
turns
OFF after the voltages in C
1
and C
2
become equal, the state
equations do not undergo further changes and their derivatives
are zero. Consequently, stages 2 and 3 can be unied in a single
stage with period DT
s
governed by the same state-space model
dened in (17).
III. STATE-SPACE AVERAGED MODEL
Fromthe dynamic equations obtained in the previous section,
the state-space averaged model of the boost converter with a
voltage multiplier cell is investigated hereinafter. First, consider
a given variable x(t). Its average value through a switching
period is represented by x(t) and is dened by
x(t) =
1
T
s
_
t
tT
s
x() d. (20)
This moving average produces the same effect of a low-pass
lter, removing the high-frequency components associated with
the switching action and preserving the slower dynamics related
3398 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013
to the natural operation of the converter [22]. Applying the
averaging concept to the state-space models given in (9) and
(17), one can determine the state-space average model of the
converter as
_

x(t) = [A
1
d

(t) +A
2
d(t)] x(t) + [B
1
d

(t) +B
2
d(t)] v
i
(t)
y(t) = [C
1
d

(t) +C
2
d(t)] x(t)
(21)
where d

(t) = 1 d(t).
A. Steady-State Operation Point
When nominal inputs d(t) = D and v
i
(t) = V
i
are applied to
the converter, it operates in steady state, so that all the derivatives
of

x are zero. Thus, the operation point of the converter can be
obtained by solving (21) for

x = 0. Assuming that the matrix
Ais invertible, the equilibrium state vectors are given by
_
X = A
1
BV
i
Y = CA
1
BV
i
(22)
where
A = A
1
D

+A
2
D (23)
B = B
1
D

+B
2
D (24)
C = C
1
D

+C
2
D. (25)
B. Introduction of Perturbations
The next step in the modeling of the converter is the intro-
duction of small ac signals in the average value of the variables,
aiming to analyze the behavior of the converter subjected to
these perturbations. Thus, the average variables become
x(t) = X+ x(t)
y(t) = Y+ y(t)
v
i
(t) = V
i
+ v
i
(t)

d(t) = D +

d(t)

d

(t) = D

d(t). (26)
To clarify the notation, the time dependence of the variables
(t) is omitted hereinafter. Substituting (26) in (21), the nonlinear
model for the converter operating in the continuous conduction
mode is given by
_

_
d x
dt
..
Linear AC
term
= AX+BV
i
. .
Equilibrium
DC term
+A x +B v
i
. .
Linear
AC terms
+[(A
1
+A
2
)X+ (B
1
+B
2
)V
i
]

d
. .
Linear AC terms
+(A
1
+A
2
) x

d + (B
1
+B
2
) v
i

d
. .
Nonlinear AC terms
Y
..
Equilibrium
DC term
+ y
..
Linear
AC term
= CX
..
Equilibrium
DC term
+C x+(C
1
+C
2
)X

d
. .
Linear DC terms
+ (C
1
+C
2
) x

d
. .
Nonlinear AC terms
.
(27)
C. Small Signal Linearized Model
The dynamic model given in (27) is nonlinear and cannot
be directly employed to design a control system with the most
commonly used techniques, which require a linear model. How-
ever, if the magnitudes of the perturbations are much smaller
than their steady-state values, the nonlinear terms can be ignored
without resulting in a signicant error, and a linear approxima-
tion of the system is obtained. Moreover, analyzing (27) and
focusing only on the ac behavior, the dc terms are neglected,
since they are already represented by the steady-state model.
Thus, a small signal reduced-order linear model for the boost
converter with a voltage multiplier cell can be dened as
_

x = A x +M u
y = C x +N u
(28)
A
1
=
_

_
r
C
1
R
L
(r
C
2
+ r
C
o
) + r
C
1
r
C
2
r
C
o
L
i
+
r
L
i
L
i
_

r
C
1
R
L
L
i

r
C
2
(r
C
o
+ R
L
) + r
C
o
R
L
L
i

r
C
1
(R
L
+ r
C
o
)
L
i
r
C
1
R
L
C
o

r
C
1
+ r
C
2
+ R
L
C
o
R
L
C
o

R
L
C
o
r
C
2
(r
C
o
+ R
L
) + r
C
o
R
L
C
1
R
L
C
1

R
L
+ r
C
o
C
1
R
L
+ r
C
o
C
1
r
C
1
r
C
o
+ r
C
1
R
L
C
2

R
L
C
2
R
L
+ r
C
o
C
2

R
L
+ r
C
o
C
2
_

_
(29)
A
2
=
_

r
L
i
L
i
0 0 0
0
1
C
o
(r
C
o
+ R
L
)
0 0
0 0
1
C
1
(r
C
1
+ r
C
2
)
1
C
1
(r
C
1
+ r
C
2
)
0 0
1
C
1
(r
C
1
+ r
C
2
)

1
C
1
(r
C
1
+ r
C
2
)
_

_
(30)
DUPONT et al.: REDUCED-ORDER MODEL AND CONTROL APPROACH FOR THE BOOST CONVERTER WITH A VOLTAGE MULTIPLIER CELL 3399
TABLE I
MAIN PARAMETERS OF THE CONVERTER EMPLOYED TO VALIDATE THE
SMALL-SIGNAL LINEARIZED MODEL
Parameter Value Parameter Value
V
i
12 V C
1
1000 F
Po 100 W r
C
1
0.5 m
Fs 50 kHz C
2
1000 F
D 0.76 r
C
2
0.5 m
L
i
40 H Co 1000 F
r
L
i
50 m r
Co
10 m
where u = [ v
i

d ]
T
is the vector with the input disturbances,
and
M= [ B ((A
1
+A
2
) X+ (B
1
+B
2
) V
i
) ]
N = [ 0 (C
1
+C
2
) X]. (31)
D. Transfer Functions
The transfer functions of the converter can be easily obtained
applying the Laplace transform in (28) assuming zero initial
conditions, so that
y(s) =
_
C(sI A)
1
M+N
_
u(s) (32)
where
y(s) = [
i
(s) v
o
(s)]
T
u(s) = [ v
i
(s)

d(s)]
T
. (33)
By solving (32), one has
_

i
(s)
v
o
(s)
_
=
_
G
11
(s) G
12
(s)
G
21
(s) G
22
(s)
__
v
i
(s)

d(s)
_
(34)
and once this model is linear, the superposition theorem can be
applied to obtain all the transfer functions of the converter, given
by
G
11
(s) = G

i
, v
i
(s) =

i
(s)
v
i
(s)

d=0
(35)
G
12
(s) = G

i
,

d
(s) =

i
(s)

d(s)

v
i
=0
(36)
G
21
(s) = G
v
o
, v
i
(s) =
v
o
(s)
v
i
(s)

d=0
(37)
G
22
(s) = G
v
o
,

d
(s) =
v
o
(s)

d(s)

v
i
=0
. (38)
IV. MODEL VALIDATION
The reduced-order model obtained in the previous section is
rst validated by simulating a converter whose main parameters
are given in Table I.
Fig. 4 shows the dynamic behavior of the output voltage
and input current waveforms under duty cycle disturbances. At
150 ms, a 1% step is applied in the duty cycle, and the input
voltage rises from its equilibrium value of 96.699.5 V with a
settling time of 19.86 ms. At 220 ms, the duty cycle returns to
0.16 0.18 0.20 0.22 0.24 0.26 0.28
0
5
10
15
Time (s)
I
n
p
u
t

c
u
r
r
e
n
t

(
A
)
O
u
t
p
u
t

v
o
l
t
a
g
e

(
V
)
96
97
98
99
100
(a)
(b)
Model
Simulation
Fig. 4. Comparison of the transient responses for a 1% disturbance in the duty
cycle: (a) output voltage and (b) input current.
its nominal value, reducing the output voltage to its equilibrium
value with approximately the same settling time. The results
showgood correspondence between the proposed model and the
electrical circuit simulation of the converter. Although effects
cannot be noticed in the results presented in Fig. 4 due to the
parameters used in the simulation, it is important to highlight that
this converter also has a right-half-plane zero as the conventional
boost converter.
A. Analysis Over a Practical Implementation of the Converter
In practical applications, the use of capacitors with values
as high as those previously presented for the voltage multiplier
cell is unusual. According to [8], it is possible to use smaller ca-
pacitance values to reduce both cost and volume. However, this
leads to an increase in the voltage ripple in C
1
and C
2
violating
the small ripple assumption and reducing the average voltage
in this intermediate stage. As a consequence, the output voltage
suffers from a slight reduction with respect to the theoretical
steady-state value.
Another consideration in the practical implementation of the
converter is related to the reverse recovery problems of diodes
D
1
and D
o
. To alleviate this problem, a resonant inductor L
r
is
included in series with capacitor C
2
as shown in Fig. 1 improving
the overall efciency of the converter [8]. This inductor also
reduces the peak current in D
2
which may be only limited by
the internal resistances of the devices.
From the point of view of the converter operation, the inclu-
sion of L
r
results in new operation stages, which have been
dened in [8]. However, the average current in this induc-
tor is zero and the conventional modeling technique by the
state-space averaging cannot be used. Therefore, more com-
plex and generalized approaches are needed to fully model this
inductor dynamic behavior.
To evaluate the dynamic behavior of the proposed reduced-
order model with practical values, a prototype with parameters
given in Table II was built. Fig. 5 shows the results for the
3400 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013
TABLE II
PARAMETERS OF THE CONVERTER EMPLOYED IN THE EXPERIMENTAL
PROTOTYPE AND PRACTICAL VALIDATION OF THE SMALL-SIGNAL MODEL
Parameter Value Parameter Value
V
i
12 V C
1
3.3 F
Po 100 W r
C
1
15 m
Fs 50 kHz C
2
3.3 F
D 0.76 r
C
2
15 m
L
i
40 H Co 410 F
r
L
i
100 m r
Co
190 m
Lr 2 H S IRFP250
r
Lr
10 m D
1
, D
2
, Do MUR1560
0.16 0.18 0.20 0.22 0.24 0.26 0.28
90
91
92
93
94
95
96
O
u
t
p
u
t

v
o
l
t
a
g
e

(
V
)
Time (s)
Model
Simulation
Fig. 5. Model and simulation responses for a 1% disturbance in the duty cycle
and employing small value capacitors in the voltage multiplier cell and with the
resonant inductor.
180
135
90
45
0
Frequency (Hz)
P
h
a
s
e

(
d
e
g
r
e
e
s
)
M
a
g
n
i
t
u
d
e

(
d
B
)
1 10 100 1k 10k
20
10
0
10
20
30
40
50
Model
Simulation
Experimental
Fig. 6. Comparison of frequency responses between the proposed model, the
circuit simulation with L
r
, and the experimental prototype.
proposed reduced-order model and circuit simulation results
obtained with a 1% disturbance in the duty cycle. As it can be
observed, the inclusion of the resonant inductor does not result in
signicant variations in the dynamic response of the converter,
but due to the increase in the voltage ripple over the multiplier
capacitors, the output voltage of the converter is smaller than
the predicted by the model. However, in practice, the converter
operates in a closed loop with integral action controllers to en-
sure asymptotic tracking of reference signals; thus this behavior
does not represent a major problem.
Fig. 6 concludes the comparison presenting the Bode dia-
grams for the proposed model, the simulated circuit, and the
experimental prototype. PSim was used to obtain the simu-
lated Bode diagram, and an analog network analyzer Model
200 of AP Instruments was employed. From these results, one
can verify that the inclusion of the resonant inductor has small
inuence over the frequency response of the converter. Even ob-
serving some discrepancies between the proposed modeling and
the practical implementation of the converter, the proposed dy-
namic reduced-order model is enough to design control systems
for the converter.
Besides the analysis for the nominal parameters given in
Table II, a brief investigation on the impact of parametric varia-
tions is carried out by means of comparisons between frequency
responses of the proposed reduced-order model and simulation
results, whose results are shown in Fig. 7. For all these cases,
switching frequency F
s
, input V
i
and output voltage V
o
are kept
constant, while input inductor L
i
, output C
o
and multiplier ca-
pacitors (C
1
and C
2
), as well the resonant inductor L
r
have
their values varied as highlighted in Fig. 7. It is worth to notice
in Fig. 7(f) that variations in the resonant inductor have impact
only in simulation results, since it is neglected in the proposed
model. However, even using the maximum value of the reso-
nant inductor that results in a resonance period equal to stage 3
(approximately 10 H), the proposed reduced-order model has
an adequate correlation with simulation results employing L
r
.
V. CONTROL STRATEGY
From the small-signal model previously presented, the next
sections investigate a control approach for the boost converter
with a voltage multiplier cell. For this task, the prototype, whose
specications are given in Table II, is used.
The open-loop poles and zeros for the transfer functions of
control to input current and control to output voltage are de-
picted in Fig. 8, where a right-half-plane (RHP) zero in the
G
v
o
,

d
(s) transfer function can be veried. Consequently, a stan-
dard voltage-mode control results in a narrowclosed-loop band-
width [22], [25], so that it does not act over the effects of the
RHP zero. If the control is done by means of the input cur-
rent (current-mode control), poles and zeros are all placed in the
left-half-plane, what allows to obtain signicantly improved dy-
namic responses when compared to the voltage-mode control.
However, the control of the output voltage is still a question to
be solved, and for this reason, a second loop is included with
this goal.
The strategy chosen to control the boost converter with a
voltage multiplier cell is presented in Fig. 9. Blocks H
i
(s)
and H
v
(s) correspond to the sensing and signal conditioning
circuits. Blocks C
i
(s) and C
v
(s) represent the input current
and output voltage controllers, respectively. For a design ex-
ample, it is considered that H
i
(s) = 0.5 and H
v
(s) = 0.1. Fi-
nally, the pulsewidth modulation (PWM) block represents the
PWM dynamic model, which can be given by Erickson and
Maksimovic [22]
G
PWM
(s) =
1
V
M
(39)
DUPONT et al.: REDUCED-ORDER MODEL AND CONTROL APPROACH FOR THE BOOST CONVERTER WITH A VOLTAGE MULTIPLIER CELL 3401
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
15
0
15
30
45
(f)
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
15
0
15
30
45
(e)
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
15
0
15
30
45
M
a
g
n
i
t
u
d
e

(
d
B
)
(d)
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
15
0
15
30
45
(c)
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
15
0
15
30
45
(b)
1 10 100 1k 10k
225
180
135
90
45
0
P
h
a
s
e

(
d
e
g
r
e
e
s
)
Frequency (Hz)
M
a
g
n
i
t
u
d
e

(
d
B
)
15
0
15
30
45
(a)
Model Simulation
L
i
= 400 H C
o
= 150 F L
i
= 400 H and C
o
= 150 F
C
1
= C
2
= 0.5 F L
i
= 400 H and C
1
= C
2
= 0.5 F L
r
= 10 H
Fig. 7. Comparison of frequency response under parametric variations (parameters shown in Table II are used unless for the highlighted parameters):
(a) Case 1: L
i
= 400 H; (b) Case 2: C
o
= 150 F; (c) Case 3: L
i
= 400 H; and C
o
= 150 F; (d) Case 4: C
1
= C
2
= 0.5 F; (e) Case 5: L
i
= 400 H;
and C
1
= C
2
= 0.5 F; (f) Case 6: L
r
= 10 H.
0.6 0.4 0.2 0 1614
0
0.4 0.2 0 16 12
0
Real Axis
I
m
a
g
i
n
a
r
y

A
x
i
s
10
6
(a)
Real Axis
I
m
a
g
i
n
a
r
y

A
x
i
s
10
6
(b)
Fig. 8. Open-loop poles and zeros: (a) G

i
,

d
(s); (b) G
vo ,

d
(s).
where V
M
is the peak-to-peak amplitude of the triangular carrier
of the PWM. Hereinafter, it is considered that V
M
= 3V .
The aims of the control system are to regulate the output
voltage so that it asymptotically follows the reference signal
v
ref
and to guarantee that input (input voltage variations) and
output disturbances (load variations) be adequately rejected.
These objectives are achieved by adjusting both the input current
i
L
, controlled to supply the power demanded by the load, and
the output voltage (v
o
) controlled to track the reference signal.
Both designs are detailed later.
H
i
(s) H
v
(s)
C
i
(s)
C
v
(s)
v
ref
PWM
v
i
S
L
i
D
1
D
2
D
o
C
1
C
2
C
o
R
L
r
Li
r
C1
r
C2
r
Co
Fig. 9. Block diagram of the strategy employed to control the boost converter
with a voltage multiplier cell.
A. Input Current Controller Design
A large number of methodologies are available in the liter-
ature to design these controllers. Here, the classic frequency
domain control has been chosen once this approach is simple
due to the design and the implementation as well as due to
3402 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013
360
315
270
225
180
135
90
45
0
Frequency (Hz)
P
h
a
s
e

(
d
e
g
r
e
e
s
)
M
a
g
n
i
t
u
d
e

(
d
B
)
1 10 100 1k 10k 100k 1M 10M
80
60
40
20
0
20
40
60
Open-loop
Closed-loop
Plant poles and zeros
Controller poles and zeros
Fig. 10. Bode diagram depicting the design of the input current controller.
the possibility to use only sensors for the input current and the
output voltage. To design this controller, criteria such as phase
and gain margins are frequently specied to ensure the stability
of control systems, and together with Bode diagrams, provide
information about how the system parameters can vary and still
achieve a stable closed-loop behavior. Based on the transfer
function G

i
,

d
(s), on the PWM gain, and on the signal condi-
tioning circuit, the input current controller can be designed. It is
worth to note that the transfer function G

i
,

d
(s) only describes
the behavior of the main low-frequency dynamics of the input
current. However, the waveform of this current usually features
high-frequency ripples from PWM that cannot be neglected.
Hence, the effects of switching harmonics are considered in the
feedback loop by using the following transfer function:
H
e
(s) =
s
2
(F
s
)
2

s
2F
s
+ 1 (40)
which is valid up to half of the switching frequency [26], [27]
and is connected in series with the signal conditioning circuit
H
i
(s).
A phase margin of 50

and a crossover frequency up to a

decade below the switching frequency (up to 5 kHz) has been
dened as design criteria for the input current controller. These
criteria were chosen to allow adequate stability margins when
the system is subject to parametric variations and unmodeled
dynamics as the case of the resonant inductor neglected by
the reduced-order model previously presented. To achieve these
criteria, a PI controller with low-pass lter was employed. The
design of this controller is depicted in Fig. 10, where the open-
and closed-loop frequency responses are shown. One of the
poles of the controller is positioned at the origin to allow the
asymptotic tracking for constant references, while the second
pole is positioned below the switching frequency to attenuate
the switching ripples in the feedback loop. Then, the zero and
the gain of the controller are adjusted to allow the desired phase
margin in the crossover frequency. For the parameters used in
this paper, the transfer function of the input current controller is
360
315
270
225
180
135
90
45
0
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
P
h
a
s
e

(
d
e
g
r
e
e
s
)
M
a
g
n
i
t
u
d
e

(
d
B
)
120
100
80
60
40
20
0
20
40
60
80
Open-loop
Closed-loop
Plant poles and zeros
Controller poles and zeros
Fig. 11. Bode diagram depicting the design of the output voltage controller.
given by
C
i
(s) = 10.69 10
3
(s + 5307)
s(s + 74.81 10
3
)
(41)
which provides a phase margin of 49.6

, a gain margin of
10.8 dB, and a crossover frequency of 4.27 kHz.
B. Output Voltage Controller Design
In the approach presented in Fig. 9, the closed-loop system
can be seen as a voltage-controlled current source, once the outer
voltage loop provides a reference to the inner input current loop,
which in turn feeds an impedance formed by the output lter
of the converter. The closed-loop transfer function of the inner
current loop is obtained by
G
i,CL
(s) =
C
i
(s) G
PWM
(s) G

i
,

d
(s)
1 +C
i
(s) G
PWM
(s) G

i
,

d
(s) H
i
(s) H
e
(s)
.
(42)
The transfer function of the output voltage as a function of
the input current is obtained by
G
v
o
,
i
(s) =
G
v
o
,

d
(s)
G

i
,

d
(s)
. (43)
These two transfer functions are employed in the design of the
output voltage controller such that the full plant to be controlled
is given by
G
v
(s) = G
i,CL
(s) G
v
o
,
i
(s). (44)
The control objectives of this controller are the output voltage
regulation when the converter is subject to disturbances such as
load and input voltage variations. To achieve these objectives, a
PI controller with a low-pass lter is also used. For the design
criteria of this controller, a phase margin of 50

and a crossover
frequency up to a quarter of the inner current controller were
dened. The design of the voltage controller is presented by
Fig. 11, where the open and closed loops are shown together
with poles and zeros of the controller C
v
(s) and the plant G
v
(s).
DUPONT et al.: REDUCED-ORDER MODEL AND CONTROL APPROACH FOR THE BOOST CONVERTER WITH A VOLTAGE MULTIPLIER CELL 3403
R
i
R
z
C
z
C
p
e(s)
u(s)
Fig. 12. Basic circuit used to implement each PI controller with a low-pass
lter.
i
i
v
o
Fig. 13. Experimental results for a load step from 50% to 100% in the output
power.
The obtained transfer function for the output voltage controller
is given by
C
v
(s) = 164.45 10
3
(s + 147.8)
s(s + 4333)
(45)
which provides a phase margin of 49

, a gain margin of 16.1 dB,

and a crossover frequency of 742 Hz.
VI. EXPERIMENTAL RESULTS
The performance of the designed control strategy is vali-
dated through an experimental prototype with parameters given
in Table II. The controllers are implemented with operational
ampliers, where the basic circuit is shown in Fig. 12 and its
transfer function is given by
C
x
(s) =
u(s)
e(s)
=
K
c
(1 +s/
z
)
s (1 +s/
p
)
(46)
where the dc gain K
c
, the high-frequency pole
p
, and the zero

z
are given by
K
c
=
1
R
i
(C
p
+C
z
)

z
=
1
R
z
C
z

p
=
C
z
+C
p
R
z
C
z
C
p
. (47)
Fig. 13 presents the experimental results for a load step from
50% to 100% of the output power. During this transient, an
undershoot of 1.1%is observed in the output voltage with a good
regulation as required. In Fig. 14, the output load is reduced from
i
i
v
o
Fig. 14. Experimental results for a load step from 100% to 50% in the output
power.
100% to 50% and an overshoot of 1.3% is observed. Notice that
in Fig. 13 the output voltage has an offset of 100 V to improve
visualization.
These results demonstrate that the reduced-order model ob-
tained in the initial sections is adequate to design the control
system for the converter, combining a well-known modeling
technique with a good representation of the main dynamics of
the converter.
VII. CONCLUSION
This paper presented a reduced-order model for the boost
converter with a voltage multiplier cell. This simplication was
adopted due to the characteristic of zero average current in the
resonant inductor, which avoids one to obtain a dynamic model
through the well-known technique of the state-space averaging.
The validity of the model has been veried through simulation
and experimental results and one can observe the good corre-
spondence of the mathematical model when the small ripple
assumption is satised. However, this assumption is not always
observed in practice in the voltage across the multiplier capaci-
tors, so that some dynamical behaviors are not precisely modeled
due to the limitations of the state-averaging technique. Never-
theless, by means of Bode diagrams it has been demonstrated
that the real frequency response of the converter is damped, and
thus the proposed model is sufcient to be employed in a control
system design.
The closed-loop operation was investigated by means of a
control strategy based on two loops with PI controllers with
low-pass lters. This approach adequately achieves its objec-
tives, ensuring good transient response when the converter is
subject to load and input voltage disturbances. Experimental re-
sults corroborate the presented analysis and demonstrate that the
proposed reduced-order model is sufcient to design controllers
capable of providing fast transient responses with good voltage
regulation and disturbance rejection.
3404 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013
REFERENCES
[1] S. V. G. Oliveira and I. Barbi, Athree-phase step-up dc-dc converter with
a three-phase high-frequency transformer for dc renewable power source
applications, IEEE Trans. Ind. Electron., vol. 58, no. 8, pp. 35673580,
Aug. 2011.
[2] C. Liu, A. Johnson, and J.-S. Lai, A novel three-phase high-power soft-
switched DC/DC converter for low-voltage fuel cell applications, IEEE
Trans. Ind. Appl., vol. 41, no. 6, pp. 16911697, Nov./Dec. 2005.
[3] J.-M. Kwon and B.-H. Kwon, High step-up active-clamp converter with
input-current doubler and output-voltage doubler for fuel cell power sys-
tems, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 108115, Jan.
2009.
[4] Y. Zhao, W. Li, Y. Deng, and X. He, Analysis, design, and experimen-
tation of an isolated ZVT boost converter with coupled inductors, IEEE
Trans. Power Electron., vol. 26, no. 2, pp. 541550, Feb. 2011.
[5] C. Yoon, J. Kim, and S. Choi, Multiphase dc-dc converters using a boost-
half-bridge cell for high-voltage and high-power applications, IEEE
Trans. Power Electron., vol. 26, no. 2, pp. 381388, Feb. 2011.
[6] H.-L. Do, A zero-voltage-switching dc-dc converter with high voltage
gain, IEEE Trans. Power Electron., vol. 26, no. 5, pp. 15781586, May
2011.
[7] A. A. Fardoun and E. H. Ismail, Ultra step-up DC-DC converter with
reduced switch stress, IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025
2034, Sep./Oct. 2010.
[8] M. Prudente, L. L. Ptscher, G. Emmendoerfer, E. F. Romaneli, and
R. Gules, Voltage multiplier cells applied to non-isolated DC-DC con-
verters, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871887, Mar.
2008.
[9] W. Li, J. Wu, R. Xie, and X. He, A non-isolated interleaved ZVT boost
converter with high step-up conversion derived from its isolated counter-
part, in Proc. Eur. Conf. Power Electron. Appl., 2007, pp. 18.
[10] S. Malo R. Gri n o, Output voltage regulation of a high-efciency high
step-up dc-dc power converter, in Proc. IEEE Int. Symp. Ind. Electron.,
Jun. 2007, pp. 854859.
[11] S. Dwari and L. Parsa, An efcient high-step-up interleaved dc-dc con-
verter with a common active clamp, IEEETrans. Power Electron., vol. 26,
no. 1, pp. 6678, Jan. 2011.
[12] S.-M. Chen, T.-J. Liang, L.-S. Yang, and J.-F. Chen, A cascaded high
step-up dc-dc converter with single switch for microsource applications,
IEEE Trans. Power Electron., vol. 26, no. 4, pp. 11461153, Apr. 2011.
[13] W. Li, Y. Zhao, Y. Deng, and X. He, Interleaved converter with voltage
multiplier cell for high step-up and high-efciency conversion, IEEE
Trans. Power Electron., vol. 25, no. 9, pp. 23972408, Sep. 2010.
[14] Y.-P. Hsieh, J.-F. Chen, T.-J. Liang, and L.-S. Yang, A novel high step-up
dc-dc converter for a microgrid system, IEEE Trans. Power Electron.,
vol. 26, no. 4, pp. 11271136, Apr. 2011.
[15] G. Spiazzi, P. Mattavelli, and A. Costabeber, High step-up ratio yback
converter with active clamp and voltage multiplier, IEEE Trans. Power
Electron., vol. 26, no. 11, pp. 32053214, Nov. 2011.
[16] K.-B. Park, G.-W. Moon, and M.-J. Youn, Nonisolated high step-up
stacked converter based on boost-integrated isolated converter, IEEE
Trans. Power Electron., vol. 26, no. 2, pp. 577587, Feb. 2011.
[17] S. Park, Y. Park, S. Choi, W. Choi, and K.-B. Lee, Soft-switched inter-
leaved boost converters for high step-up and high-power applications,
IEEE Trans. Power Electron., vol. 26, no. 10, pp. 29062914, Oct. 2011.
[18] W. Li and X. He, Review of non-isolated high step-up DC/DC converters
in photovoltaic grid-connected applications, IEEE Trans. Ind. Electron.,
vol. 58, no. 4, pp. 12391250, Apr. 2010.
[19] F. S. Garcia, J. A. Pomilio, and G. Spiazzi, Modeling and control de-
sign of the six-phase interleaved double dual boost converter, in Proc.
IEEE/IAS 9th Int. Conf. Ind. Appl., Nov. 2010, pp. 16.
[20] Y. J. A. Alcazar, W. G. C. Cabero, R. P. Bascop e, S. Daher, D. S. Oliveira
Jr., and G. J. M. de Sousa, Modeling and control of the high voltage gain
boost converter based on three-state switching cell and voltage multipliers
(mc), in Proc. Brazil. Power Electron. Conf., Sep./Oct., pp. 655664.
[21] Y.-H. Liao, C.-M. Lai, and Y.-L. Ke, Modeling and design of an improved
current-fed converter with new voltage multiplier circuit combination, in
Proc. IEEE Ind. Appl. Soc. Annu. Meet., Oct. 2011, pp. 18.
[22] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,
2nd ed. Norwell, MA: Kluwer, 2001.
[23] J. C. Mayo-Maldonado, R. Salas-Cabrera, J. C. Rosas-Caro, J. De Leon-
Morales, and E. N. Salas-Cabrera, Modelling and control of a DC-DC
multilevel boost converter, IET Power Electron., vol. 4, no. 6, pp. 693
700, 2011.
[24] J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power
Electronics. Reading, MA: Addison-Wesley, 1991.
[25] D. M. Mitchell, Tricks of the trade: Understanding the right-half-plane
zero in small-signal DC-DC converter models, IEEE Power Electron.
Soc. Newslett., pp. 56, Jan. 2001.
[26] F. A. Huliehel, F. C. Lee, and B. H. Cho, Small-signal modeling of the
single-phase boost high power factor converter with constant frequency
control, in Proc. IEEE 23rd Annu. Power Electron. Spec. Conf., Jun./Jul.
1992, vol. 1, pp. 475482.
[27] W. Tang, F. C. Lee, and R. B. Ridley, Small-signal modeling of average
current-mode control, IEEETrans. Power Electron., vol. 8, no. 2, pp. 112
119, Apr. 1993.
Fabrcio Hoff Dupont (S10) was born in Cerro
Largo, Brazil, in 1984. He received the B.S. degree in
telecommunications engineering from the Regional
University of Blumenau (FURB), Blumenau, Brazil,
in 2007, and the M.S. degree in electrical engineer-
ing from FURB, in 2010. Currently, he is working
toward the Ph.D. degree in electrical engineering in
the Federal University of Santa Maria, Santa Maria,
Brazil, with the Power Electronics and Control Re-
search Group.
His research interests include modeling and con-
trol techniques of static converters, fuel cells, photovoltaic cells, fuzzy logic,
and genetic algorithms.
Cassiano Rech (S01M06) was born in Carazinho,
Rio Grande do Sul, Brazil, in 1977. He received
the B.S., M.S., and Ph.D. degrees in electrical en-
gineering from the Federal University of Santa Maria
(UFSM), Santa Maria, Brazil, in 1999, 2001, and
2005, respectively.
From 2005 to 2007, he was with the Regional
University of Northwestern Rio Grande do Sul, Iju,
Brazil. From 2008 to 2009, he was with the Santa
Catarina State University, Joinville, Brazil. Since
2009, he has been with the Power Electronics and
Control Research Group of the UFSM, where he is currently a Professor. His
research interests include multilevel converters, renewable energy sources, dis-
tributed generation and modeling, and digital control of static converters.
Roger Gules (M10) was born in Bento Goncalves,
RS, Brazil, in 1971. He received the B.S. degree from
the Federal University of Santa Maria, Santa Maria,
Brazil, and the M.S. and Ph.D. degrees from the
Federal University of Santa Catarina, Florian opolis,
Brazil, in 1998 and 2001, respectively.
From 2001 to 2005, he was a Professor in the
Universidade do Vale do Rio dos Sinos, Brazil. Since
2006, he has been a Professor at the Federal Tech-
nological University of Paran a, Curitiba, Brazil. His
research interests include high-frequency power con-
version, lighting systems, and renewable energy applications.
Jos e Renes Pinheiro (S93M95) was born in Santa
Maria, Brazil, in 1958. He received the B.S. de-
gree from the Federal University of Santa Maria,
Santa Maria, Brazil, and the M.S. and Ph.D. degrees
from the Federal University of Santa Catarina, Flo-
rian opolis, Brazil, in 1981, 1984, and 1994, respec-
tively, all in electrical engineering.
Since 1985, he has been a Professor at the Fed-
eral University of Santa Maria, where, in 1987, he
founded the Power Electronics and Control Research
Group. He was the Technical Program Chairman of
the 1999 Brazilian Power Electronics Conference and of the 2000 and 2005
Power Electronics and Control Seminar. From 2001 to 2002, he was with the
Center for Power Electronics Systems, Virginia Polytechnic Institute and State
University (Virginia Tech), Blacksburg, as a Postdoctoral Research Scholar. He
has authored more than 200 technical papers published in the proceedings of
conferences and journals. His current research interests include high-frequency
and high-power conversion, power supplies, multilevel converters, and model-
ing and control of converters.