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AbstractThe design and simulation of a CMOS Low

Noise Amplifier (LNA) is presented operating between 2.0
2.2 GHz. The LNA has a noise factor less than 4.5dB
and a amplifier gain value of greater than 10dB. The
design was completed in 250nm technology with a 3.0V
power supply.

I ndex TermsLNA, Noise factor, Amplifier gain, Cascode.

HE Low Noise Amplifier amplifies weak signals and
reduces the noise in subsequent stages by its gain.
As the noise generated by the LNA is directly injected
into the received signal, it is important that it has a low
noise figure, while boosting the output signal power. A
good LNA has a high enough gain, low noise figure,
high enough intermodulation and compression point.
Designing an LNA in Radio Frequency (RF) circuit
requires the trade-off of many importance characteristics
such as gain, Noise Figure (NF), stability, power
consumption and complexity

This design focuses on achieving a good noise figure,
and gain, as it is essential for an LNA to inject as little
noise as possible. The design is done in various steps.
The ideal design is worked out through hand
calculations. The ideal values obtained are then
attempted to be matched with simulation results. The
final simulated output is obtained with certain
adjustments in the components.

The design requirements of the Low Noise Amplifier
are given in Table 1. The basic design is an inductively
degenerated cascode amplifier. The gain is high with
input matching in this configuration. The size of the
active transistor requires a parallel thought about the
circuit noise. For this purpose, the transistor length is
kept at the minimum value of 250 nm. This reduces gate
and drain noise. The width, on the other hand, was
chosen based on power limited noise optimization.
I. ANALYTICAL ANALYSIS OF LNA
Two NMOS transistors are in cascode and is modeled
in Agilents Advance Design System (ADS) as shown


in Fig. 1. Here matching networks are used on both
sides of the transistor to transform the input and output
impedances to source and load impedances.

A. Matching Networks
A microwave transistor amplifier can be modeled by
using and input and an output matching network. The Z0
is transformed to the source and load impedances. The
impedance matching network is between input source
and device. The need for this arises as maximum power
needs to be transferred to the load. Proper termination at
input and output ports will also make the network
perform in a desired way. The impedance matching
networks can be designed by hand calculation or Smith
Chart. We made sure that the Real(Z11) is close to 50
and the Im(Z11) is close to 0. This has been done,
using the Smith Chart design guide in Agilents ADS
tool. It helped us choose the capacitance and resistive
elements for the input matching network.
For designing the output matching network, we
followed a similar procedure using the Agilent ADS
tool, and ensured that the S22 value is well below the
given specification of -10dB.

Initially, the inductive degeneration and gate
inductance were determined to optimize the resonant
frequency 2.0 to 2.2 GHz. The inductance values were
found to be the best match, when varied to optimize
noise performance. The values of load inductor Ld, gate
inductor Lg are calculated using the given quality factor
Design of a 2.0 GHz Low Noise Amplifier
Vaibhav Tiwari, Shrijit Mukherjee, Nandhini Botta, Rohan Bhattacharya
T
TABLE I
DESIGN SPECIFICATIONS
Parameter Specified Value

Operating frequency

2.0-2.2 GHz

Gain(GT) >10 dB
in < -10 dB

out < -10 dB
NF < 4.5 dB
Source voltage 3.0 V


Table . 1. Design Specifications of LNA
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of 50 at 1 GHz according to the specification.

Fig . 1. Circuit Diagram of cascode LNA


B. Noise Figure considerations



Noise figure as, shown, varies with Cgs1, as well as gm1.
The length of the transistor comes into play where
frequency is concerned. The factor gm/ Cgs1 goes up
with 1/L
2
. The length is kept at a minimum of 250 nm.
Cgs1 and gm1 is dependent on the width of the NMOS.

C. Gain
The amplifier gain of the system is the most useful of
the gain definitions for amplifier design. It accounts
for both source and load mismatch. Amplifier gain
includes all resistances in the gain diagram.


II. CIRCUIT DESCRIPTION

The input matching, output matching, as well as the
width of the circuit was decided by keeping gain and
noise considerations in mind. Every component placed
created a substantial change in either of these factors.
The bypass capacitor is given as an off-chip component
and meanwhile, a Vdc of 3.0 V is given through the
gate. it is found that the cascode amplifier is more
versatile of the three topologies, providing most stable
gain over a wider bandwidth with a small trade-off in
noise figure performance and design complexity.


Characteristic CS CG Cascode
Noise Figure Lowest Increases
with
frequency
Slightly
more than
CS
Gain Moderate Lowest Highest
Linearity Moderate High Highest


We started with a common source amplifier. However
after several adjustments for component values we were
unable to obtain the desired gain. This led us to
implement the amplifier as a cascode amplifier to obtain
the desired gain and the components were matched
accordingly to obtain an operational frequency in the
given frequency range.

The requirements were met in the following way.

A. Common Source Stage

A common source stage with just a resistive load
provides improper matching. Also the output node time
constant may make operation at higher frequencies
impossible. Also as supply voltages scale down with
technology, the gain decreases according to:


The gain is worsened further at smaller channel
lengths by channel length modulation. To negate this
effect, the CS stage can include an inductive load. This
allows us to support a lower DC voltage as compared to
a resistor. However the induction can also be made to
resonate with the capacitance at the output node and
thus enable operation at a higher frequency.


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Fig. 2. Inductively loaded CS stage, input impedance in
presence of CF and equivalent circuit

It is possible to match the input resistance of the
circuit to 50 ohms using the formula:


Here D is a positive quantity. We note that the
numerator falls to zero at a frequency given by:

This value should be avoid to prevent a scenario of
negative input impedance leading to instability.

B. Cascode

The Cascode is a combination of a common-source
device (ie our LNA) with a common-gate load.
This has the effect of increasing the output impedance.
We have assumed we are using a resistive
load, but if we are going to connect to another
stage say another LNA or mixer, then the load
will be capacitive. This capacitance will limit the
frequency response of the first amplifier stage (resulting
in lower gain) due to the Miller effect.
The additional cascode device has been configured
as a diode (ie at DC the gate is connected to the
source) as shown in Figure 3. The inductor between
the cascode source and supply blocks any
RF leaking to the supply rail and maybe varied in
value to optimize the gain response of the LNA.

C. Gain
GT is basically | S21|
2
, when | L| and | S | is zero.
Hence, when input and output are conjugate matched,
GT value reached its optimum value. The width of the
transistor is a factor that was varied to get optimum
gain. Thus the gain reaches a high value of 14.538 dB at
2.0 GHz and 14.744 dB at 2.2 GHz.

D. Noise Figure

Where 2 Z0 Cgs1 0 =1 / Qin, Qin is a factor that affects
NF inversely. Hence, as a whole, at a fixed Qin or Cgs1,
increasing power consumption or transconductance,
decreases noise figure. Noise figure of the circuit is
hence at a low value of 0.474 dB at 2.0 GHz and 0.579 dB
at 2.2 GHz.

E. Trade-offs

The major trade-off for designing low noise amplifier
is the gain and the noise figure. It is not possible to get
maximum gain and minimum noise figure at same time.
Therefore, we need trade off the gain and noise figure to
get more gain and less noise figure.

III. SIMULATION RESULTS

Fig .3. Circuit schematic

Fig .5. Amplifier Gain

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Fig .5. S11 parameter

Fig .6. Noise Figure

IV. CONCLUSION

The LNA design was successful. It met the goals.
The amplifier gain is greater than 10 dB over the desired
frequency (2.0-2.2 Ghz), noise figure is between 0.474
dB to 0.579 dB much lesser than the specification of 4.5
dB, and the input and output reflection coefficient is
lesser than the specified -10 dB. Also pre-calculations
just serve as a reference and are never accurate enough
to fully model the circuit making some adjustments
absolutely necessary.

V. REFERENCES
[1] RF Microelectronics Behzad Razavi, second edition
[2] http://www.circuitsage.com/tools/tool_view&tool_id=34
[3] The design of CMOS Radio-Frequency Integrated circuits Thomas H.
Lee, second edition.

VI. ACKNOWLEDGEMENT
We would like to thank Dr. William Eisenstadt for
teaching us concepts necessary for understanding the
functioning of RF circuits and providing us with a
project with a scope that allowed us to implement this
understanding. We would also like to thank Dooyoung
Kim for being available to help us out whenever we
needed it.
VII. AUTHORS
Vaibhav Tiwari is a graduate student in the Electrical
and Computer Engineering Department at University of
Florida specializing in Digital Hardware design, RF
Circuits and Systems, Advanced VLSI Design and
Wireless Communication.

Shrijit Mukherjee is pursuing his Masters in Electrical
and Computer Engineering at University of Florida. His
interests lie in the domains of Device Noise, Device
Physics, RF Circuit Design and VLSI Design. He has
obtained his Bachelor of Engineering in Electronics
from University of Mumbai.

Nandhini Botta received her B. Tech in Electrical and
Electronics Engineering from the Anna University in
2012. Currently, she is pursuing her Masters in
Electrical and Computer Engineering at University of
Florida. Her research interests include Digital VLSI
design, Energy Systems and Reconfigurable Computing.

Rohan Bhattacharya is a graduate student at University
of Florida in the Electrical and Computer Engineering
Department. His specializations include Digital VLSI,
Device Physics, Computer Architecture and RF Circuits.
He has done his Bachelor of Engineering in Electronics
from University of Mumbai in 2009.