Quy trnh thit k FPGA tng qut.

M t ban u v thit k. (Specification)

Khi xy dng mt chip kh trnh (FPGA) vi ngha dnh ch! mt "ng
d#ng ri$ng %i&t' v x()t ph*t t+ m,i "ng d#ng tr!ng thc ti-n c(c ./ng' .0 12t ra
y$( c3( phi thi4t k4 56 thc hi&n t/i 7( nh)t nh8ng "ng d#ng 19: ;7c 13( ti$n

QUY TRNH THIT K FPGA
QU TRNH NHI!" #$

%&NG %$


"& T'
(P)%IFI%ATI*N
"& T' THIT K

+'N #,

"& PH-NG %H.%
N/NG

NG&N NG0
H12

"& PH-NG

T3NG H4P 2*GI%

%&NG %$
(YNTH)(Y(

HI!U %H5NH KT
N6I

PH7N T8%H
TH9I GIAN

TH:% THI
I"P2)")NTA;
TI*N
NH <= "APPING

>?T KH6I

>@NH TUYN

%&NG %$ >?T
KH6I #A>@NH
TUYN

%BU HNH
%*NFIGURA;
TI*N
N=P HAY 2CP
TRNH

%&NG %$
%U HNH

c<a =(y trnh thi4t k4 ny c9 nhi&m v# ti4p nh>n c*c y$( c3( c<a thi4t k4 v xy
dng n$n ki4n tr?c t@ng =(*t c<a thi4t k4:
- M t thit k(Design Specification)
Ar!ng %7c ny' t+ nh8ng y$( c3( c<a thi4t k4 v da tr$n kh nBng c<a
cCng ngh& hi&n c9' ng7Di thi4t k4 ki4n tr?c .0 xy dng n$n t!n % ki4n tr?c t@ng
=(an ch! thi4t k4: Egha F tr!ng %7c ny ng7Di thi4t k4 ki4n tr?c phi mC t 17Gc
nh8ng v)n 1H .a(I
Ahi4t k4 c9 nh8ng kh/i n!J
K,i kh/i c9 ch"c nBng gJ
L!Mt 1ng c<a thi4t k4 v c<a m,i kh/i ra .a! J
Phn tNch c*c kO th(>t .P d#ng tr!ng thi4t k4 v c*c cCng c#' ph3n mHm h,
trG thi4t k4:
Kt thi4t k4 c9 thQ 17Gc mC t .P d#ng ngCn ng8 mC t ph3n c"ng' nh7 RLST hay
RUriF!g LST h!2c c9 thQ mC t =(a %n v0 mMch (.chUmatic capt(rU): Kt thi4t k4
c9 thQ v+a %a! gVm %n v0 mMch mC t .W 1V kh/i ch(ng' v+a c9 thQ dXng ngCn ng8
LST 1Q mC t chi ti4t ch! c*c kh/i tr!ng .W 1V:
- M phng chc nng (Function simulation).
Ya( khi mC t thi4t k4' ng7Di thi4t k4 c3n mC phZng t@ng thQ thi4t k4 vH m2t ch"c
nBng 1Q kiQm tra thi4t k4 c9 h!Mt 1ng 1?ng vi c*c ch"c nBng y$( c3(:
- !ng h"p logic (#ogic S$nthesis).
A@ng hGp F!gic F =(* trnh t@ng hGp c*c mC t thi4t k4 thnh .W 1V %/ trN
mMch (nUtFi.t): [(* trnh chia thnh \ %7cI ch(yQn 1@i c*c m] ^AT' m] LST
thnh mC t d7i dMng c*c %iQ( th"c 1Mi ./ ;!!FUan v da tr$n c*c %iQ( th"c ny
k4t hGp vi th7 vi&n t4 %! ch(_n .`n c9 1Q t@ng hGp n$n mt thi4t k4 t/i 7(:
ECE 545 Introduction to VHDL 57
architUct(rU KTabSAAAFTcd !e KTa i.
.ignaF AfIYASbTcG56g
.ignaF ;fIYASbTcG56g
.ignaF hfIYASbTcG56g
.ignaF Kaibj' Kaibf' Kaib\' KaibkI YASbTcG56g
%Ugin
AflmA nhUn (EoGbAmpjp) UF.U
n!t Ag
;flm; nhUn (EoGb;mpjp) UF.U
n!t ;g
hlmhf nhUn (EoGbhmpjp) UF.U
n!t hfg
KaibjlmAf and ;fg
KaibflmAf !r ;fg
Kaib\lmAf x!r ;fg
KaibklmAf xn!r ;fg
nith (Tf q Tj) .UFUct
hflmKaibj nhUn rjjr'
Kaibf nhUn rjfr'
Kaib\ nhUn rfjr'
Kaibk nhUn !thUr.g
Und KTabSAAAFTcdg
VHDL description
Circuit netlist
Logic Synthesis
- %i&u ch'nh c(c kt n)i (Datapath Schematic).
Eh>p nUtFi.t v c*c rng %(c vH thDi gian v! mt cCng c# phn tNch thDi
gian (timing anaFy.ic): 6Cng c# phn tNch ny .0 t*ch rDi t)t c c*c k4t n/i c<a thi4t
k4' tNnh thDi gian tr- c<a c*c k4t n/i da tr$n c*c rng %(c: Sa tr$n k4t =( phn
tNch (rUp!rt) c<a cCng c# phn tNch' x*c 1snh c*c k4t n/i khCng thZa m]n vH thDi
gian: AXy thU! ng(y$n nhn dtn 14n khCng thZa m]n m ta c9 thQ vi4t FMi m] v ti4n
hnh FMi t@ng hGp F!gic h!2c hi&( chunh FMi c*c rng %(c:
3.1.2 Thc thi (!p"e!entation).
Aa 1] c9 .W 1V %/ trN nUtFi.t mC t t@ng thQ thi4t k4 tMi m"c c@ng (chu gVm c*c c@ng
F!gic cW %n v c*c mMch F!gic kh*c nh7I Kai): [(* trnh ny .0 12t .W 1V nUtFi.t
ny F$n chip' gvi F =(* trnh thc thi (SUvicU 5mpFUmUntati!n):
[(* trnh gVm c*c %7cI
# $nh %& (mapping hay cwn gvi eitting x Bn khp) I ch(_n %s d8 Fi&( 13( v!' x*c
1snh kNch th7c c*c kh/i: 6*c kh/i ny .0 phi phX hGp vi c)( tr?c c<a f t4 %! cW
%n c<a FPGA: (gVm nhiH( c@ng F!gic) v 12t ch?ng v! c*c vs trN t/i 7( ch! vi&c
chMy dy:
ECE 545 Introduction to VHDL 63
Mapping
TaA\
TaAk
TaAy
TaAz
TaAf
FFf
FF\
TaAj
# '(t kh)i v* +nh tu,n (-"ace . /oute)0
{ |2t kh/iI 12t c*c kh/i *nh xM v! c*c t4 %! (cUFF) } vs trN t/i 7( ch! vi&c chMy
dy:
ECE 545 Introduction to VHDL 64
Placing
6T; YT56oY
FPGA
{|snh t(y4nI ;7c ny thc hi&n vi&c n/i dy c*c t4 %!:
ECE 545 Introduction to VHDL 65
Routing
PrDgrEFFEGHI %DnnIJtiDnK
FPGA
|Q thc hi&n vi&c ny' ch?ng ta c3n c9 c*c thCng tin .a(I
6*c thCng tin v>t F vH th7 vi&n t4 %!' vN d# kNch th7c t4 %!' c*c 1iQm
1Q k4t n/i' 1snh thDi' c*c tr} ngMi tr!ng khi 1i dy:
Kt nUtFi.t 17Gc t@ng hGp .0 chu ra chi ti4t c*c in.tancU v m/i =(an h& k4t
n/i %a! gVm c c*c 17Dng dtn %s hMn ch4 tr!ng thi4t k4:
A)t c c*c y$( c3( c<a ti4n trnh ch! c*c Fp k4t n/i' %a! gVm c*c F(>t thi4t
k4 ch! c*c Fp chMy dy' tr} kh*ng v 1i&n d(ng' ti$( th# nBng F7Gng' c*c
F(>t vH . dtn 1i&n tr!ng m,i Fp:
3.1.3. 1u2 t34nh 5&p (6o7n"oa6) v* "8p t34nh (p3o93a!).
Ya( =(* trnh thc hi&n' thi4t k4 c3n 17Gc nMp v! FPGA d7i dMng dwng %it
(%it .trUam):
[(* trnh nMp thi4t k4 (d!nnF!ad) v! FPGA th7Dng nMp v! % nh %ay
hWi' vN d# nh7 Y^AK: AhCng tin c)( hnh .0 17Gc nMp v! % nh: Swng %it 17Gc
tr(yHn F?c ny .0 mang thCng tin 1snh ngha c*c kh/i F!gic c~ng nh7 k4t n/i c<a
thi4t k4: A(y nhi$n' F7( rng' Y^AK .0 m)t d8 Fi&( khi m)t ng(Vn n$n thi4t k4 .0
khCng F7( 17Gc 14n phi$n Fm vi&c k4 ti4p:
T>p trnh (pr!gram) F th(>t ng8 1Q mC t =(* trnh nMp ch7Wng trnh ch! c*c
% nh khCng %ay hWi' vN d# nh7 P^cK: Eh7 v>y' thCng tin c)( hnh vtn .0 17Gc
F7( tr8 khi m)t ng(Vn: