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1.HOW TO COMPILE AND SIMULATE THE MENTOR
GRAPHICS TOOL

Aim: To operate Mentor Graphics Tool (Compile and Simulation only)
Procedure:
I. 1. Go to START-All Programs
2. Go to Modelsim SE 6.6b Licensing Wizard Usertool Edit Environment
Variables
Enter 17171@10.10.60.134 and update it.
Go to MGLS License, enter the same value and update it. Close the window.

II. To create a folder in local drive:
1. Go to Z drive(any local drive)
2. Create a new folder with name VHDLOCT2011NAME

III. To compile a program using MODELSIM
1. Go to START All Programs Modelsim SE6.6b Modelsim window.
2. In Modelsim, go to New Project Browse for the path where the folder is created in
Step II give project name (combinational circuits) and click OK.
3. A new window pops up to provide the file name inside the folder specified in step 2.
Eg:AND2GATE
4. Write program in editor window.

library ieee;
use ieee.std_logic_1164.all;

entity and2gate is
port(a,b : in std_logic;
c: out std_logic);
end and2gate;

architecture andarc of and2gate is
begin
c<=(a and b);
end andarc;
5.save the program
IV. Compilation of the program
Go to Compile Compile Selected
In Transcript Window message gets displayed compile of and2gate.vhd was successful


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V. Simulation of the program
Go to Simulate Start Simulation select the specified program(and2gate) entity type
inside WORK folder. Click OK

Now the object window appears where the input values are forced.

1. To give a forced input
We have a and b as input signals. Right click on i/p signals and give FORCE option
and in the popped window give the value of corresponding signal.
2. To add the signals into waveform
Go to ADD To Wave Selected Signals(for single signal)
Signals in Region (for all signals)

Now the Wave window appears.
3. To obtain waveforms
Click on RUN icon. Repeat for all combination of inputs to obtain the corresponding
i/p and o/p waveforms.

This is Forced Simulation.

Result:
Familiarized with compilation and simulation of Mentor Graphics Tool.











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2.HOW TO WRITE AND SIMULATE A TEST-BENCH

Aim: To write a test bench and simulate for a two input AND gate.

Procedure:
Test bench is used to simulate input samples continuously and check in the output.
library ieee;
use ieee.std_logic_1164.all;

entity and2gatetestbench is
end;

architecture testbenchandarc of and2gatetestbench is

component and2gate
port(a,b : in std_logic;
c : out std_logic);
end component;
signal s1,s2,s3:bit;
begin
L1:and2gate port map(s1,s2,s3);
s1<='1','0' after 100 ns,
'1' after 200 ns,
'0' after 300 ns;
s2<='0','1' after 200 ns;
end testbenchandarc;


Compile the program :
Compile Compile Selected

Simulate the program:
Simulate Start Simulation Work select both and2gate and and2gatetestbench and
click on Enable Optimization so that it is disabled then click OK.








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Now select the SIM testbenchprogram right click ADD To Wave All items in
region.
Wave window pops out. Click RUN icon. The waveform is obtained.

Result:
Familiarized to write a Test-Bench and simulate using VHDL program.





























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q r


TRUTH TABLE

q r
0 1
1 0





Fig: Output waveform of not gate




nnotgate

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3.LOGIC GATES

Aim: To design all logic gates

3.1 NOT GATE
library ieee;
use ieee.std_logic_1164.all;
entity nnotgate is
port(q: in bit; r: out bit);
end nnotgate;
architecture nnotgate of nnotgate is
begin
r<= (not q);
end nnotgate;











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q
s
r


TRUTH TABLE










Fig: Out put waveform of And gate



q r s
0 0 0
0 1 0
1 0 0
1 1 1
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3.2 AND GATE
library ieee;
use ieee.std_logic_1164.all;
entity and2gate is
port(q,r:in bit;s:out bit);
end and2gate;
architecture and2gate of and2gate is
begin
s<=q and r;
endand2gate;

















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TRUTH TABLE










Fig: Output waveform of Nand gate


q r s
0 0 1
0 1 1
1 0 1
1 1 0
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3.3 NAND GATE
library ieee;
use ieee.std_logic_1164.all;
entity nand2gate is
port(q,r:in bit;s:out bit);
end nand2gate;
architecture nand2gate of nand2gate is
signal S1:bit;
begin
process(q,r)
begin
if q='0' and r='0' then
S1<='1';
elsif q='0' and r='1' then
S1<='1';
elsif q='1' and r='0' then
S1<='1';
elsif q='1' and r='1' then
S1<='0';
end if;
s<=S1;
end process;
end nand2gate;


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TRUTH TABLE










Fig: Out put waveform of OR gate



O1 O2 O3
0 0 0
0 1 1
1 0 1
1 1 1
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3.4 OR GATE
library ieee;
use ieee.std_logic_1164.all;
entity or2gate t is
port(q,r:in bit;s:out bit);
end or2gate;
architecture a_or2gate of or2gate is
begin
s<=q or r;
end a_or2gate;















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TRUTH TABLE











Fig: Out put waveform of NOR gate



q r s
0 0 1
0 1 0
1 0 0
1 1 0
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3.5 NOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity nor2gateis
port(q,r:in bit;s:out bit);
end nor2gate;;
architecture NOR_2bit of nor2gate
signal S1:bit;
begin
process(q,r)
begin
if q='0' and r='0' then
S1<='1';
elsif q='0' and r=1 then
S1<='0';
elsif q='1' and r='0' then
S1<='0';
elsif q='1' and r='1' then
S1<='0';
end if;
end process;
s<=S1;
end NOR_2bit;


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TRUTH TABLE












Fig: Out put waveform of Xor gate



X1 X2 X3
0 0 0
0 1 1
1 0 1
1 1 0
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3.6 XOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity xxor2gate is
port(q,r : in bit; s: out bit);
end xxor2gate;
architecture xor_2 of xxor2gate is
begin
process(q,r)
begin
if q='0' and r='0' then s<='0';
elsif q='0' and r='1' then s<='1';
elsif q='1' and r='0' then s<='1';
elsif q='1' and r='1' then s<='0';
end if;
end process;
end xor_2;




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TRUTH TABLE










Fig: Out put waveform of XNOR gate




q r s
0 0 1
0 1 0
1 0 0
1 1 1
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3.7 XNOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity xnor2gate is
port(q,r:in std_logic;s:out std_logic);
end xnor2gate;
architecture x nor2gate of x nor2gate is
begin
s<=q nor r;
end xnor2gate;
















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Fig: output waveform of three input nand gate







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3.8 THREE INPUT NAND GATE
library ieee;
use ieee.std_logic_1164.all;
entity nand3gate is
port(q,r,s:in std_logic;t:out std_logic);
end nand3gate;
architecture nand3gate of nand3gate is
begin
t <=q nand r nand s;
end nand3gate;


















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Fig: output waveform of three input nor gate





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3.9 THREE INPUT NOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity nor3gate is
port(q,r,s:in std_logic;t:out std_logic);
end nor3gate;
architecture nor3gate of nor3gate is
begin
t <=q nor r nor s;
end nor3gate;


















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Fig: output waveform of four input nand gate




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3.10 FOUR INPUT NAND GATE
library ieee;
use ieee.std_logic_1164.all;
entity nand4gate is
port(q,r,s,t:in std_logic;u:out std_logic);
end nand4gate;
architecture nand4gate of nand4gate is
begin
u <=q nand r nand s nand t;
end nand4gate;


















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Fig: output waveform of four input nor gate






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3.11 FOUR INPUT NOR GATE
library ieee;
use ieee.std_logic_1164.all;
entity nor4gate is
port(q,r,s,t:in std_logic;u:out std_logic);
end nor4gate;
architecture a_nor of nor4gate is
begin
u<=(not q) and (not r) and (not s) and (not t);
end a_nor;
















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Fig: Out put waveform of test bench (and gate)

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3.12 TEST BENCH (AND GATE)
library ieee;
use ieee.std_logic_1164.all;
entity t_AND2bit is end;
architecture t_AND_2bit of t_AND2bit is
component AND2bit
port(A1,A2:in bit;A3:out bit);
end component;
signal S1,S2,S3:bit;

begin
B1:AND2bit port map(S1,S2,S3);
S1<='1' after 50ns, '0' after 100ns, '1' after 150ns;
S2<='1' after 100ns;
end t_AND_2bit;











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TRUTH TABLE










Fig: output waveform of half adder

q r s t
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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4.ADDER AND SUBTRACTOR

Aim: To design full adder, half adder, full subtractor and half subtractor

4.1 HALF ADDER
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(q,r:in bit;s,t:out bit);
end ha;
architecture a_ha of ha is
begin
s<=q xor r;
t<=q and r;
end a_h








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TRUTH TABLE


Fig: Out put waveform of full adder



p q r s t
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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4.2 FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(p,q,r:in bit;s,t:out bit);
end fulladder;
architecture full_adder of fulladder is
component halfadder
port(a,b:in bit;s,c:out bit);
end component;
component OR2bit
port(O1,O2:in bit;O3:out bit);
end component;
signal s1,s2,s3:bit;
begin
a1:halfadder port map(p,q,s1,s2);
a2:halfadder port map(r,s1,s,s3);
a3:OR2bit port map(s3,s2,t);
end full_adder;






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TRUTH TABLE








Fig: Out put waveform of half subtractor



q r s t
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
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4.3 HALF SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity hs is
port(q,r:in bit;s,t:out bit);
end hs;
architecture hs of hs is
begin
s<=(q xor r);
t<=(not q) and r;
end hs;















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TRUTH TABLE
q r s t u
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 1 0 0 0
1 1 1 1 1



Fig:output wave form of full subtractor

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4.4 FULL SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity fs is
port(q,r,s:in std_logic;t,u:out std_logic);
end fs;
architecture a_fs of fs is
begin
t<=q xor r xor s;
u<=((not q) and r) or ((q xnor r) and s) ;
end a_fs;















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Fig: output waveform of adder cum subtractor



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4.5 ADDER CUM SUBTRACTOR
library ieee;
use ieee.std_logic_1164.all;
entity acs is
port(Q1,R1:in bit_vector(3 downto 0);M:in bit; S1: out bit; T1: out bit_vector(3 downto 0));
end acs;
architecture a_acs of acs is
component fa
port(q,r,s:in bit;t,u:out bit);
end component;
component xxor2gate
port(q,r:in bit;s:out bit);
end component;
signal a:bit_vector(3 downto 0);
signal b:bit_vector(2 downto 0);
begin
X1:xxor2gate PORT MAP(M,R1(0),a(0));
X2:xxor2gate PORT MAP(M,R1(1),a(1));
X3:xxor2gate PORT MAP(M,R1(2),a(2));
X4:xxor2gate PORT MAP (M,R1(3),a(3));
F1:fa PORT MAP(Q1(0),a(0),M,T1(0),b(0));
F2:fa PORT MAP(Q1(1),a(1),b(0),T1(1),b(1));
F3:fa PORT MAP(Q1(2),a(2),b(1),T1(2),b(2));
F4:fa PORT MAP(Q1(3),a(3),b(2),T1(3),s1);
end a_acs;
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Fig: output wave form of test bench (half adder)




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4.6 TEST BENCH(HALF ADDER)
library ieee;
use ieee.std_logic_1164.all;
entity t_halfadder is end;
architecture t_half_adder of t_halfadder is
component halfadder
port(a,b:in bit;s,c:out bit);
end component;
signal s1,s2,s3,s4:bit;
begin
b1:halfadder port map(s1,s2,s3,s4);
s1<='1' after 50ns,'0' after 100ns,'1' after 150ns;
s2<='1' after 100ns;
end t_half_adder;











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Fig:output waveform of ripplecarry adder


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5. CARRY LOOK AHEAD ADDER,CARRY SAVE ADDER,
RIPPLE CARRY ADDER

Aim: To write program for ripple carry adder, carry look ahead adder and carry save adder

5.1 RIPPLE CARRY ADDER
library ieee;
use ieee.std_logic_1164.all;
entity rca is
port(q,r:in bit_vector(3 downto 0);i:in bit;t:out bit_vector(3 downto 0);sout:out bit);
end rca;
architecture rca of rca is
component fa
port(q,r,s:in bit;t,u:out bit);
end component;
signal s:bit_vector(2 downto 0);
signal a:bit_vector(2 downto 0);
begin
f1:fa port map(q(0),r(0),i,t(0),s(0));
f2:fa port map(q(1),r(1),a(0),t(1),a(1));
f3:fa port map(q(2),r(2),a(1),t(2),a(2));
f4:fa port map(q(3),r(3),a(2),t(3),sout);
end rca;




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Fig: output waveform of carry look ahead adder


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5.2 CARRY LOOK AHEAD ADDER
library ieee;
use ieee.std_logic_1164.all;
entity cla is
port(q,r:in bit_vector(3 downto 0);tin:in bit;tout:out bit;s:out bit_vector(3 downto 0));
end cla;
architecture cla of cla is
component fa
port(q,r,s:in bit;t,u:out bit);
end component;
component or2gate
port(q,r:in bit;s:out bit);
end component;
component xxor2gate
port(q,r:in bit;s:out bit);
end component;
component and2gate
port(q,r:in bit;s:out bit);
end component;
signal g:bit_vector(2 downto 0);
signal ge,pr,t:bit;
begin
x1:xxor2gate port map(q(0),r(0),pr);
x2:xxor2gate port map(pr,tin,s(0));
a1:and2gate port map(pr,ge,t);
a2:and2gate port map(q(0),r(0),ge);


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o1:or2gate port map(t,ge,g(0));
f1:fa port map(q(1),r(1),g(0),s(1),g(1));
f2:fa port map(q(2),r(2),g(1),s(2),g(2));
f3:fa port map(q(3),r(3),g(2),s(3),tout);
end cla;






















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Fig: output waveform of carry save adder



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5.3 CARRY SAVE ADDER
library ieee;
use ieee.std_logic_1164.all;
entity csa is
port(q,r,s:in bit_vector(3 downto 0);t,m:out bit_vector(3 downto 0));
end csa;
architecture a_csa of csa is
component fa
port(q,r,s:in bit;t,u:out bit);
end component;
begin
b1:fa port map(q(0),r(0),s(0),t(0),m(0));
b2:fa port map(q(1),r(1),s(1),t(1),m(1));
b3:fa port map(q(2),r(2),s(2),t(2),m(2));
b4:fa port map(q(3),r(3),s(3),t(3),m(3));
end a_csa;










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Fig: output waveform of multiplier



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6. MULTIPLIER AND DIVIDER CIRCUIT

Aim: To write program for multiplier and divider

6.1 MULTIPLIER
library ieee;
use ieee.std_logic_1164.all;
entity mul is
port(q,r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));
end mul;
architecture mul of mul is
component and2gate
port(q,r:in bit;s:out bit);
end component;
component ha
port(q,r:in bit;s,t:out bit);
end component;
signal v:bit_vector(4 downto 1);
begin
a1:and2gate port map(q(0),r(0),s(0));
a2:and2gate port map(q(0),r(1),v(1));
a3:and2gate port map(q(1),r(0),v(2));
a4:and2gate port map(q(1),r(1),v(3));
h1:ha port map(v(1),v(2),s(1),v(4));
h2:ha port map(v(3),v(4),s(2),s(3));
end mul;
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0010(rem)






Fig: output waveform of divider






INDEX(i)
q-inp comp r-input s(qoutient) Operation on 1
st

column
3 1011 < 0011000 0 none
2 1011 < 0001100 0 none
1 1011 > 0000110 1 q-input(i)-r-
input(i)
0 0101 > 0000011 1 q-input (i)-r-
input(i)
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6.2 DIVIDER
library ieee;
use ieee.std_logic_1164.all;
entity div4 is
generic(n1:integer:=3);
port(q,r:in integer range 0 to 15; s:out std_logic_vector(3 downto 0);t:out integer range 0 to 15;
err:out std_logic);
end div4;
architecture div of div4 is
begin
process(q,r)
variable temp1,temp2:integer range 0 to 15;
begin
temp1:=q;
temp2:=r;
if (r=0)
then err<='1';
else err<='0';
end if;
for q in n1 downto 0 loop
if(temp1>=temp2*2**q )
then s(q)<='1';
temp1:=temp1-temp2*2**q;
else s(q)<='0';
end if;
end loop;
t<=temp1;
end process; end div;
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Fig :output waveform of multiplier test bench




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6.3 MULTIPLIER TEST BENCH
library ieee;
use ieee.std_logic_1164.all;
entity mul_tb is
end;
architecture tb_mularc of mul_tb is
component mul
port(q,r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));
end component;
signal a,b:bit_vector(1 downto 0);
signal c:bit_vector(3 downto 0);
begin
L1 : mul port map(a,b,c);
a(0) <= '0','1' after 10ns,'0' after 20ns;
a(1) <= '1','0' after 20ns,'1' after 30ns;
b(0) <= '0','1' after 10ns,'0' after 30ns;
b(1) <= '1','0' after 10ns,'1' after 30ns;
end tb_mularc;








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Fig: output waveform of magnitude comparator





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7 . MAGNITUDE COMPARATOR

Aim: To write program for magnitude comparator

PROGRAM
library ieee;
use ieee.std_logic_1164.all;
entity comparator is
generic(n:integer:=7);
port(q,r:in std_logic_vector(n downto 0);s1,s2,s3:out std_logic);
end comparator;
architecture acomp of comparator is
begin
s1<='1' when q>r else '0';
s2<='1' when q=r else '0';
s3<='1' when q<r else '0';
end acomp;









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TRUTH TABLE







Fig:output wave form of mux 2:1


s t
0 q
1 r
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8 MUX AND DMUX, DECODER AND ENCODER

Aim: To write programs for MUX and DMUX,DECODER and ENCODER


8.1 MUX 2:1
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port(q,r,s : in bit; t : out bit);
end mux2to1;
architecture mux2to1 of mux2to1 is
begin
process(q,r,s)
begin
if s='0' then t<=q;
else if s='1' then t<=r;
end if;
end if;
end process;
end mux2to1;







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TRUTH TABLE






Fig: Output waveform of 1:2 DMUX




r s t
0 q 0
1 0 q
64

8.2 DMUX 1:2
library ieee;
use ieee.std_logic_1164.all;
entity demux1to2 is
port(q,r:in std_logic;s,t:out std_logic);
end demux1to2;
architecture demux of demux1to2 is
begin
process(q,r)
begin
if r='0' then s<=q;t<='0';
elsif r='1' then s<='0';t<=q;
end if;
end process;
end demux;






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CIRCUIT DIAGRAM


Fig: output waveform of 4:1 MUX

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8.3 MUX 4:1
library ieee;
use ieee.std_logic_1164.all;
entity mux4to1 is
port(q,r,s,t,t1,t0:in std_logic;u:out std_logic);
end mux4to1;
architecture mux of mux4to1 is
begin
u<=((q and (not t1)and (not t0)) or ((not t1)and t0 and r)or (t1 and (not t0) and s)or(t1 and t0
and t));
end mux;








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CIRCUIT DIAGRAM


Fig: Output waveform of 1:4 DMUX

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8.4 DMUX 1:4
library ieee;
use ieee.std_logic_1164.all;
entity demux1to4 is
port(q,r1,r0:in std_logic;s,t,u,v:out std_logic);
end demux1to4;
architecture demux of demux1to4 is
begin
s<=q and (not r1) and (not r0);
t<=q and (not r1) and r0;
u<=q and r1 and (not r0);
v<=q and r1 and r0;
end demux;







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Fig: Output waveform of Octal to Binary Encoder

INPUT ( q
0
to q
7
) OUTPUT ( r
2
to r
0
)
100000000
01000000
00100000
00010000
00001000
00000100
00000010
00000001
000
001
010
011
100
101
110
111
70

8.5 OCTAL TO BINARY ENCODER
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port(q:in std_logic_vector(0 to 7);r:out std_logic_vector(2 downto 0));
end encoder;
architecture encoder of encoder is
begin
r(0)<=q(1) or q(3) or q(5)or q(7);
r(1)<=q(2) or q(3) or q(6)or q(7);
r(2)<=q(4) or q(6) or q(5)or q(7);
end encoder;















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INPUT(q2 to q0) OUTPUT( r7 to r0)
000
001
010
011
100
101
110
111
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000


Fig: Output waveform of 3 to 8 Decoder

72

8.6 DECODER 3 TO 8
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(q:in bit_vector(2 downto 0);r:out bit_vector(7 downto 0));
end decoder;
architecture decoder of decoder is
begin
r(0) <= ((not q(2)) and (not q(1)) and (not q(0)));
r(1) <= ((not q(2)) and (not q(1)) and ( q(0)));
r(2) <= ((not q(2)) and ( q(1)) and (not q(0)));
r(3) <= ((not q(2)) and ( q(1)) and ( q(0)));
r(4) <= ( q(2) and (not q(1)) and (not q(0)));
r(5) <= (q(2) and (not q(1)) and ( q(0)));
r(6) <= ( q(2) and ( q(1)) and (not q(0)));
r(7) <= ( q(2) and ( q(1)) and ( q(0)));
end decoder;












73






Fig: Output waveform of testbench(MUX 2:1)









74

8.7 TEST BENCH(MUX 2:1)
library ieee;
use ieee.std_logic_1164.all;
entity tb_mux2to1 is end;
architecture tb_mux_2to1 of tb_mux2to1 is
component mux2to1
port(q,r,s : in bit; t : out bit);
end component;
signal s1,s2,s3,s4:bit;
begin
b1:mux2to1 port map(s1,s2,s3,s4);
s1<='0','1' after 100ns;
s2<='1','0' after 100ns;
s3<='0','1' after 50ns,'0' after 100ns,'1' after 150ns;
end tb_mux_2to1;






75



BINARY GRAY
q3 q2 q1 q0 r3 r2 r1 r0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 1 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
76

9 CODE CONVERTERS

Aim:To design and implement different code converters using VHDL.
i. Binary to gray code converter
ii. Gray code to binary converter
iii. Binary to BCD converter
iv. BCD to Excess3 converter

9.1 BINARY TO GRAY CODE CONVERTER
library ieee;
use ieee.std_logic_1164.all;
entity btog is
port(q:in std_logic_vector(3 downto 0);r:out std_logic_vector(3 downto 0));
end btog;
architecture btogarc of btog is
begin
r(3)<=q(3);
r(2)<=q(3) xor q(2);
r(1)<=q(1) xor q(2);
r(0)<=q(0) xor q(1);
end btogarc;


77










Fig: Output waveform of binary to gray code converter


78




























79



GRAY BINARY
q3 q2 q1 q0 r3 r2 r1 r0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
80

9.2 GRAY TO BINARY CODE CONVERTER
library ieee;
use ieee.std_logic_1164.all;
entity gb is
port(q:in std_logic_vector(3 downto 0);r:inout std_logic_vector(3 downto 0));
end gb;
architecture gbarc of gb is
begin
r(3)<=q(3);
r(2)<=q(3) xor q(2);
r(1)<=r(2) xor q(1);
r(0)<=r(1) xor q(0);
end gbarc;











81








Fig: Out put waveform of gray to binary code converter
82




























83



BINARY BCD
q3 q2 q1 q0 r4 r3 r2 r1 r0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1

84

9.3 BINARY TO BCD CODE CONVERTER
library ieee;
use ieee.std_logic_1164.all;
entity btob is
port(q:in std_logic_vector(3 downto 0);r:inout std_logic_vector(4 downto 0));
end btob;
architecture btobarc of btob is
begin
r(4)<=((q(3)and q(2))or(q(3) and q(1)));
r(3)<=(q(3)and (not q(2))and (not q(1)));
r(2)<=((not q(3))and q(2))or(q(2) and q(1));
r(1)<=((q(3)and q(2)and (not q(1)))or((not q(3)) and q(1)));
r(0)<=q(0);
end btobarc;












85


r0=q0 r1=q3q2q1 +q3
r3=q3 q2 + q1

r4=q3q2+q2 q1

Fig: Out put waveform of binary to bcd code converter

86




























87









88

9.4 BCD TO EXCESS-3 CODE CONVERTER
library ieee;
use ieee.std_logic_1164.all;
entity bcdtoexcess3 is
port(q,r,s,t:in bit;u,v,w,x:out bit);
end bcdtoexcess3;
architecture bcdfun of bcdtoexcess3 is
component and2gate
port (q,r:in bit;s:out bit);
end component;
component xor2gate
port (q,r:in bit;s:out bit);
end component;
component or2gate
port (q,r:in bit;s:out bit);
end component;
component not1gate
port (q:in bit;r:out bit);
end component;
signal a1,o1,x1:bit;
begin
G1:or2gate port map (q,a1,u);
G2:and2gate port map (r,o1,a1);
G3:or2gate port map (s,t,o1);
G4:xor2gate port map (o1,r,v);
G5:xor2gate port map (s,t,x1);
G6:not1gate port map (x1,w);
G7:not1gate port map (t,x); end bcdfun;
89



Testbench














Fig:output waveform for test bench for Binary to Gray code converter

S1(0)
to
S1(3)
S2(0) to
S2(3)
q r
B2G
90

9.5 TEST BENCH( BINARY TO GRAY CODE CONVERTER)
library ieee;
use ieee.std_logic_1164.all;
entity b2gtestbench is
end;
architecture testbench of b2gtestbench is
component btog
port(q:in std_logic_vector(3 downto 0);
r:out std_logic_vector(3 downto 0));
end component;
signal s1,s2: std_logic_vector(3 downto 0);
begin
L1:B2G port map(s1,s2);
s1(0)<= '0','1' after 10 nS,'0' after 20 nS,'1' after 30 nS,'0' after 40 nS,'1' after 50 nS;
s1(1)<= '0','1' after 20 ns,'1' after 40 nS,'0' after 60 nS,'1' after 90 ns ;
S1(2)<= '0','1' after 40 nS,'0'after 80 nS,'1' after 90 nS;
S1(3)<= '0','1' after 80 nS;
end testbench;








91

s q
r qb
clk

TRUTH TABLE
S R Clk q qb
0
0
1
1
0
1
0
1
1
1
1
1
q

0
1
X

qb
1
0
X



Fig: Output waveform of SR FlipFlop




sr
92

10 FLIP FLOPS

Aim:To design and implement the following flipflops using VHDL.

10.1 SR flipflops
library ieee;
use ieee.std_logic_1164.all;
entity sr is
port(s,r,clk,rst:in std_logic;q:inout std_logic;qb:out std_logic);
end sr;
architecture sr of sr is
begin
process(s,r,clk)
begin
if rst='1' then
q<='0';qb<='1';
elsif (clk='1' and clk'event) then
if s='0' and r='0' then
q<=q; qb<=not q;
elsif s='0' and r='1' then
q<='0'; qb<='1';
elsif s='1' and r='0' then
q<='1';qb<='0';
else report "not defined";
end if;
end if;
end process;
end sr;
93



TRUTH TABLE










Fig: Output waveform of JK Flip Flop
J K Clk q qb
0
0
1
1
0
1
0
1
1
1
1
1
q

0
1
qb

qb
1
0
Q
94

10.2 JK FLIP FLOP
library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk,rst:in std_logic;q,qb:out std_logic);
end jkff;
architecture jkff of jkff is
signal qt,qbt:std_logic;
begin
process(j,k,clk,rst,qt,qbt)
begin
if rst='1' then
qt<='0'; qbt<='1';
elsif(clk ='1' and clk'event) then
if j='0' and k='0' then
qt<=qt; qbt<=(not qt);
elsif j='0' and k='1' then
qt<='0'; qbt<='1';
elsif j='1' and k='0' then
qt<='1'; qbt<='0';
else
qt<=(not qt); qbt<=qt;
end if;
end if;
end process;
q<=qt; qb<=qbt;
end jkff;

95


d q
clk qbar




TRUTH TABLE


d Clk q qbar
0
1
1
1
0
1
1
0




Fig: Output waveform of D Flip Flop

dff
96

10.3 D FLIP FLOP
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk,rst:in std_logic;q,qbar:inout std_logic);
end dff;
architecture dff of dff is
begin
process(d,clk,rst)
begin
if rst='1' then
q<='0';
qbar<='1';
elsif(clk ='1' and clk'event) then
q<=d;
qbar<=not d;
end if;
end process;
end dff;








97

T q
clk qbar
rst


TRUTH TABLE

T Clk rst q qbar
0
1
X
1
1
X
0
0
1
1
0
0
0
1
0




Fig: Output Waveform of T Flip Flop


tff
98

10.4 T FLIP FLOP
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port(t,clk,rst:in std_logic;q,qbar:inout std_logic);
end tff;
architecture tff of tff is
begin
process(t,clk,rst)
begin
if rst='1' then
q<='0';
qbar<='1';
elsif(clk ='1' and clk'event) then
if t='1' then q<= (not q);
qbar<=(not qbar);
elsif t='0' then
null;
end if;
end if;
end process;
end tff;





99

t_dff

q t

r u






Fig: Output waveform of test bench (D Flip Flop)
d q

Clk qb
100

10.5 TEST BENCH(D FLIP FLOP)
library ieee;
use ieee.std_logic_1164.all;
entity t_dff is end;
architecture t_d_ff of t_dff is
component dff
port(d,clk,rst:in std_logic;q,qbar:inout std_logic);
end component;
signal q,r,s,t,u: std_logic;
begin
a1:dff port map(q,r,s,t,u);
q <='0','1' after 100ns,'0' after 200ns,'1' after 300ns;
r <='0','1' after 100ns,'0' after 150ns,'1' after 200ns;
s <='1','0' after 100ns;
end t_d_ff;













101

q(3)
q(2)
clk q(1)
q(0)

Clk Q
3
Q
2
Q
1
Q
0

1
2
3
4
5
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0



Fig: Output waveform of Ring Counter






ring1
102

11 SYNCHRONOUS COUNTER

Aim: To write program for Synchronous Counters

11.1 RING COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity ring1 is
port(clk:in std_logic;q:inout std_logic_vector(3 downto 0));
end ring;
architecture ring1 of ring1 is
begin
process(clk)
variable r: std_logic_vector(3 downto 0):= "0001";
variable s: std_logic;
begin
if (clk'event and clk='1')then
s:=r(0);
r:=s & r(3 downto 1);
end if;
q<= r;
end process;
end ring1;




103



q3
q
2
q2
clk q
1
q
0


TRUTH TABLE
Clk Q
3
Q
2
Q
1
Q
0

1
2
3
4
5
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1



Fig: Output waveform of Johnson Counter

johnson
104

11.2 JOHNSON COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity johnson is
port(clk:in std_logic;q:out std_logic_vector(3 downto 0));
end johnson;
architecture johnson of johnson is
begin
process(clk)
variable r:std_logic;
variable s:std_logic_vector(3 downto 0):="0000";
begin
if(clk'event and clk='1') then
r:=not s(0);
s:=r& s(3 downto 1);
end if;
q<=s;
end process;
end johnson;








105

Clk count


Clk Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111


Fig: Output waveform of Up- Counter

upcounter
106

11.3 UP-COUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity upcounter is
port(clk:in std_logic;count:out std_logic_vector(3 downto 0));
end upcounter;
architecture behavioural of upcounter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clk)
begin
if(clk'event and clk='1') then
temp<=temp+1;
end if;
end process;
count<=temp;
end behavioural;








107


clk Count


Clk Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000


Fig: Output waveform of Down Counter

downcounter
108

11.4 DOWN COUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity downcounter is
port(clk:in std_logic;count:out std_logic_vector(3 downto 0));
end downcounter;
architecture behavioural of downcounter is
signal temp:std_logic_vector(3 downto 0):="1111";
begin
process(clk)
begin
if(clk'event and clk='1') then
temp<=temp-1;
end if;
end process;
count<=temp;
end behavioural;








109


clk Count


clk Q
3
Q
2
Q
1
Q
0
1
2
3
4
5
6
7
8
9

0000
0001
0010
0011
0100
0101
0110
0111
1000



Fig: Output waveform of Decade Counter

decadecounter
110

11.5 DECADE COUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decadecounter is
port(clk:in std_logic;count:out std_logic_vector(3 downto 0));
end decadecounter;
architecture decadecounter of decadecounter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clk)
begin
if(clk'event and clk='1') then
temp<=temp+1;
if(temp="1001" )then
temp<="0000";
end if;
end if;
end process;
count<=temp;
end decadecounter;





111



tb_ring
ring1

r s






Fig: Output waveform of Test bench (Ring Counter)

Clk Count
112

11.6TEST BENCH (RING COUNTER)
library ieee;
use ieee.std_logic_1164.all;
entity tb_ring is end;
architecture tb_ring of tb_ring is
signal r:std_logic;
signal s:std_logic_vector(3 downto 0);
component ring
port(clk:in std_logic;q:inout std_logic_vector(3 downto 0));
end component;
begin
a1:ring port map(r,s);
r<='1','0'after 100ns,'1' after 200ns,'0' after 300ns,'1' after 400ns,'0' after 500ns,'1' after
600ns,'0' after 700ns,'1' after 800ns;
end tb_ring;








113




TRUTH TABLE









Fig: Output waveform of Up-Counter
clk q(0) q(1) q(2) q(3)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
clk q(0) q(1) q(2) q(3)
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
114

12 ASYNCHRONOUS COUNTER

Aim: To write program on Asynchronous Counter
i. Up counter
ii. Down counter

12.1 UP-COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity a_upcounter is
port(clk,rst:in std_logic;q:inout std_logic_vector(3 downto 0));
end a_upcounter;
architecture a_upcounter of a_upcounter is
component tff
port(t,clk,rst:in std_logic;q,qbar:inout std_logic);
end component;
signal qbar:std_logic_vector(3 downto 0);
begin
s1:tff port map('1',clk,rst,q(0),qbar(0));
s2:tff port map('1',qbar(0),rst,q(1),qbar(1));
s3:tff port map('1',qbar(1),rst,q(2),qbar(2));
s4:tff port map('1',qbar(2),rst,q(3),qbar(3));
end a_upcounter;




115


TRUTH TABLE









Fig: Output waveform of Down counter


clk q(0) q(1) q(2) q(3)
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
clk q(0) q(1) q(2) q(3)
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
116

12.2 DOWN COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity a_downcounter is
port(clk,rst:in std_logic;q:inout std_logic_vector(3 downto 0));
end a_downcounter;
architecture a_downcounter of a_downcounter is
component jkff
port(j,k,clk,rst:in std_logic;q,qb:out std_logic);
end component;
begin
q1:jkff port map('1','1',clk,rst,q(0),open);
q2:jkff port map('1','1',q(0),rst,q(1),open);
q3:jkff port map('1','1',q(1),rst,q(2),open);
q4:jkff port map('1','1',q(2),rst,q(3),open);
end a_downcounter;










117



q1 q2
clk
Count_up/count_down
TRUTH TABLE count_up=1 count_down=1


Fig::Output waveform of Up-Down Counter
clk q2(0) q2(1) q2(2) q2(3)
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0
clk q1(0) q1(1) q1(2) q1(3)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

a_upcounter


a_downcounter

118

13 UP- DOWN COUNTER

Aim: To design asynchronous and synchronous up-down counters.

13.1 ASYNCHRONOUS UP- DOWN COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity a_updowncounter is
port(clk,rst,count_up,count_down:in std_logic;q:inout std_logic_vector(3 downto 0));
end a_updowncounter;
architecture a_updowncounter of a_updowncounter is
component jkff
port(j,k,clk,rst:in std_logic;q,qb:inout std_logic);
end component;
component and2gate
port (q,r:in std_logic;s:out std_logic);
end component;
component or2gate
port (q,r:in std_logic;s:out std_logic);
end component;
signal qbar:std_logic_vector(3 downto 0);
signal t:std_logic_vector(8 downto 0);
begin
f1:jkff port map('1','1',clk,rst,q(0),qbar(0));
a1:and2gate port map(count_up,q(0),t(0));
a2:and2gate port map(count_down,qbar(0),t(1));

119





























120


o1:or2gate port map(t(0),t(1),t(2));
f2:jkff port map('1','1',t(2),rst,q(1),qbar(1));
a3:and2gate port map(count_up,q(1),t(3));
a4:and2gate port map(count_down,qbar(1),t(4));
o2:or2gate port map(t(3),t(4),t(5));
f3:jkff port map('1','1',t(5),rst,q(2),qbar(2));
a5:and2gate port map(count_up,q(2),t(6));
a6:and2gate port map(count_down,qbar(2),t(7));
o3:or2gate port map(t(6),t(7),t(8));
f4:jkff port map('1','1',t(8),rst,q(3),qbar(3));
end a_updowncounter;















121


clk Count
drn

Clk drn Count Clk drn Count
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000


Fig: Output waveform of synchronous Up-Down Counter

updowncounter
122

13.2 SYNCHRONOUS UP-DOWN COUNTER
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity updowncounter is
port(clk:in std_logic;drn: in std_logic;count:out std_logic_vector(3 downto 0));
end updowncounter;
architecture behavioural of updowncounter is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clk,drn)
begin
if(clk'event and clk='1') then
if drn='1' then
temp<=temp+1;
else
temp<=temp-1;
end if;
end if;
end process;
count<=temp;
end behavioural;




123






clk SIPO
din q[3:0]




Fig: output waveform of sipo




SIPO
124

14 SHIFT REGISTERS

Aim: To design various shift registers.

14.1SERIAL IN PARALLEL OUT SHIFT REGISTER
library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(din, clk: in bit;
dout: out bit_vector(0 to 3));
end sipo;
architecture sipo of sipo is
variable a:bit_vector (0 to 3);
variable b:bit;
begin
process(din,clk)
begin
if (clkevent and clk=1) then
b:=din;
a:=b&a(0 to 3);
endif;
dout<=a;
end process;
end sipo;


125


clk PISO
dout
d[3:0]







Fig:output waveform of piso shift register





PISO
126

14.2 PARALLEL IN SERIAL OUT SHIFT REGISTER
Library ieee;
Use ieee.std_logic_1164.all;
Entity piso is
Port(clk,din:in bit;d:in bit_vector( 3 downto 0) ;dout:out bit);
End piso;
Architecture a_piso of piso is
signal a:integer:= 3;
signal b:bit_vector(0 to 3);
begin
process(din,clk)
begin
If (clk'event and clk='1') then
dout<=b(a);
a<=a-1;
end if;
end process;
End a_piso;









127




clk PIPO
dout[3:0]
din[0:3]

CIRCUIT DIAGRAM





Fig: output waveform of PIPO register





PIPO
128

14.3 PARALLEL IN PARALLEL OUT SHIFT REGISTER
Library ieee;
Use ieee.std_logic_1164.all;
Entity pipo is
Port(clk:in bit;din:in bit_vector (0 to 3);dout:out bit_vector(0 to 3));
end pipo;
architecture a_pipo of pipo is
begin
Process(din,clk)
begin
If (clk'event and clk='1') then
Dout<=din;
End if;
End process;
End a_pipo;












129







Fig: output waveform of left shift siso register




130

14.4 LEFT SHIFT SERIAL IN SERIAL OUT SHIFT REGISTER
library ieee;
Use ieee.std_logic_1164.all;
entity l_siso is
Port(d,clk:in bit;dout:out bit);
End l_siso;
architecture a_siso of l_siso is
begin
Process(d,clk)
Variable a:bit_vector(3 downto 0);
Variable b:bit;
begin
If (clk'event and clk='1') then
b:=d;
a:=a(2 downto 0) & b;
end if;
Dout<=a(3);
end process;
End a_siso;









131







Fig: output waveform of right shift siso




132


14.5 RIGHT SHIFTSERIAL IN SERIAL OUT SHIFT REGISTER
library ieee;
Use ieee.std_logic_1164.all;
entity r_siso is
Port(d,clk:in bit;dout:out bit);
End r_siso;
architecture a_siso of r_siso is
begin
Process(d,clk)
Variable a:bit_vector(0 to 3);
Variable b:bit;
begin
If (clk'event and clk='1') then
b:=d;
a:=b & a(0 to 2);
end if;
Dout<=a(3);
end process;
End a_siso;







133




Fig :output waveform of siso left testbench




134

14.6 TEST BENCH OF SISO-LEFT
library ieee;
use ieee.std_logic_1164.all;
entity t_lsiso is end;
architecture t_lsiso of t_lsiso is
component lsiso is
Port(d,clk:in bit;dout:out bit);
end component;
signal s1,s2,s3: bit;
begin
a1:l_siso port map(s1,s2,s3);
s1<='1';
s2<='1' after 100ns,'0' after 200ns,'1' after 300ns,'0' after 400ns, '1' after 500ns,'0' after
600ns, '1' after 700ns,'0' after 800ns;
end t_lsiso;











135

Q[3:0] BARREL-SHIFTER
R[1:0] S[3:0]


TRUTH TABLE

R1 R0 Q3 Q2 Q1 Q0 S3 S2 S1 S0
0 0 0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0 1 0
1 0 0 1 0 1 0 1 0 1
1 1 0 1 0 1 1 0 1 0




Fig :output waveform of barrel shifter






BARREL-SHIFTER
136

15. BARREL SHIFTER

Aim: To design a barrel shifter .

PROGRAM
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
port(q:in bit_vector(3 downto 0); r:in bit_vector(1 downto 0);s:out bit_vector(3 downto 0));
end barrel_shifter;
architecture barrel_shifter of barrel_shifter is
begin
process(q,r)
begin
case r is
when "00"=> s<=q;
when "01"=> s(3)<=q(0);
s(2 downto 0)<=q(3 downto 1);
when "10"=> s(3 downto 2)<=q(1 downto 0);
s(1 downto 0)<=q(3 downto 2);
when "11"=> s(3 downto 1)<=q(2 downto 0);
s(0)<=q(3);
when others=> s<=q;
end case;
end process;
end barrel_shifter;

137





STATE DIAGRAM




138

16.TRAFFIC LIGHT CONTOL USING FSM

Aim:To design a traffic light controller using FSM and implement using VHDL.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity traffic is
port (clk: in std_logic;
clr: in std_logic;
q: out std_logic_vector(5 downto 0));
end traffic;

architecture traffic of traffic is
type state_type is (s0, s1, s2, s3, s4, s5);
signal state: state_type;
signal count: std_logic_vector(3 downto 0);
constant SEC5: std_logic_vector(3 downto 0) := "1111";
constant SEC1: std_logic_vector(3 downto 0) := "0011";
begin
process(clk, clr)
begin
if clr = '1' then


139


Fig:Six colored LEDs can represent a set of traffic lights

State North-South East-West Delay(Sec.)
0 Green Red 5
1 Yellow Red 1
2 Red Red 1
3 Red Green 5
4 Red Yellow 1
5 Red Red 1

Table 1 Traffic Light States







140

state <= s0;
count <= X"0";
elsif clk'event and clk = '1' then
case state is
when s0 =>
if count < SEC5 then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= X"0";
end if;
when s1 =>
if count < SEC1 then
state <= s1;
count <= count + 1;
else
state <= s2;
count <= X"0";
end if;
when s2 =>
if count < SEC1 then
state <= s3;
count <= count + 1;
else
state <= s3;
count <= X"0";

141

SIMULATION RESULT










142

end if;
when s3 =>
if count < SEC5 then
state <= s3;
count <= count + 1;
else
state <= s4;
count <= X"0";
end if;
when s4 =>
if count < SEC1 then
state <= s4;
count <= count + 1;
else
state <= s5;
count <= X"0";
end if;
when s5 =>
if count < SEC1 then
state <= s5;
count <= count + 1;
else
state <= s0;
count <= X"0";
end if;
when others =>
state <= s0;
143






















144

end case;
end if;
end process;
C2: process(state)
begin
case state is
when s0 => q <= "100001";
when s1 =>q <= "100010";
when s2 =>q <= "100100";
when s3 => q <= "001100";
when s4 => q <= "010100";
when s5 => q <= "100100";
when others =>q <= "100001";
end case;
end process;
end traffic;












145



CLK PATTERNDETECTOR
Q S

STATE DIAGRAM



Fig: output waveform of pattern recognizer





MEALY
146

17 PATTERN RECOGNIZER

Aim:To design a pattern recognizer using FSM and implement using VHDL.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;

entity patterndetector is
port (clk,q:in bit;
s:out bit);
end patterndetector; -- detect a 0110 sequence

architecture mealy of patterndetector is
type states is (t1,t2,t3,t4,t5);
signal state: states := t1; -- initial value is a
signal next_state: states := t1; -- initial value
begin
clock: process(clk)
begin
if clk'event and clk = '1' then
state <= next_state;
end if;
end process clock;



147





























148

state_trans: process(state,q) --reacts to changes in state and x
begin
next_state <= state; --update next state
case state is
when t1 => if q = '0' then
s <= '0';
next_state <=t2;
else
next_state <= t1;
s <= '0';
end if;
when t2 => if q = '1' then
next_state <= t3;
s <= '0';
else
s <= '0';
next_state <= t2;
end if;
when t3 => if q = '1' then
next_state <= t4;
s <= '0';
else
next_state <= t2;
s <= '0';
end if;
when t4 => if q = '0' then
next_state <= t5;

149





























150

s <= '0';
else
next_state <= t1;
s <= '0';
end if;
when t5 => if q = '0' then
next_state <= t2;
s <= '1';
else
next_state <= t1;
s <= '1';
end if;
end case;
end process state_trans;
end mealy;












151
























152


MINI
PROJECTS







153






Fig1:Serial data transmission using UART



Fig2:Timing diagram of UART message




154

18.UART TRANSMITTER

ABSTRACT
A UART is a Universal Asynchronous Receiver Transmitter device utilizing RS232
serial protocol. It is used in all personal computers to provide an interface between the CPU and
the external devices through a serial port. A UART consists of a transmitter partition and
receiver partition. In this project,a simple UART design is considered with no personality
registers,no parity and no error detection logic.A commercial UART includes a set of
programmable registers to characterize the device environment and error reporting features. The
environment includes baud rate,number of stop bits and insertion of parity. The error reporting
features include framing error(message with no STOP bit),overrun error(UART receives a new
message prior to the CPU reading the old message) and parity error.

OPERATION OF UART TRANSMITTER
A CPU loads an eight bit word into a UART. The UART frames the word with a
START bit ( a logical 0) at the beginning and a STOP bit (a logical 1) at the end of the word. It
sends the framing information along with data in a serial manner from Least Significant data Bit
(LSB) to the Most Significant Bit(MSB).
Timing diagram of UART message
In the example shown(fig 2),CPU loads a value 54(hex) to the transmitter.TxDataT
represents the CPU parallel data,and Shift_Ldf is the synchronous load,active low pulse to
UART. As soon as data is loaded,UART asserts TxSerial_Out signal START bit ,followed by 8
bit data from LSB to MSB,followed by STOP bit.Here the data 0101_0100 in binary is sent as
0_0010_1010_1 when START and STOP bits are considered. The transmit UART deasserts a
transmitter empty (XmitMT) signal when data is sent.This flags the CPU that it cannot receive
another character.When all bits are sent,it reasserts the XmitMT signal so that at the next cycle a
new data can be loaded.

BLOCK DIAGRAM DESCRIPTION OF UART TRANSMITTER
Fig 3 represents an architecture for a simple UART transmitter.It consists of a 10-bit
transmit register that gets loaded with either a STOP bit concatenated with the 8-bit transmit
data concatenated with the START bit during normal load cycle, or with a 10-bit value of all
155



Fig3:Block diagram of UART transmitter











156

ones during a reset cycle.A state machine is used to control the data paths ,and to identify the
state of the transmit register ,empty or in use.
PROGRAM
library ieee;
use ieee.std_logic_1164.all;
entity uart is
port(shift_ldf:in bit; clkenbt:in bit; clk: in bit; datat : in bit_vector(7 downto 0); resetf:in bit;
Serial_out:out bit; xmitmt:out boolean);
end uart;
architecture uart of uart is
subtype Int0to9_typ is integer range 0 to 9;
signal xmit_r:bit_vector(9 downto 0); --transmit register
signal count_r:Int0to9_typ; -- # of serial bits sent
begin
-----------------------------------------------------------------------------------------------------
-- Purpose: Models the transmit register of a UART
-- Operation is as follows
--All operations occur on rising edge of clk
--If reset =0 then xmit_r is reset to 1111111111, count_r is reset to 0
--If clkenbt=1 and shift_ldf=0 and resetf=1 then 1 & datat & 0 get loaded in
-- to xmit_r
--If clkenbt=1 and shift_ldf=1 and resetf=1 then 1 & xmit_r(9 downto 0) get loaded --
into xmit_r
--(shift right with a 1 shifted in)
--count_r is incremented to no more than 10
--(i.e. if it is 9 ,then it stays at 9)
----------------------------------------------------------------------------------------------------------
Process
begin
157



SIMULATION RESULT

















158


wait until clk'event and clk='1'; --rising edge of clock
if resetf='0' then
xmit_r<="1111111111";
count_r<=9;

elsif clkenbt='1'and shift_ldf='0' and resetf='1' then
xmit_r<='1' & datat &'0';
count_r<=0;

elsif clkenbt='1'and shift_ldf='1' and resetf='1' then
xmit_r<='1' & xmit_r(9 downto 1);

if count_r/= 9 then
count_r<=count_r + 1;
end if;
end if;
end process;
Serial_out < =xmit_r(0);
Xmitmt < = true when count_r =9
else false;
end uart;

CONCLUSION
A UART is essential for the serial data transmission. In this mini project a simple code
for UART transmitter is written using VHDL and simulated using ModelSim.

159






BLOCK DIAGRAM








160

19. ARITHMETIC AND LOGIC UNIT

ABSTRACT
As name says ,it is a circuit capable of executing both kind of operations, arithmetic & logical.
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and
arithmetic micro-operations on a pair of n-bit operands (eg. A[7:0] and B[7:0]). The operations
performed by an ALU are controlled by a set of function-select inputs.The mode input selects
between a Logic and Arithmetic operation.
BLOCK DIAGRAM EXPLANATION
Here ALU is split into two modules, one Logic and one Arithmetic module. Designing
each module separately will be easier than designing a bit-slice as one unit.It consists of three
modules: 2:1 MUX, a Logic unit and an Arithmetic unit.The output(arithmetic or logical) is
selected by the MSB of sel, while the specific operation is selected by sels other 3 bits.
PROGRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port(a,b:in std_logic_vector(7 downto 0);sel:in std_logic_vector(3 downto 0);cin:in
std_logic;y:out std_logic_vector(7 downto 0);
end alu;
architecture dataflow of alu is
signal arith,logic:std_logic_vector(7 downto 0);
begin


161

TRUTHTABLE SHOWING OPERATION OF ALU












162

--------arithmetic unit----------
With sel (2 downto 0) select
arith<=a when 000,
a+1 when 001,
a-1 when 010,
b when 011,
b+1 when 100,
b-1 when 101,
a+b when 110,
a+b+cin when others;
--------logic unit----------
With sel (2 downto 0) select
logic<=NOT a when 000,
NOT b when 001,
a AND b when 010,
a OR b when 011,
a NAND b when 100,
a NOR b when 101,
a xor b when 110,
not(a xor b) when others
------mux--------




163


SIMULATION RESULTS












164

CONCLUSION
Here an 8 bit ALU is implemented and the output is verified. It can perform eight
arithmetic operations and eight logical operations.





















165






BLOCK DIAGRAM


R/W OUTPUT
Din



EXCITATION TABLE

R/W DATA-IN CURRENT
STATE
NEXT
STATE
OUTPUT LATCH
S R
0 0 0 0 0 0 X
0 0 1 0 0 0 1
0 1 0 1 1 1 0
0 1 1 1 1 x 0
1 0 0 0 0 0 X
1 0 1 1 1 X 0
1 1 0 0 0 0 X
1 1 1 1 1 X 0


SRAM
166

20.STATIC RAM

ABSTRACT
Memory can be of two types: ROM and RAM.ROM stands for READ ONLY
MEMORY. We can perform only write operation in ROM RAM stands for RANDOM ACESS
MEMORY.We can perform both write operation and raed operation in RAM.RAM can be of
many types.SRAM is one method of realizing RAM.SRAM stands for static RAM.It consists of
two cross coupled inverters with output of first inverter being connected to input of next.
This project propose a way to realize SRAM using VHDL.The design incorporates two
inputs and one output.One input is used to give inputs and other one is used to select whether
read or write has to done.

OPERATION
A simple memory cell has being designed using an SR latch,but we could have used any
other latches,such as a D-latch.The cell has tri-state output.If select line(sel) is low,the output of
cell is in high impedence.A Read/Write(R/w) input signal controls the cells cycle mode.If R/W
is high ,the cell is in write cycle.Table1 shows the excitation table of the cell,with
inputs(select,r/w,Data-in,current state ) and the corresponding outputs (next-state,output).From
the current state and next state we determine S and R of the latch. For example,if the current state
is 0 and next state 0,then two combinations of SR latch can generate this transition:s=0,R=0 and
s=0,R=1;so SR=OX ,where x is dont care.

STEPS IN IMPLEMENTING SRAM
1. Develop excitatation table for circuit based on required function.
2. Obtain reduced Boolean expressions based on k-map reduction.
3. Implement the function using basic gates and sr flip flop.
4. Writethe VHDL code for SRAM



167



CIRCUIT DIAGRAM







168


PROGRAM
library ieee;
use ieee.std_logic_1164.all;
entity memory is
port(sel,rw,din:in std_logic;output:out std_logic);
end memory;
architecture ram of memory is
component and3gate
port(i,j,k:in std_logic;l:out std_logic);
end component;
component or2gate
port(a,b:in std_logic;c:out std_logic);
end component;
component not1gate is
port(a:in std_logic;b:out std_logic)
end component;
component sr2 is
port(s,r:in std_logic;q,qbar :inout std_logic );
end component;
signal s1,s2,s3,s4,s5,s7:std_logic;
begin
n1 : not1gate port map(din,s1);
n2 : not1gate port map(rw,s2);
a1 : and3gate port map(s1,s2,sel,s4);
a2 : and3gate port map(din,s2,sel,s3);
169

K-MAP SIMPLIFICATION
DIN/Q
SEL/RW
00 01 11 10
00 Z Z Z Z
01 Z Z Z Z
11 0 1 1 0
10 0 0 1 1
S = Sel RW Din

DIN/Q
SEL/R
W
0
0
0
1
1
1
1
0
00 0 0 0 0
01 0 0 0 0
11 X 0 0 X
10 X 1 0 0
R = Sel RW Din

DIN/Q
SEL/RW
00 01 11 10
00 0 0 0 0
01 0 0 0 0
11 0 X X 0
10 0 0 X 1
OUTPUT = Sel RW Din + Sel RW = R + Sel RW0 ( for sel = 1)
170

ff : sr2 port map (s3,s4,s5,open);
a3 : and3gate port map(rw,sel,s5,s7);
o1 : or2gate port map(s3,s7,output);
end ram;




















171

SIMULATION RESULT

















172


CONCLUSION
An SRAM module was developed using VHDL.It can perform read and wrire
operations.A single signal R/W is used to select between read and write operations.

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