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This paper discusses design trade-offs for mixed-signal radio frequency integrated circuit (RF IC) transceivers for wireless applications
in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise,
adjacent interfering users, image signals, and multi-path fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit
non-linearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design
trade-offs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching
noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined.
Methods to minimize mixed-signal noise coupling and to model substrate noise effects are presented.
1. Introduction
(S/N )I 1 NO
F = = , (9)
(S/N )O G NI Figure 8. Noise figure for cascade of devices.
• Image spur. The image spur (fI ) occurs one IF fre- An important consideration in the design of receiver RF
quency away from the LO frequency in the opposite di- circuitry is the noise introduced by electronic (active and
rection from the RF frequency and is applied at the RF passive) components. Device noise is particularly impor-
input of the mixer as an undesired signal (figure 11). tant in the design of voltage-controlled oscillators where it
Protection from the image can be provided by selec- contributes to noise in the oscillator phase response which
tivity ahead of the mixer. For example, for low IF at sensitizes the receiver to interferers as will be seen in sec-
455 kHz, the image is at 910 kHz from the desired input tion 3.6. Moreover, in amplifiers and mixers, device noise
signal. For this reason 4 poles of crystal selectivity are must be considered in designing for acceptable noise figure.
typically required ahead of the second mixer. The level of noise generated by device noise mechanisms
• Half-IF. The half-IF spur (fHIF ) occurs at a frequency such as thermal noise, 1/f noise, and shot noise represents
of 1/2 the IF frequency from the RF frequency towards a minimum level of noise in a system and its control is
the injection frequency. For low side injection accomplished through optimal circuit design, topology se-
lection, bandwidth limiting of signals, and semiconductor
fHIF = fLO + fIF /2. (23) process control.
The most significant contributor to device noise is ther-
Spurs are characterized by their order typically written
mal noise (also called Johnson noise) due to the Brownian
as order (m, n) where m is the harmonic of the incoming
motion of charges in resistors. This random thermal motion
spurious signal and n is the harmonic of the local os-
can be represented as lattice vibrations within the material
cillator required to produce a signal at the IF frequency.
which result in a random disruption of current flow. The
In the case of the half-IF spur of order (2, 2),
mean-square thermal noise voltage generated by a resistor
2fHIF − 2xfLO = fIF , (24) is
fHIF = fLO + fIF /2. (25) e2n = 4kT R∆f , (28)
The half-IF spur is even more difficult to protect against where en represents the rms noise voltage developed across
than the image spur because it is located only half an the resistor of value R over the (brickwall) bandwidth ∆f
IF from the desired RF frequency. In order to minimize at absolute temperature T , a 1 MOhm resistor generates
48 S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers
Figure 14. Noise coupling from the noisy digital portion of the IC to the
4. Mixed-signal noise coupling sensitive RF/analog portion via substrate and supply lines.
The received RF signal can range from 20 dBm to Substrate coupling is a key problem both in purely ana-
−120 dBm; i.e., the incoming signal can be as low as log circuits and in mixed-signal circuits. Although the
0.22 µV at 1.8–2 GHz. Any internal on-chip noise can mechanism of coupling in the substrate is identical in both
corrupt the desired signal. The main source of on-chip cases, the effect of the parasitic crosstalk tends to be slightly
noise in mixed-signal ICs is digital switching noise. In different in these two classes of circuits. In purely analog
purely digital applications, CMOS static logic offers several circuits, the substrate acts as a signal feedback path which
attractive features including zero static power dissipation, can lead to changes in small signal performance functions
high packing densities, wide noise margins, high operating like amplifier gain and bandwidth. Additionally, impact
frequencies, etc. For high-frequency wireless applications, ionization can cause currents to be injected into the sub-
however, its major drawback is the generation of a large strate even under DC operating conditions, causing sub-
amount of digital switching noise [1,2,7,12,15,29,31–34]. strate biases to vary, which in turn cause variations in MOS
When many static gates change states, a large cumulative threshold voltages, depletion capacitances and other circuit
current spike flows through parasitic resistances and induc- bias and performance quantities. In mixed-signal circuits,
tances creating power supply noise voltage spikes known in addition to impact ionization-generated substrate cur-
as ‘Vdd bounce’ or ‘Gnd bounce’. Some fraction of this rents, significant substrate currents are generated as a re-
noise inevitably propagates, as shown in figure 14, to the sult of digital switching nodes capacitively connected to
sensitive analog circuitry through the substrate, power sup- the substrate through both interconnect and device junction
ply lines, bonding wires, package pins, etc., where it often (depletion) capacitances. The switching noise injected into
limits the achievable accuracy. The switching noise cur- the substrate is picked up by sensitive analog devices on
rent can range from 0.1 mA to several mA per CMOS gate the same substrate, through both their junction capacitances
depending on the device sizes. to substrate and through the MOS device body effect. This
results in induced spikes of noise in both device currents
4.1. Substrate coupling and node voltages [33].
One of the key problem areas in integrating a receiver (or 4.2. Mixed-signal design considerations
transceiver) onto a single chip is the common silicon sub-
strate. Transistors fabricated on the same die interact with Designers frequently rely on heuristic guidelines to im-
each other through the common conductive substrate lead- munize their designs from substrate crosstalk. These in-
ing to a phenomenon referred to as “substrate coupling”. clude noise prevention techniques to minimize generation
This parasitic crosstalk can cause otherwise normal designs of switching noise and noise reduction techniques using
to malfunction. With increasing demands on both the fre- layout isolation and noise tolerant circuit design techniques
quency of operation and the analog resolution of integrated for sensitive analog circuitry [33].
circuits, substrate coupling is becoming an increasingly im- Less noisy alternatives to static CMOS logic families
portant determinant of mixed analog/digital (mixed-signal) such as current steering logic (CSL) and folded source cou-
RF IC performance and behavior. pled logic (FSCL) that reduce switching currents in the
50 S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers
power supply [1,2] are used wherever possible, especially impact ionization, device/interconnect capacitance, pack-
at higher frequencies. In many transceiver systems, the syn- age/bondwire inductance and substrate resistance (and ca-
thesizer is designed using Bi-CMOS technology where the pacitance).
highspeed dividers and scalers are implemented with ECL
(emitter coupled logic) topologies and at lower frequen- 5.1. Impact ionization
cies standard CMOS or CSL/FSCL components are used.
Clocks and buffered outputs are ramped or have their rise With increasing speeds of operation and decreasing tech-
times reduced to prevent excessive switching currents into nology feature sizes, impact ionization is becoming a pri-
the supplies and the substrate. Buffered outputs are skewed mary cause of substrate current injection in integrated cir-
to prevent them from switching simultaneously and instants cuits. When the electric field in the depleted drain end of
of analog sampling are timed away from primary switching a MOS transistor becomes large enough to cause impact
events [32]. Power buses are routed to minimize impedance ionization, electron-hole pairs are created causing a current
using multi-level gridded buses with regular on-chip (and flow to the substrate. The hot-electron induced substrate
on-board) capacitive decoupling to defuse current spikes. current can be expressed in semi-analytical form as [13]
Power buses are also tied to multiple power pads/package 1/3 1/2
C2 tox · xj
pins to minimize lead inductance. (Package/bondwire in- Isub = C1 (Vds − Vdsat )Id exp − , (32)
ductance is the subject of a following section.) Layout Vds − Vdsat
isolation techniques help reduce the severity of crosstalk where C1 and C2 are process-related, empirically deter-
on some substrates. Physical separation between noisy and mined parameters, tox is the oxide thickness and xj is the
quiet circuits, separate analog and digital power/substrate junction depth. Using results from device simulations or
supplies and diffused guard rings around a sensitive circuit measurements, it is possible to determine the empirical co-
are commonly employed layout strategies. efficients, C1 and C2 and to incorporate impact ionization
Noise tolerant analog circuits can also be employed to induced substrate currents into existing device models for
minimize the impact of coupled noise. By using fully circuit simulation.
differential analog circuitry as in doubly balanced mixers
and fully differential low noise amplifiers (LNA) with high 5.2. Device and interconnect capacitance
common-mode rejection ratio (CMRR) and power-supply
rejection ratio (PSRR), advantage can be taken of the fact Every transistor on an IC die is coupled capacitively
that the switching noise appears as common-mode and is to the substrate through its p–n junction depletion capaci-
easily rejected by the circuit. In employing differential tances. Moreover, every interconnect routed on an IC has
analog circuitry, care must be taken to ensure symmetric some capacitance to substrate. This capacitively coupled
layout so that the coupled noise appears as common-mode substrate current is of significant consequence in mixed-
between the differential device pairs. The unfortunate by- signal circuits, due to the presence both of a large number
product of using differential circuits is that the device noise
√ of switching digital nodes that inject current into the sub-
contribution of the circuit now increases by a factor of 2 strate and of high impedance analog nodes that are affected
on a rms basis. Typically however, additional device noise by this injected current. Since the amount of injected cur-
is easier to live with. rent is directly proportional to the slew rate of the switch-
Sophisticated processing techniques utilizing triple-wells ing voltage, at higher rates of circuit operation the sub-
and trench structures or bondedwafer Silicon on Insulator strate coupling problem is greatly aggravated. Moreover,
(SOI) processes may also be used to DC isolate devices with decreasing technology feature sizes, the interconnect
from one another. Such processes help isolate sensitive RF capacitances to substrate are becoming increasingly impor-
subsections from low frequency noise coupling from the tant contributors of injected current. In order to account
digital sections. The aforementioned methods provide a for capacitively coupled substrate currents, it is necessary
partial solution to minimizing on-chip noise coupling. to perform a parasitic capacitance extraction on the design
to determine all significant capacitances to substrate in the
circuit.
5. Modeling substrate coupling
5.3. Package/bondwire inductance
Without suitable analysis to predict substrate crosstalk
during the design process, the effectiveness of design guide- The effect of non-ideal (inductive) power supplies has
lines cannot be determined until a circuit is fabricated and a tremendous impact on the amount of substrate coupled
tested. Consequently, a basic understanding of the substrate switching noise in an IC design. Since the bondwires and
coupling problem and techniques to model it [1,7,29,31–33] package pins associated with the substrate supplies have
are assets to every RF integrated circuit designer. finite and often large inductances, any substrate current
Several mechanisms must be understood and suitably picked up by these supplies can cause large glitches in the
modeled in an electrical circuit in order to analyze it for value of the substrate supply bias. This phenomenon is
substrate coupling problems. These include the effects of referred to as inductive or Ldi/dt noise. The presence of
S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers 51
Figure 15. Methods for minimizing the coupling between the digital por-
tion of Transceiver and the sensitive Analog portion.
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nical Report (1993). Sayfe Kiaei, Ph.D., Washington State University, 1987. He was with
[10] G.C. Hess, Land Mobile Radio System Engineering (Artech House, Boeing Research and Technology Center at Renton, WA, during 1985–
Boston, 1993). 1986 and with Motorola Inc. Wireless Technology Center from 1993 to
[11] K.M.D. Hess and D.E. Fague, Performance evaluation of a single 1997. Dr. Kiaei has been with the Department of Electrical Engineering at
chip radio transceiver, in: Proc. IEEE VTS 46th Vehicular Technol- Oregon State University from 1987–1993 and 1996–present where he is an
ogy Conference, pp. 1048–1051. Associate Professor. His current research activities includes design of high
S. Kiaei et al. / Noise considerations for mixed-signal RF IC transceivers 53
performance IC’s for mixed-mode applications, wireless communication Symposium on Low-Power Electronics and Design, and the IEEE Inter-
systems, VLSI system design for digital signal processing, and design national Solid-State Circuits Conference. He is currently on the executive
of ASIC’s. He has authored several book chapters and over 30 papers committee of the IEEE International Solid-State Circuits Conference. He
in the fields of wireless communications, DSP, and Mixed-signal CMOS was a co-recipient of the 1980 IEEE W.R.G. Baker Award and the 1995
IC’s. Dr. Kiaei is a senior member of the IEEE, and was a member IEEE Circuits and Systems Society Darlington Award, and has received
of the editorial board of IEEE Transactions on Circuits and Systems II. excellence in teaching awards from SMU, OSU, and CMU. He is a mem-
He is the Technical Co-Chair of the International Symposium on Low- ber of Eta Kappa Nu and Sigma Xi and a fellow of IEEE.
Power Electronics and the member of the technical program committee of
a number of conferences. Dr. Kiaei is the recipient of the IEEE circuits and
systems society Darling best paper award in 1994, and was the recipient Ken Hansen. MS, University of Illinois, 1976. Principal Member of the
of the Loyd-Carter award for the best teacher in the college of engineering Technical Staff and Director of the Wireless Integration Technology Center
at Oregon State University. Dr. Kiaei is the associate director of the NSF for Radio Products Group of Motorola in Austin, TX. He has over 20 years
Center for the Design of Analog–Digital IC’s (CDADIC). of experience in RF circuits, bipolar, CMOS, and BiCMOS analog and
digital circuit design in the field of wireless communications. He holds 7
David J. Allstot received the B.S. degree in engineering science from patents in this area and is a member of IEEE.
the University of Portland, the M.S. degree in electrical and computer
engineering from Oregon State University, and the Ph.D. degree in elec-
trical engineering and computer Science from the University of California Nishath K. Verghese received the B.E. (Hons.) degree from Birla Insti-
(Berkeley) in 1979. His Ph.D. dealt with the analysis, design, and imple- tute of Technology and Science, Pilani, India, in 1990, and the M.S. and
mentation of switched-capacitor filters. He has held industrial positions Ph.D. degrees from Carnegie Mellon University, Pittsburgh, PA, in 1993
with Tektronix, Texas Instruments, and MOSTEK, and academic positions and 1995, respectively. From 1990 to 1991 he was with the VLSI Design
with UC Berkeley, Southern Methodist University, and Carnegie Mellon Laboratory at McGill University, Montreal, Canada, where he worked on
University. He is currently the Hewlett-Packard Professor of Electrical new circuit implementations of sigma–delta A/D converters and on es-
and Computer Engineering at Oregon State University. He has advised timation techniques for power bus current in CMOS logic circuits. At
about 50 M.S. and Ph.D. students and has published several papers and CMU, his research focussed on extraction and simulation techniques for
one book with colleagues. Dr. Allstot’s professional service has included: substrate-coupled noise in mixed-signal ICs. In 1994, he worked for five
Associate Editor and Editor of the IEEE Transactions on Circuits and Sys- months at the Mixed-Signal Design Department, Texas Instruments, Dal-
tems, Guest Editor of the IEEE Journal of Solid-State Circuits, member of las, applying these techniques to the design of a video A/D converter. He
the IEEE Circuits and Systems Society Board of Governors, and Techni- is currently a Member of Consulting Staff at Cadence Design Systems,
cal Program Committee member of the IEEE Custom IC Conference, the San Jose, CA. His research interests include design and verification of
IEEE International Symposium on Circuits and Systems, the International analog and mixed-signal circuits.