TCAD News
June 2007
Contents
4
TCAD Distortion Analysis Based on the
Harmonic Balance Method
5 Introduction
An Efficient Simulation Environment for
Modeling Single Event Effects with the
Sentaurus Tool Suite
6 (IC) failures are due to ESD [1]. Discharge
Impact of Gettering Effects in Solar Cells
7 IC chip pins with very high currents (up to
Simulation of 4H-SiC Vertical Junction FET
in Sentaurus Device
Latest Edition
Welcome to the latest issue of TCAD
News. Over the years, TCAD has proven to
be an enabling methodology for reducing
technology development costs and time.
The use of TCAD, however, extends beyond
nanoscale silicon CMOS devices. In this
issue, I am delighted to present articles
showing the wide application of TCAD
tools for modeling and analyzing physical
phenomena and effects beyond nanoscale
silicon CMOS devices.
As device features continue to scale down,
the threat of device or circuit failures caused
by reliability issues such as electrostatic
discharge (ESD) and single event effects
(SEEs) grows. For example, device engineers
face difficult challenges of designing robust
ESD protection and meeting the required
ESD levels in new designs. The first article
outlines a TCAD-driven ESD approach
that enables chipmakers to develop a
comprehensive methodology to analyze
and treat ESD-related problems. Another
reliability issue is SEE, which can cause
unwanted changes to semiconductor
devices when highly energetic particles
strike an IC chip. We include an article to
show an efficient way of modeling the effects
of single event upset on CMOS devices.
This edition also includes articles on specialty
devices. For readers interested in analog
RF devices, one article examines the use
of harmonic balance in Sentaurus Device
to analyze the distorting characteristics
of an SiGe BJT and Si NMOS RF device.
Recent progress in improving SiC material
with zero micropipe defects is pushing
SiC electronic devices for high-power and
high-temperature applications into the
mainstream. We include an article showing
the benefits of using TCAD to explore and
optimize an emerging technology such as
SiC. In addition, we highlight the impact of
gettering effects in solar cells.
I trust that you will enjoy this edition of TCAD
News. Please contact us for your comments
and feedback.
With best regards,
Terry Ma
Group Director, TCAD Business Unit
TCAD for Electrostatic Discharge
Electrostatic discharge (ESD) is a major threat
to the reliability of integrated circuits, where
approximately 20% of total integrated circuit
of charged objects or human discharge into
10 A) and short duration (1 ns to 200 ns)
causes serious damage to the very sensitive
devices of the circuitry. This happens during
manufacturing, assembly, shipment, and in the
field.
This article demonstrates the successful use
of TCAD for the simulation and investigation
of ESD-related problems, as well as for
the development and optimization of ESD
protection devices and methodologies with
respect to ESD robustness. The full range from
ESD calibration, ESD device simulation, to
ESD compact modeling for circuit simulation
is covered.
Background
The operational regime of devices under
ESD stress is far beyond the range of normal
operation conditions. Among the most
important effects to be considered within the
ESD regime are self-heating, conductivity
modulation due to high carrier injection,
nonuniform operation (current filamentation),
and avalanche breakdown at reverse-biased
junctions.
To characterize the device high-current
regime, mostly the transmission line pulsing
(TLP) technique is used [2]. This two-terminal
technique consists of feeding a constant
current pulse into the device under test (DUT)
and monitoring the voltage response. The
pulse has a typical duration of 100 ns with a
rise-time of 10 ns. The characterization using
TLP allows for obtaining device characteristics
up to very high current levels, while preventing
early destruction due to self-heating.
Within the device simulation environment,
TLP is used to calibrate high-current, high-
temperature regimes to measurements. For
the qualification and specification of ESD
robustness, other more realistic ESD stress
models are used. The most prominent one
is the human body model (HBM), which
reproduces the discharge of the body of a
human being. Additional models used are
the machine model (MM) and the charged
device model (CDM). Apart from the field of
application, they differ from the HBM due to a
different rise-time, peak current, duration, and
polarity [3].
In summary, the basic functionality of an ESD
protection device or circuit is to provide a
low-resistivity discharge-current path, which
prevents the internal circuitry as well as the
protection device/circuit itself from being
damaged during an ESD event. The ESD
protection functionality is ‘transparent’ to
the internal circuitry under normal operation
conditions. Figure 1 shows the most important
parameters of the so-called ESD design
window.
TCAD-Driven ESD Optimization
TCAD is a powerful tool for identifying and
investigating ESD-relevant effects, providing
I process and device simulation model set in
Trend for
1D and 2D. In a further step, ESD-related
Thinner Oxides
modeling shown in Figure 3 is addressed by:
VSUPPLY VBD
• High-temperature calibrated models: Impact
Latch-Up ionization and mobility (low-field, carrier-to-
Margin carrier scattering, high-field saturation)
Device Damage
Margin
• Bipolar-specific models: Recombination
and bandgap narrowing
Vh Vt1 V • Electrothermal effects: Self-heating
Figure 1. Typical ESD design window for mechanisms and heat flows
protection devices. • Information about layout and measurement
setup: Contact resistances and 3D layout
insights into the internal device behavior (such features
as temperature and current distributions, and
electric fields) under ESD stress conditions, 100
Self-heating
which are generally not accessible by (mobility, impact ionization)
1500
measurement. In particular, TCAD can be Snapback
used successfully for the study of 3D effects
Maximum Temperature [K]
10-1 (bipolar effect)
Drain Current [A]
arising from device layout or inhomogeneous
1000
current flow as shown in Figure 2. TCAD is
invaluable for modeling these complex ESD
10-2
effects [4][5], providing simulation results that Breakdown
complement expensive measurements and (impact ionization)
500
reducing expensive experiments on wafers. 10-3
0 10 20 30 40
From the device or TCAD engineering Drain Voltage [V]
perspective, establishing a full-fledged Figure 3. Physical effects considered for
ESD TCAD workbench from process and successful ESD modeling. The example shows
layout information, and from the calibration the high-current behavior of a power MOS device
of simulation models including the high obtained by simulation.
current/high temperature regime, allows the
evaluation of process variation influences, the Essential for correct device modeling and
determination of layout dependency, and the calibration is knowledge about the TLP tester
optimization of ESD structures. The improved rise-time, the pulse duration, and the voltage
understanding of the internal device failure extraction method used in measurements in
modes results in building better input/output order to implement the same conditions in
protection structures and the possibility simulation. The HBM tester–equivalent circuit
of virtual testing and development of new model must be known if HBM robustness is to
structures. TCAD also helps speed up ESD be simulated and compared to measurements.
design to keep pace with IC developments The mixed-mode simulation capability of
at reduced design-cycle times by reducing Sentaurus Device permits the integration
time-to-market and cost-to-market. of the HBM tester–equivalent circuit model
From the circuit or library design perspective, with the physical device model of the DUT
TCAD permits the development and in the simulation environment. A comparison
application of physically based SPICE of TLP versus HBM measurement/simulation
ESD compact models and parameter methodologies is shown in Figure 4.
extraction methodologies from simulation Methodology for ESD Device
and measurement. The SPICE ESD compact Calibration and Simulation
models allow for simple and fast use within
circuit and analog design, and for optimization The junction breakdown characteristics due
of protection configurations. The simulation- to impact ionization and tunneling should be
based methodology allows checking of critical already in good agreement with measurements
input/output protection configurations before at room temperature. Nevertheless, in some
IC tape-out and avoiding redesigns. cases, a fine-tuning of model parameters
may be necessary. The onset of breakdown
Requirements for ESD Modeling is influenced mainly by the doping profile
The starting point for a successful calibration (gradient), the bending of material interfaces
of the ESD characteristics of a device is a (for example, LOCOS bird’s beak), and the
well-calibrated, low-current and breakdown doping profile corner effects (3D).
Figure 2. Formation of
current filament leading
Abs(TotalCurrentDensity)
1.0e+06 to temperature hot-spot in
6.3e+04 a device during an ESD
4.0e+03
pulse using Sentaurus
2.5e+02
Device 3D device
1.6e+01
simulation.
1.0e-00
 TCAD News
Voltage Response
TLP Current
Increasing Current Level
70% of tp
Time
tr tp tf
Current
Voltage
Figure 4. TLP versus HBM measurement/simulation methodologies. TLP is more suitable for calibration
purposes due to controlled current condition. HBM tries to reproduce the discharge through the human
body and is used for ESD robustness assessment. Both methods have comparable pulse energies, and
their ESD failure levels show a clear correlation [2].
The temperature dependence of impact
ionization must be calibrated as well to obtain
the correct behavior at high temperatures.
Ideally, breakdown voltage measurements
at different temperatures are used for this
purpose.
For calibrating the snapback point (It1, Vt1),
the most important quantity is the effective
base resistance Rb of the bipolar device (or
the inherent parasitic bipolar device between
the drain, body, and source in the case of
MOS). Bipolar snapback is triggered after the
collector-base junction is driven into avalanche
breakdown (see Figure 5). As a result, in the
case of NPN, the impact-generated hole
current is conducted from the avalanche
region (G) through the p-region to the base
contacts. Consequently, the hole current
causes a voltage drop across the Rb, which
induces a forward bias to the base‑emitter
junction. Eventually, a sufficient base-emitter
current flow results in the triggering of the
NPN transistor. The positive feedback loop
formed by increasing impact ionization and
increasing forward bias of the base-emitter
junction produces the well-known voltage
snapback behavior with a negative differential
resistance (NDR) regime until a holding
voltage Vh is reached.
+
B E B C
e h
h G
e
Figure 5. Schematic cross section of NPN
transistor (or parasitic NPN transistor in MOS
case) showing carrier flow in snapback operation.
The calibration of the snapback current
level It1 may require some adjustment of the
parameters of the low-field mobility model
for low- and medium-range temperatures
because self-heating may play a role. If
evidence of inhomogeneous current flow is
found (inhomogeneous triggering [6]), it is
necessary to use 3D simulations to correctly
predict snapback behavior (see Example
of 3D ESD Simulation). In a later step, the
inhomogeneous triggering can be accounted
for in 2D simulations by adding an external
base resistance Rbext extracted from 3D
simulation. Rbext increases the total base
resistance and reproduces the effect of
current constriction in a physically correct
manner.
The snapback voltage Vt1 is, in general, more
difficult to control. It depends mainly on the
voltage drop across the portion of the device
between the location of the maximum impact
ionization and the base-collector (source-
drain) terminals.
The holding voltage Vh depends on the bipolar
transistor effective current gain and on the
impact ionization as a function of the internal
collector-base voltage and temperature.
Recombination lifetimes and the parameters
 TCAD News June 2007
HBM-equivalent Lumped Element Circuit
Cs
Ls
S1 S2
Rhbm
Vhbm
Chbm Ctb DUT
HBM Current
Double Exponential
Current Waveform
Time
of the bandgap narrowing model may need
to be adjusted in this case. Some influence
of high-field saturation (carrier velocity
saturation) may be seen as well.
A further increase of the collector (drain)
current leads to an increase of the device
voltage due to its on-resistance Ron = collector
or drain resistance. Usually, the holding region
after snapback in TLP measurements is not
very well resolved due to the small load-line
resistance (50 W) of the equipment. For the
calibration of Vh, such measurements may
be sufficient because of the low Ron (almost
vertical characteristics) after the holding point.
At the current levels, after holding point, self-
heating plays the predominant role. Therefore,
the definition of suitable thermal boundary
conditions for electrothermal simulation
is mandatory. The importance of these
conditions even increases if the temperature
hot-spot lies near the simulation boundary.
The temperature distribution may become
inhomogeneous in the third dimension as
well. In that case, 3D simulation is needed.
Similar to the case of the snapback point, this
situation can be considered in 2D by adding
an external series resistance extracted from
3D simulation.
For tuning Ron in this regime, besides the
temperature dependence of bulk mobility,
carrier–carrier scattering and high-field
saturation model parameters can be used. The
voltage drop across the series resistances of
the measurement setup and across the device
contacts are taken into account; otherwise,
this can lead to erroneous calibration. At the
point where the device becomes intrinsic (the
thermally generated carrier concentration
exceeds the doping concentration), the
so-called second breakdown or thermal
breakdown sets in. The device is damaged
irreversibly by the melting of silicon as a
result of the fast thermal runaway caused
by the positive feedback loop, consisting
of decreasing resistivity and increasing
temperature. The current level at which this
happens is called It2. By its nature, the second
breakdown is a 3D effect. The thermal runaway
instability occurs in a very confined region of
the device, drawing the total device current
into this region and causing the temperature
to exceed the melting temperature of silicon
locally. Analyzing the device after stressing
by physical failure analysis reveals the molten
filament, as shown in Figure 6.
The most simple and direct criterion for
simulating the second breakdown is given
by Tmax ≥ Tmelt. Using this criterion is
questionable because even the more
advanced simulation models are calibrated
to measurements only up to T = 1000 K, a
temperature that is much lower compared
to the melting temperature of silicon (Tmelt
= 1690 K). Nevertheless, an extrapolation
of the model into higher temperature ranges
should not lead to dramatic errors and, at
least, should preserve the trends. Other more
sophisticated methods for extracting It2 from
10-2
DCG = 1 µm
DCG = 2 µm
10-3 Holding Point
10-4
Nonsalicide blocked Snapback Point
10-5
Id [A]
10-6
10-7
10-8
Salicide blocked Drain 10-9
10-10
0 2 4 6
Vd [V]
Gate
DCG = 1 µm
Source 0.015
DCG = 2 µm
It2
Bulk
0.01 Ron
Id [A]
Figure 6. ESD failure signature: molten silicon
0.005 Holding Point
between drain and source contacts due to current
filaments.
0 2 4 6
Vd [V]
Figure 8. (Top) Snapback I–V characteristics
of 3D NMOS in logarithmic current scale and
simulation are found in literature [5][7][8]. They (bottom) linear current scale.
all try to avoid the use of high-temperature
device simulations because of expected lower leads to an inhomogeneous current flow. At
accuracy and convergence problems. the holding point, Id = 3 x 10–3 A, the current
In summary, the starting point is a well- flow is still inhomogeneous but starts to
calibrated simulation environment for normal homogenize. The current constriction during
operation conditions, and then models snapback cannot be modeled with 2D device
required for modeling ESD behavior are simulations. Therefore, 2D simulations would
added and calibrated step-by-step from lower predict too low a holding voltage because a
to higher current levels. In the end, the goal is larger effective device width is assumed.
to obtain one set of parameters that allow the Above the holding point, the current starts
predictive simulation of ESD behavior and, at to flow more and more homogeneously
the same time, that can be used for normal over the entire width of the device, and the
operation conditions. An accuracy of It1, Vt1, temperature starts to rise. The hot spot lies
Vh, and Ron compared to TLP measurements at the drain junction towards the gate, and
of 10% is reasonable. For It2 using the the temperature is higher in the middle of the
abovementioned method, 30% is feasible. device. This leads eventually to a destructive
Example of 3D ESD Simulation current filament in the middle of the device
when the temperature approaches the intrinsic
Electrothermal ESD simulations of a 3D temperature of silicon.
NMOS structure are presented to demonstrate
the capabilities of TCAD for ESD. Figure 7
Id = 3e-4 A Id = 3.4e-4 A Id = 3e-3 A
shows the structure of the NMOS simulated.
Only half of the device has been modeled to
save mesh points by taking advantage of the
symmetry plane in the middle of the device.
The gate length is 0.35 mm, and the entire
simulation area is 6.3 x 3.5 x 10 mm. The
Id = 1e-2 A Id = 1.4e-2 A Id = 1.5e-2 A
distance between the drain-contact and gate
has been varied as indicated.
DopingConcentration
3.1e+20 TotalCurrentDensity
9.8e+16 5.0e+06
3.1e+13 9.1e+05
1.7e+05
-2.6e+13
-8.3e+16
3.0e+04
5.5e+03
-2.7e+20
1.0e+03
DCG Id = 3e-4 A Id = 3.4e-4 A Id = 3e-3 A
Id = 1e-2 A Id = 1.4e-2 A Id = 1.5e-2 A
Figure 7. Three-dimensional NMOS structure
simulated; the DCG has been varied.
Figure 8 shows the typical snapback
LatticeTemperature
I–V characteristics during an ESD surge. The 1.3e+06
1.1e+05
structure with the smaller drain-contact to
9.0e+05
gate (DCG) spacing shows a lower resistivity 7.0e+04
5.0e+03
in the high-current regime as expected. The
3.0e+03
important ESD quantities, snapback point,
holding point, and Ron, are shown also Figure 9. Contour plots of total current density
in Figure 8. Even It2 can be identified by a (upper six graphics) and temperature (lower six
sudden increase of the voltage due to current graphics) at the drain current level indicated.
filament formation and the subsequent voltage
drop when the silicon becomes intrinsic.
Figure 9 shows contour plots of the total In the last few years,  the transient
current density and the temperature at six interferometric mapping (TIM) characterization
different current levels. technique from TU Vienna has proven to be
The first picture, at Id = 3 x 10–4 A, shows the invaluable in characterizing internal device
situation immediately before snapback. The behavior such as hot spots during high-
breakdown occurs at the drain-to-bulk junction current pulses [9].
towards the gate. The impact ionization is The quantity measured in a TIM measurement is
homogeneous along the junction, indicated by the phase shift of the laser probe beam. Only a
the homogeneous current density. The picture qualitative comparison of the measured phase
at Id = 3.4 x 10–4 A is taken immediately shift to simulation results (temperature, current
after snapback. The parasitic NPN transistor density) has been possible. To compare TIM
triggers first in the middle of the device, which measurements directly to simulation results,
 TCAD News
the tool Absorption and Phase shift Extraction
(APEX) was developed by Synopsys. APEX is
a postprocessor that extracts the phase shift
from Sentaurus Device results so that it can
be compared to the measured phase shift
directly. An advanced example showing the
use of APEX is available from SolvNet [10].
Compact Modeling for ESD
There is a great need to include ESD compact
models in circuit simulations to predict critical
current paths and critical (I,V) node values, and
to enhance input/output design quality [11].
The insight gained by TCAD permits developing
physically based compact model add-ons
for ESD. Internal device characteristics not
accessible by measurements can be studied.
Calibrated process and device simulation
allows parameter extraction for ESD compact
models. Expensive, noisy, and destructive
measurements can be avoided.
To keep the compact model development
effort to a reasonable level, a modular
modeling strategy is chosen. This strategy
is often referred to as macro-modeling or
subcircuit modeling in the literature [12]. The
standard model of the corresponding device
(for example, a Gummel–Poon or BSIM
model) has been retained for normal operation
conditions, and it has been extended by ESD-
specific add-on modules to form a full ESD
compact model.
The operational regime of devices under ESD
stress is beyond the range in which standard
compact models have been tested and verified;
whereas, the full ESD compact models allow
for reproducing behavior under ESD stress
in circuit simulation. Thermal effects are
included by establishing a feedback loop
between electric and thermal domains. The
thermal domain is modeled using first-order or
higher-order thermal RC networks, depending
on the complexity of the temperature fields of
the device (one or more highly localized hot
spots or almost homogeneous distribution).
Figure 10 shows how the ESD compact
models are set up.
ESD Compact Model Subcircuit (T dependent)
Including Parasitic Devices
Thermal RC Network
Standard Models
Electric Contacts
Pel
ESD Add-ons
T1, T2, ..., Tn
Figure 10. Modular setup of ESD compact models
including thermal network fed by dissipated
power Pel. The resulting temperatures T1…Tn
complete the feedback loop.
A dedicated methodology for the extraction of
ESD compact model parameters is developed,
based on TCAD results and measurements.
The calibrated ESD compact models can be
used within circuit simulations to determine
critical current paths, to identify endangered
devices, and to optimize protection circuitry.
Circuit simulations with up to ten ESD
protection devices and 100 standard devices
are feasible. The limitation arises from the
well-known convergence problems caused by
the strong nonlinear behavior of the protection
devices under ESD stress conditions and from
their interaction with the rest of the circuit.
The nonlinearities cannot be eliminated, but
they can be reduced to an acceptable level
by giving particular attention to numeric
issues. While nonlinear behavior (for example,
snapback devices) is one key issue to account
for in ESD simulations, it makes the numeric
treatment extremely unstable and computing
intensive. Nevertheless, the circuit complexity
extends simple input/output pad protection
configurations, including large parts of the
internal circuit. For the implementation of
the ESD add-on model equations, Verilog-A
behavioral modeling language can be used.
Verilog-A can be read by most common circuit
simulators such as HSPICE® and Spectre.
TCAD News June 2007
Figure 11 shows an example of a protection
NPN transistor ESD compact model.
Current- and temperature-dependent series
resistors account for conductivity modulation
effects and self-heating, and are modeled
externally. Thermal breakdown is modeled by
R_Tc, which switches irreversibly from a very
high to a very low Ohmic state at a critical
temperature. The modeling of avalanche
breakdown at the collector-base junction is
the key element for simulating the snapback
behavior. To eliminate the singularity at Vcb
= BVcbo in the original Miller [13] formulation
of the avalanche multiplication factor M, the
method reported in [4] is followed, with an
extension to account for weak avalanche
current contribution. The resulting function
is an approximation of the original M, but its
value is limited at Vcb = BVcbo and it shows a
significantly better convergence behavior.
Apart from the core transistor itself, the
parasitic PNP between the source, collector,
and base is included.
S
Parasitic T
Rs
C P→T Rc
T
Re
Avalanche
Source
Rb
B V_D2
R_Tc
Figure 11. Protection NPN transistor ESD
compact model: (red) standard models, (black)
ESD compact model add-ons, and (green)
coupling to thermal network.
The transient triggering behavior [14] is
influenced mainly by the junction capacitances
(displacement current triggering), which
cause a decreasing trigger voltage peak for
increasing stress current rise-times, as well as
by the base forward transit time (finite amount
of time required by the carriers to traverse the
base region leading to base-emitter diffusion
Rth1 Rth2 Rthn
Rthn+1
Cth1 Cth2 Cthn
capacitance), which reduces the triggering
Tamb speed. Capacitances and base transit time
as well as the current gain of the bipolar
transistors, which determines the holding
voltage Vh, are parameters belonging to the
standard compact model instances. Their
extraction is usually performed by simulations
or measurements under normal operation
conditions. Their values in the very diverse
ESD current regimes may differ considerably
compared to normal operation conditions.
Therefore, a readjustment of these parameters
may be necessary to obtain the correct
behavior under ESD stress conditions.
ESD Circuit Simulation
In Figure 12, the ESD compact models for
a protection NPN transistor and for two
protection diodes are used within an input pin
protection HBM circuit simulation.
For simplicity, the internal circuitry comprising
the first stages of the circuit is sketched
by a box only. The protection diode ESD
compact models include effects such as
voltage overshoot due to forward recovery
[15], reverse breakdown, and conductivity
modulation due to high injection. Applying
a positive HBM stress between the input
pin and ground leads to a main current flow
through D2 and the protection NPN, which
goes into snapback and, therefore, limits the
voltage at the VCC line. The voltage at the
input pin is given by the sum of the voltages
at VCC and the voltage drop across D2.
Due to voltage overshoot, the voltage drop
across D2 can exceed the stationary DC
voltage drop considerably. It is shown that
the transient voltage peak at the input pin is
V_input ∆V_input
VCC
C
Protection ESD Vce
Diode D2 Compact
Voltage [V]
V_D2 Model:
S
A Protection
Transistor
Input Internal
Circuitry
HBM 2.0 kV C
C B
Vce ∆Vh
Protection
Diode D1
S
Vinput
Rbext E
V_D2
A
10-10 10-9 10-8 10-7
Time [s]
Solid: Rbext = 0
Dashed: Rbext = 2.5 kΩ
∆t_trigger
Figure 12. Additional external base resistor Rbext increases the protection NPN triggering speed during
an HBM stress simulation. Consequently, the effect of the D2 voltage overshoot peak on the voltage at
the input node is reduced. Rbext also leads to a reduction of the holding voltage. Time axis is plotted in
logarithmic scale to show the details of the protection NPN transistor triggering.
Thermal Overload
Tc
Protection Transistor
VCC Temperature
E 1000
V_input
C
Protection ESD
Temperature [°C]
V_D2
Diode D2 Compact
Voltage [V]
Model:
S
Protection
A
Transistor
Input Internal
Circuitry
HBM 4.5 kV C Vce 500
Vce
C
Protection
B
S
Vinput Diode D1
Rbext E
A
0 1e-07 2e-07 3e-07
Time [s]
Transition into permanent low
Ohmic state (device damaged)
Figure 13. Increasing the HBM stress voltage to 4.5 kV leads to damage of the protection NPN
transistor. This is modeled by an abrupt and irreversible voltage drop at a predefined critical temperature
Tc. Time axis is plotted in linear scale.
reduced by increasing the triggering speed References
of the protection NPN using an external base [1] “Fundamentals of ESD, Part One–An Introduction to ESD,”
resistance. The external base resistance Electrostatic Discharge Association. Article available at <http://
www.esda.org/basics/part1.cfm>, May 2007.
decreases the amount of current needed to
[2] J. E. Barth et al., “TLP Calibration, Correlation, Standards, and
forward-bias the base-emitter junction and, New Techniques,” IEEE Transactions on Electronics Packaging
therefore, the snapback occurs earlier. If the Manufacturing, vol. 24, no. 2, pp. 99–108, 2001.
[3] G. Notermans, P. de Jong, and F. Kuper, “Pitfalls when correlating
HBM precharge voltage increases from 2 kV TLP, HBM and MM testing,” in Electrical Overstress/Electrostatic
to 4.5 kV, the protection NPN transistor is Discharge Symposium (EOS/ESD), pp. 170–176, 1998.
damaged by the second breakdown. In the [4] M. P. J. Mergens, On-Chip ESD Protection in Integrated Circuits:
Device Physics, Modeling, Circuit Simulation, Ph.D. thesis, ETH
circuit simulation shown in Figure 13, this Zurich, Switzerland, 2001.
happens as soon as the protection NPN [5] K. Esmark, H. Gossner, and W. Stadler, Advanced Simulation
temperature reaches a predefined critical Methods for ESD Protection Development, Amsterdam: Elsevier,
2003.
temperature Tc.
[6] C. Russ et al., “Non-Uniform Triggering of gg-nMOSt Investigated
by Combined Emission Microscopy and Transmission Line
Summary
Pulsing,” in Electrical Overstress/Electrostatic Discharge
ESD is a real threat to IC reliability; therefore,
Symposium (EOS/ESD), pp. 177–186, 1998.
[7] C. H. Díaz, S.-M. Kang, and C. Duvvury, “Simulation of Electrical
meeting ESD robustness specifications is Overstress Thermal Failures in Integrated Circuits,” IEEE
mandatory. Treating ESD-related problems Transactions on Electron Devices, vol. 41, no. 3, pp. 359–366,
1994.
is a challenging task. The use of TCAD
[8] C. Salaméro et al., “Accurate prediction of the ESD robustness
to simulate and investigate ESD-related of semiconductor devices through physical simulation,” in 43rd
problems enables robust and reliable design Annual International Reliability Physics Symposium, San Jose,
CA, USA, pp. 106–111, 2005.
of ESD protection devices/circuits, thereby [9] D. Pogany et al., “Quantitative Internal Thermal Energy Mapping
reducing IC development costs and cycle of Semiconductor Devices Under Short Current Stress Using
time. Backside Laser Interferometry,” IEEE Transactions on Electron
Devices, vol. 49, no. 11, pp. 2070–2079, 2002.
However, reliable modeling of devices and [10] “Simulation of Current Filament During Electrostatic Discharge
circuits under ESD stress conditions requires
Pulse (Z-2007.03),” available from SolvNet <https://solvnet.
synopsys.com/retrieve/020415.html>, May 2007.
specialized knowledge and broad experience. [11] V. Vassilev et al., “A CAD assisted design and optimisation
The TCAD-driven ESD methodology, which methodology for over-voltage ESD protection circuits,” in 15th
European Symposium on Reliability of Electron Devices, Failure
has been developed by the Synopsys Physics and Analysis (ESREF), Zurich, Switzerland, 2004.
Consulting and Engineering group and has [12] J. Li, S. Joshi, and E. Rosenbaum, “A Verilog-A Compact Model
been outlined in this article, has a proven for ESD Protection NMOSTs,” in Proceedings of the IEEE
Custom Integrated Circuits Conference, San Jose, CA, USA,
track record of success in helping customers pp. 253–256, September 2003.
meet their challenges of treating ESD-related [13] S. L. Miller, “Ionization Rates for Holes and Electrons in Silicon,”
problems. The two service offerings, TCAD Physical Review, vol. 105, no. 4, pp. 1246–1249, 1957.
[14] H. Wolf, H. Gieser, and W. Wilkening, “Analyzing the
ESD Workbench and ESD Compact Model Switching Behavior of ESD - Protection Transistors by Very Fast
Development, can be customized specifically Transmission Line Pulsing,” in Electrical Overstress/Electrostatic
Discharge Symposium (EOS/ESD), Orlando, FL, USA,
to protect your IC products from ESD pp. 28–37, September 1999.
damage. [15] K. J. Tseng, “Modelling of diode forward recovery characteristics
using a modified charge-control equation,” International Journal
Contact tcad_team@synopsys.com for more of Electronics, vol. 84, no. 5, pp. 437–444, 1998.
information on our ESD service offerings.

 TCAD News
TCAD Distortion Analysis Based on the Harmonic Balance Method
Introduction
The dynamic range of linearity is a critical
specification in most analog applications.
Even if the output signal changes almost
linearly with the input signal, intrinsic device
distortion effects are present, and higher
harmonics draw power from the fundamental
signal.
Besides small-signal and noise characteristics,
these distortion effects are the most important
properties in analog radio frequency (RF)
circuits such as power amplifiers, mixers, and
drivers. Although distortion is the fundamental
mechanism of mixers to generate signals at
various frequencies, it must be as low as
possible for most other applications.
Distortion characteristics are divided typically
into two groups:
• Harmonic distortion: A sinusoidal input
signal at frequency f (also called one-tone)
results in an output signal with spectral
components at f (first harmonic), 2f (second
harmonic), and 3f (third harmonic) (see
Figure 1 (left)). The extrapolated crossing
point of the first and third harmonics is
called the third-order interception point
(IP3) and is a typical metric to characterize
the linearity of a device or system (see
Figure 2).
• Intermodulation distortion: The input signal
comprises two sinusoidal signals with
fundamental frequencies f1 and f2 (also
called two-tone) with equal amplitudes.
The resulting, more complex, spectrum
of the output signal is shown in Figure 1
(right). The typical quantity to characterize
this situation is the extrapolated crossing
point of the fundamental signal at f1 with
the amplitude at 2f1-f2, which is called the
third-order intermodulation intercept point
(IIP3).
In most applications, the intercept points are
not reached due to saturating signals at high
input amplitudes. Nevertheless, the intercept
points serve as main figures of merit for
distortion.
Although distortion characteristics are
relatively easy to measure, little is known
about the physical origin at the device level. In
addition, most modeling activity has focused
on compact models, which inherently miss
the important physics behind distortion and
are often not scalable.
Harmonic Balance in Sentaurus Device
Conventional TCAD time-domain analysis
could, in principle, be used to analyze
distortion in semiconductor devices, but this
approach is often prohibitively expensive in
terms of computing resources:
• The applied input signals in distortion
experiments are sinusoids that may have
very narrowly spaced frequencies. This
requires a time integration over an enormous
number of periods of the input frequencies.
• The steady-state behavior of the system is
usually of primary interest. The presence
of filtering and matching circuitry around
the primary device can introduce extremely
long time constants. This results, again, in a
huge number of necessary time steps.
The harmonic balance module (HBM), the
latest analysis technique implemented in
Sentaurus Device Version Z-2007.03, uses
a mixed frequency-domain time-domain
method [1], which addresses the above
problems.
The HBM captures directly the large-signal
steady-state response of nonlinear systems
without tedious time-stepping algorithms.
In addition, the HBM exhibits an excellent
dynamic range to resolve low-level distortion
products.
 TCAD News June 2007
Input
Output
f1 2f1 3f1 4f1
Frequency
Figure 1. (Left) Input signal with modulation frequency f1 (black) results in output signal with spectral
components at f1 and integer multiples of f1 (harmonic distortion). (Right) Two-tone input signal at f1
and f2 also generates spectral components at 2f1-f2 and 2f2-f1 (intermodulation distortion).
The HBM can be used for 1D, 2D, or 3D
simulation setups using drift-diffusion or
hydrodynamic frameworks. Arbitrary devices
and circuits can be simulated including various
classes of FETs, (hetero) bipolar transistors,
HEMTs, as well as optoelectronic devices
such as semiconductor lasers [2]. As a major
advantage of the HBM, arbitrary large-signal
modulation conditions can be captured within
one single simulation using a ramping strategy.
This is more efficient compared to transient
simulations, where a new simulation must be
started for each modulation condition.
As a consequence of the increased system
size that must be solved during an HBM
simulation, the memory requirements are
typically 5–20 times higher than for a classical
DC, AC, or transient simulation. However, on
shared-memory architectures, the simulation
speeds up linearly with the number of
processors.
SiGe Bipolar Transistor Distortion
Analysis
Silicon germanium (SiGe) is a key technology
for RF integrated-circuit design. In the first
example, the frequency-dependent harmonic
distortion characteristics of a typical SiGe
bipolar transistor (BJT) (see Figure 3) are
analyzed using a 2D simulation setup. For
the harmonic balance investigation, eight
harmonics are taken into account.
The device is biased (without matching circuit)
to Vce = 1.5 V and Vbe = 0.9 V. The biasing
is chosen such that the transit frequency
ft reaches its maximum value of 77 GHz. In
addition, the base voltage is modulated with
10 mV at varying frequencies.
Figure 4 shows the frequency-dependent
harmonic distortion characteristics for this
device. BJTs feature very strong frequency-
dependent distortion effects.
For both bipolar and MOS transistors, the two
major nonlinear sources of distortion are the
Emitter
Base
Figure 3. Doping profile of npn SiGe bipolar transistor.
Input log(Output)
Output
First Harmonic
(10 dB/decade)
IP3
(IIP3)
Third Harmonic
(30 dB/decade)
2f1-f2 f1 f2 2f2-f1
Frequency log(Input)
Figure 2. Schematic of third-order intercept point,
which is defined by the extrapolated crossing
point of the fundamental first and third harmonics
of the output signal.
transconductance and the input impedance. Figure 5 shows a generic NMOS with a
The input impedance diffusion capacitance nominal gate length of 65 nm, width of 1 µm,
Cbe in BJTs is more nonlinear compared oxide thickness of 2 nm, and substrate doping
to the gate capacitance Cgs in MOSFETs, of 5 x 1017 cm–3. The device is biased to Vds
causing the strong frequency-dependent = 1.2 V and is modulated with a gate source
distortion characteristics in BJTs; whereas, voltage of 0.1 V at 1 MHz.
the MOS devices feature a very low frequency Figure 6 shows the V_IP3 characteristics
dependence of distortion. Figure 4 also as a function of the DC gate voltage Vgs for
shows that the third harmonic of the collector different substrate dopings Ns and oxide
current features a second-order low-pass thicknesses tox. With increasing Vgs, the
characteristic, causing a strong decrease of linearity increases and features a sharp peak
the third-order intercept voltage (V_IP3) in the around the threshold voltage, which originates
GHz regime. from cancellation effects of the higher order
harmonics [3][4].
Figure 7 shows the first harmonic of the
102 Ic3 1
Ic2
electron density in a cut through the channel
Ic1
V_IP3
10 1
as a function of the DC bias voltage Vgs. For
100
0.5
low bias Vgs, the electron density towards the
First Harmonic
drain side is modulated remarkably stronger
V_IP3 [V]
10-1
IC [mA]
0
Second Harmonic than for high Vgs. This is one cause of the
10-2
higher distortion at low bias Vgs observed in
10-3
-0.5 Figure 6.
10 -4
Third Harmonic The HBM can be used also to investigate
10-5 -1 high-amplitude modulation conditions
108 109
Frequency [Hz]
1010
such as the 1-dB compression point or
Figure 4. Frequency-dependent harmonic the saturation behavior of first-order and
distortion characteristics of SiGe. Third-order third-order modulation products in two-tone
voltage intercept point (V_IP3) strongly decreases experiments.
in low GHz regime due to increasing third
harmonic of collector current.
Gate
65 nm NMOS Distortion Analysis
The scaling of CMOS technology offered a
significant improvement in RF performance in
MOS devices. In view of the fast growth of the Source Drain
wireless communication market, designers DopingConcentration [cm-3]
1.2e+20
are exploring conventional CMOS instead
1.2e+17
of III–V or SiGe in RF circuits. Since system 1.3e+14
requirements on linearity become more
-1.7e+12
-1.8e+15
stringent for future wideband RF applications, -1.7e+18
the inherent superior linearity compared to the
faster SiGe BJTs is a significant advantage for Figure 5. Doping profile of 65 nm NMOS.
CMOS [3].
Figure 8 shows the results of an intermodulation
Collector distortion simulation for the 65 nm NMOS
with a DC bias Vgs of 0.7 V and f1 = 1 MHz,
f2 = 1.001 MHz for increasing modulation
amplitude Vg1. For gate voltage modulation
amplitudes higher than 0.2 V, saturation of
both the fundamental harmonic and the third-
order modulation products of the drain current
increases, limiting the maximum available
modulation power.
DopingConcentration [cm-3] The examples without matching circuits
1.5e+20
investigated so far are used mainly for low-
6.6e+16 frequency amplification applications with
2.9e+13 modulation frequencies below 10% of the
transit frequency of the device.
-1.9e+13
For high-frequency amplification, a suitable
-4.4e+16
matching circuit (reactive or resistive) must
-9.9e+19 be optimized for each specific application.
This can be performed also using the HBM
where the matching elements are added in a
SPICE-like manner.
 TCAD News
Conclusion
In summary, the harmonic balance module
available in Sentaurus Device opens the
possibility to analyze distortion effects at the
device level in an efficient way. Applications
include harmonic distortion, intermodulation
distortion, and signal compression analysis
for a wide range of devices using a one-
dimensional, two-dimensional, or three-
dimensional geometry, and a mixed-mode
simulation setup. Sentaurus Device is the ideal
simulation tool for optimization with respect to
distortion effects already in the device design
phase.
References
[1] B. Troyanovsky, Z. Yu, and R. W. Dutton, “Physics-based
simulation of nonlinear distortion in semiconductor devices using
the harmonic balance method,” Computer Methods in Applied
Mechanics and Engineering, vol. 181, no. 4, pp. 467–482,
2000.
[2] S. Odermatt, B. Witzigmann, and B. Schmithüsen, “Harmonic
balance analysis for semiconductor lasers under large-signal
modulation,” Optical and Quantum Electronics, vol. 38, no. 12‑14,
pp. 1039–1044, 2006.
[3] B. Murmann et al., “Impact of Scaling on Analog Performance
and Associated Modeling Needs,” IEEE Transactions on Electron
Devices, vol. 53, no. 9, pp. 2160–2167, 2006.
[4] R. van Langevelde et al., “RF-Distortion in Deep-Submicron
CMOS Technologies,” in IEDM Technical Digest, San Francisco,
CA, USA, pp. 807–810, December 2000.
An Efficient Simulation Environment for Modeling Single Event Effects with the
Sentaurus Tool Suite
Introduction
Single event effects (SEEs) in microelectronics
are caused when highly energetic particles
present in packaging materials, or in natural
space and terrestrial environments (for
example, protons, neutrons, alpha particles,
or heavy ions), strike sensitive regions of a
microelectronic circuit [1]. Similar effects can
occur also when an incident particle collides
with an atom and produces a reaction product
capable of depositing a significant amount of
energy. Depending on a number of factors, the
particle strike can cause no observable effect,
or a transient disruption of circuit operation,
or a change of logic state, or even permanent
damage to the device or integrated circuit
(IC) [1]. SEEs have long been a consideration
for electronics applications in space
environments (where ionizing radiation is
abundant) and for some terrestrial electronic
applications.
Scaling of CMOS device sizes to nanometer
dimensions and low operating voltages mean
that the amount of charge associated with ‘bits’
of information, and circuit noise margins, is
becoming extremely small. In addition, the high
transistor packing density means that a single
ionizing particle potentially impacts multiple
transistors. All of this increases the challenge
of using advanced CMOS technologies in
space and radiation environments and elevates
SEEs as a major reliability consideration in
commercial electronics.
Analysis of SEEs in advanced circuitry
involves the determination of the response of
multiple interactive devices, coupled with the
application-specific overall circuit response,
to energy deposition by a particle using
ionization or secondary reactions. TCAD
and mixed-mode simulations can be used to
determine the device and circuit responses
to radiation events. The characteristics of the
energy deposition produced by the events, as
well as the event rates, can be simulated using
Monte Carlo codes such as SEMM2 [2] and
Geant4-based codes such as MRED [3][4].
The increase in obtainable computing power
per cost over recent years enables problems
of much larger computational complexity to be
examined using such simulations.
In this article, a single-event simulation
methodology based on the use of the TCAD
Sentaurus Version Z-2007.03 tool suite
is presented. To fully characterize SEEs, a
TCAD News June 2007
101
V_IP3 [V]
10 0
Ns = 5e17 cm-3, tox = 2.0 nm
Ns = 5e16 cm-3, tox = 2.0 nm
Ns = 5e17 cm-3, tox = 1.5 nm
10-1
Ns = 5e16 cm-3, tox = 1.5 nm
0.2 0.4 0.6
Vgs[V]
Figure 6. Bias dependence of third-order voltage
intercept point (V_IP3) for varying substrate
dopings and gate oxide thicknesses. Around the
threshold voltage, V_IP3 features a peak due to
cancellation effects of higher order harmonics.
Figure 1. Six-transistor SRAM cell built in a
90-nm process. Circuit schematic represents
mixed-mode connections for SRAM cell. Although
all six devices are modeled in a single TCAD
structure, the nodes are wired up in mixed-mode
to allow for voltage perturbations.
systematic and rigorous simulation matrix with
more than 100 simulations is needed. The
new capabilities in the Sentaurus tool suite
allow us to take advantage of a parallel high-
performance computing system at Vanderbilt
University and to run the simulations
efficiently.
We use such simulation capabilities to examine
various aspects of SEEs, including charge-
sharing, the impact of nuclear reactions in the
overlayers, and single event transients and
upsets [5]. The simulations presented in this
article focus on the single event response of
a baseline (unhardened) 90-nm SRAM cell
designed from a commercial 90-nm process.
Simulation Environment
This work was conducted in part using the
resources of the Advanced Computing
Center for Research and Education
(ACCRE) at Vanderbilt University, Nashville,
Tennessee [6]. The ACCRE high-performance
computing system consists of approximately
1500 processors and has a capacity of
approximately 6 TFLOPS. Each node is built
with dual processors, and each processor
has at least 1-GB memory. The latest version
of the Sentaurus tools allows users to run a
TCAD simulation on a node, fully utilizing both
processors and all available memory on that
node for a single simulation. This provides
a significant speedup in simulation time,
compared to running the same simulation on
a single processor.
Device Simulation
As noted, the small size and proximity of
multiple devices requires the modeling of
Vgs Low
2e+11
1.5e+11 Vgs High
n [cm–3]
Id [mA]
1e+11
5e+10
0
0.8
1
-0.1 -0.05 0 0.05
X [µm]
Figure 7. First harmonic component of electron
density in NMOS channel. At low DC bias
voltage Vgs, the electron density is modulated
more strongly at the drain side.
multiple devices using 3D TCAD. A six-
transistor 90-nm SRAM cell has been modeled
with the Sentaurus tool suite, as shown in
Figure 1. As device sizes shrink, memory
cells are becoming much more compact in
Voltage [V]
size, with entire cell areas now comparable
to single-transistor drain-node areas of only a
few generations ago.
However, the size of the ion-induced charge
filament does not scale. In the past, with larger
size devices, the simulation of a cell using a
single transistor in TCAD, while the others
were represented using compact models
(that is, mixed mode), provided a reasonably
accurate representation of how the circuit
would respond to a single event. However,
as we move towards more compact circuitry,
issues such as multi-node charge collection
and parasitic transistor action are important in
determining circuit responses [7].
The SRAM cell comprises two NMOS
transistors and two PMOS transistors as the
cross-coupled inverter pair, and an additional
set of two NMOS transistors that are access
transistors and are used to read or write the
cell. The mesh consists of 85 000 vertices,
or 5000 2D elements and 450 000 3D
elements. Each NMOS and PMOS transistor
is calibrated to SPICE and process data
before building the SRAM cell. This ensures a
high level of fidelity in the SRAM cell model.
The simulations are all run in the mixed-mode
environment, as represented in Figure 1. In
this case, the mixed-mode connections are
made to allow the cell to operate as it would in
real conditions. All transistors are simulated in
TCAD, but the mixed-mode connections allow
the node voltages to change in response to the
ion-induced perturbation and potentially for
the cell to flip states, consistent with charge
moving through the structure. If all nodes
were hardwired to a source, the cell would
never change states due to a perturbation.
Figure 2 shows the response of the bit lines
of the SRAM cell following a heavy ion strike
to the drain of the off-state NMOS transistor.
Although many of the simulations use the
heavy ion statement inside the Sentaurus
Device simulator, we have developed an
alternative method of depositing charge
using the physical model interface (PMI) to
Sentaurus. Monte Carlo–based codes (such
as Geant4) can provide a realistic distribution
100
10-1
10-2
10-3
10-4
10-5
Id1 at f1
Id3 at 2f1−f2
10 -2
10 -1
100
Vg1 [V]
Figure 8. NMOS saturation behavior of
fundamental and third-order drain current
components for increasing modulation voltage.
For modulation amplitudes above 0.2 V, saturation
effects start limiting the available current and
power gain.
1.5
1
Bit Line
Bit Line Bar
0.5
0
-0.5
10-12 10-11 10-10 10-9 10-8
Time [s]
Figure 2. Node voltages versus time for bit lines
of SRAM cell as a result of a single event strike.
In this case, the cell switched states.
of generated charge corresponding to a
particular event, rather than an idealized
description of an average event. Ions can
interact with the Si substrate, dopant atoms,
or materials above the active silicon and can
cause nuclear reactions [5][8].
The charge distributions generated by these
events do not necessarily look like single
vector columns of charge. In many cases,
the events actually have several ‘fingers’ of
charge, as seen in Figure 3.
Having the capability to analyze these realistic
events is vital to understanding how reaction
products, including those originating in the
overlayer materials, can alter the response of
the device or circuit.
Simulation Matrix and Parallel
Simulations
To characterize and understand the single
event response of an SRAM cell, a large
simulation matrix is designed. The matrix
includes various ion-strike locations, linear
energy transfer (LET) values, and incident
ion angles, resulting in more than 100
simulations.
Figure 4 shows an example of a matrix of
hit locations, where X indicates the area on
the surface of the structure where an ion will
impact the silicon. The Sentaurus Workbench
software package allows us to set up these
complex matrices easily, to interface with the
ACCRE computing cluster, and to utilize fully
the available processing power. This permits
many jobs to be run simultaneously, rather
than one after another, greatly enhancing data
collection and simulation performance.

 TCAD News
Currently, all of the nodes on ACCRE consist
of dual processors. Parallelization of the device
solver allows the use of both processors and
all the memory on a node, reducing the time for
each simulation by up to 41%. Accounting for
hit location, incident angle, ion species, and
energy, characterization of the single event
response of the SRAM cell may involve more
than 100 simulations that take 4–5 days each
to complete on a single processor; the time
savings obtained by using the multiprocessor
capability are significant.
Conclusion
The high level of integration associated with
scaled devices requires multiple-device
3D simulations to characterize single event
effects. Such simulation capabilities allow
the prediction of the performance of design
variants operating in different radiation
environments. However, these simulations
are very complicated and can demand
Impact of Gettering Effects in Solar Cells
In 2005, the photovoltaic market exceeded
US$10 billion, showing an exponential annual
growth of 30%. Consequently, the shortage of
silicon feedstock has forced cell manufacturers
to look for new sources. To satisfy the market
in the short-term to mid-term, extending
feedstock to low-quality materials such as
solar-graded silicon or thin film techniques
is feasible and has been widely discussed.
These approaches require a detailed
understanding of not only the carrier transport
mechanisms but also process physics,
namely, diffusion and gettering processes.
With its comprehensive capabilities in device
and process simulation, TCAD can provide
solar cell engineers with valuable insights to
harness the last percentage of cell efficiency.
Weber et al. [1] recently successfully
reproduced Fe gettering experiments in
boron-doped diffusion processes using
Sentaurus Process and Sentaurus Device. In
this article, we illustrate the implementation of
an aluminum gettering process described by
Plekhanov et al. [2].
A crucial material parameter for solar cells to
achieve reasonable efficiency is the minority
carrier lifetime or diffusion length. A high
lifetime is achieved by reducing the number of
recombination centers (traps) in the Si wafer.
Therefore, for the successful use of solar-
graded materials, it is essential to consider
defect engineering in the design of the
fabrication process. In particular, an optimized
design of gettering processes, which reduce
the amount and impact of impurities present
in the Si wafer, is vital to obtain high cell
efficiencies.
Aluminum gettering uses the fact that,
above the eutectic temperature of 577°C,
the solubility of metals in Al is very high
(1021 cm–3) compared to their solubility in
Si (1017 cm–3). This provides a tremendous
driving force for metal atoms to segregate into
the Al or Al–Si liquid layer. As the segregation
process occurs simultaneously with the
impurity diffusion, the gettering process can
be described by:
• A segregation equation at the Al–Si material
boundary.
• A diffusion equation for the impurity diffusion
in bulk silicon.
• Reaction terms for cluster dissolution and
formation if impurity clusters such as metal
precipitates are taken into account in the
model.
Basically, for impurity gettering, the same
physics can be applied as for dopant
diffusion.
 TCAD News June 2007
significant amounts of computing power. Figure 3. References
TCAD Sentaurus Version Z-2007.03 gives Representation of [1] P. E. Dodd and L. W. Massengill, “Basic Mechanisms and
users the ability to design and build these charge generated Modeling of Single-Event Upset in Digital Microelectronics,” IEEE
by a Monte Carlo– Transactions on Nuclear Science, vol. 50, no. 3, pp. 583–602,
cells, and provides the flexibility needed to 2003.
based code in which
integrate into a high-performance computing an ion interacted
[2] P. C. Murley and G. R. Srinivasan, “Soft-error Monte Carlo
modeling program, SEMM,” IBM Journal of Research and
cluster environment such as ACCRE, for a with materials above Development, vol. 40, no. 1, pp. 109–118, 1996.
comprehensive characterization of complex the active silicon and [3] S. Agostinelli et al., “Geant4—a simulation toolkit,” Nuclear
physical phenomena such as single event showered charge Instruments and Methods in Physics Research A, vol. 506, no. 3,
pp. 250–303, 2003.
effects. into the device. The
[4] C. L. Howe et al., “Role of Heavy-Ion Nuclear Reactions
output of the Monte
About ISDE Carlo code was
in Determining On-Orbit Single Event Error Rates,” IEEE
Transactions on Nuclear Science, vol. 52, no. 6, pp. 2182–2188,
ISDE is the applied research division of the used as input to the 2005.
Vanderbilt University School of Engineering Sentaurus Device [5] K. M. Warren et al., “The Contribution of Nuclear Reactions to
Heavy Ion Single Event Upset Cross-Section Measurements in
Radiation Effects Group, which is the largest
simulation.
a High-Density SEU Hardened SRAM,” IEEE Transactions on
Nuclear Science, vol. 52, no. 6, pp. 2125–2131, 2005.
program of its kind in the United States. ISDE
[6] For more information, go to <http://www.accre.vanderbilt.edu/>,
studies radiation effects in microelectronics May 2007.
equipment by leveraging a combination of [7] O. A. Amusan et al., “Charge Collection and Charge Sharing in
experienced people, custom-developed Figure 4. Top view of a 130 nm CMOS Technology,” IEEE Transactions on Nuclear
Science, vol. 53, no. 6, pp. 3253–3258, 2006.
software, commercially available software, six-transistor SRAM
[8] D. R. Ball et al., “Simulating Nuclear Events in a TCAD Model
and the Vanderbilt University ACCRE high- cell; X indicates the of a High-Density SEU Hardened SRAM Technology,” IEEE
performance computing facility. locations where Transactions on Nuclear Science, vol. 53, no. 4, pp. 1794–1798,
heavy ions with 2006.
varying LETs will
strike the device.
Plekhanov et al. developed a set of equations 10-2
to describe the gettering of the impurities C,
taking into account the decreasing size of
Shockley–Read–Hall Lifetime [s]
10-3
metal precipitates C* in silicon:
2 10-4
∂C ∂C
+ 4πrρD (C *– C)
Gettering Time [minute]
= D 10
∂t ∂x 2 20
10-5
30
40
where D is the diffusivity of the impurity, r is
10-6
the radius of the metal precipitate, and ρ is the
precipitate density.
10-7 Figure 2. Spatially varying SRH lifetimes
Sentaurus Process allows users to define new 0 20 40 60 80 100
Depth [µm] for the device simulation.
species in silicon and to define new equations
for the diffusion, segregation, and reactions of
these new species as simple text strings. For In the next step, the trap distribution passes propagation method, and the finite-difference
example, the following line defines the partial to the device simulator Sentaurus Device. time-domain full-wave Maxwell solver.
differential diffusion-segregation equation for The trap density Ntrap together with a capture
Finally, the influence of process variation on
the impurity Fe in silicon: cross section σn translates to a spatially
device characteristics is evaluated. Figure 3
varying Shockley–Read–Hall (SRH) lifetime shows the influence of gettering time on solar
 pdbSetString Silicon Fe Equation \  (see Figure 2): cell efficiency. In this setup, after 40 minutes,
  “ddt(Fe)-$Dm*grad(Fe)-PrecDissol” all Fe atoms are gettered by the Al rearside,
τ SRH, n = 1/Ntrapνthσn resulting in a strong increase of the short-
circuit current efficiency.
For each time step, Sentaurus Process solves where νth is the thermal carrier velocity.
Figure 4 shows the dependency of the
this differential equation and provides the
To calculate the white-light generation, the gettering time on external quantum efficiency
spatial distribution of the species.
transfer matrix method is used. Sentaurus (EQE). Due to a lower minority lifetime, the
After the reactions and diffusion equations Device offers a variety of different optical EQE is lowered in the red part of the spectrum
are set up, the process flow with arbitrary solvers such as raytracing, the beam as the carriers generated at the rear are unable
temperature ramps can be defined. Here,
to reach the p-n junction.
a 1D simulation with a very simple ramp,
18
References
namely, a constant temperature at 900°C
for four different gettering times (10, 20, 30, 17 [1] T. Weber et al., “Numerical Simulation of Gettering and
Recombination in Iron-Contaminated Boron Emitters,” in
and 40 minutes) is investigated. The rear of
Proceedings of the 21st European Photovoltaic Solar Energy
Efficiency [%]
16
the 100-μm thick silicon wafer is covered by Conference (EUPVSEC), Dresden, Germany, September 2006.
Al (at a depth of 100 μm). The main result of 15 [2] P. S. Plekhanov et al., “Modeling of gettering of precipitated
impurities from Si for carrier lifetime improvement in solar
the process simulation is the trap distribution cell applications,” Journal of Applied Physics, vol. 86, no. 5,
14
shown in Figure 1. In addition to the trap pp. 2453–2458, 1999.
distribution, the emitter doping profile can 13
be modeled for use in subsequent device 12
simulations, but this is not discussed further 0 20 40 60
in this article. Gettering Time [minute]
Figure 3. Dependency of cell efficiency on
gettering time.
1
1013
External Quantum Efficiency [1]
0.8
Traps [cm-3]
1012
Gettering Time [minute]
10
20 0.6
30
40
1011
Gettering Time [minute]
0.4 10
20
1010 30
40
0 20 40 60 80 100 0.2
Depth [µm]
Figure 1. Depth-dependent trap distribution in die 400 600 800 1000 Figure 4. Influence of gettering time
silicon wafer for different gettering times. Wavelength [nm] on EQE.
 TCAD News

Simulation of 4H-SiC Vertical Junction FET in Sentaurus Device

Introduction Another key aspect of exploring a new Source
Vg = Simulations (Measurements)
Vg = 2.954 V (5.0 V)
0.3 Measured

Silicon carbide (SiC) has long been semiconductor technology is understanding Simulated

recognized as a superior semiconductor for discrepancies between theoretical projections 0.25

Vg = 2.936 V (4.5 V)

high-power and high-temperature applications and experimental results. The challenges Gate Gate Vg = 2.914 V (4.0 V)
0.2
faced by SiC MOSFETs provide an important

Drain Current [A]

in view of its high breakdown electric field
and excellent thermal conductivity. Since the illustration of this point. Despite ongoing 0.15
Vg = 2.877 V (3.5 V)

pioneering work of Tairov and Tsvetkov [1] improvements, the inversion layer mobility is Vg = 2.781 V (3.0 V)

who developed the modified seed sublimation still too low for commercial-grade devices. 0.1

growth process that spearheaded today’s TCAD simulations suggest that a high number 0.05
Vg = 2.500 V (2.5 V)

SiC substrate technology, the industry of interface traps can explain the experimentally Vg = 0.000 V (0.0 V)

has improved steadily the quality, size, and extracted inversion layer mobility [7]. On the 0
0 1 2 3 4 5

cost of SiC substrates, all of which are key other hand, oxide reliability in SiC MOSFETs Drain Voltage [V]

manufacturability considerations in any
semiconductor technology.
A major quality concern has been the so-called
micropipe defects that are considered to be
associated with screw dislocations and to
align themselves along the c-axis of the crystal.
Since a single micropipe defect in the device
is a topic of concern when targeting high- Figure 3. Measured (points) and simulated (lines)
voltage and high-temperature applications. Ids–Vds characteristics of VJFET. Gate voltages
SiC MOSFET design can lead to electric in parentheses are the actual gate voltages. The
fields in the oxide substantially higher than in discrepancy is due to gate contact resistance,
silicon devices, which combined with a lower which is not explicitly considered in the
injection barrier for carriers due to the higher simulation [9].
band gap of SiC can lead to poor reliability. As 4H-SiC Measurement
a consequence of these remaining challenges, 100
Impact Ionization Simulation

active area is sufficient to degrade or destroy SiC oxide-free power-switching devices have
the device, these defects have hindered the been investigated recently. An example is the Drain 80

Drain Current [A/Cm2]

realization of large-area power devices [2].
Over the last several years, significant progress
has been made in reducing micropipe defects,
and 100-mm diameter substrates are now
commercially available. While the substrate
vertical junction field effect transistor (VJFET)
Figure 2. Simulation mesh of VJFET. Inset shows 60
discussed in the next section. mesh refinement surrounding the critical regions
Simulation of 4H-SiC VJFET at the bottom of the vertical channel. 40
TCAD simulations rely on physical models 20

cost is approximately an order of magnitude
higher than silicon, SiC technology has
already demonstrated commercial feasibility in
high-voltage Schottky barrier diodes (SBDs),
and new devices and applications are being
considered [3].
Emerging Applications for SiC
Electronic Devices
The recent commercial interest in hybrid
electric vehicles has extended the
opportunities for electronic content in
automobiles. The high temperature and
harsh environmental conditions prevalent in
automotive applications provide a natural
medium for SiC relative to lower-temperature
rating semiconductors such as silicon. One
of the most intriguing possibilities is the
simplification of cooling requirements – for
example, the elimination of secondary cooling
loops necessary to maintain existing silicon-
describing the operational phenomena and Figure 2 shows the meshed VJFET structure.
model parameters calibrated to the process The inset shows a finely meshed p-n junction
and materials used to fabricate the devices. region and parts of the vertical channel. Such
In a previous article, we compiled the key a refinement is needed to resolve properly
material and model parameters for the 4H- the space-charge regions and to capture
SiC polytype [8]. In this article, we perform accurately the impact ionization effects
simulations of a 4H-SiC trenched-and-
for breakdown simulation. These meshing
implanted VJFET, a type of device that holds constraints can be easily implemented in
commercial promise. The device structure and Sentaurus Structure Editor using either
experimental data are from Zhao et al. [9].
its graphical user interface or its powerful
scripting capabilities.
Source
0 Electrical simulations are performed with
Sentaurus Device using physical models
Gate Gate incorporating:
2 [4] R. Kelley, M. S. Mazzola, and V. Bondarenko, “A Scalable SiC
• Doping-dependent and temperature-
dependent Shockley–Read–Hall (SRH)
4 recombination and Auger processes.
• Doping-dependent mobility models with
6 high-field velocity saturation effects.
Y [µm]
0
0 500 1000 1500 2000
Drain Voltage [V] at Vg = 0 V
Figure 4. Measured and simulated breakdown
voltage.
References
[1] Y. M. Tairov and V. F. Tsvetkov, “Investigation of Growth Processes
of Ingots of Silicon Carbide Single Crystals,” Journal of Crystal
Growth, vol. 43, no. 2, pp. 209–212, 1978.
[2] P. G. Neudeck and J. A. Powell, “Performance Limiting Micropipe
Defects in Silicon Carbide Wafers,” IEEE Electron Device Letters,
vol. 15, no. 2, pp. 63–65, 1994.
[3] P. Friedrichs and R. Rupp, “Silicon Carbide Power Devices
- Current Developments and Potential Applications,” in 11th
European Conference on Power Electronics and Applications
(EPE), Dresden, Germany, September 2005.
Device for DC/DC Converters in Future Hybrid Electric Vehicles,”
in Twenty-First Annual IEEE Applied Power Electronics
Conference and Exposition (APEC), pp. 460–463, March 2006.
[5] Y. Sugawara et al., “12.7kV Ultra High Voltage SiC Commutated
Gate Turn-off Thyristor: SICGT,” in 16th International Symposium
on Power Semiconductor Devices & ICs (ISPSD), Kitakyushu,
Japan, pp. 365–368, May 2004.

[6] X. Li et al., “Multistep junction termination extension for SiC power

Doping Concentration [cm-3]
based devices at 85ºC base plate temperature 6.0e+18
• Impact ionization (Okuto–Crowell model). devices,” Electronics Letters, vol. 37, no. 6, pp. 392–393, 2001.

– thereby reducing costs [4]. In this scenario,
the higher cost of SiC devices relative to Si
devices is offset by the lower system costs.
Another high-visibility, potential application
is improving power grid efficiency. Wind and
solar energy sources produce direct current
and rely on inverter modules for conversion
to alternating current used by the power grid.
Current inverter module technology is based
on silicon devices and operates at 90–96%
efficiency. Though this efficiency seems high,
SiC devices offer the potential to increase the
efficiencies of inverter modules to the 95–98%
range, which is significant. An example of the
potential for SiC in this application is the
recent demonstration of a SiC commutated
gate turn-off thyristor (GTO) with a blocking
voltage of 12.7 kV [5].
Motivation for Simulating SiC Devices
As with other maturer semiconductor
technologies, the early stages of process
definition, device design, and optimization
8 [7] H. Linewih and S. Dimitrijev, “Channel-Carrier Mobility Parameters
5.8e+15 Sentaurus Device accounts for the anisotropic
5.5e+12 properties of 4H-SiC resulting from the
10 -4.7e+13 hexagonal crystal structure. Table 1 lists
-5.0e+16 some important model parameters used in the
-5.2e+19 4H-SiC simulations for mobility and impact ionization.
12
Simulation results for a single-cell VJFET with
Drain an active area of 320 µm x 293 µm, showing
Idrain versus Vdrain characteristics for various
0 2 4 6
gate biases, are presented in Figure 3.
X [µm]
Figure 4 shows the breakdown characteristics
Figure 1. Device structure and doping profile of for the same device, as well as the region
VJFET. of the device undergoing acute avalanche
generation. The simulated results show good
The VJFET structure allows the realization of agreement with experimental data.
‘normally off’ devices, which are desirable for
fail-safe protection. The device structure is
defined in Sentaurus Structure Editor and is
shown in Figure 1. The device is created on Table 1. Important model parameters used in the simulations for mobility and impact ionization.
the Si face of the 4H-SiC material and has Model Parameter Coefficients
an n- vertical channel and drift region with a
Mobility
doping concentration of 6.5 x 1015 cm–3. The
p+ gate regions, with a doping concentration For Electrons
for 4H SiC MOSFETs,” in Proceedings of the 23rd International
Conference on Microelectronics (MIEL), Niš, Yugoslavia,
pp.  425–430, May 2002.
[8] “TCAD Simulation of Silicon Carbide Devices: Part I. Models and
Parameters,” TCAD News, pp. 3–5, September 2006.
[9] J. H. Zhao et al., “3.6 mΩcm2, 1726 V 4H-SiC normally-off
trenched-and-implanted vertical JFETs and circuit applications,”
IEE Proceedings – Circuits, Devices and Systems, vol. 151,
no. 3, pp. 231–237, 2004.
[10] W. J. Schaffer et al., “Conductivity Anisotropy in Epitaxial 6H and
4H SiC,” in Materials Research Society Symposia Proceedings,
vol. 339, pp. 595–600, April 1994.
[11] T. T. Mnatsakanov et al., “Universal Analytical Approximation
of the Carrier Mobility in Semiconductors for a Wide Range of
Temperatures and Doping Densities,” Semiconductors, vol. 38,
no. 1, pp. 56–60, 2004.
[12] T. Hatakeyama et al., “Physical Modeling and Scaling Properties
of 4H-SiC Power Devices,” in International Conference on
Simulation of Semiconductor Processes and Devices (SISPAD),
Tokyo, Japan, pp. 171–174, September 2005.
For Holes Unit Reference

can greatly benefit from TCAD simulation. of 1.0 x 1018 cm–3, are created on the MuMax 947 124 cm2/(Vs) [10]
Arguably, the motivation for TCAD simulation sidewalls of the trenches. The p++ contact Anisotropic Mobility
of SiC devices is even higher than in other regions have a doping concentration of 5.0 x
MuMax 700 114 cm2/(Vs) [7][11]
technologies since SiC substrate cost is still 1019 cm–3.
Impact Ionization G = alpha * exp( -beta / E)
relatively high, making large-scale experimental The n+ substrate, above the drain contact,
wafer splits very costly. Moreover, the is doped with a concentration of 6.0 x
alpha 2.10e+07 2.96e+07 1/cm [12]
exceptional material attributes of SiC provide 1018 cm–3, and the n+ source region has a beta 1.70e+07 1.60e+07 V/cm
fertile ground for exploring truly novel device concentration of 1.0 x 1018 cm–3. The trench Anisotropic Impact
structures that transcend the operational region comprises a 50-nm thick thermal Ionization
principles and range of silicon-based devices. oxide, followed by a 200-nm thick silicon alpha 1.76e+07 3.41e+08 1/cm [12]
Since many of these device structures want nitride layer, and the remaining portion is filled beta 3.30e+07 2.50e+07 V/cm
to exploit the high breakdown field in SiC to with oxide. The vertical channel is designed to
realize high-blocking voltages, careful design have an opening of 0.63 µm, and the blocking
and simulation of junction terminations are layer or the n- drift region is designed to have
essential [6]. a thickness of approximately 9.4 µm.

TCAD News June 2007 

TCAD News

TCAD Events 2007

Conferences and Trade Shows

USA Europe

July 16–20 September 11–13

SEMICON West 37th European Solid-State Device
San Francisco, California, USA Research Conference (ESSDERC) /
33rd European Solid-State Circuits
Conference (ESSCIRC)
July 23–27 Munich, Germany
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Conference (NSREC)
September 25–27
Honolulu, Hawaii, USA
12th International Conference
on Simulation of Semiconductor
September 17–21 Processes and Devices (SISPAD)
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Monterey, California, USA

September 24–27 Asia-Pacific

7th International Conference on
Numerical Simulation of Optoelectronic September 7–14
Devices (NUSOD)
TCAD Asia-Pacific Seminar Series
University of Delaware, Newark, Delaware,
USA September 7 Hsinchu
September 10 Singapore

September 30 – October 3 September 12 Seoul

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December 10–12
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