Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in
Stand-by Mode
Lava Kumar P
(lavakumarreddy@gmail.com)
Department of Electrical Engineering, IIT Kanpur, India.
Abstract
An effective technique for reducing leakage currents
in an SRAM cell in standby mode is by reducing
effective supply voltage across the cell. It is shown that
raising of negative supply voltage level (VSS) is more
effective in reducing subthreshold leakage currents,
while reduction in positive supply voltage level (VDD)
has relatively larger impact on gate leakage currents.
As a result, for a fixed effective supply voltage across
the cell in standby mode, there is an optimum
combination of supply rails that minimizes leakage
currents depending on the relative importance of
subthreshold and gate leakage currents. Simulation
results based on BPTM (Berkeley Predictive
Technology Model) are presented that show that for a
net voltage across the cell of 0.5V, supply voltages
(VDD, VSS) of (0.35, 0.85), (0.25, 0.75) and (0.1, 0.6)
yield minimum leakage currents in 90nm, 65nm and
45nm technology nodes respectively.
1. Introduction
As a result of continued scaling of MOS transistor, a
dramatic increase in the performance of VLSI ICs has
been achieved. However, as a result of scaling, power
dissipation due to leakage currents has also increased
dramatically and is a major source of concern especially
for low power applications. According to projections
from ITRS, memory will occupy about 71% of the chip
area by 2005 and 90% by 2013 [1]. In view of its
importance, a number of techniques have been
proposed in literature for reducing the impact of
leakage power dissipation in SRAM cells [2].
One common technique for reducing leakage currents
through an SRAM cell in standby mode is through
reduction of supply voltage across the cell. This can be
done either by raising the negative supply rail voltage
VSS or by reducing the positive supply rail voltage VDD
[3]. It can be shown that while raising VSS is more
effective in reducing subthreshold leakage current,
scaling of VDD is more effective in reducing the gate
leakage currents through the SRAM cell. Since in
general both subthreshold and gate leakage currents are
significant, scaling of only single supply rail is not
optimum. In the present work we show that for a
20th International Conference on VLSI Design (VLSID'07)
0-7695-2762-0/07 $20.00 © 2007
Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:10 from IEEE Xplore. Restrictions apply.
Baquer Mazhari
(baquer@iitk.ac.in)
constant supply voltage (VDD – VSS) across the cell in
inactive mode, there is an optimum combination of VDD
and VSS that minimizes leakage currents while
maintaining a constant noise margin. Results are shown
for 90, 65 and 45nm technology nodes obtained through
simulations carried out using BPTM device models.
The rest of the paper is organized as follows; in section
2 the impact of scaling of positive and negative supply
rails individually are described. Section 3 describes
determination of optimum combination of supply rail
voltages for leakage minimization while section 4
summarizes the main conclusions from the work.
2. Basic Concept
Fig. 1. illustrates different components of leakage
currents in an SRAM cell. These include subthreshold
and gate leakage current components. To illustrate that
neither raising of negative supply rail nor reduction of
positive supply voltage alone represents an optimum
method for reduction of leakage currents, the SRAM
cell was simulated with different combinations of Vdd
and Vss voltages while maintaining the difference of
the two (Vdd-Vss) constant at 0.5Volts.
Vdd
M3 M4
Vdd
M5 0V Vdd Vdd
M6
M1 M2
WL=0V WL=0V
sub-threshold
gate leakage
leakage
Fig. 1: Schematic showing different leakage current
components through an SRAM cell.
Since the effective supply voltage across the cell
remains constant, the noise margin also remains almost
unchanged as shown in Fig. 2. The simulation results
 were obtained using AIM SPICE simulator and BPTM
model files released on 30/9/2005.
9.0n
Total Subthreshold Leakage Current
8.0n Total Gate Leakage Current
1.0
7.0n

Leakage Current (A)

0.8
6.0n

0.6 5.0n
SNM(V)

4.0n
0.4
3.0n

0.2 2.0n

0.0 0.1 0.2 0.3 0.4 0.5

0.0 Vss (V)
0.0 0.1 0.2 0.3 0.4 0.5
Vss(V)

Fig. 3. Effect of increase in negative supply rail

Fig. 2: Variation of SNM with increasing Vss voltage VSS on total gate and subthreshold leakage
while keeping voltage across the SRAM cell fixed currents for 65nm technology at 27°C.
at 0.5V (i.e. Vdd=Vss+0.5V). Results shown are
On the other hand, as Vss increases, Vdd decreases
for 65nm Tech and temperature of 27°C.
causing source-body junction of transistor M3 to
Fig.3. illustrates how subthreshold and gate
become less reverse biased. This reduces its
leakage currents change as negative supply rail
threshold voltage and causes an increase in its
voltage is increased from one extreme value of 0V to
subthreshold leakage current. However, since
the other extreme value of 0.5V. The word and bit
subthreshold leakage current is dominated by M2
lines are maintained at zero and full supply voltage
and M5 transistors, the overall subthreshold current
respectively. It can be seen that the total
reduces as Vss is increased.
subthreshold current through the cell decreases
rapidly with increasing negative supply rail (Vss)
even though the effective voltage across the cell is
maintained constant at 0.5V. It can also be seen that
4.0n
with increasing negative supply rail, the total gate M2
leakage current through the cell has the opposite M3
Subthreshold Leakage (A)

3.0n M5
trend.
Assuming that zero is stored in the cell as shown in
2.0n
Fig. 1, it can be readily seen that subthreshold
current arises primarily from transistors M2, M3 and
M5. Variation of subthreshold current through these 1.0n

transistors with Vss is shown in Fig. 4. Even though

drain-source voltages across these transistors remain 0.0

unchanged, the subthreshold current still changes due 0.0 0.1 0.2 0.3 0.4 0.5
to change in body bias of transistors in the SRAM Vss (V)
cell. For NMOS transistors M2 and M5, the body is
connected to ground so that increase in Vss causes
Fig. 4: Variation of subthreshold leakage currents
source-body junction to become increasingly reverse
through individual transistors in the conventional
biased thereby resulting in rise in threshold voltage
SRAM cell in 65nm technology at 27°C
of these transistors. This causes a decrease in
Gate leakage is pre-dominantly due to NMOS
subthreshold current in these two transistors. The
transistors M1, M2, M5 and M6. Variation of gate
subthreshold current in M5 falls because gate-source
leakage current through each of these transistors with
voltage becomes negative as Vss rises.
Vss is shown in Fig.5. The gate to source and gate
to drain voltages of M1 and M2 transistors remains
unchanged as Vss is increased so there is little
change in their gate leakage.

20th International Conference on VLSI Design (VLSID'07)

0-7695-2762-0/07 $20.00 © 2007

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:10 from IEEE Xplore. Restrictions apply.
 6.0n
5.0n M1
M2
5.0n
M3

Total Subthreshold Current(A)

4.0n M4
M5 4.0n
M6
Gate Leakage (A)

3.0n 3.0n

2.0n 2.0n

1.0n
1.0n
0.0

0.0 0.0 0.1 0.2 0.3 0.4 0.5

0.0 0.1 0.2 0.3 0.4 0.5
Vss(V)
Vss(V)

Fig. 5: Variation of gate leakage currents through

Fig. 6: Variation of total subthreshold current
individual transistors in the SRAM cell for 65nm
through SRAM cell for 90nm technology at 27°C
technology at 27°C
Fig.7 shows the variation of total gate leakage
However, the voltage at source terminals of M5
current with increasing Vss. As discussed earlier,
increases resulting in increased voltage across the
the total gate leakage current increases with
gate dielectric of M5 thereby resulting in higher gate
increasing Vss.
leakage in this transistor. Thus gate leakage current
increases with increase in negative supply rail
voltage.
From the above discussion it is clear that increase in 280.0p
negative supply rail (accompanied by a simultaneous
Total Gate Leakage Current(A)

increase in positive supply rail voltage to maintain a 260.0p

constant voltage across the cell) reduces subthreshold
current but increases gate leakage currents. As a result,
240.0p
it is expected that total leakage current would reach a
minimum at some intermediate value of Vss between 0
220.0p
and 0.5V depending on the relative importance of the
two leakage current components.
200.0p

3. Optimum Supply Rail Voltages for 180.0p

Leakage Minimization in Inactive Mode 0.0 0.1 0.2 0.3 0.4 0.5
Vss(V)
In this section, variation of subthreshold, gate and
total leakage currents through the SRAM cell in three Fig. 7: Variation of total gate leakage current
different technology nodes is described as a function of through SRAM cell for 90nm technology at 27°C
supply voltages and an optimum combination of supply
Fig.8 shows the variation of total leakage current
voltage levels that minimizes total leakage is
with increasing Vss. The shape of the curve in Fig. 8
determined.
is similar to the plot shown in Fig. 6 because
3.1 90nm Technology node subthreshold leakage current is one order of
magnitude larger than gate leakage current.
Fig.6 shows the variation of total subthreshold Minimum total leakage current in 90nm technology
current with increasing Vss. The total subthreshold is achieved at Vss=0.35V; Vdd=0.85V for a net
current decreases until Vss rises to 0.35V, but further voltage across the cell of 0.5V. This is 27.9% better
increase in Vss causes a slight rise in total subthreshold if only negative supply rail is increased to 0.5V and
current. The initial drop occurs because increasing Vss Vdd = 1V and 89% better if only positive supply rail
decreases subthreshold current through transistors M5, is reduced to 0.5V and Vss = 0V.
M2 and the subsequent increase occurs due to increases
in the subthreshold current through transistor M3.

20th International Conference on VLSI Design (VLSID'07)

0-7695-2762-0/07 $20.00 © 2007

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:10 from IEEE Xplore. Restrictions apply.
 6.0n
8.5n

5.0n 8.0n

Total Gate Leakage(A)

Total Leakage Current(A)

4.0n 7.5n

7.0n
3.0n
6.5n
2.0n
6.0n
1.0n
5.5n
0.0 0.1 0.2 0.3 0.4 0.5
0.0 Vss(V)
0.0 0.1 0.2 0.3 0.4 0.5

Vss(V) Fig. 10: Variation of total gate leakage current

through SRAM cell for 65nm technology at 27°C
Fig. 8: Variation of total leakage current through The plot shown in Fig.11 shows the variation of
SRAM cell for 90nm technology at 27°C total leakage current with increasing Vss.

3.2 65nm Technology node

15.0n
Fig.9 shows the variation of total subthreshold current
with increasing Vss. 14.0n

Total Leakage(A) 13.0n

9.0n 12.0n

8.0n 11.0n
Total Sub Threshold Current(A)

7.0n
10.0n
6.0n
9.0n
5.0n
0.0 0.1 0.2 0.3 0.4 0.5
4.0n Vss(V)

3.0n
2.0n
0.0
Fig. 9: Variation of total sub threshold current
through conventional SRAM cell in 65nm
technology at 27°C
In this case the total subthreshold current continues to
fall until Vss rises to 0.4V. Fig.10 shows the variation
of total gate leakage current with increasing Vss. The
total gate leakage current is relatively larger due to
thinner gate dielectric and increases rapidly with
increasing Vss.
Fig 11 Variation of total leakage current through
SRAM cell for 65nm technology at 27°C
0.1 0.2 0.3 0.4 0.5 Since subthreshold and gate leakage currents in
Vss(V) 65nm technology are comparable and contribute
equally to total leakage current, the positive and
negative supply rails have to be altered by about the
same amount and minimum leakage occurs at Vss =
0.25V; Vdd = 0.75V. The leakage current is 16.35%
lower compared to the case where only negative
supply rail is increased to 0.5V and Vdd = 1V and
36.5% lower compared to the case where only
positive supply rail is reduced to 0.5V and Vss = 0V.
3.3 45nm Technology node
Fig. 12 shows the variation of total subthreshold
leakage current with increasing Vss. The subthreshold
current falls until Vss rises to 0.15V.

20th International Conference on VLSI Design (VLSID'07)

0-7695-2762-0/07 $20.00 © 2007

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:10 from IEEE Xplore. Restrictions apply.
 60.0n

58.0n
16.0n
Total Subthreshold Leakage(A)

Total Leakage Current(A)

56.0n

54.0n
14.0n 52.0n

50.0n

48.0n
12.0n
46.0n

44.0n
10.0n 0.0 0.1 0.2 0.3 0.4 0.5
Vss(V)

0.0 0.1 0.2 0.3 0.4 0.5

Vss(V) Fig.14Variation of total leakage current through 6-T
SRAM cell in 45nm technology at 27°C
Fig. 12: Variation of total sub threshold current 4. Conclusions
through conventional SRAM cell in 45nm
technology at 27°C In summary, it has been shown that neither reduction
in positive supply voltage nor increase in negative
The plot shown in Fig.13 shows the variation of total supply voltage alone is optimum for reducing total
gate leakage current with increasing Vss. Although the leakage current in an SRAM cell in inactive mode.
shape of the curve is same as earlier technologies, gate Depending on the relative importance of subthreshold
leakage is larger than subthreshold leakage current. and gate leakage currents, there is an optimum
combination of supply rail voltages that minimizes
leakage currents. As the importance of gate leakage
48.0n
currents increases during transition from 90nm to 65
and 45nm technologies, the optimum value of negative
45.0n supply rail reduces from 0.35V to 0.1V while optimum
Total Gate Leakage(A)

value of positive supply voltage reduces from 0.85 to

42.0n
39.0n
36.0n
33.0n
0.0 0.1
Fig. 13: Variation of total gate leakage current
through conventional SRAM cell in 45nm
technology at 27°C
Fig. 14 shows the variation of total leakage current
with increasing Vss. Minimum leakage occurs at a
relatively smaller value of Vss = 0.1V because gate
leakage is the dominating factor in total leakage and
reduction in positive supply rail has more impact on it.
At the optimum value of supply rails, the leakage is
smaller by 12.66% compared to the case where only
negative supply rail is increased to 0.5V and Vdd = 1V
and 11.72% lower compared to the case where only
positive supply rail is reduced to 0.5V and Vss = 0V.
0.6V for a net voltage across the cell of 0.5V.
5. References
[1] K.Nill, Y.Tsukamoto, T.Yoshizawa, S. imaoka, Y.
Yamagami, T.suzuki, H.shibayama, “A 90-nm low-power 32-
kb Embedded SRAM with gate leakage suppression circuit
0.2 0.3 0.4 0.5
for mobile Applications” IEEE journal of solid-state circuits,
Vss(V)
vol.30.pp684-693.
[2] T. Enomoto, Y.Oka and K. Shikano, “ Self-
Controllable Voltage Level (SVL) Circuit and its Low-
Power High-Speed CMOS Circuit Applications”, IEEE
Journal of solid State Circuits, Vol.38, No.7, pp. 1220-
1226, July 2002.
[3] Baquer Mazhari, Ankur Goel. “Gate leakage and its
reduction in deep sub micron SRAM” IEEE Proceedings of
18th international conference on VLSI design 2005.
6. Authors
Lava Kumar P: Pursued M. Tech degree from
Indian Institute of Technology, Kanpur in Electrical
Engineering. Currently working with LSI Logic,
India.
Dr. B. Mazhari: Professor, Dept. of EE, Indian
Institute of Technology, Kanpur.

20th International Conference on VLSI Design (VLSID'07)

0-7695-2762-0/07 $20.00 © 2007

Authorized licensed use limited to: University of Central Florida. Downloaded on October 25, 2008 at 23:10 from IEEE Xplore. Restrictions apply.