Power Supply Current Detectability of SRAM Defects
Jian Liu and Rafic Makki
Department of Electrical Engineering
University of North Carolina at Charlotte, Charlotte, NC 28223
Abstract
We investigate correlations between SRAM cell
defects and power supply current including ZDDQ (peak
value of quiescent power supply current) and iDDT (tran-
sient power supply current). Our results show that the
power supply current can be used to detect cell shorts, cell
opens, and disturb-type pattem sensitivity. We also investi-
gate the effect of total current leakage in the power sup-
ply, which is proportional to SRAM size, on the power
supply current detectability of SRAM cell defects. We
present limits (obtained from simulation) on current
detectability of SRAM cell defects as a function of normal
power supply current leakage.
Keywords: transient power supply current, quiescent
power supply current, physical defects, large circuit sizes
I. Introduction
At the 1981 International Test Conference Levi
showed that fully CMOS (FCMOS) circuits can be tested,
in part, by measuring ZDDQ. Normal ZDDQ levels in a
FCMOS circuit are mostly due to current leakages. Ele-
vated IDDQ levels could indicate circuit defects such as
gate-oxide shorts. This is a significant result because ZDDQ
is directly observable and yet can indicate defects any-
where in the circuit. Since that time the test industry has
recognized the advantages of ZDDQ and a wealth of ZDDQ
research results have been compiled [11-[29]. Researchers
have developed sensors for built-in monitoring of ZDDQ
[15]-[21], proposed new test generation techniques [21]-
[%I, studied the use of scan techniques to enhance control-
lability for ZDDQ testing [251, experimented with ZDDQ. in
production testing 1261, utilized ZDDQ for fault locatton
[27], and reported on testing static RAMS with IDDQ [28]-
[29]. The test industry is in the process of developing stan-
dards for off-chip ZDDQ sensors as was presented at the
recent 1994 International Test Conference [30]. Recently,
iDDT has been proposed as an additional testability mea-
sure for detecting SRAM defects including cell disturbs
[31]. The iDDT provides a window of observability into
the internal switching characteristics of a circuit. Every
time a circuit switches, it is expected to produce an ~DDT
pulse whose peak level is appreciably greater than IDDQ.
0-8186-7129-7/95$4.00 0 1995 IEEE
The Fourth Asian Test Symposium
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The iDDT pulse peak level is due to two components;
direct transient path between power and ground, and path
between the output of the switching gate (gates) and either
power or ground (depending on whether the circuit is
switching from a high state to a low state or from a low
state to a high state). Defects such as opens may prevent
the gate from having a normal conducting path between
power and ground during switching which can apprecia-
bly change the level of iDDp A power tree distribution
technique was presented in order to isolate normal current
transients from those which result from defects. Experi-
mental results on a small size SRAM (8K) indicate that
when combined together, ZDDQ and ZDDT present a formi-
dable test that can reduce the number of escaping defects
[31] 4331 (100% coverage of both read and write single
cell disturbs was obtained) using test lengths of 5n where
n is the number of cells.
In this paper, we investigate correlations between
SRAM opens, shorts, and cell disturbs as a function of cir-
cuit size. We attempt at qualifying the power supply cur-
rent detectability of these defects as a function of total
current leakage which is a function of SRAM size. Large
SRAMs are typically divided into a number of array
islands. The results presented in this paper can be used as
estimates on the size of arrays that can practically be
tested with power supply current.
II.Background
In this section we present simple examples on the
power supply current detectability of SRAM defects.
Throughout this paper, the following notation shall be
employed.
&i denotes the complete supply current
ZDDQ: denotes the level of the quiescent supply current
ZDDY denotes the peak value of the transient supply
current
~DDT:denotes the complete transient supply current
II. 1Z D ~ Example
e
Consider the SRAM cell of Figure 1-b and assume
367
 that there is a resistive bridge between the gate line of tran-
sistor m4 and the data line d connecting the gate of transis-
tor m4 to Vdd and the Bit line to GND results in a path
via the bridge between Vdd and GND. Such a path may
increase the level of JDDQ. In using IDDQ to detect the
fault, there are several issues. These issues include: the
B
the switching of ce112. Recently, Su et. al. [31] have pro-

(4
level of normal leakage into the power supply, the level of
current noise in the power supply, and the smallest current
resulting from a defect which can be detected by a sensor
[34]. If the level of IDDQresulting from a defect is outside
the design range (appreciably higher than the normal;
ZDDQ), the defect can be detected by a sensor. However, if
the level of ZDDQ resulting from a defect is not a p p i a -
bly different from the normal leakage level (lies within the
normal noise level or is smaller than the smallest defective
that can be detected by a sensor), the defect may not
be detected by testing. The remedy would be to parti-
GND
tion the circuit into segments that individually have lower (b)
normal leakage levels. These issues affect the selection of
a pass/fail value for ZDDQ limit. The ZDDQ limit settings Figure 1. Normal S R A M Cell Structure and Model
can significantly vary from circuit to circuit. posed a method for power supply distribution that uses an
additional test Vdd line for isolating normal iDDT pulses
II.2 iDDTExample from those resulting from defects. For convenience, Fig-
Assume that the drain of transistor m l is open in Fig- ure 3 shows an example of this power tree partitioning
ure 1-b and that the cell is initially set to logic 1. If the cell technique.
is intended to switch to logic 0 by applying a 0 to the bit
line and activating the word line, a normal iDDT pulse
would result. However, in the presence of the open, the
actual ZDDT level may be appreciably smaller than the
expected value. A current sensor can detect this difference
by allowing the iDDT pulse to charge a capacitor and using
an analog comparator to compare the resulting voltage to
a reference vdue. Now consider the cell pair of Figure 2.
If one performs a write operation to celll involving
switching of its state, only celll is expected to switch and
cell2 should be unaffected. However, in the presence of a
cell disturb, the state of cell2 may also switch as a result Figure 2. Cell Disturb Fault
of writing to celll. This results in a transient pulse due to

PassiFail
Vdd

. ,
System GND

Figure 3. Power Tree distribution for iDDT Observability

368

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 The SRAM utilizes one Vdd line (Vdd2) and one
GND line (GND2) dedicated for viewing abnormal ~DDT
pulses. In this scheme, if a particular cell is addressed, say
cell(l,l), its Vdd and GND lines get connected to the nor-
mal System power and GND lines. All other cells are con-
nected to either Vdd2, GND2, or both. The test power and
GND lines are connected to ~ D D Tsensors. If cell (1,l) dis-
turbs any other cell in the array, an abnormal iDDT pulse
will be sensed on either Vdd2 or GND2. The circuitry
required to perform the power tree distribution consists of
a pair of transistors per array column and a pair per array
row [31].
An iDDT sensor involves using the transient pulse to
charge a capacitor and comparing the resulting charge to a
reference value. In some respects, the design of the iDDT
sensor is simpler than that of ZDDQ because, in the latter
case, one has to not allow the transient pulse which pre-
cedes the quiescent current to disrupt the quiescent current
measurement. The issues involved in ~DDTtesting include:
the smallest pulse that can be detected by a sensor, the nor-
mal system noise levels, the normal amount of leakages,
and the amount of capacitance on the power supply con-
nected to the sensor. In the case of open faults, an impor-
tant issue is the open fault voltage because that could
affect the excitation of the power-GND path. Other issues
include the effects of power tree partitioning in terms of
performance degradation as addressed in [321.
III. Short Defects
In this section, we investigate the effect of shorts
including those that can cause faults on power supply cur-
rent levels. We considered five different resistive shorts.
Table 1 gives the simulation results for a 0 to 1 write
operation. Similar results were obtained for a 1 to 0 write
operation. The row labelled “good” represents the good
circuit response. The data were obtained by using a stan-
dard SRAM cell layout (from Cascade Logic tool set) and
performing Spice simulation using the HP 1.2 pm process
parameters. The LUDDQ/ AZDDT column refers to the
change in quiescent/transient current between the good
and faulty circuits. In the case of ~DDTa good measure is
the effect of the current (area of iDDT pulse) in terms of
charging the capacitor on the supply line connected to the
tester. This is quantified in the Test Vdd and Test AVdd
columns. Establishing detectability percentages requires
setting current limits to be used by the sensors. In the case
of ZDDQ, all shorts provide ZDDQ levels which are signifi-
cantly different than the good circuit levels when both
write operations (0 to 1 and 1 to 0) are performed. Thus
these defects should be easily detected by ZDDQ for any
reasonable current limit. In the case of iDDT, if we assume
a detect for up to a 1 V change in voltage, all the shorts
369
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are detected between the two sets of write operations.
However, practical size SRAh43 have much higher
leakage currents and much bigger capacitances on the
power supply connected to the current sensors. Both of
these factors can influence the current detectability of
defects as was discussed in Section 11. The effect of these
parameters is discussed in more detail in Section V.
IV. Open Defects
We considered five different open defects. An impor-
tant consideration is the voltage on the open which can be
due to parasitic capacitances. Table 2 shows the effect of
the open voltage on both ZDDQ and ZDDT for a double float-
ing gate defect. The open voltage was varied from 0.5 V
to 4.5V. The ZDDQ and ZDDT levels were recorded for a 0
to 1 write operation and 1 to 0 write operation. For the
write1 operation, the faulty current values approach the
good current values as the voltage in the open approaches
4.5 V, as is expected. However, for the write-0 Operation,
the faulty current responses increase as the voltage in the
open increases because the write operation results in a 1
on db (Figure 1) which in turn tries to pull the open to 0.
As a result, the open is being pulled high and low simulta-
neously giving rise to a Vdd to GND short which becomes
stronger as the open voltage is increased.
IaaaaBs
In the case of an open voltage of 0.5 V, two of the
opens were detected with the write-l operation and one
with the write-0 operation. Two of the opens result in a
AZDDQof approximately 1 pA (for the write-0 operation)
with normal leakage of 6.6 pA. This could result in a
detect depending on the levels of normal system noise
margins and the sensor characteristics. An appreciable
ZDDT difference results for all opens in the case of the
write 0 and write 1 operation. In the case of the double
floating gate defect, although we see an appreciable value
of NDDT(better than 50% change from normal ZDDT), the
resulting Test AVdd, which is a better measure, is less
than 50% of the normal value. Thus, the open may or may
not be detected depending upon variables such as normal
system noise and accuracy of the current sensor.
@eh ODen Voltage
An open voltage of 4 . W is probably unrealistic but
gives a sense of what happens to the current levels in
extreme situations. However, as we saw from Table 2, the
current detectability profile of the open does not signifi-
cantly change as the open voltage goes beyond 2.5 V. We
found that three of the opens may be detected with ZDDe if
the sensor can delineate a 1 pA change for normal operat-
 Short4 1601.889 I 1595.278 903.7 738.0 4951.6 3499.6
Short5 294.669 I 288.058 174.4 8.7 2759.3 1307.3

Table 2: Effect of Open Voltage for a Double Floating Gate Defect.

~~ ~ ~ ~-
Initial i Test
Cell Test ZDDQ NDDQ ZDDT MDDT Test Vdd
Voltage AVdd
(V) @A) (PA) (km @A) (mV)
(my)
Good N/A 0-->1 6.611 -i"- 165.7 1T.o 1480.6 0.0
1 -->0 6.612 0.OOO 168.4 0.0 1486.9 0.0
Defect 0.5 0--> 1 139.988 133.387 252.9 87.2 207 1.3 590.7
1 -->0 11.672 5.060 4.8 -163.6 1546.7 59.8
Defect 1.o 0-->1 111.321 104.710 226.5 60.8 1847.4 366.8
1--> 0 41.939 35.327 35.3 -133.1 1725.7 238.8
Defect 1.5 0--> 1 86.789 80.178 83.9 -82.7 1635.6 155.0
1--> 0 165.357 158.745 141.6 -26.8 2272.2 785.3
Defect 2.0 0-->1 64.341 57.730 54.3 -111.4 1467.3 -13.3
1--> 0 373.385 366.773 131.6 -36.8 2105.8 618.9
Defect 2.5 0--> 1 44.471 37.860 35.2 -130.5 1387.1 -93.5
1 -->0 594.439 587.827 120.6 -47.8 2430.3 943.4
Defect 3.5 0-->1 13.280 6.669 4.1 -161.6 1353.2 -127.4
1 --> 0 776.318 769.706 107.3 -61.1 2594.4 1107.6
Defect 4.5 0--> 1 6.774 0.163 1.3 164.0 1350.4 -130.2
1--> 0 765.904 759.292 110.9 -57.5 2694.1 1213.5

Table 3: InDeand i ~ Current

n ~ of the Five Types of Cell-Cell Shorts.

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 ing levels of 6 PA. Two of the opens are easily detected
by Z D D ~ with the write-0 operation. In iDDT testing, all
opens are detected except one open drain because the high
voltage on the open drain representing the output of the
inverter affects its switching characteristics only to a very
small extent.
V. Large Circuit Effects
In this section, we examine the current detectability
of SRAM shorts and opens as the level of normal current
leakage gets large and the value of the capacitance on the
test power bus connected to the tester gets large. We chose
two faults for this analysis: resistive bridge and double
floating gate. The SRAM size was varied from 10 cells to
10, 000 cells. Since Spice simulations run times are pro-
hibitive, the size of the SRAM was emulated by adding
leakage into the power supply and connecting a capacitor
on the power bus connected to the sensor. The SRAM
leakage and capacitance values of a single cell were used
to compute the estimates for the larger SRAM sizes. Fig-
ure 4 and 5 show a summary of the results. The Figures
indicate the percentage of change in current between the
good and faulty circuits for different values of normal
leakage currents. This data can be used to help determine
the maximum normal leakage current for a given sensor
measurement precision. In turn, this can help in power
tree partitioning and/or determination of number of sen-
sors required.

Figure 5.The Current Percentage Change vs the Leakage Current for

bndging Defect.

371

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 VI. Disturb Defects
In this section, we investigate the effect of disturb
faults on IDDQ and iDDT. We considered five bridging
defects between two SRAM cells. The test results are
given in table 3. It was found that defects 2,3, and 4 cause
cell disturbs when both cells are initialized to 0 and a
write-1 operation is performed on the top cell.We did not
employ the testable SRAM structure of Figure 3 which
would have made the defects easily detected by iDDT since
no iDDT pulse would have been expected on the supply
line of cell2 if only cell1 is written to. The test results
Show iDDT to detect dl disturb defects. None Of the dis-
turb-causing defects could be detected with IDDQ.
VII. Conclusions
In this paper, we studied the power supply current
detectability (both transient and quiescent) of various
SRAM defects. These defects include shorts, opens, and
disturbs. It was shown that when combined together, IDDQ
and iDDT form a strong test vehicle for reducing the number
of escaping defects. We also presented data on the effects
of large circuit parameters such as large leakages and
capacitance loading. This data can be used to estimate the
size of partitions for current testing.
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