2366
11, NOVEMBER 2006
SRAM Circuit With Expanded Operating Margin
and Reduced Stand-By Leakage Current
Using Thin-BOX FD-SOI Transistors
Masanao Yamaoka, Member, IEEE, Ryuta Tsuchiya, and Takayuki Kawahara, Senior Member, IEEE
Abstract—The deterioration of operating margin and increasing
leakage current in SRAM are becoming critical problems with the
advance of process scaling. To solve these problems, we propose
a low-power SRAM circuit using thin buried-oxide fully depleted
silicon-on-insulator transistors. The back-gate bias is introduced to
the SRAM circuits and acquires high operating margin and high-
speed operation under low supply voltage. The leakage current in
stand-by state is reduced. This SRAM achieves 30% faster writing
time under low-voltage operation and 90% less stand-by power.
Index Terms—Back-gate bias, low-leakage current, operating
margin, SRAM, thin buried-oxide fully depleted silicon-on-insu-
lator (thin-BOX FD-SOI) transistor.
I. INTRODUCTION
T ODAY, mobile devices are widely used, and they process
various applications, for example, dealing with a video
phone, playing TV programs or DVDs, and processing office
files. One of the key devices in these mobile devices is the
system-on-a-chip (SoC). The SoC embeds many modules, such
as the processor cores, hardware accelerators, various embedded
memories, and so on. Therefore, the SoC is required to have both
higher operating performance to process various applications
and lower power consumption to prolong the battery life. To ac-
quire the best performance, voltage scaling along with process
scaling is effective.
However, to continue the voltage scaling is now very difficult
because of the difficulty of the SRAM operation. The SRAM
cell is composed of the smallest size MOS transistors, which
are heavily influenced by the growing manufacturing-process
fluctuations [1]. Therefore, SRAM has many obstacles to over-
come to achieve low-voltage operation, such as reductions in
the static-noise margin (SNM) [2], writing margin [3], and op-
erating speed. The reduction in the operating margins is caused
by the threshold-voltage mismatch between the transis-
tors in one memory cell. The deterioration in the SRAM oper-
ating speed is caused by the reduction in the SRAM-cell current,
which is imposed by the reduction in the supply voltage and the
increase in the random variations with the advance of the
process scaling.
Manuscript received February 18, 2006; revised June 23, 2006.
The authors are with the Central Research Laboratory, Hitachi Ltd., Tokyo
185-8601, Japan (e-mail: yamaokam@crl.hitachi.co.jp).
Digital Object Identifier 10.1109/JSSC.2006.882891
0018-9200/$20.00 © 2006 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO.
Moreover, there is a large increase in the leakage current
of transistors. The leakage current is now a critical problem
to achieve a low-power SoC, especially in the SRAM mod-
ules, which need to retain their data while the other modules
are standing by. Therefore, SRAM supports the stand-by state
where it must retain its data with very little power consumption.
In this paper, we describe a SRAM circuit composed of thin
buried-oxide (BOX) fully depleted (FD) silicon-on-insulator
(SOI) transistor [4]. The of the thin-BOX FD-SOI tran-
sistor can be controlled by changing its well-node (back-gate)
voltage, like the back-gate bias used in bulk transistors, without
an increase in extra current. We effectively use this back-gate
bias effect and improve the operating margins and the operating
speed [7]. Moreover, its stand-by power is also reduced by
about 90%.
This paper is organized as follows. Section II presents a
back-gate controllable transistor, a thin-BOX FD-SOI tran-
sistor. Section III shows the high-operating margin SRAM,
in which the back-gate bias of memory cells in same column
is commonly controlled. Section IV describes the method to
reduce the SRAM cell leakage current for low stand-by power.
Section V shows the measurement results of the thin-BOX
FD-SOI transistor and the results of circuit simulation of newly
developed high-operating margin and low-leakage SRAM
circuits. Section VI concludes this paper.
II. THIN-BOX FD-SOI TRANSISTOR
Fig. 1 shows a cross-sectional view of a thin-BOX FD-SOI
transistor. This transistor has an ultrathin SOI thickness
nm and an ultra-thin BOX thickness nm .
This transistor is expected to be a low- variation device.
The FD-SOI structure controls the local component of
variation by almost completely eliminating the variation due
to channel-dopant distribution. A Ni-silicide gate (mid-gap
work-function metallic gate) and deep impurity doped under
channel are used to give the device a suitable value for
use in low-power circuits. The substrate is doped by means of
implantation through ultrathin SOI and BOX are used. The
is mainly determined by the work function of the metal gate;
this reduces the effects of fluctuation in , , and and
thus controls the global component of the variation.
The other important feature of this thin-BOX FD-SOI tran-
sistor is the back-gate-bias controllability. Because the BOX
layer is very thin, can be controlled by changing the voltage
of the well layer (back gate) under the BOX layer. This effect
YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS
Fig. 1. Cross-sectional view of the thin-BOX FD-SOI transistor.
is the same as the back-gate bias in the bulk transistor. How-
ever, the FD-SOI transistor has a BOX layer different from the
bulk transistor, and the well layer is isolated from the diffusion
regions by the BOX layer. Therefore, the p–n junction current
from the diffusion layer to the well layer does not flow even
when a forward-back-gate bias is applied. The back-gate-bias
technique can easily be used even in low-power SoCs. The back-
gate bias is applied through a well contact, which is formed
through the BOX layer. In this structure, a triple-well struc-
ture is used, and the back-gate node of each transistor is iso-
lated from the p-subtrate. The back gate of each transistor can
be individually controlled, because the well is also separated
from that of the adjacent transistor by using shallow trench iso-
lation (STI). Moreover, when not using the STI and connecting
the well layers, the back gates of the adjacent transistors can be
connected.
Fig. 2 shows the – characteristics when is 1.0 V. This
figure shows the drive current , the leakage current
and the substrate current . By using a forward back-gate
bias, can be increased by about 20%. By using a reverse
back-gate bias, can be reduced by about one order of mag-
nitude. Even if we apply some voltages to the back gate, the
substrate current does not increase. In the thin-BOX FD-SOI
transistor, the back-gate bias can be applied to the well layer
that is under the BOX layer. Because the BOX layer works as
capacitance, we use a MOS transistor symbol with capacitance
at the back-gate node for the symbol of the thin-BOX FD-SOI
transistor.
Fig. 3 shows a circuit symbol of the thin-BOX FD-SOI tran-
sistor. In the thin-BOX FD-SOI transistor, the back-gate bias
can be applied to under the BOX layer, which works as a capac-
itance. Therefore, in the symbol, a capacitance symbol is added
to a normal bulk transistor symbol.
III. HIGH-OPERATING MARGIN AND HIGH-SPEED SRAM CELL
In SRAM circuits, there are two access operations, read and
write, and each operation can defines its own operating margin,
read margin (SNM), and write margin. These two operating
margins have a tradeoff relationship [5]. Therefore, it is diffi-
cult to improve the both operating margin at the same time, and,
to improve both operating margins, the SRAM circuit has to be
controlled by the individual methods suitable for each operation.
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2367
Fig. 2. I –V characteristics.
Fig. 3. Symbol of thin-BOX FD-SOI transistor.
Fig. 4 shows a key structure to improve both read and write mar-
gins. We refer to the transfer MOS [the nMOS transistor whose
gate node is connected to the word line (WL)] as TrMOS, the
driver MOS (the nMOS transistor whose source node is con-
nected to ) as DrMOS, and the load MOS (the pMOS tran-
sistor in the memory cell) as LdMOS. The back-gate nodes of
, TrMOS and DrMOS (same side in memory cell) are connected.
The back-gate nodes of the transfer MOS (TrMOS in Fig. 4) and
the driver MOS (DrMOS in Fig. 4) in the same column are con-
nected through the well layer . The back-gate nodes
of the load MOS (LdMOS in Fig. 4) in the same column are
also connected through the well layer . Fig. 5 shows
the well structure of the memory-cell layout. The regions sur-
rounded by the bold lines are the well layers, which are the
back-gate nodes of the transistors. The well layer of one column
is isolated by STI. The back-gate biases are supplied through a
well contact, which is placed between the arrayed memory cells
and the sense and write amplifiers. Therefore, the back-gate
nodes and have relatively large loads and re-
quire some delays. This back-gate-node-voltage delay is dis-
cussed in Section V.
The back-gate nodes and are controlled
along with the SRAM operation. Fig. 6 shows the voltage
of the power-source nodes in each operating state. In this
circuit, the supply voltage of the core circuit is 1.0 V.
During read operation and nonaccessed cycle, and
are controlled to 0 V. The LdMOS is forward-biased, and
the of LdMOS is lowered. The lowered of LdMOS
helps prevent the data flip in the memory cell and improves
the SNM. During the write operation, the back-gate node of
the accessed columns and , are controlled
to a higher voltage than 0 V. The nMOS transistors in the
2368
Fig. 4. Circuit diagram of key structures of the proposed SRAM.
accessed columns are forward-biased, and the of TrMOS
and DrMOS is lowered. Moreover, the back-gate bias of the
LdMOS returns to the no-bias state, and its is raised.
These states are suitable for write operation, because the
write current from the memory-cell storage node to the bit
line (BLT, BLB) is large, and the data keeping current flowing
through the LdMOS is small. Therefore, the write operating
margin is improved. Moreover, the cell current flowing through
the TrMOS is large, and the operating speed increases. On
the other hand, in the nonaccessed column, the back-gate bias
of the transistors is the same as that during read operations.
Therefore, the data retention characteristics are good and are
protected from being destroyed in the nonaccessed column.
Fig. 7 illustrates the timing diagram. The ys[n] is the column-
select signal, and the bwen is the signal that indicates that new
data are written to the column. Thus, these structures enable the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
improvement of the read and write margins. On the write cycle,
at first the clock signal (CLK) arises, the word line (WL), the
column-select signal (y[0]) and the bit-write signal (bwen) are
activated, and a new data information is put to the bit-line pair
(BLT, BLB). The bwen signal is activated when a new piece of
data is written to the column. The back gates of the memory
cells in the accessed columns are controlled by the y[0] and
the bwen, and then the condition of the memory cells changed
to the state to which a new data is easily written. The back
gates in the memory cells of the other (nonaccessed) columns
are not controlled and the SNM (read margin) keeps high, and
the condition of the memory cells are keeping the state that the
data-retention characteristics are good. On the read cycle, the
back gates in the memory cells are controlled to the state to
keep the SNM high, and the data-retention characteristics are
good.
YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS 2369

Fig. 7. Timing diagram.

therefore the leakage current of the nMOS transistors is greatly

reduced. However, the leakage current of the pMOS transistors
is only slightly reduced. Conventionally higher pMOS tran-
sistors are used to match the leakage target, but this causes the
SNM deterioration during the read and write operations.
The right-hand state in Fig. 6 shows the voltage of the
power-source node during the stand-by state. The voltage
Fig. 5. Well structure with memory cell layout.
is 0.3 V to reduce the nMOS-transistor leakage current as the
conventional circuits. The back-gate voltage of pMOS tran-
sistors is 2.5 V; a higher level than 1.0-V (supply
voltage for core circuits). Therefore, the pMOS transistor is
reverse back-gate biased and the subthreshold leakage current
is drastically reduced. The back-gate voltage of 2.5 V is
the same as the supply voltage of the input/output (IO) circuits.
The thickness of the BOX layer in this SOI transistor is 10 nm,
and the reliability of the layer is not influenced by the higher
voltage application. The same voltage between the IO and
back-gate bias does not require an extra power generator to
produce the back-gate bias voltage, and, therefore, there is no
area or power penalty when using high-voltage bias in this
technique.
This voltage application is realized by using the circuit shown
in Fig. 4. When the STBY signal is asserted (and is low),
2.5-V power is supplied to the back-gate node . The thicker
gate–oxide transistors prevent the higher-voltage application to
the thinner gate–oxide transistor and protect its reliability.

Fig. 6. Voltage of the power-source node in each operating state. V. MEASUREMENT AND SIMULATION RESULTS
Fig. 8 shows a cross-sectional SEM micrograph of a fabri-
cated thin-BOX FD-SOI transistor. The thickness of BOX layer
IV. STAND-BY LOW-LEAKAGE MEMORY ARRAY is 10 nm and the thickness of SOI layer is 20 nm. The Ni-sili-
Reducing the leakage current during the stand-by state is a cide metal gate is properly produced.
very important issue for achieving a low-power SoC. In partic- Fig. 9 shows the measured of a fabricated nMOS device
ular, large memory modules that can be accessed from many as the back-gate bias is changed. The reverse back-gate bias
SoC functional blocks are required to retain their data during the raises the value, and the leakage current can be reduced. The
stand-by state. Raising the voltage of the source line of DrMOS forward back-gate bias lowers the value, and the on current
( in Fig. 4) can reduce the leakage current through the can be increased.
memory cells [6]. The higher voltages of than (ground Fig. 10 shows the simulated butterfly curves. The curves are
level) apply the back-gate bias to the nMOS transistors, and simulated by using a device-and-circuit mixed-mode simulator.

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2370 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 8. SEM micrograph.

Fig. 11. Simulated waveform.

Fig. 12. Write delay.

Fig. 9. I versus V when V is changed.

by using a device-and-circuit mixed-mode simulator. In this

Fig. 10. Static noise margin.
The arrows between the curves show SNM, which is the read
operation margin. These curves are simulated with 6- vari-
ation. The curve of the conventional one is simulated by using a
memory cell without back-bias control using the FD-SOI tran-
sistors. By using forward back-gate bias to the load transistor,
the SNM is improved. The forward back-gate bias lowers the
, and the lowering has large effect in the lower- re-
gion. Even under a 0.4-V supply voltage, the SNM value is
enough high to operate correctly.
Fig. 11 shows the simulated waveforms of the voltages of
memory-cell storage nodes, WL, and back-gate nodes during
the write operation in a 128-row 256-column SRAM array,
when the supply voltage is 0.4 V. The curves are also simulated
simulation, the variation is considered, and the condition is
severe for the write operation. The curves of the conventional
one are simulated by using a memory cell without back-bias
control using the FD-SOI transistors. The write characteristics
are improved and the write speed increases. In Fig. 11, the
speed of changing the voltages of the back-gate nodes
and is slow, because these nodes have large loads, as
explained in Section III. However, when the voltages of the
back-gate nodes are changed to a certain level, the storage node
voltage is flipped, the write operation is completed, and the
necessary time to complete the write operation is sufficiently
shorten. This means that, even if the back-gate nodes have large
loads, the write characteristics are improved. Of course, if the
number of rows becomes larger, the change of voltage needs
a longer time, and the write time gets longer. Therefore, the
number of rows has to be adequately designed.
The delay times from WL activation to the low-node rise
are shown in Fig. 12. The delay time is greatly improved, es-
pecially in the lower supply voltage region, and the operating
speed under a 0.4-V supply voltage is improved by about 30%.
Fig. 13 shows the leakage-current estimation when using a
65-nm process. A 1.0-V supply voltage is assumed. The normal
leakage indicated the leakage-current values of one memory
cell without any leakage reduction techniques. The conventional
process indicated that with a conventional leakage-reduction
technique [6]. Using only the conventional-leakage reduction
technique, the subthreashold leakage of the pMOS transistor

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YAMAOKA et al.: SRAM CIRCUIT USING THIN-BOX FD-SOI TRANSISTORS 2371

this back-gate controllable SRAM can operate at a faster speed

under the same supply voltage. When decreasing its supply
voltage to the minimum voltage, under which the SRAM can
operate at the same speed, the power consumption is reduced to
a level that is almost equal to that of the conventional SRAM.
In this estimation, the supply voltage of conventional circuit is
assumed as 0.9 V, and the decreased supply voltage is assumed
to be 0.8 V. Moreover, if the SRAM modules have a bank
structure, more power is consumed in the bank-control circuit,
and the power-increase ratio in the back-bias-control circuit is
smaller.

VI. CONCLUSION

We propose a high-performance and low-leakage SRAM

circuit that uses the thin-BOX FD-SOI transistor, whose
back-gate bias can be controlled. The back-gate bias effect was
confirmed using a 10-nm BOX device. Applying this device to
the SRAM circuit in a 65-nm process and using the back-gate
bias effectively, the operating margin of the SRAM cell is im-
proved and the SRAM circuit acquires a 30% faster write time
and 90% leakage reduction. This performance is suitable for
the next-generation SoCs required in next-generation mobile
applications.
Fig. 13. Leakage current of one memory cell in a 65-nm process.

ACKNOWLEDGMENT

The authors would like to thank K. Itoh, S. Kimura, K. Osada,

K. Yanagisawa, K. Ishibashi, and S. Maegawa for their valuable
discussions and advice, and N. Irie for managing and encour-
aging the project.

Fig. 14. Active-power consumption comparison.
cannot be sufficiently reduced, however, this technique can re-
duce the leakage current. In a 65-nm process, the gate-leakage
current is also one of the greatest leakage-current factors.
Therefore, under room temperature (25 C), accounts for a
large percentage of the total leakage current of the memory cell,
thus reducing the effectiveness of our work. However, at higher
temperatures, the increases and the effects of this work are
quite large.
Fig. 14 shows the active power of a 32-kb SRAM module.
This module has one 128-row 256-column array, and the
memory cell size is assumed as about 0.6 m . This back-gate
bias control SRAM needs extra power to control the back-gate
node. The value of conventional is simulated by using a memory
cell without back-bias control using the FD-SOI transistors.
The increase in the active power was about 27% when com-
pared with the same supply voltage and frequency. However,
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2372
Masanao Yamaoka (M’01) was born in Fukuyama,
Japan, in 1973. He received the B.E. and M.E. de-
grees in electronics and communication engineering
from Kyoto University, Kyoto, Japan, in 1996 and
1998, respectively.
In 1998, he joined the Central Research Labo-
ratory, Hitachi Ltd., Tokyo, Japan, where he has
been engaged in the research and development of
low-power embedded SRAM and CMOS circuits.
His current research interests include handling V
variation in circuit design.
Ryuta Tsuchiya received the B.S., M.S., and Ph.D.
degrees in material science from the Tokyo Institute
of Technology, Tokyo, Japan, in 1993, 1995, and
1998, respectively.
He joined the Central Research Laboratory,
Hitachi Ltd., Tokyo, Japan, in 1998, where he
has been engaged in research on fabrication and
characterization of high-performance and low-power
MOSFETs including thin-film SOI and BOX
transistors.
Dr. Tsuchiya is a member of the Japan Society of
Applied Physics.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
Takayuki Kawahara (M’91–SM’98) received
the B.S. and M.S. degrees in physics and the
Ph.D. degree in electronics from Kyusyu Univer-
sity, Fukuoka, Japan, in 1983, 1985, and 1993,
respectively.
In 1985, he joined Central Research Laboratory,
Hitachi Ltd., Tokyo, Japan. Since then, he has made
fundamental contributions in many areas in the field
of low-power high-speed memories. In the field
of DRAM circuits, from 1985 to 1993, his major
contributions concerned low-power, low-voltage
circuits including subthreshold-current reduction by gate-source self-reverse
biasing technique and an over-drive sense-amplifier scheme coupled with
direct sensing. He also pioneered the charge-recycling scheme, which concept
is now widely applied to various circuits. In the field of Flash memory,
from 1994 to 1998, he and his team developed a bit-line clamped sensing
scheme for fast sensing, a high-voltage generator scheme under a low voltage
supply, and a pioneering high-speed programming method. In addition, he
headed the ultralow-power system LSI project in the laboratory from 1999 to
2002. Currently, his mission is exploring a new concept memory. He was a
Visiting Researcher with the Electronics Laboratory, Swiss Federal Institute of
Technology Lausanne, Lausanne, Switzerland, from 1997 to 1998. He was a
Guest Editor of the Memory section of a special issue of the IEEE JOURNAL
OF SOLID-STATE CIRCUITS in November 2002. He has been a member of
the ISSCC program committee since 2000 (also a member of the executive
committee since 2004), and a program committee member of the Symposium
on VLSI Circuits since 2003 and Secretary of Publicity of the 2006 JFE Circuits
Symposium Committee.