SRAM Variability Measurements

Faculty Investigator: Borivoje Nikolić, University of California, Berkeley

IBM Technical Contact: Kevin Nowka, IBM Austin Research Laboratory
Description
SRAM arrays occupy a large fraction of the chip area in many of today’s digital designs. As memory will continue to
consume a large fraction of many future designs, scaling of memory density must continue to track the scaling trends of
logic. Increased transistor leakage and parameter variations present challenges for scaling of conventional six-
transistor (6-T) SRAM cells. Statistical dopant fluctuations, variations in oxide thickness, and line-edge roughness
increase the spread in transistor threshold voltage and thus the on- and off- currents as the MOSFET is scaled down in
the nanoscale regime.
The functionality and density of a memory array are its most important properties. Functionality is guaranteed for large
memory arrays by providing sufficiently large design margins (to be able to be read without changing the state, to hold
the state, to be writable and to function in specified time), which are determined by device sizing (channel widths and
lengths), the supply voltage and, marginally, by the selection of transistor threshold voltages. Although upsizing the
transistors increases the noise margins, it increases the cell area and thus lowers the density. Since the control of
process variables does not track the scaling of minimum features, design margins would need to be increased to achieve
large functional memory arrays. This trend reverses the advantages of technology scaling, and has been perceived as a
major roadblock.

We plan to experimentally investigate the impact of the SRAM cell design and bitline column design on stability of the
memory. A test structure will be built that measures the distribution of the key design margins within the array. Various
arrays will be tested that differ in layouts and sizes of the memory cells as well as in different bitline organizations.
The key challenge in this project is to develop a test structure and an on-chip measurement circuitry that allows for
direct or indirect observation of noise margins within individual cells or groups of cells. Our approach relies on precise
on-chip current measurements with on-chip analog-to-digital conversion of measured values. This measurement will
involve obtaining:
1. Read currents vs. bitline leakage scatter plots for the cells in the array,
2. Estimation of the static noise margins in the cells
3. Estimation of the hold margins.
Read current, which is below 100uA in modern CMOS memories, can be accurately measured, e.g. using a single-slope
or a dual-slope analog-to-digital converter (ADC) that would be integrating the read current over the specified period of
time. In our previous projects we have demonstrated to be able to measure currents with 1-10nA accuracy. Measuring
the bitline leakage currents for short bitlines is significantly more challenging (currents are sub-1nA), requiring a
refinement in the measurement circuitry and the use of a dual-slope ADC. By writing various data into the cells and
then accessing them, a map of read and leakage currents can be obtained. Since the variations in the leakage currents
are larger than in read currents, because of their exponential dependence on the technology parameters, even low-
resolution measurements should provide interesting data when correlated with read currents.
Distribution of the SNMs in the array can be measured by dissecting the SRAM cells in halves and using a high-
resolution ADC. Alternatively, a distribution of SNM can be estimated by measuring the currents vs. voltages in the
cell storage nodes (these are known as ‘N-curves’ in IBM).

Finally, by lowering the wordline voltages during cell access either read/write access fails, another distribution in the
array can be achieved. Supply voltage can also be lowered and raised until the cell fails. The plot of minimum
voltages at which the hold margin is not compromised is yet another indication of variability.

Project objectives and goals

Objective of this research is to provide a methodology for on-chip measurements of variability in SRAM, as well as to
experimentally quantify the impact of the cell sizing and layout on a tradeoff between the density and stability. This
goal would be achieved through a theoretical study of variations in the memory and building of a test chip in 90nm or
65nm CMOS technology that evaluates the proposed ideas. Ultimately, the data collected through these experiments
will be used to design robust dense memory arrays. The measurement circuitry can be used for other precise on-chip
current and voltage measurements.

Long-term impact
Deceleration in memory scaling has been perceived as one of the major roadblocks to future technology scaling. The
measurement results from this project can be used to extend the scaling of static memory and CMOS technology in
general.