9th International Symposium on Quality Electronic Design
Statistical Data Stability and Leakage Evaluation of
FinFET SRAM Cells with Dynamic Threshold Voltage
Tuning under Process Parameter Fluctuations
Zhiyu Liu, Sherif A. Tawfik, and Volkan Kursun
Department of Electrical and Computer Engineering
University of Wisconsin – Madison
Madison, Wisconsin 53706 - 1691
Abstract – A new six transistor (6T) FinFET static memory
cell with dynamic access transistor threshold voltage
tuning is evaluated in this paper for statistical power and
stability distributions under process parameter variations.
The independent-gate (IG) FinFET SRAM cell activates
only one gate of the double-gate data access transistors
during a read operation. The disturbance caused by the
direct data access mechanism of the standard 6T SRAM
cell topology is significantly reduced by dynamically
increasing the threshold voltage of the access transistors.
All the transistors in the presented SRAM cell are sized
minimum without producing any data stability concerns.
The average read static-noise-margin of the statistical
samples with the independent gate bias technique is 82%
higher as compared to the standard tied-gate FinFET
SRAM cells under process variations. Furthermore, the
IG-FinFET SRAM circuit reduces the average leakage
power and the cell area by up to 53.3% and 17.5%,
respectively, as compared to the standard tied-gate
FinFET SRAM circuits sized for comparable data stability
in a 32nm FinFET technology.
Index Terms – Cache memory, static noise margin
distribution, robust operation, active power, standby
power distribution, double gate MOSFET, process
variations.
I. INTRODUCTION
The channel length of the conventional single-gate
transistors has been scaled from 2μm to 45nm over the past 20
years. The subthreshold and gate-dielectric leakage currents
and the enhanced device sensitivity to parameter fluctuations
are currently the primary barriers against further device
scaling [1]. As the channel length of a conventional single-
gate-MOSFET is reduced to the nanometer scale, the drain
potential begins to strongly influence the channel potential,
thereby causing significant subthreshold leakage current.
Furthermore, the gate dielectric thickness has been reduced to
a point where the power drained by the gate tunneling current
is comparable to the power consumed due to switching
activity [1].
The multi-gate FinFETs offer significant advantages for
suppressing the subthreshold and the gate dielectric leakage
currents in the deeply scaled nanometer technologies [1]-[2].
The structure of a FinFET is shown in Fig. 1. The two
electrically coupled gates (front and back gates in Fig. 1b) and
the thin silicon body of the FinFET reduce the short-channel
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effects, thereby suppressing the subthreshold leakage current.
The suppressed short-channel effects and the enhanced gate
control over the channel area permit the use of a thicker gate
oxide in a FinFET as compared to a conventional single-gate
transistor. The gate oxide leakage current is thereby
significantly reduced in the FinFET technologies. FinFET is
currently the most promising device candidate for continuing
the CMOS technology scaling process to the 32nm technology
node and beyond [1]-[2].
The FinFET technology provides a unique design flexibility
where the multiple gates can be tied or independently biased
[3]. An independent-gate (IG) FinFET resembles two single-
gate-MOSFETs in parallel, sharing a common thin body. A
single IG-FinFET is, for instance, sufficient to implement
either the pull-up network of a two-input NAND gate or the
pull-down network of a two-input NOR gate [5]. Compact
CMOS circuits with reduced number of transistors based on
IG-FinFET technologies have been reported in the literature
[4]-[5].
Lowering of voltages and smaller device dimensions lead to
a significant degradation in SRAM cell data stability with the
scaling of CMOS technology. Maintaining the data stability of
SRAM cells is expected to become increasingly challenging
as the device dimensions are scaled to the sub-45nm regime.
In addition to the data stability issues, SRAM arrays are also
an important source of leakage due to the enormous number of
transistors in the memory caches. The development of a new
SRAM cell that can provide higher data stability and lower
leakage power characteristics with the emerging FinFET
technologies is highly desirable.
A new six-transistor (6T) SRAM cell exploiting the unique
threshold voltage modulation aspect of the independent-gate
FinFETs for providing lower power consumption, higher
memory integration density, and enhanced data stability is
presented in this paper. The new IG-FinFET SRAM cell
provides two separate data access mechanisms for the read
and write operations. During a read operation, the threshold
voltage of the access transistors is dynamically increased,
thereby suppressing the coupling between the data storage
nodes and the bitlines. The average read SNM of the new IG-
FinFET SRAM cell is thereby enhanced by up to 82% as
compared to the standard tied-gate FinFET SRAM cells under
process parameter variations. Due to the enhanced data
stability, all of the six transistors of the new IG-FinFET
SRAM cell are sized minimum without causing any reliability
concerns. The average leakage power consumption and area
305
 of the IG-FinFET SRAM cell are thereby reduced by up to
53.3% and 17.5%, respectively, as compared to the 6T tied-
gate FinFET SRAM cells.
The paper is organized as follows. The FinFET operation is
described in Section II. The new IG-FinFET SRAM cell is
presented in Section III. Data stability, power, and delay
characteristics of the standard tied-gate and the new IG-
FinFET SRAM cells are compared under process parameter
variations in Section IV. Finally, some conclusions are offered
in Section V.
The maximum drain current produced at the DGM is therefore
2.6 times higher as compared to the SGM, as illustrated in Fig.
2. The unique Vt modulation aspect of IG-FinFETs through
selective gate bias is exploited in this paper to dynamically
tune the read and write strength of the access transistors in
SRAM circuits.

Fig. 2. Drain current density of an n-type IG-FinFET. VDS = 0.8V.

III. SRAM CELLS

The design considerations for the reliable operation of 6T
SRAM circuits with the standard single-gate MOSFETs and
the emerging FinFETs are provided in this section. The tied-
Fig. 1. The multi-gate FinFET structure. (a) 3D structure of the one-fin
FinFET. (b) Cross sectional top view of the FinFET.
gate FinFET SRAM cells are presented in Section III-A. The
new IG-FinFET SRAM circuit is described in Section III-B.
II. FINFET TECHNOLOGY A. Standard Tied-Gate FinFET SRAM Cells
The physical and electrical characteristics of the n-type and The operation of a 6T FinFET SRAM cell is similar to a
the p-type FinFETs are presented in this section. The FinFETs conventional 6T single-gate-FET SRAM circuit [6]. Similar to
used in this paper have a symmetrical structure, as shown in the SRAM circuits with standard single-gate MOSFETs, there
Fig. 1. The physical parameters used for MEDICI simulations are strict constraints on the sizing of transistors to be able to
are listed in Table I [8]. The minimum channel length and the maintain the data stability and functionality of a 6T SRAM
fin height are 32nm. VDD is 0.8V. cell in a FinFET technology. Despite the similarity of the
TABLE I design constraints, however, the transistor sizes from a
DEVICE TECHNOLOGY PARAMETERS conventional single-gate-FET CMOS technology can not be
Parameter Value directly transferred to a FinFET technology due to the
Channel length (Lgate) 32nm
quantization of the FinFET width. A tied-gate FinFET SRAM
Effective channel length (Leff) 25.6nm
Fin thickness (Tfin) 8nm cell with parameterized sizing (N) for the pull-down
Fin height (Hfin) 32nm transistors is illustrated in Fig. 3.
Oxide thickness (Tox) 1.6nm
Channel doping 1015cm-3
Source / Drain doping 2 x 1020cm-3
Gates work function (NMOS) 4.5eV
Gates work function (PMOS) 4.9eV

The width of a FinFET is quantized due to the vertical gate

structure. Since the fin height (Hfin) is fixed (determined by
the technology), multiple parallel fins are utilized to increase
the width of a FinFET. The total physical transistor width of
an IG-FinFET with n parallel fins is
WIG-total = n × (2 × Hfin). (1)
Fig. 3. The tied-gate FinFET SRAM cell. The size of each transistor is given
An IG-FinFET provides two different active modes of as (number of fins × Hfin) / Lgate. Hfin: fin height. Lgate: channel length.
operation. In the Dual Gate Mode (DGM), the two gates are
biased with the same signal to control the formation of a Three tied-gate FinFET SRAM cells with different sizes are
considered in this paper. All of the six transistors in the first
conducting channel. Alternatively, in the Single Gate Mode
FinFET SRAM cell (SRAM-DG-1) are sized minimum (one
(SGM), one gate is biased with the input signal to induce fin, N = 1). The widths of the pull-down transistors in the
channel inversion while the other gate is disabled. The cross-coupled inverters of the second SRAM cell (SRAM-
variation of the drain current of an n-type IG-FinFET for two DG-2) are double sized (two fins, N = 2) to enhance the data
different operating modes is shown in Fig. 2. The threshold stability as compared to SRAM-DG-1. The widths of the pull-
voltage (Vt) is lowered at the DGM as compared to the SGM. down transistors in the cross-coupled inverters of the third

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 SRAM cell configuration (SRAM-DG-3) are triple sized
(three fins, N = 3) for further enhancing the data stability. This
standard approach of achieving higher data stability through
transistor sizing, however, comes at a significant cost of
increased active and standby mode power and larger cell area.
B. New IG-FinFET SRAM Cell
A six transistor SRAM cell based on an IG-FinFET
technology [9], [10], [14] is presented in this section for
simultaneously reducing the active and standby mode power
consumption while enhancing the data stability and the
integration density. The IG-FinFET SRAM cell is shown in
Fig. 4. All the transistors have single fin (minimum width).
The transistors in the cross-coupled inverters are tied-gate
FinFETs. Alternatively, the access transistors are independent-
gate FinFETs. An IG-FinFET has a higher threshold voltage
(high-Vt) in the SGM as compared to the DGM as described
in Section II. The unique Vt modulation aspect of IG-FinFETs
through selective gate bias is exploited with the new technique
by dynamically tuning the read and write strength of the
access transistors in SRAM circuits. One gate of each access
transistor is controlled by a read/write signal (RW). The other
gate of each access transistor is controlled by a separate write
signal (W), as shown in Fig. 4.
The operation of the IG-FinFET SRAM cell is as follows.
Both RW and W signals are maintained low in an un-accessed
SRAM cell. The two access transistors are cut-off. The data is
maintained by the cross-coupled inverters whenever a cell is
not accessed. To start a read operation, RW signal transitions
high while W is maintained low. Provided that Node1 stores
“0”, BL is discharged through N3 and N1. Alternatively,
provided that Node2 stores “0”, BLB is discharged through
N4 and N2. As compared to the tied-gate FinFET SRAM-
cells, the access transistors N3 and N4 act as high-Vt devices
with weaker current conducting capability during a read
operation with the independent-gate-bias technique. The
intrinsic data disturbance that occurs due to the direct-data-
read-access mechanism of the 6T SRAM cell topology is
thereby significantly suppressed and the read stability is
enhanced with this technique.
Alternatively, to start a write operation, both RW and W
transition high. The two access transistors N3 and N4 act as
strong low threshold voltage (low-Vt) devices. Write ability is
thereby achieved with minimum sized access transistors
operating in the DGM. The write speed of an IG-FinFET
SRAM circuit is similar to SRAM-DG-1 with identical
transistor sizing.
Fig. 4. The IG-FinFET SRAM cell. The size of each transistor is given as
(number of fins × Hfin) / Lgate.
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Due to the enhanced data stability, all six transistors of the
IG-FinFET SRAM cell are sized minimum. The cell area is
reduced as compared to the tied-gate FinFET SRAM cells
which need to be sized significantly larger for similar data
stability. The memory integration density of the SRAM-IG
circuit is, therefore, significantly enhanced. Furthermore, the
leakage power consumption of the SRAM-IG is suppressed
since the total effective transistor width that produces the
leakage current is reduced as compared to the tied-gate
FinFET SRAM cells.
IV. SIMULATION RESULTS
The read stability, active mode power, speed, and leakage
power of the three tied-gate FinFET SRAM cells and the IG-
FinFET SRAM cell (SRAM-IG) are compared in this section.
The three tested tied-gate FinFET SRAM cells are: SRAM-
DG-1, SRAM-DG-2, and SRAM-DG-3 as described in
Section III-A. The transistor sizing of the SRAM cells are
shown in Figs. 3 and 4. Active mode data are measured at
70°C. Leakage power consumption is measured at both 70°C
and 27°C in order to evaluate the effectiveness of the
presented technique for suppressing leakage over the entire
range of a typical memory temperature spectrum. The leakage
reduction and the data stability enhancement provided by the
SRAM-IG are verified with the statistical data produced under
process parameter variations in a 32nm FinFET technology.
A. Read Stability
Static noise margin (SNM) is the metric used in this paper
to characterize the read stability of the SRAM cells. The SNM
is the minimum DC noise voltage that can flip the state of an
SRAM cell [7]. When Node1 of the SRAM cells is maintained
at VDD, Node2 rises to a voltage higher than Vgnd due to the
voltage division between the access transistors and the pull-
down devices of the cross-coupled inverters. The Node2
voltage and SNM of the different SRAM circuits during a read
operation are listed in Table II.
The transistors in SRAM-DG-1 and SRAM-IG cells are
sized identical (W = Wmin for all the transistors). As listed in
Table II, the disturbance induced at Node2 during a read
operation is significantly suppressed by dynamically
increasing the Vt of the access transistors with the SRAM-IG
as compared to the SRAM-DG-1. The Node2 of SRAM-DG-1
and SRAM-IG rises to 80mV and 30mV, respectively, during
a read operation. The read SNM of the SRAM-IG is enhanced
by 2× as compared to the SRAM-DG-1 despite the identical
transistor sizing with the two techniques, as listed in Table II.
TABLE II
READ SNMS AND NODE2 VOLTAGES
SRAM Cell Read SNM (mV) Node2 Voltages (mV)
SRAM-DG-1 120 80
SRAM-DG-2 210 30
SRAM-DG-3 220 20
SRAM-IG 240 30
The pull-down devices of SRAM-DG-2 and SRAM-DG-3
are sized 2× and 3× larger, respectively, as compared to the
access transistors for enhanced read stability. SRAM-DG-2
and SRAM-DG-3 therefore experience a smaller voltage
 disturbance at Node2 as compared to SRAM-DG-1 during a unintentional read access to the inactive blocks does not
read operation. SRAM-IG has a similar Node2 voltage produce a data stability problem with the SRAM-DG-2 and
disturbance as compared to SRAM-DG-2 and SRAM-DG-3 the SRAM-DG-3 which are sized for read stability.
(difference less than 10mV), as listed in Table II. SRAM-IG Alternatively, for an interleaved cache architecture with the
however has relatively stronger pull-up strength in the cross- SRAM-DG-1 or the SRAM-IG cells, the unintentionally
coupled inverters as compared to both SRAM-DG-2 and accessed cells in the inactive blocks could lose data during a
SRAM-DG-3, thereby having a stronger immunity against the write operation since the access transistors are fully activated
data disturbance caused by a read access. The read SNM of and the cross-coupled inverters are sized minimum. The
SRAM-IG is 14.3% and 9.1% higher as compared to the read SRAM-IG and the SRAM-DG-1 are, therefore, not suitable
SNMs of SRAM-DG-2 and SRAM-DG-3, respectively. for an interleaved cache architecture.
B. Leakage Power Consumption
The IG-FinFET SRAM cell also lowers the total leakage
power. When an SRAM cell is in the idle mode, the access
transistors are cut-off and the bitlines are charged to VDD. The
WL of the tied-gate FinFET SRAM cells is maintained at
Vgnd. Similarly, both the RW and W signals are maintained at
Vgnd in the idle/unaccessed SRAM-IG cells.
The leakage power consumption of the SRAM cells at 70°C
and 27°C are compared in Fig. 5. The leakage power of an
SRAM cell is determined by the total effective transistor
width that produces the leakage current. In SRAM-DG-1 and
SRAM-IG, the transistors that produce the leakage current
have minimum width. SRAM-DG-1 and SRAM-IG therefore
consume the lowest leakage power. Since SRAM-DG-3 has
the largest total transistor width, SRAM-DG-3 consumes the
highest leakage power in the idle mode. The leakage power
consumed by SRAM-IG is 51.7% and 53.5% lower at 70°C
and 27°C, respectively, as compared to SRAM-DG-3.

Fig. 5. The normalized leakage power consumptions of the FinFET SRAM
cells at 70°C and 27°C. For each SRAM cell, the leakage power is normalized
with respect to SRAM-DG-1 at the same temperature.
C. Area and Application Discussion
The layouts of SRAM-DG-1, SRAM-DG-3, and SRAM-IG
(with the thin-cell memory layout style [11]-[12]) are shown
in Fig. 6. The fin pitch is assumed to be 6 times the fin
thickness [2] in the layouts.
SRAM-DG-3 has the largest area since the pull-down
transistors in the cross-coupled inverters have three fins.
SRAM-DG-1 and SRAM-IG have the smallest area. The area
of SRAM-IG is 17.5% smaller than SRAM-DG-3.
In the interleaved caches, the SRAM cells in each row are
grouped into different blocks (banks). When a row of cells in
an active block is selected, the cells in the corresponding row
of the inactive blocks are also simultaneously accessed. This
Fig. 6. Thin-cell layouts of the FinFET SRAM cells. (a) SRAM-DG-1. Area =
0.23µm2. (b) SRAM-DG-3. Area = 0.28µm2. (c) SRAM-IG. Area = 0.23µm2.
The area of each SRAM cell is determined by a dotted rectangle. The contacts
that would be shared by the adjacent cells in a memory array are intersected by
the dotted lines for an accurate per-cell area calculation.
D. Active Mode Power and Speed
The parasitic capacitance of the access transistors attached
to the bitlines is extracted for each FinFET SRAM cell based
on the “thin-cell” layouts. The length of the bitlines is
estimated based on the cell layout height. A Π-type RC
network that represents the bitline parasitics of a 256-bit
SRAM column is attached to the FinFET SRAM circuits. The
read delay is the time period from the 50% point of the WL
(RW in case of the SRAM-IG) low-to-high transition until a
200mV voltage difference is developed between BL and BLB.
The normalized active mode power and delay of the four
FinFET SRAM circuits are shown in Fig. 7. The power and

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 delay of each SRAM circuit are normalized to the power and
delay of SRAM-DG-1.
Fig. 7. The active mode power and delay of the SRAM circuits. For each
SRAM circuit, the power and delay are normalized with respect to SRAM-
DG-1.
All of the FinFET SRAM cells have a similar bitline length.
SRAM-IG and SRAM-DG-1, therefore, have similar write
power and write delay. Since SRAM-DG-3 has the highest
capacitance at the data storage nodes, the write power and the
write delay of SRAM-DG-3 are 12.8% and 51.2% higher,
respectively, as compared to SRAM-IG.
The pull-down devices of the cross-coupled inverters of
SRAM-DG-2 and SRAM-DG-3 are sized 2× and 3× larger,
respectively, as compared to SRAM-DG-1. The read delays of
SRAM-DG-2 and SRAM-DG-3 are therefore 57.1% and
71.4% lower, respectively, as compared to SRAM-DG-1. The
read delay of the SRAM-IG is increased by 57.1% as
compared to the SRAM-DG-1 due to the dynamically
increased threshold voltage of the access transistors during a
read operation.
The SRAM-IG has the lowest voltage disturbance at the
node which stores “0” during a read operation. The cross-
coupled inverters of the SRAM-IG, therefore, produce the
lowest static DC current during a read access. The read power
consumption of the SRAM-IG is 8.6% lower as compared to
the SRAM-DG-1.
E. Process Variations
Random and systematic fluctuations in the channel length,
the silicon body thickness, the fin height, and the gate oxide
thickness cause variations in the FinFET characteristics. The
read stability of a 6T SRAM cell is primarily determined by
the ratio of the current produced by the access transistors and
the NMOS transistors in the cross-coupled inverters. The
relative strength of the NMOS transistors in the inverters can
vary as compared to the access transistors due to process
parameter fluctuations. The read stability, therefore, fluctuates
with the process parameters. Furthermore, the subthreshold
and gate oxide leakage currents vary with the fluctuations of
the threshold voltage and the gate oxide thickness, thereby
inducing variations in the leakage power consumption of the
SRAM cells.
In this section, read stability and leakage power variations
of the FinFET SRAM cells due to process fluctuations in the
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gate length (Lgate), the silicon body thickness (tsi), the fin
height (Hfin), and the gate oxide thickness (tox) are evaluated.
Lgate, tsi, Hfin, and tox are assumed to have independent normal
Gaussian statistical distributions. Each parameter is assumed
to have a three sigma (3σ) variation of 10% [13]. Monte Carlo
simulations are run to evaluate the read stability and the
leakage power statistical distributions. The distributions of the
read SNM of the FinFET SRAM cells at 70°C are shown in
Fig. 8. The statistical data for the read SNM of the FinFET
SRAM cells are listed in Table III.
Fig. 8. The statistical distributions of the read SNMs of SRAM-DG-1, SRAM-
DG-3, and SRAM-IG under process parameter variations. T = 70°C.
TABLE III
AVERAGE AND STANDARD DEVIATION (SD) OF SNM OF THE
FINFET SRAM CELLS AT 70°C
Read SNM (mV)
Average Standard Deviation
SRAM-DG-1 122 9
SRAM-DG-3 207 3
SRAM-IG 222 3
SRAM-IG has the highest average read SNM among all of
the FinFET SRAM cells. The average read SNM of the
SRAM-IG is 82% and 7.2% higher as compared to the
SRAM-DG-1 and the SRAM-DG-3, respectively. The read
SNM distribution curves of the SRAM-DG-3 and the SRAM-
IG cross at 214mV, as shown in Fig. 8. Read SNMs of 99.7%
of the samples with the SRAM-IG are higher than 214mV.
Alternatively, 98.7% of the statistical samples with the
conventional SRAM-DG-3 have read SNMs lower than
214mV.
The distributions of the leakage power consumption of the
FinFET SRAM cells at 70°C and 27°C are shown in Figs. 9
and 10, respectively. The statistical data for the leakage power
consumption of the FinFET SRAM cells are listed in Table
IV. The leakage power distribution curves of SRAM-DG-3
and SRAM-IG cross at 18nW at 70°C, as shown in Fig. 9.
Leakage power consumption of 99.5% of the samples with the
SRAM-IG technique is lower than 18nW. Alternatively,
99.5% of the samples with the conventional SRAM-DG-3
consume leakage power higher than 18nW. The average
leakage power consumptions of SRAM-DG-3 and SRAM-IG
are 25.6nW and 12.5nW, respectively, at 70°C as listed in
Table IV. A 51.2% and 53.3% average leakage power
 reduction is provided with the SRAM-IG as compared to the Due to the enhanced stability of the stored data, all of the
SRAM-DG-3 based on the statistical data produced under transistors in an IG-FinFET SRAM cell are sized minimum.
process parameter variations at 70°C and 27°C, respectively. The area of the IG-FinFET SRAM cell is, therefore, 17.5%
smaller than a tied-gate FinFET SRAM cell with comparable
data stability.
The leakage power reduction and the read stability
enhancement provided by the IG-FinFET SRAM technique
are evaluated with the statistical data produced under process
parameter variations in a 32nm FinFET technology. The
average leakage power consumption of the IG-FinFET SRAM
circuits is reduced by 51.2% and 53.3% at 70°C and 27°C,
respectively, as compared to the tied-gate FinFET SRAM
circuit with comparable data stability. Furthermore, the
average read SNM of the IG-FinFET SRAM cell is enhanced
by up to 82% as compared to the standard tied-gate FinFET
SRAM cells under process parameter variations.
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