1964
9, SEPTEMBER 2008
X-Calibration: A Technique for Combating
Excessive Bitline Leakage Current
in Nanometer SRAM Designs
Ya-Chun Lai and Shi-Yu Huang, Member, IEEE
Abstract—In an SRAM circuit, the leakage currents on the bit
lines are getting increasingly prominent with the dwindling of
transistors’ threshold voltages as the technology scales down to
90 nm and beyond. Excessive bit-line leakage current results in
slower read operations or even functional failure. In this paper,
we present a new technique, called X-calibration, to combat this
phenomenon. Unlike the previous method that attempts to com-
pensate the leakage current directly, this scheme first transforms
the bit-line leakage current into an equilibrium offset voltage
across the bit-line pair, and then simple circuitry is utilized to
cancel this offset accurately at the input of the sense amplifier
so that the sensing is not affected by the bit-line leakage. SPICE
simulation of a 1 Kbit SRAM macro shows that this X-calibration
scheme can handle 83% higher bit-line leakage current than the
previous bit-line leakage compensation scheme. Measurement
results of the test chip show that the SRAM macro adopting
X-calibration scheme can cope with up to 320 A bit-line leakage
current.
Index Terms—Bitline leakage current, on-off ratio, sense ampli-
fier, SRAM, X-calibration scheme.
I. INTRODUCTION
A S CMOS process technology scales down into the
nanometer scale, a number of unexpected side effects,
such as raised leakage current of transistors, larger process
variation, worse matching of symmetric devices, and deterio-
rated power and ground lines, start to emerge. These nanometer
effects not only bring enormous challenges to circuit designers
but also greatly reduce the manufacturing yield. Consequently,
to design a robust circuit to deal with these effects has become
much more important.
For logic circuits, the threshold voltage of transistors is often
reduced to retain high performance as the supply voltage de-
clines. In turn, the reduced threshold voltage results in increased
leakage current, which does not lead to catastrophic results for
logic circuits. Yet, the raised leakage current could not only de-
grade the performance for an SRAM circuit but also lead to er-
roneous operations.
Bitline leakage current is the most significant component
of leakage in memories and will become increasingly large
Manuscript received April 13, 2007; revised April 25, 2008. Current version
published September 10, 2008. This work was supported by the National Sci-
ence Council of Taiwan under Grant NSC 96-2220-E-007-028.
The authors are with the Department of Electrical Engineering, Na-
tional Tsing Hua University, Hsinchu, Taiwan 30013, R.O.C. (e-mail:
yclai@larc.ee.nthu.edu.tw; d935916@oz.nthu.edu.tw).
Digital Object Identifier 10.1109/JSSC.2008.2001937
0018-9200/$25.00 © 2008 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.
in the nanometer technology. According to the report of [1],
the worst-case bit-line leakage current can reach 117 A
under high temperature and large column height. Because the
non-evaluating bit-line is discharged by the bit-line leakage
current, the effective bit-line voltage swing developed by the
cell current of the accessed memory cell during a read op-
eration will decline. The degraded effective bit-line voltage
swing either increases the delay of the sense amplifier or makes
the sense amplifier react incorrectly. Several methods have
been proposed to solve this problem. These methods can be
classified into two categories: leakage suppression [2]–[4] and
leakage compensation [5]–[7]. These studies try to solve the
problem by means of either adapting the manufacturing process
or changing the circuitry.
The negative word-line scheme proposed in [2] forces an
inactive word-line to a voltage level lower than the ground to
reduce the leakage through access transistors. Yet, this scheme
may still suffer from the so-called gate-induced drain leakage
current. The scheme proposed in [3] uses both dual threshold
voltage and aggressive biasing on the word-lines, the bit-lines,
and the power lines of the storage cells to curb the leakage
currents. Hence, this scheme can cope with excessive bit-line
leakage current in a 100-nm dual- technology as demon-
strated [3]. However, as technology advances, the leakage
current could become even more severe and thus this leakage
suppression technique may still need some compensating
techniques that help to tolerate the leakage currents in addition
to curbing them in the future. Also, as the process variation
increases, the biasing circuits may not be able to generate the
bias voltages as accurately. In [4], a dynamic leakage cut-off
scheme was also proposed. The drawback is that this scheme
may degrade the operation speed due to the large additional
time required for generating a reverse substrate bias.
The bit-line compensation (BLC) scheme described in [5]
modifies the pre-charge circuitry to detect the amount of the
bit-line leakage. After that, similar amount of current is injected
into the bit-line so as to compensate the loss due to leakage. Nev-
ertheless, this scheme is sensitive to the process variation due to
the dynamic current mirror structure, which is extremely sus-
ceptive to the variation of the threshold voltage. The modified
BLC schemes described in [1] and [6] attempt to overcome some
weaknesses in [5] such as the mismatch problem of the dynamic
current mirror. The modified circuit proposed by [6] success-
fully uses the same transistor to detect the bit-line leakage cur-
rent and inject the compensation current. Notwithstanding, the
gate voltage of the transistor that decides the injected amount
LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS
Fig. 1. Conventional SRAM column with bit-line leakage.
of the compensation current is still sensitive to the coupling
noise from the bit-line. The bit-line leakage equalization tech-
nique mentioned in [7] does not require additional control sig-
nals and time to detect the amount of leakage current on the
bit-line pairs. This technique, nonetheless, has about 40% area
overhead because the conventional 6-transistor cell is replaced
with the new 8-transistor leakage-equalized cell. Also, dupli-
cating leakage current on one bit-line for the other may double
total leakage current and cause more power consumption. In this
paper, we propose a new scheme to solve the bit-line leakage
current problem. The basic idea is to transform the leakage cur-
rent into an equilibrium offset voltage across the bit-line pair.
Then, offset cancellation techniques can be applied to resolve
the problem. The circuitry we propose here can work under a
wide-range bit-line leakage current. Moreover, there are only
two additional control signals in this scheme. Consequently, the
new bit-line sensing circuitry is power efficient.
The rest of this paper is organized as follows. Section II
describes the problem caused by bit-line leakage current.
Section III presents the proposed X-calibration scheme.
Section IV gives a transient analysis of the proposed scheme
and chip implementation. Section V shows the experimental
results. Finally, we conclude the paper in Section VI.
II. PROBLEM DEFINITION
First, we will point out the problem caused by bit-line leakage
current in detail. Fig. 1 shows a single-column circuit for a con-
ventional SRAM. The accessed cell stores logic-1 while the
others store logic-0. This is the worst scenario when the bit-line
leakage impacts the circuit’s operation most. For each non-ac-
cessed cell, there is subthreshold leakage current flowing from
the bit-line, passing through one access transistor, and finally
into the storing node of logic-0 as shown in Fig. 1. Under this
condition, these leakage currents jointly contribute to the overall
bit-line leakage current. When the accessed cell is read, this joint
bit-line leakage current will become the noise against the cell
current (i.e., the current flowing into the accessed cell) and may
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
1965
Fig. 2. Waveforms of the bit-line pair for a conventional SRAM (a) without
bit-line leakage and (b) with bit-line leakage.
hinder the bit-line differential signal detection performed by the
sense amplifier.
Fig. 2 shows the waveforms of the bit-line pairs with and
without the bit-line leakage. As shown in the figure, we can see
that the bit-line voltage difference reduces when the excessive
bit-line leakage current exists. The reduced bit-line difference
degrades the performance and increases the read access time
because the sense amplifier needs more time to detect smaller
input differential voltage. If the bit-line leakage becomes close
to or larger than the cell current, the read operation would fail
due to potentially incorrect detection of the sense amplifier.
The so-called on–off ratio has been popularly used as a de-
sign criterion for taking the bit-line leakage current into account,
and is defined as the ratio of the cell current being accessed
to the total leakage current drained by the non-accessed cells.
As a rule of thumb, this ratio is often larger than 10 to pro-
vide a good leakage immunity when designing a robust SRAM
circuit. This criterion could therefore impose on the maximum
height of a cell column, or the number of bit cells connected
to a single column of the SRAM cell array. Unfortunately, as
the process continues to scale down, the threshold voltage of
transistor is often reduced accordingly in order to compensate
for the speed loss due to lower supply voltage. In turn, the sub-
threshold leakage current becomes even larger and this on–off
ratio target becomes harder to achieve. Sometimes, the same
on–off ratio is retained at the sacrifice of the reduced height.
However, this strategy is only a tradeoff and not a good solu-
tion because it forms a limit on the capacity of an SRAM and
reducing the area efficiency as well [3].
The bit-line leakage current is dependent on the data pattern
stored in one column and on the operating temperature. As a re-
sult, the amount of the bit-line leakage current will change after
1966 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

Fig. 3. Basic concept of the X-calibration scheme.

Fig. 4. Schematic of the calibration circuitry.

each write operation, which varies the data pattern. The amount
of bit-line leakage also increases as the operating temperature
rises.

III. PROPOSED METHOD

In this section, we first explain the basic concept of the X-cal-
ibration scheme and then describe its detailed implementation.

A. Basic Concept
We regard the bit-line leakage current as an offset voltage
and then cancel the offset voltage by means of the calibration
circuitry attached to the sense amplifier. This basic idea can be
explained in two parts, as follows.
• Generation of the equilibrium offset voltage: The bit-line
leakage current is transformed into an offset voltage across
the bit-line pair. As shown in Fig. 3, we use the conven-
tional bit-line static load circuitry to provide pull-up cur-
rent against the bit-line leakage current. Finally, the voltage
level of each bit-line reaches an equilibrium level after
some time. The difference of the equilibrium levels across
the bit-line pair is referred to as the equilibrium offset
voltage or simply the offset voltage for the rest of this
paper.
Fig. 5. (a) Waveforms of the bit-line pair and input pair of the sense amplifier.
• Cancellation of the offset voltage: The offset voltage men- (b) Timing diagram of the control signals.
tioned above is first recorded and then cancelled by the
calibration circuitry attached to the inputs of the sense am-
plifier as shown in Fig. 3. The detailed operations of the
in Fig. 5(a). This scheme is called X-calibration because of the
calibration circuitry will be described later.
crossing structure formed by the switches controlled by .
The operation of an SRAM column with the calibration cir-
B. Circuit Architecture and Operation
cuitry can be divided into the following three phases, shown in
The schematic of the calibration circuitry shown in Fig. 4 is Fig. 5(a).
mainly composed of several switches and two coupling capac- 1) Pre-charge phase: In this phase, the bit-line pair is pre-
itors. There are two additional control signals, and , the charged to an initial level (namely in the design) and
timing diagrams of which are shown in Fig. 5(b). The transient the input pair of the sense amplifier is left floating. At this
waveforms of the bit-line pair and the input pair of the sense am- moment, all switches in the calibration circuitry are turned
plifier in the presence of the bit-line leakage current are shown off.

Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS
Fig. 6. Illustration of each operation phase. (a) Pre-charge and equalization. (b) Detection. (c) Calibration and read.
2) Detection phase: The pre-charge circuit is turned off and
the switches controlled by are turned on to detect the
offset voltage developed by the bit-line static load. Note
that this offset voltage has been flipped around by the
crossing structure of the switches controlled by . This
reversal of the offset voltage is designed intentionally to
support easy offset cancellation later.
3) Calibration and read phase: The switches controlled by
are turned off and then those controlled by are turned
on to couple the voltages at the bit-lines to the inputs of
the sense amplifier. At the beginning of this phase, the re-
versed offset voltage detected in phase 2 was stored across
the bottom nodes of the two coupling capacitors and will
be deducted from the differential voltage across the bit-line
pair to cancel out the offset voltage during this coupling
process. Therefore, the offset voltage disappears from the
input pair of the sense amplifier in this phase and the oper-
ation performed by the sense amplifier will not be affected
at all by the bit-line leakage.
Since the operation of the calibration is hidden within the
read operation, there is no access time penalty in this scheme.
Also, the calibration circuitry works well for the write operation.
The timings of the two control signals ( and ) should not
overlap each other.
In order to clearly demonstrate the three operation phases of
an SRAM column with the calibration circuitry, we give an ex-
ample with bit-line leakage, as shown in Fig. 6. For simplicity,
each node’s voltage designated in Fig. 6 is just an approximate
value and thus slightly different from the real case. In Fig. 6(a),
the column is in the pre-charge phase and the bit-line pair is
pre-charged and equalized to initial voltage level, 1.8 V. Then, in
Fig. 6(b), the column gets into the detection phase. The bit-line
voltage level drops down and eventually balances at the lower
voltage level of 1.4 V due to the bit-line leakage current. This
voltage level is carried to the bottom node of the coupling ca-
pacitor on the other side through the crossing switch controlled
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
1967
by . At the end of this phase, the equilibrium offset voltage
across the bit-line pair has been generated and stored in the cali-
bration circuitry. Finally, the column comes into the calibration
and read phase shown in Fig. 6(c). The cell current discharges
the complementary bit-line so that the voltage level of the com-
plementary bit-line falls down and balances at the voltage level
of 1.45 V. This voltage drop can be transferred to the comple-
mentary input of the sense amplifier by means of the coupling
capacitor. Now, we can clearly see that the offset voltage is per-
fectly cancelled at the input pair of the sense amplifier from
Fig. 6(c).
The sense amplifier we used is the latch-type sense amplifier
mentioned in [8] and [9]. In order to use capacitive coupling to
achieve the offset cancellation, the input impedance of a sense
amplifier must be infinite and the inputs of sense amplifier need
to be floating during the calibration phase. In addition, the ca-
pacitance of the coupling capacitor should be selected appropri-
ately. If its capacitance is too small, the coupling effect will be
too weak and the offset voltage cancellation will be less accu-
rate. On the other hand, using too large capacitance will cause
excessive area overhead. Therefore, the selection of the capac-
itance of the coupling capacitor is a tradeoff between coupling
efficiency and area. In our design, the capacitance of the cou-
pling capacitor is determined according to simulation result and
consideration of physical implementation.
IV. TRANSIENT ANALYSIS AND CHIP IMPLEMENTATION
A. Transient Analysis of X-Calibration Scheme
Fig. 7 shows transient waveforms of bit-lines under diverse
bit-line leakage currents during a read operation, where BL is
discharged by bit-line leakage current and /BL is discharged by
cell current when WL is turned on. The entire read cycle can
be divided into three phases: 1) pre-charge; 2) detection; and
3) calibration and read. Because the detection time borrows the
1968
Fig. 7. Transient waveforms of bit-lines under diverse bit-line leakage currents.
Fig. 8. Relationship between equilibrium time and bit-line leakage current.
timing margin from the pre-charge time and the calibration op-
eration is performed together with the normal read operation at
the same time, there is no access time penalty. However, the
cycle time could rise a little due to the insertion of the detec-
tion phase between the pre-charge and the read operation phase.
In our X-calibration scheme, the circuit designer can adjust the
detection time on the design stage according to the equilibrium
time, which is defined as the time interval between the end of
the pre-charge phase and the time instant that the non-evalu-
ating bit-line (i.e., BL in Fig. 7) reaches equilibrium level as
mentioned in Section III-A. By means of simulation analysis, it
is known that the equilibrium time is dependent on the amount
of bit-line leakage current and is less than 25% cycle time at an
operating frequency of 200 MHz when the bit-line leakage cur-
rent is under 285 A as shown in Fig. 8. In fact, the detection
time can be less than the equilibrium time at the cost of max-
imum tolerable bit-line leakage current when the timing budget
is tight.
B. Implementation of Fabricated Test Chip
In order to evaluate the effectiveness of the proposed scheme,
we have fabricated a test chip of an SRAM macro of 1 Kb in a
0.18- m standard CMOS process technology. For comparison,
the test chip has also included a conventional SRAM macro with
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
Fig. 9. Micrograph of the test chip.
Fig. 10. Micrograph of the SRAM macro using X-calibration.
the same configuration but without the calibration circuitry. The
micrograph of the test chip is shown in Fig. 9. The upper part of
the test chip is the SRAM macro using the X-calibration scheme
and the lower is the conventional SRAM macro. The memory
built-in self-test (BIST) circuitry in the middle of the test chip
is also included. The detailed micrograph of the SRAM macro
using X-calibration is shown in Fig. 10. The switching transis-
tors in the calibration circuitry are PMOS pass transistors, and
coupling capacitors implemented in the test chip are metal–insu-
lator–metal (MIM) capacitors. The area of the proposed SRAM
macro increases by 7.55% as compared with the conventional
SRAM macro due to the calibration circuitry.
C. Methods for Mimicking Bit-Line Leakage
In the test chip, we use 0.18- m CMOS technology. There are
two possible methods to mimic the leakage phenomena we may
encounter at 90 nm process and beyond. One method is to adjust
the voltage levels of those inactive word-lines from ground to
slightly higher voltage level. This method, however, is difficult
to realize for the whole SRAM macro and all SRAM columns
would have the same bit-line leakage. In practice, each column
may have different bit-line leakage current due to different data
pattern. The other method is to add one NMOS transistor pair to
each bit-line pair. These transistors connect bit-lines to ground
and we can adjust the gate voltage of the transistor to generate
appropriate drain current as bit-line leakage current. We adopt
LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS
TABLE I
COMPARISONS OF POWER, DELAY, AND MAXIMUM TOLERANT BIT-LINE LEAKAGE
Fig. 11. Bit-line leakage current generator.
the latter method because of its simplicity. The bit-line leakage
current generator is shown in Fig. 11.
V. EXPERIMENTAL RESULTS
A. Simulation Results
In order to compare the X-calibration scheme with the pre-
vious bit-line leakage compensation (BLC) scheme [5], we also
implemented an SRAM macro of 1 Kb using the circuit ar-
chitecture of the BLC scheme. Table I lists the read current,
the write current, the access time, and the maximum tolerable
bit-line leakage of these three SRAM macros. These circuit per-
formance parameters are obtained by running SPICE simula-
tion. The following is the meaning of each column of Table I.
• Read current: The average supply current for performing a
read operation during one cycle.
• Write current: The average supply current for performing
a write operation during one cycle.
• Access time: The delay from the rising edge of the clock
to the transition edge of the data output during a read
operation.
• Maximum tolerable bit-line leakage: The maximum toler-
able bit-line leakage current under which the SRAM circuit
can operate correctly.
The impact of the bit-line leakage current on the access time
for each of the three SRAM macros is shown in Fig. 12. In prac-
tice, there is cell current distribution due to process variation or
noise emerging on the bit-line pair. Therefore, the upper bound
of bit-line leakage for the conventional SRAM macro could be
lower. Because the number of memory cells on each column for
these SRAM macros is 32, the bit-line loading capacitance is too
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
1969
Fig. 12. Impact of bit-line leakage on access time for the three SRAM macros
in a 0.18-m CMOS technology with extra bit-line loading capacitance of
(a) 200 fF and (b) 500 fF, respectively.
small as compared with the SRAM macro with a large column
height, e.g., 256 or 512. As a result, we added extra loading ca-
pacitance on each bit-line pair and run SPICE simulation for the
three SRAM macros when deriving the data.
The experimental results show that the X-calibration scheme
can handle 61% and 83% higher bit-line leakage current than
the BLC scheme under 200 fF and 500 fF extra bit-line loading
capacitance, respectively. In addition, when the extra bit-line
loading capacitance increases, the upper bound of the bit-line
leakage current that all SRAM macros can cope with will
decline. However, the X-calibration scheme can still function
correctly up to 300 A bit-line leakage current, as shown in
Fig. 12(b).
The size of the critical transistors of both BLC and X-cali-
bration scheme may influence the experimental results, so we
use similar dimensions for those transistors in both schemes
so as to guarantee fair comparison. The critical transistors for
BLC scheme refer to those for detecting bit-line leakage and for
1970 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008

TABLE II
RELATIONSHIP BETWEEN BIAS AND BIT-LINE LEAKAGE

TABLE III
TEST CHIP CHARACTERISTICS

Fig. 13. Relationship between the sensing time and the column height under Fig. 14. Shmoo plots of supply voltage versus BIAS for (a) conventional
(a) the room temperature 25 C and (b) a higher temperature 125 C for a 22-nm SRAM macro and (b) X-calibration SRAM macro.
CMOS technology.

X-calibration can still function correctly and has better sensing

injecting compensation current. For X-calibration scheme, the
critical transistors refer to the bit-line static loads.
The experimental results of Fig. 13 show the relationship be-
tween the sensing time and the column height under different
temperatures, e.g., 25 C and 125 C, in a 22-nm CMOS tech-
nology. The definition of the sensing time is the delay time from
the word-line activation to the time when the voltage difference
at the input pair of the sense amplifier, i.e., , reaches
0.1 , namely 80 mV for 0.8-V in a 22-nm CMOS tech-
nology. Moreover, the column height signifies the total number
of bit cells connected to each bit-line pair. The data are de-
rived by performing SPICE simulation using a 22-nm Predictive
Technology Model (PTM) [10], [11]. When the column height
becomes larger or the temperature increases, the worst-case bit-
line leakage current increases. Therefore, the sensing time in-
creases and eventually the read operation of the conventional
SRAM circuit could fail. However, the SRAM circuit using our
time than the BLC scheme.
B. Measurement Results
Measured shmoo plots of the test chip are shown in Fig. 14.
The parameter, BIAS, in the horizontal axis is the gate voltage
of the NMOS transistor in the bit-line leakage current generator
to induce bit-line leakage current. Hence, if BIAS goes up,
the bit-line leakage will increase as well. The relationship
between BIAS and bit-line leakage, , is shown in Table II.
When BIAS is low, both SRAM macros function correctly.
When BIAS rises over 0.68 V, the conventional SRAM macro
will fail. However, the X-calibration SRAM macro still works
correctly until the BIAS goes up to 1 V. According to the
measured results in Table II, it can be seen that the upper bound
of tolerable bit-line leakage of the conventional SRAM macro
is only 76.6 A. However, the X-calibration SRAM macro can
work correctly under 320 A bit-line leakage. As a result, the

Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS
SRAM macro using X-calibration scheme can break through
the boundary of maximum tolerable bit-line leakage of the
conventional SRAM macro and reach a new boundary of as
much as 320 A bit-line leakage current.
The test chip characteristics are summarized in Table III.
Compared with the conventional 1 Kb SRAM macro, the area
overhead of the SRAM macro using the X-calibration scheme
is 7.55%. The measured extra power consumption due to this
scheme is 9.7% at the operating frequency of 150 MHz. The
measured access time includes off-chip delay, i.e., the delay
of the pad, the package, and the load-board on the ATE. As a
result, the measured access time for each SRAM macro in the
test chip is much larger than the simulation results, which only
include on-chip delay. Additionally, since the data output pin
of the X-calibration SRAM macro in the test chip encounters
a longer routing wire of the load-board on the ATE than that
of the conventional SRAM macro, the measured access time
of the X-calibration SRAM macro is greater than that of the
conventional SRAM macro.
VI. CONCLUSION
We have developed a new scheme called X-calibration to
solve the problem induced by bit-line leakage current. This
problem, if not coped with well, will become increasingly dev-
astating in nanometer technologies due to the ever-increasing
leakage current. In the X-calibration scheme, the calibration
circuitry consisting only of capacitors and switches is simple
to build to shield the sense amplifier from the disturbance of
bit-line leakage current. Compared with the conventional 1 Kb
SRAM macro, the area overhead of the SRAM macro using the
X-calibration scheme is only 7.55%. Moreover, if the column
height increases or the area of the coupling capacitor decreases,
the area overhead can be reduced further. The measured extra
power consumption due to this scheme is only 9.7% at the
operating frequency of 150 MHz. Measurement results of the
fabricated test chip validate that the X-calibration scheme is
not only feasible but also capable of increasing the maximum
tolerable bit-line leakage current up to 320 A, which is 4.18
times as much as in the conventional SRAM macro.
ACKNOWLEDGMENT
The authors would like to thank National Chip Implemen-
tation Center (CIC) and L.-M. Denq for technical support,
Taiwan Semiconductor Manufacturing Company (TSMC) for
chip fabrication, and M.-F. Chang and C.-W. Wu for their
valuable discussions.
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
1971
REFERENCES
[1] A. Natarajan, V. Shankar, A. Maheshwari, and W. Burleson, “Sensing
design issues in deep submicron CMOS SRAMs,” in Proc. IEEE Com-
puter Society Annu. Symp. VLSI, May 2005, pp. 42–45.
[2] H. Tanaka, M. Aoki, T. Sakata, S. Kimura, N. Sakashita, H. Hidaka,
T. Tachibana, and K. Kimura, “A precise on-chip voltage generator
for a Gigascale DRAM with a negative word-line scheme,” IEEE J.
Solid-State Circuits, vol. 34, no. 8, pp. 1084–1090, Aug. 1999.
[3] Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, and V. De, “A 6-GHz
16-kB L1 cache in a 100-nm dual-VT technology using a bit-line
leakage reduction (BLR) technique,” IEEE J. Solid-State Circuits, vol.
38, no. 5, pp. 839–842, May 2003.
[4] H. Kawaguchi, Y. Itaka, and T. Sakurai, “Dynamic leakage cut-off
scheme for low-voltage SRAM’s,” in Proc. Symp. VLSI Circuits, Jun.
1998, pp. 140–141.
[5] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bit-line leakage
compensation scheme for low-voltage SRAMs,” IEEE J. Solid-State
Circuits, vol. 36, no. 5, pp. 726–734, May 2001.
[6] M. Khellah, Y. Ye, D. Somasekhar, D. Casper, B. Bloechel, T. Nguyen,
G. Dermer, K. Zhang, G. Pandya, A. Farhang, and V. De, “Bitline
leakage compensation (BLC) and leakage reduction (BLR) techniques
for 2–3 GHz on-chip cache arrays in microprocessors on 90 nm logic
technology,” in Proc. Symp. VLSI Circuits, Jun. 2005, pp. 262–263.
[7] A. Alvandpour, D. Somasekhar, R. Krishnamurthy, V. De, S. Borkar,
and C. Svensson, “Bitline leakage equalization for sub-100 nm caches,”
in Proc. 29th European Solid-State Circuits Conf. (ESSCIRC’2003),
Sep. 2003, pp. 401–404.
[8] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A current-
controlled latch sense amplifier and a static power-saving input buffer
for low-power architecture,” IEEE J. Solid-State Circuits, vol. 28, no.
4, pp. 523–527, Apr. 1993.
[9] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed op-
timization of a latch-type voltage sense amplifier,” IEEE J. Solid-State
Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.
[10] Predictive Technology Model (PTM). Nanoscale Integration and
Modeling (NIMO) Group, Arizona State Univ., Phoenix, AZ [Online].
Available: http://www.eas.asu.edu/~ptm, last updated Feb. 28, 2008.
[11] W. Zhao and Y. Cao, “New generation of predictive technology model
for sub-45 nm design exploration,” in Proc. Int. Symp. Quality Elec-
tronic Design, Mar. 2006, pp. 585–590.
Ya-Chun Lai was born in Taiwan in 1981. He re-
ceived the B.S. degree in electrical engineering from
National Tsing Hua University, Hsinchu, Taiwan,
R.O.C., in 2004, where he is currently working
toward the Ph.D. degree in electrical engineering.
He was a summer intern with Taiwan Semicon-
ductor Manufacturing Company, Ltd., in 2005. His
recent research interests include VLSI design and
high-yield SRAM design for nanometer technology.
Shi-Yu Huang (S’93–M’97) received the B.S. and
M.S. degrees in electrical engineering from National
Taiwan University, Taipei, Taiwan, R.O.C., in 1988
and 1992, and the Ph.D. degree in electrical and com-
puter engineering from the University of California at
Santa Barbara in 1997, respectively.
He joined the faculty of the Department of Elec-
trical Engineering, National Tsing-Hua University,
Taiwan, in 1999, where he is currently an Associate
Professor. His research interests are mainly in VLSI
design, automation, and testing, with an emphasis on
power estimation, fault diagnosis, CMOS image sensor design, and nanometer
SRAM design.