8085 Microprocessor

8085 Microprocessor
Fundamentals, Peripherals & Problems

(A vade mecum)

- M B Rapara

!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Contents

Fundamentals of 8085
- Specification of 8085 ...(1)
- Few things related to Memory in Microprocessor ...(1)
- Introduction to the Microprocessor Based System ...(2)
- Functional Pin Diagram and Architecture of 8085 & Signals ...(4)
- Cycles and Operations ...(8)
- Interfacing & Data Transmission Techniques ...(11)
- Interrupts ...(14)

8085 Programming
- Understanding About Instructions of 8085 ...(17)
- Programming Techniques ...(19)
- How to Deal With the Problem / Assembly Language Prog. ...(21)
- Debugging ...(22)

8085 Programming Peripheral Devices.
- 8155 I/O Ports and Timer ...(23)
- 8279 Keyboard / Display Interface ...(25)
- 8255A Programmable Peripheral Interface (PPI) ...(28)
- 8253 / 8254 Interval Timer ...(30)
- 8259A Programmable Interrupt Controller (PIC) ...(32)
- 8237 DMA Controller ...(34)
- 8251A USERT(Universal Synchronous/Asynchronous Receiver Transmitter) ...(35)

Frequently Ask Quotations for 8085
- Short Questions ...(36)
- Few Fat Model University Exam Questions ...(47)

Appendix A 8085 Instruction Set ...(I)
Appendix B Sample Assembly Language Programs ...(VIII)

Bibliography and Closing Words

|| : ||
1
st
Edition
M B Rajpara 8085 Microprocessor (A vade mecum) 1

www.vidyanuragi.wordpress.com

FUNDAMENTALS of 8085

Specification of 8085

o Intel 8085 was released on April 1974.
o 8085 has 40-pin DIP (Dual inline Package) chip design using NMOS.
o 8085 works on +5 Volt. (V
CC
power supply connected ; V
SS
Power supply ground)
o 8085 is 8 bit microprocessor
o 8085 incorporates the functions of the 8224 (clock generator) and the 8228 (system controller)
o 8085 operated on 2, 3 and 5 MHz clock frequency, the minimum frequency of operation is 500 KHz.
o 8085 has 16 address line (so can access or address 2
16
/ 64KB of memory) and 8 bit of I/O address (so
can access 2
8
/ 256 I/O ports)
o 8085 can supports 74 basic instructions and 246 total instructions.
o 8085 supports five hardware interrupts (TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR)

Few things relate to Memory in Microprocessor

- A memory is a peripheral which stores the information in Magnetic, Electrical or Optical form.
Semiconductor memory is very in use because their low cost, high performance and good reliability
and its easiness in expansion of memory.
- Memory is made of storage elements calls cell, which can store one bit of data.
- Also classified in two types. A. Volatile, lost the stored information in it when power off. B. Non-
Volatile, information remains even after power off the device (because it has a small battery attached
with it which helps to store the info. in memory).
- It is divided in two parts.
a. Primary / Main / Working Memory
Less in storage but faster in operation and can directly used by CPU.
It is volatile or non-volatile in nature.
Ex. RAM, ROM
b. Secondary / Auxiliary / Mass Memory (for backup or storage)
Huge in storage but slower in speed and not directly useable by CPU.
It is always non-volatile in nature.
Ex. Magnetic tapes, HDD, CD.
- In computer we take 1024 as 1K, with 8 bits each. A group of 256 registers is defined as one page
and each register is viewed as a line to write on.
- Kinds of memory
a. RAM (Random Access Memory)
Its a primary volatile memory. CPU can alter the data in it, in lively manner.
Very faster in nature. But cost high compare to tapes. And lack in size.
Two types Dynamic DRAM and Static (also calls cache memory) SRAM.

Static SRAM Dynamic DRAM
1

2
3
4
5
Stored data is retained as long as power
remains ON.
Stored data do not change with time.
Consumes more power.
Expensive.
These memories have less packing density.
Stored data gets lost and repeated refreshing
is required.
Stored data changes with time.
Consumes less power than static memory.
Less expensive.
Higher packing density.


6
7
8
These memories are not easy to construct.
No maintenance.
No refreshing required and easy in operation.

Simpler in construction.
Maintenance needed.
Refreshing required with additional memory
circuitry and hence complicated operation.

b. SAM (Sequential Access Memory)
In this the access time is not constant for all memory locations. Ex. Magnetic tapes.
c. CAM (Content Addressable Memory)
Special Purpose RAM which performs association operation, in read/write operation.
d. ROM (Read Only Memory)
A program which is never going to change is usually written in ROM. Once you write on it
that will never going to change. Generally basic I/O and peripheral access are stored in this way.
e. Masked ROM
Manufacture by making special marks. And problem oriented programmed and by
manufacturing company. Its less in cost.
f. PROM (Programmable Read Only Memory)
Manufactured by blowing fusible nichrome wire links; done by user (only once). And it cost
more.
g. EPROM (Erasable Programmable Read Only Memory)
It has isolated gate structure. You can reprogram it on high voltage. To erase it, it must be
taken out of the circuit and erased fully.
h. EE-PROM (Electrical Erasable Programmable Read Only Memory) / EAPROM
As can be erased and programmed with electrical signals.
The voltage on the floating gate structure allows storage of information.
Higher speed of operation.
Relatively easy to manufacture, but very expensive.
Erasing takes several minutes.
i. UVEPROM (Ultraviolet Erasable Programmable Read Only Memory) / UVPROM
Can be erased and programmed with ultraviolet light.
The photo current from the insulated gate structure allows storage of information.
Lower speed of operation.
Relatively difficult to manufacture, but less in cost.
j. Flash Memory
Provide very fast access and take very less power. It can also workout with vibration and
shocks. Usually used in Laptops and cell phones.

Fig: Semiconductor Memory Hierarchy
- Memory Map: is a guide showing how the entire system memory has been allocated to ROM, RAM so
that any future memory expansion can be done easily.

M B Rajpara

Introduction to The Microprocessor Based Systems

A system designed using a microprocessor as its CPU is called a microcomputer. The Microprocessor
based system (single board microcomputer) consists of microprocessor as CPU, semiconductor memories
like EPROM and RAM, input device, output device and interf
The memories, input device, output device and interfacing devices are called peripherals. The popular
input devices are keyboard and floppy disk and the output devices are printer, LED/LCD displays, CRT
monitor, etc.

The above block diagram shows the organization of a microprocessor based system. In this system,
the microprocessor is the master and all other peripherals are slaves. The master controls all the
and initiates all operations.
The work done by the processor can be
1. Work done internal to the processor
(Addition, subtraction, logical operations, data transfer operations, etc.)
2. Work done external to the processor
(Reading/writing the memory and
3. Operations initiated by the slaves or peripherals.

The microprocessor is the master, which controls all the activities of the system. To perform a
job or task, the microprocessor has to execute a program stored in memo
instructions. It issues address and control signals and fetches the instruction and
instruction is executed one by one internal to the processor and based on

of Microprocessor based system
1. Computational/processing speed is high.
2. Intelligence has been brought to systems.
3. Automation of industrial processes and office administration.
4. Since the devices are programmable, there is flexibility to alter
alone.
5. Less number of components, compact in size and cost less. Also it is more reliable.
6. Operation and maintenance are easier.

8085 Microprocessor (A vade mecum)

Introduction to The Microprocessor Based Systems
like EPROM and RAM, input device, output device and interfacing devices.
ram shows the organization of a microprocessor based system. In this system,
the microprocessor is the master and all other peripherals are slaves. The master controls all the
The work done by the processor can be classified into the following three groups.
Work done internal to the processor
Work done external to the processor
(Reading/writing the memory and reading/writing the I/O devices or the peripherals)
Operations initiated by the slaves or peripherals.
The microprocessor is the master, which controls all the activities of the system. To perform a
job or task, the microprocessor has to execute a program stored in memory. The program
instructions. It issues address and control signals and fetches the instruction and
instruction is executed one by one internal to the processor and based on the result it takes appropriate action.
of Microprocessor based system
1. Computational/processing speed is high.
2. Intelligence has been brought to systems.
3. Automation of industrial processes and office administration.
4. Since the devices are programmable, there is flexibility to alter the system by changing the
6. Operation and maintenance are easier.
3

ram shows the organization of a microprocessor based system. In this system,
the microprocessor is the master and all other peripherals are slaves. The master controls all the peripherals
classified into the following three groups.
devices or the peripherals)
The microprocessor is the master, which controls all the activities of the system. To perform a specific
ry. The program consists of a set of
instructions. It issues address and control signals and fetches the instruction and data from memory. The
the result it takes appropriate action.
he system by changing the software


of Microprocessor based System
1. It has limitations on the size of data.
2. The applications are limited by the physical address space.
3. The analog signals cannot be processed directly and digitizing the analog signals introduces errors.
4. The speed of execution is slow and so real time applications are not possible.
5. Most of the microprocessors do not support floating point operations.

Functional pin diagram of 8085 & Signals

8085 Microprocessor Signals are classified in five groups:

1. Power Supply and Clock Frequency Signals
- X1 and x2: A two input pins for Crystal, it generates constant and accurate frequency. (Frequency of
microprocessor is half of the crystal frequency, because crystal freq. is divided in X1 and X2. So if
you want MPU of 3MHz then crystal must be of 6MHz.)
- V
SS
Ground the power, V
CC
+5 V power
- CLK (OUT): This signal is used as the system clock for other devices.


2. Bus Signals
- AD
0
to AD
7
: drives the signal for 8 bit Data or Low Address bus (A
0
to A
7
) its bidirectional.
- A
8
to A
15
: drives signal for Higher Order Address bus. Unidirectional.

3. Control and Status Signal
- ALE: (Address Latch Enable) when it is high, it
shows that AD
0
to AD
7
is used as address bus.
- R
: Read Signal actives LOW. To read/ fetch data

from specified address in memory to CPU.
- wR
: Write Signal actives LOW. To write data into

memory.
- I0N
: If it is high operation is doing with IO. If it

is low then do memory operation.
- S
0
and S
1
: To identify various operations.

4. Externally initiated Signals and their Acknowledgement.
Interrupts
- INTR, INTA, RST 7.5, RST 6.5, RST 5.5, TRAP, HOLD, HLDA, READY
Interrupts are used to handle the interrupt which comes in between the execution. It executes the
service routine. After that, microprocessor resumes the main program.

- READY: When the signal is low microprocessor goes into wait state. This signal is use to
synchronize with the external peripherals.
- HOLD: it is special signal use by external peripheral to get access of the buses.
Ex. DMA use data bus for data transfer.

Reset Signals
- RESEI IN
: Program Counter is set to 0. (Address goes to 0000H ) MPU is reset.

- RESET OUT: To reset other devices.

5. Serial I/O Signals.
- SID: Serial Input Data
- SOD: Serial Output Data

Note:
(bar) on any signal shows that it works in LOW signal.

There is no real control bus. Instead, the control bus is made up of a number of single bit control
signals.

Fig: Programming Model of 8085
Machine Cycle
ID
M

S
1
S
0

Opcode Fetch 0 1 1
Memory Read 0 1 0
Memory Write 0 0 1
I/O Read 1 1 0
I/O Write 1 0 1
Interrupt
Acknowledge
1 1 1
Halt Z 0 0
This fig. shows the programming model of
8085.
- It is what the available resources
programmer has.
- Which can be use to write a program.


Architecture of 8085

A. Registers
Microprocessor use these while operation on data. To interact with the microprocessor data
should be loaded in the registers. They are typed in :

a. General purpose registers (B, C, D, E, H , L)
- They are 8 bit reg. and we can also use them in pair of 16 bit (ex. BC, DE, HL).
- HL pair is takes as M in instruction and it also called scratchpad registers (high speed internal
memory used for temporary storage of preliminary information) sometime.

b. Temporary registers
- In ALU has two inputs, one is supplied from Accumulator and another is from temp. register (It
is not accessible by programmer)
- W and Z are also temp. reg. used by ALU of microprocessor.

c. Special purpose registers
- Register A(accumulator), after the execution of the logical or arithmetic instruction the result is
rests in this register.
- Flag registers



D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

S Z AC P CY
.

- Instruction register
CPU fetches the opcode of the instruction and stores it to the instruction reg.
- PC Program Counter
It keeps track on how many instructions are executed. It's 16 bit reg.
- SP Stack Pointer
It is used to hold the address of the most recent stack memory. It is 16 bit reg.

B. ALU (Arithmetic Logic Unit)
It performs arithmetic and logical functions on 8 bit data.

C. Instruction decoder and Machine Cycle encoding.
It decodes the opcode from Instruction reg. and control register, data buffers, ALU and other signals with
use of timing and control signals.

D. Buffer
a. Address buffer: 8 bit unidirectional buffer, which drives higher order address bus (A
15
-A
8
)
b. Address/Data buffer: 8 bit bi-directional buffer, which drives lower order address bus (A
7
-A
0
) and
Data bus (D
7
-D
0
).

E. Address Latch
16 bit reg., used to work out with PC and SP reg.

F. Timing and Control Circuit
It helps 8085 to synchronies with other peripherals with the use of clock signal. It is main circuit which
controls the operations.

G. Interrupt Control
Whenever we want to work out with the interrupt this control circuit comes in fore to control the signals
for interrupt.

H. Serial I/O Control Circuit
It handles two line SOD(Serial Output Data) and SID (Serial Input Data).

S Sign Flag : set 1 if
the result is negative.
Z Zero Flag :
set 1 if result is
zero.
AC Auxiliary Carry /
Adjust Flag : Indicates
decimal carry. Carry out bit
3 to bit 4 of the result. Set 1
if result carry from LSB to
MSB. Only work in BCD.
P Parity : set 1 if the
result contains even
number of 1s.
CY Carry Flag: set 1 if
overflow happens (out of
bit 7)


Cycles and Operations

- Instruction Cycle: The time required to complete the execution of an instruction.

All instructions are divided into a few basic machine cycles and these machine cycles are divided in
into some precise system clock periods /T-States.

- Machine Cycle: The time required to complete one operation of accessing memory, I/O, or
acknowledging the external request.
- T-State: One subdivision of the operation performed in one clock period.
Each T-State is equal to one clock period.
Execution of any instruction done in three steps:
a. Check the memory location by its address, with the use of address bus
b. Get the data from that memory address, with the use of data bus
c. Control a. and b. step with control and timing signals.

All of the operations of the microprocessor can be classified into one of three types:
- Microprocessor Initiated Operations
- Internal Operations
- Peripheral Initiated Operations

It is important to note that the microprocessor treats memory and I/O devices the same way.
o Input and output devices simply look like memory locations to the microprocessor.
- For example, the keyboard may look like memory address A3F2H. To get what key is being
pressed, the microprocessor simply reads the data at location A3F2H.
o The communication process between the microprocessor and peripheral devices consist of the
following three steps:
- Identify the address.
- Transfer the binary information.
- Provide the right timing signals.

Here the
1. Opcode Fetch Machine Cycle.

- In every execution of instruction, the first operation is
always Opcode Fetch Cycle. It fetches the machine
code from memory.
- This cycle takes 4 or 6 T-states in execution. The first
three T-states are used for fetching the opcode from
memory and the remaining T-states are used for
internal operations by the processor.
- It is as similar to memory read cycle; the difference is
in status signal. For opcode fetch the signal is
I0N
=0, S
1
=1, S
0
=1.



2. Read or Write Machine Cycle.
[Memory Read Operation] To read the contents of a memory location, the following steps take place:
- The microprocessor places the 16-bit address of the memory location on the address bus.
- The microprocessor activates a control signal called memory read which enables the memory chip.
- The control signals are [I0N
=0, S
1
=1, S
0
=0]
- The memory decodes the address and identifies the right location.
- The memory places the contents on the data bus.
- The microprocessor reads the value of the data bus after a certain amount of time.

[Memory Write Operation]
- As you can see in the figure, it is same as read operation, but the difference is in signals and line of
transfer. In this signals are [ I0N
=0, S
1
=0, S
0
=1 ]. And the data will transfer from microprocessor to
memory.
- The control signal will enable the chip select logic and write will be performed.

[I/O Read Operation]
- It is executed by the MPU to read a data byte from I/O port or from the peripheral which is I/O
mapped in the system.
- It is almost similar as memory read cycle.
- It takes 3 T-state to in execution.

[I/O Write Operation]
- It is executed by the MPU to write data byte in the I/O port or a peripheral which is I/O mapped in
the system.
- It is almost similar as memory write cycle.
- It takes 3 T-state to in execution.



Machine cycles T-States
Opcode fetch 4 / 6 T
Read or Write [Memory or I/O] 3 T
Interrupt Acknowledge 6 / 12 T
Bus Idle 2 / 3 T



Interfacing & Data Transmission Techniques

The data transfer schemes are broadly classified into two categories:
Microprocessor Controlled Data Transfer / Programmed Data Transfer
Data transfer takes place under the control of a program which resides in the main memory of the
system. It is relatively slow and applied for cases when the number of bytes of data is small. This scheme
is suitable for relatively slow peripherals.

Programmed data transfer scheme is sub-divided into the following:
A. Synchronous mode of data transfer.
Used when peripherals timing characteristics is precisely known. In this mode the status of the
device is not checked before undertaking any data transfer (the device is assumed as always ready
for data transfer). This is simplest amongst all other methods and minimum overhead in terms of
hardware/software is needed to implement this scheme.

B. Asynchronous mode of data transfer.
The device (peripheral) status is checked by the CPU before undertaking data transfer. This
mode is used when the timing characteristics of the device is unpredictable. In this mode, the CPU
confirms the readiness of the device status before undertaking data transfer. This is why this scheme
is known by the name handshaking I/O.
Handshake singles prevent the processor from reading the same data more than once, from a
slow device, and from writing new data before the device has accepted the previous data.

C. Interrupt driven mode of data transfer.
When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
interrupt signal to the processor. If the processor accepts the interrupt then the processor suspends its
current activity and executes an interrupt service subroutine to complete the data transfer between
the peripheral and processor. After executing the interrupt service routine the processor resumes its
current activity. This type of data transfer scheme is called Interrupt Driven Data Transfer Scheme
This mode is used for data transfer with slow peripherals and also when the occurrence of data is
unpredictable in nature.
It is further divided into two categories:
Polled Interrupt
- It is used when many devices are connected to the system.
- MPU check whether data is available from peripheral in a continuous looping. Its called
polling, because it checks the status time by time.
- Each device is tested, using either hardware / software, until the device which has
requested the interrupt, is identified. (If testing is done by Hardware then its call Hardware
polling, and if it is by written code then it calls Software polling)
- Corresponding to the device thus identified, the program is then diverted to the ISS written
for that device.
Vectored Interrupt
- In the vectored interrupt scheme the requesting device causes the program to be branched
to the ISS (Interrupt Service Subroutine) straightway.
- In general, vectored interrupt schemes are faster than polled interrupt schemes.

Note:
In the asynchronous mode of data transfer scheme it is the processor which goes on checking the device
status; in the interrupt driven mode of data transfer scheme it is the device which interrupts the system.

In polled interrupt scheme (whether hardware/software) the priority of each device is fixed (by the
programmer). It will take time before the interrupting device is identified.



Peripheral Controlled Data Transfer / Direct Memory Access (DMA) transfer.
In DMA mode, straight data exchange takes place between memory and I/O device bypassing the
processor. This is done with the help of a DMA controller. In DMA mode, the DMA controller acts as a
Master and the processor as a Slave.

The processor must have the following features to facilitate DMA mode of data transfer:
- An input line through which the processor accepts request from DMA controller for DMA mode of
data transfer (This is the HOLD pin for 8085).
- An output line through which the processor tells the DMA controller that it (processor) has accepted
the request (This is the HLDA pin for 8085)
- The processor must tri-state its AB, DB and necessary control lines before handing over the control
to the DMA controller.

The DMA controller IC must have the following features:
- An output line through which it requests the processor for DMA mode of data transfer.
- An input line through which it accepts the granted DMA request

Interfacing
The functions needed for peripheral interfacing are:
Buffering, Address decoding, Command decoding, and timing & control
- Buffering is necessary to increase drive and also to synchronize data exchange between the
microprocessor and peripheral.
- Address decoding helps to select particular I/O.
- Command decoding is needed for some special I/Os that perform jobs other than data transferse.g.
rewinding a tape drive.
- For coordinating the above three, timing & control is needed.

Problems in interface I/O device with a processor:
- Speed Incompatibility: In many cases the I/O devices are slower than the processor so that a situation
may arise when the processor is in a position to accept data but the peripheral dont.
- Format Incompatibility: If a 12/16-bit ADC/DAC is tried to be interfaced with an 8-bit MPU.
- Electrical Characteristic Incompatibility: Due to current or voltage incomparability or both.

It is relatively easy to interface a memory with a processor because memories are usually
manufactured with the same technology as those of the CPUs and they are compatible to the CPUs with
regard to speed and electrical compatibility.

Address Space and its partitioning.
- Address space is a set of all possible addresses that a microprocessor can generate.
- 8085 MPU has a 16-bit address bus so that it can address 216 or 64 KB of address, called the address
space of 8085. This total address space can be partitioned / allocated to memory or I/O devices so that
they can be addressed properly; its calls address space partitioning.
- The address space can be partitioned in two scheme / ways:
a. Memory mapped I/O scheme
In this, there is only one address space, which is allocated to both memory and I/O devices, in
some degree.
The address for I/O devices is different from the addresses which have been assigned to
memories. An I/O device is also treated as a memory location.
Each memory location and I/O device are assigned with separate addresses.(different to all)
In this, I0N
signal is not used to distinguish between memory and I/O devices. An I/O device
is interfaced in the same manner as a memory device.
All data transfer instructions of the microprocessor can be used for transferring data from and
to either memory or I/O devices.


This scheme is suitable for small systems.

b. I/O mapped I/O scheme
Some MPUs provide more control lines, the status of which indicates either memory or I/O
operation.
The status of I0N
indicates I/O operation or memory operation. In this case, the same address
may be assigned to both, memory or an I/O device.
Here two separate address spaces exist; one space is meant exclusively for memory operations
and the other for I/O operations. Usually, the space earmarked for I/O is much smaller than
memory space.

Memory Mapped I/O I/O Mapped I/O
1 Address length is 16-bit. Address length is 8-bit.
2
MEMR & MEMW signals are used to control
read and write I/O operations respectively.
IOR & IOW signals are used to control read and
write I/O operations respectively.
3
Each I/O device is treated like a memory
location and they are accessed using
instructions related to memory operations.
IN and OUT are the only available instructions.
4
Data transfer takes place between any register
and I/O device.
Data transfer takes place between accumulator
and I/O device.
5
Maximum number of I/O devices that can be
addressed is 65536 (theoretically).
Maximum number of I/O devices that can be
addressed is 256.
6
Execution speed Using STA, LDA it is 13 T-
state. And for MOV M, r, etc., it is 7-T states.
Execution speed is 10 T-states, for both IN and
OUT.
7
Decoding 16-bit address will require more
hardware circuitry.
Decoding 8-bit address will require less
hardware circuitry.
8 Used when memory requirement is small. Used when whole big memory is required.

Microprocessor can communicate (read or write) with only one device at any given instant. Because
the data, address and the control bus for all the devices connected to the microprocessor are common. Thus
to communicate properly with a device (memory or I/O), decoding of address is a must required. Thus
address decoding pinpoints a particular memory location or I/O.
Two kinds of address decoding techniques: a. Absolute (Full decoding) b. Linear (Partial decoding)

Absolute (Full Address Decoding) Linear (Partial Address Decoding)
1 Used in large memory systems Used in small memory systems.
2 All higher order address lines are decoded
to select the memory or I/O device.
A few high order address lines are utilized to select
individual memory or I/O chips.
3 Decoding logic requires more hardware. Hardware requirement for decoding is very small
and not required in very small dedicated systems.
4 No multiple addresses Suffers from the drawback of multiple addresses (It
calls Shadow Addresses).
5 Higher cost of decoding Lesser cost of decoding.
6 Memory expansion is easier. Memory expansion is difficult.
7 No bus contention problem May bus contention problem (occur if more than one
memory chip gets selected because of wrong address
generation.)



Interrupts

Interrupt is a signal sends by an external device to the processor, to perform a particular task. Mainly
in the microprocessor based system the interrupts are used for data transfer between the peripheral and the
microprocessor.

EI Use this instruction to enable the interrupt.
DI Use this instruction to disable the interrupt.
INTR Microprocessor checks the status of this signal time by time
during the execution of the program. If signal goes high, it
shows that interrupt occur.
INTA
This signal is use to insert the RST instruction through

external hardware, to handle the interrupt. (RST works in a
similar way as CALL)

Note: It could be possible that before completing the Service Routine a new interrupt arrive. In this
condition what to do is must be specified by the programmer. You can disable the interrupt while executing
any ISR to simplify. And you can also handle multiple interrupt with priorities.

Classification of Interrupt Requests

Software interrupts:
- The software interrupts are program instructions.
- When the instruction is executed, the processor executes an ISR (interrupt service routine) stored
in the vector address of the software interrupt instruction.
- When the processor encounters the software interrupt, it PUSH the content of PC to stack. Then
loads the Vector address of ISR in PC and starts executing it. At the end of ISR, a return
instruction is executed and the processor POP the content of stack to PC.
- Execution of ISR is referred to as servicing of interrupt.
- All software interrupts of 8085 are vectored interrupts.
- The software interrupts cannot be masked and they cannot be disabled.
- Ex. RST 0 to RST 7

Hardware interrupts:
- Are initiated by an external device by placing an appropriate signal at the interrupt pin of the
processor.
- The processor keeps on checking the interrupt pins at the second T -state of last machine cycle of
every instruction. If the processor finds a valid interrupt signal and if the interrupt is unmasked and
enabled, then the processor accepts the interrupt.
- The acceptance of the interrupt is acknowledged by sending an INTA signal to the interrupted
device. The processor saves the content of PC in stack and then loads the vector address of the
interrupt in PC. (If the interrupt is non-vectored, then the interrupting device has to supply the
address of ISR when it receives INTA signal). It starts executing ISR in this address. And at the
end drive back the PC from stack.
- The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Interrupts may be classified into:

a. Vectored Interrupt
In vectored interrupts, the processor automatically branches to the specific address in response to an
interrupt. In this, the manufacturer fixes the address of the ISR to which the program control is to be
transferred.
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
RST Restart Instructions
Memonics Hex Code
Call
Location
RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038


b. Non-Vectored Interrupt
In non-vectored interrupts the interrupted device should give the address of the ISR. The INTR is a
non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR
after receiving interrupt acknowledge signal.

The hardware vectored interrupts are further classified into Maskable and Non-Maskable Interrupts
One bit is used to set the interrupt Maskable or Non-Maskable Interrupt (NMI). We can ignore the
interrupt by set that bit. But the interrupts which we cannot ignore is called NMI.
TRAP is Non-Maskable interrupt. (you cannot disable it, must attend)
RST 7.5, RST 6.5 and RST 5.5 are Maskable interrupt.
- Masking is preventing the interrupt from disturbing the main program.
- When an interrupt is masked the processor will not accept the interrupt signal.
- The interrupts can be masked by moving an appropriate data (or code) to accumulator and then
executing SIM (Set Interrupt Mask) instruction.
- The status of Maskable interrupts can be read into accumulator by executing RIM instruction
(RIM - Read Interrupt Mask).

Edge and Level sensitivity of Interrupts
- Edge level interrupts are recognized on the falling or rising edge of the input signal.
- They are generally used for high priority interrupts and are latched internally inside the processor.
- If this latching was not done, the processor could easily miss the falling edge (due to its short
duration) and thus not respond to the interrupt request.

- Level sensitive interrupts overcome the problem of latching, in that the requesting device holds the
interrupt line at a specified logic state (normally logic zero) till the processor acknowledges the
interrupt.
- This type of interrupt can be shared by other devices in a wired 'OR' configuration, which is
commonly used to support daisy chaining and other techniques.

Interrupt Response Time: The time interval between the CPU recognizing the interrupt to the time when the
first instruction of the ISR is executed. This is determined by the processor architecture and clock speed.

- INTR (Interrupt Request) Used for general purpose interrupt.
- INTA
(Interrupt Acknowledge) to acknowledge the interrupt.

- TRAP interrupt is edge and level sensitive. It is Non-Maskable and highest priority interrupt.
- Restart Interrupts:
RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal has to
make a low to high transition and it need not remain high until it is recognized
RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the interrupting
signal should remain high, until it is recognized.

Priority: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR

All the hardware interrupts (except TRAP) are disabled, when the processor reset the Interrupt Enable Flip-
Flop.

SIM (Set Interrupt Mask) Instruction:
- It is 1 byte instruction, used to set the hardware interrupt.



RIM (Read Interrupt Mask) Instruction:
- It is a 1 byte instruction to read the interrupt mask.
- When many interrupt occurs, and one ISR is running, other interrupts may occur and pending.
The RIM handles this pending req.

B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0

SOD SDE X R 7.5 MSE M7.5 M6.5 M5.5
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0

SID I 7.5 I 6.5 I 5.5 IE M7.5 M6.5 M5.5
RST 7.5, RST 6.5, RST 5.5 MASK
0 = Available 1 = Masked

If B
6
is 1, then B
7
is output to
Serial Output data. B
7
will
ignored if B
6
=0
Mask Set Enable 0 bits 0-2 ignored
1 Mask is set
RESET RST 7.5
If 1, RST 7.5 is
reset OFF
Fig: SIM Instruction
Interrupt Mask:
1 Masked
Pending Interrupt:
1 Pending
Interrupt
Enable Flag:
1 Enable
Fig: RIM Instruction


8085 PROGRAMMING

Understating about instructions of 8085.

In general lives human use different techniques to communicate, for exchange of thoughts. That may be
language, for example sign language and general languages. That may be in a form of written, picture, or in
speech. So to communicate with the computer we require some language, to perform operation on it and get
result. As in human language theres also an grammar for machine language. So,

Word: a number of bits microprocessor recognize and process at a time. Nibble: group of four bits
Bit: Basic unit of memory to store a signal (0 or 1). Byte: group of eight bits

Computer system works on 0 and 1 form, or says Binary form. There is only two condition Yes or No.
So we can send high(0) and low(1) signal to processor and can perform operation. This is called Machine
Language, basic language which machine can understand and execute it. We can make a set of the binary bits
and use it for different commands. This set of bits is called Instruction. In microprocessor there is a
memory which stores the set of instruction; to perform appropriate operation is called Instruction set. Here
the number of bits used in this instruction is becomes the microprocessors bit. For example 8085 is 8-bit
MPU, because the bit length of instruction is 8 bit.
By the series of instruction (calls a program) we can perform full operation. And to write that kind of
program is called programming of microprocessor.
Well to send data in Binary form takes too much time and its also an error inductive. To simply this we
can use Hexadecimal Number according to their binary instruction. (For example, 1010 1011 = AB,
1111 1111 = FF, 0001 0010 = 12). If the hex-number has some meaning or says any instruction is associated
with it, then that number is called Hex Code. We can send this Hex Code to MPU through the Hex Keyboard
and fire/execute it.

Hex Code is also difficult to remember, so to simplify it the manufacturer of microprocessor has devised
a symbolic code for each instruction, called mnemonic.
For example: NOP instead 00 and HLT instead 76
The use of Hex Code or mnemonic in writing is called Assembly Language. So the programming in this
language is called Assembly Language Programming.

Classification of Instructions by its Word Size / Group of Instruction
The instruction set of 8085 is defined by the manufacturer Intel Corporation (another set is also available
by ASCII). The instruction set is grouped by its Word size. Instruction commands the processor to perform a
given task on given data. It has two parts: [Instruction = Opcode + Operand]
1 Opcode (Operation Code), operation to de performed on data.
2 Operand, data to be operated on.
Each instruction of 8085 has 1-byte (8-bit) of opcode. (With 8 bit binary code, we can generate 256
different binary codes.)

One byte:

Two byte:

Three byte:

8 Bit Data / Address Opcode
Opcode
Opcode 8 bit Low-Address / Data 8 Bit High-Address / Data


Binary Code Hex
Code
Opcode Operand Operation Note:
In 3-byte instruction Lower
Order address byte will be in
2
nd
byte and 3
rd
will contain
Higher Order address.
1000 0000

80 H ADD B Add the content of reg. B in A
0011 1110
0011 0010

3E
32
MVI A, 32H Load 8-bit data in A
0011 1010
0001 1010
0010 1011
3A
1A
2B
LDA 2B1AH Load content of memory
address 2A1B in A

Classification of Instructions by its Nature:
a. Data Transfer (to transfer the data from or into memory / IO ports)
b. Arithmetic (To perform Arithmetic operation on data.)
c. Logical (it performs AND, OR, X- (Exclusive), Compare and Rotate operation on data)
d. Branch (it helps to entertain program counter, to control program)
e. Machine Control and I/O (to control Processor and other attached devices.)

ADDRESSING MODES
Every instruction of a program has to operate on a data. The method of specifying the data to be
operated by the instruction is called Addressing. The 8085 has the following 5 different types of addressing.
1. Immediate Addressing
- In this, the data is specified in the instruction itself.
- All instructions that have I in their mnemonics are of Immediate addressing type.
Ex. MVI C, 45H - Move the data 45H given in the instruction to C register.

2. Direct Addressing
- In this, the address of the data is specified in the instruction.
- This type of addressing can be identified by 16-bit address present in the instruction.
Ex. LDA 1050H - Load the data available in memory location 1050H to accumulator.

3. Register Addressing
- In this, the instruction specifies the name of the register in which the data is available.
- This type of addressing can be identified by register names (such as A, B, ) in the instruction.
Ex. MOV A, B -Move the content of B register to A register

4. Register Indirect Addressing / Indirect Addressing
- In this, the instruction specifies the name of the register in which the address of the data is available.
Here the data will be in memory and the address will be in the register pair.
- This type of addressing can be identified by letter M present in the instruction.
Ex. MOV A, M - The memory data addressed by HL pair is moved to A register.

5. Implicit Addressing / Implied Addressing
- In this, the instruction contains only opcode, there is no operand.
Ex. CMA - Complement the content of accumulator.



Programming Techniques

Programming is a logical approach to instruct the microprocessor to perform operation in a given
sequence.

Looping & Indexing
The programming technique used to instruct the microprocessor to repeat the task is called looping.
It has two groups:
1. Continuous: repeat a task continuously (in infinite manner)
2. Conditional: repeat a task until certain data conditions are met.

Indexing: means pointing or refreshing objects with sequential numbers.

Counter and Time Delay Techniques
Counters are primarily used to keep track of events. Time delays are important in setting up accurate
timing between tracks of events.
You can setup a counter by making a looping program and set a counter for it.
The counter can be set as register or register pair, and also do nesting of loop.
The time delay is a total time we obtain in finishing the counter.

Time Delay TL = T * Loop T-stats * N
10
Here, T System Clock Period (T=1/f, f is a frequency of MPU)
Loop T-Stats: one subdivision of the operation performed in one clock period.
N
10
Equivalent decimal number of the hexadecimal count loaded in delay register/counter.

Example:

External clock frequency = 6 MHz
So, Internal clock frequency f = External Frequency/2
= 6 / 2 = 3 MHz

Time period for 1 T-State (T) = 1 / f = 1 / 310
-6
= 0.333 S

TL = 0.333 10
-6
14 100 (suppose N=64H. So its decimal is 100)
= 4.66 10
-4

0.46 ms

Stack and Subroutine
The stack is a group of memory location in the r/w memory that is used for temporary storage of
binary information during the execution of the program.
- The stack is generally allocated at the end of the memory, to eliminate the collision between user
program and binary stack. So when you add data in stack the SP will decrees.
- The stack pointer (SP) is used to point a stack (shows the address of the TOP of the stack).
- Stack works in LIFO system.
- Stack is used to store instruction, data or program (temporarily in between the execution of the
program). Also use in subroutine calls to store the return address.
- The stack pointer is decremented by one memory location before data starts storing into the stack.
- So the SP can be initialized with a value which is one higher then the highest read/write memory
location which is available.

Number of
T-States
MVI B, N ; Load Counter with value N 7
Loop: DCR B ; Decrement count 4
JNZ Loop ; If count 0, then repeat 10/7


Define the stack pointer in two ways:
a. Direct way: LXI SP, XXXX H
b. Indirect way: LXI H, XXXX H then => SPHL
To add date in stack : PUSH R
To remove data from stack : POP

A subroutine is a group of instruction that perform a subtask of repeated occurrences of same
operation.
The different types of subroutines:
- Multiple-calling of a subroutine
By making condition we can call a subroutine many times. And also calls different subroutines from
a single program. It calls multiple calling of subroutine.

- Nesting of subroutines
One subroutine calls second subroutine and second calls third and so on, it calls nesting.
Conditional Call and Return instructions used for nested subroutines. Theoretically we can nest
infinite number of subroutine but, in actual it is limited by the size of memory.
It has two types: a. Recursive b. Re-entrant

a. Recursive: A recursive subroutine is a subroutine which is called by itself and is used with complex
data structures, known as trees.
b. Re-entrant: In nested subroutines, if a latter subroutine calls an earlier one, then it is known as re-
entrant subroutine.

- Multiple ending subroutines
Like a multiple calling return or ending is also possible with condition. That calls multipal ending
subroutine.

Main
Program
Call SB Call SB
Call SB
SB SB SB
END
Main
Program
Call SB2
Call SB1
SB2 SB1
END
RET RET
RET
Return to
MP / SB2
Call SB1
Fig: Recursive Subroutine Fig: Re-entrant Subroutine
SB = Subroutine
SB1= Subroutine1
SB2= Subroutine2
RET
(Indirect way is used when
programmer wants to set the SP to
deal with complex program)


How to Deal With the Problem / Assembly Language Prog.

- First understand the problem. That what kind of program it is.
- Then break it in section if the problem is bigger.
- Then check the prog. that what kind / class of instruction you have to use. Try to find the alternative
for the instruction which is not available.
- Try to make prog. with few instructions.
- Find out that can you use a counter, stack of subroutine. If you require a stack then initialize the SP
in beginning. On the last memory address.
- Try to max use of subroutine, because you can use it in other problems too. For example you made a
subroutine for display image on projector screen. You can use it in any prog. where you want to
display the image.
- Make counter simple and reusable with the you of parameter passing.
-



Debugging

A debugger is a software tool which separates the problems / drawbacks in a programmers program.

A debugger helps in debugging a program in the following ways:
- Debuggers helps in checking the contents of memory locations and various registers and also alter the
same if required and rerun the program to check the correctness of the modified program.
- Program execution can be stopped after each instructionhence step by step checking is possible with a
debugger.
- A debugger can set a breakpoint at any place in a program.

A program then can run up to the breakpoint address and not beyond. Thus any fault in the program up
to the breakpoint address can be checked by having a look at the various registers and memory contents. If
no fault occurs the breakpoint is set at a latter address in the program and the debugger can again be rerun to
check for the correctness of the program. This way the whole program can be corrected by judiciously
inserting breakpoints in a program.

Static Debugging: Just check the flowchart and machine code.
Dynamic Debugging: Observing the output or register contents, following the execution of each instruction
(the single step technique) or of a group of instruction (the breakpoint technique).

Tools of Dynamic Debugging:
a. Single Step
Execute the program step by step or say one by one instruction, and observe the results after each
instruction.
b. Breakpoint
It allows executing the program in section. You can make breakpoint in program, to check the result
of group of instruction after the execution. It is just like single step accept that here we execute a
group of instruction.
c. Register Examine
You can check the register status and flag status to know the flow of program. You can also use it
with single step or break point.



8085 Programmable Peripheral Dei!e"

Programmable devices are designed to carry out various I/O functions. They are flexible, versatile,
economical and widely used in microprocessor based system. It provides support to the main system. As its
name shows we can program/function these devices, by writing instructions in its internal registers (calls
control registers). And we can change these functions in between the execution, by changing the instructions
(instruction is calls control word in sense of device) in control registers.

Programmable Interface Devices:
- 8155 I/O and Timer - 8279 Keyboard / Display
Requirement of these devices: 1. I/O Register (a group of letches to hold data)
2. Tri-State Buffers 3. Capability of bidirectional data flow 4. Control Signal
5. Chip select logic 6.Handshake and interrupt signal 7. Interrupt control logic

General Purpose Programmable Devices:
- 8255A Peripheral Interface - 8254 Interval Timer
- 8259A Interrupt Controller - 8237 DMA Controller

8155 I/O Ports and Timer

Functionally, it has two sections: (a) a R/W memory and (b) programmable I/O and timer section.


The essential features of 8155 are: 1. 8-bit 256 word RAM memory
2. Two programmable 8-bit I/O port 3. One programmable 6-bit IO port
4. An internal decoder 4. One programmable 14-bit binary Timer/Counter
6. An internal address latch 5. A control/status (C/S) registers

Control Word Format

D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

Status Word
X Timer INTE
B
BF
B
INTR
B
INTE
A
BF
A
INTR
A

INTR Interrupt Request
A
for port A &
B
for port B
BF Buffer Full Timer Timer interrupt (Is latched High when terminal count is reach-
INTE Interrupt Enable ed, and is reset to Low upon reading of C/S reg. and by hardware reset)

Port A 0 = Input

Port B 1 = Output
Port C
00 ALT1, 11 ALT2
01 ALT3, 10 ALT4
IE
A
= Interrupt Enable Port A 1 = Enable
IE
B
= Interrupt Enable Port B 0 = Disable
00 NOP (No effect on timer)
01 Stop (Stop the counter if timer is running; else no effect)
10 Stop after TC(Terminal Count)
Stop after at end of the counter if timer is running; else no effect on timer.
11 Start. Start the timer if it is not running; if it is running, stop at the end of count.
Reload new mode and count, and start again.


8279 Keyboard / Display Interface

Features / Boasts:
Provides three input mode for keyboard interface.
Provide scanned interface to 64 contact key matrix, using CONTROL and SHIFT key.
Supports multiplexed display interface with blanking and control option and two modes.
Support 16 byte display RAM.
Support key debounce.
It scans the keyboard, then detects the key press and transmits to the CPU information which
corresponds to the particular key pressed. (So no need of s/w polling)
It puts out data received from the CPU, for use by the display devices.

- The Functional Blocks of 8279:
A. CPU interface
It looks after the data transmission between 8279 and MPU, with eight bidirectional data lines
DB0 to DB7.
The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
The 8279 require an internal clock frequency of 100 kHz. (This can be obtained by dividing
the input clock by an internal pre-scale)
The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard
modes.

B. Input lines for key data
It consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard
matrix and also have an 8 x 8 FIFO (First In First Out) RAM.
It has two additional input: shift and control/strobe. The keys are automatically debounced.


The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and
control key are also stored along with key code. The 8279 generate an interrupt signal when
there is an entry in FIFO.
In sensor matrix mode the condition of 64 switches is stored in FIFO RAM. If the condition of
any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

C. Set of scan lines
The scan lines are common for keyboard and display.
One scan counter and four scan lines, SL0 to SL3.
In decoded scan mode, the output will be similar to a 2-to-4 decoder.
In encoded scan mode, the output will be binary count. (An external decoder can be used to
convert the binary count to decoded output.)
The scan lines are used to form the rows of a matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.

D. Output lines for display data.
Eight output lines divided into two groups A0-A3 and B0-B3.
Supports 16 x 8 display RAM.
The output lines can be used either as a single group of 8 lines or as two groups of 4 lines, in
conjunction with the scan lines for a multiplexed display.
The output lines are connected to the anodes through driver transistor in case of common
cathode 7-segment LEDs.
The display can be blanked by BD (low) line.

- Input Modes: Three Basic input modes.
1. Scanned Keyboard Mode
This mode further divided into two: A. 2 key lockout and B. N-key rollover
A. 2 Key Lockout:
In this Mode, when any key is pressed, it waits for next two scans to check whether any other
key is pressed or not. Two possibilities while scanning are,
I) If no other key press is detected. Then data corresponding to key press is taken to RAM in
8279 and IRQ output line goes into high state. If internal RAM of 8279 is already full, the keyed
data is ignored and the error flag is set.
II) If one or more additional key pressing occurs, no data entry into RAM is allowed. In this
case two possibilities occur:
1. If the first key (the key which was pressed first) is released ahead of others, then the key
press is ignored.
2. If all the keys are released before the key first pressed, then data corresponding to first key
pressed, is load into the RAM of 8279.
III) Another possibility is pressing of two keys within one debounce cycle (the time required
for eliminating contact bounce effect is known as contact debounce time). In this case, no key is
recognized. When one key is released, the other key that remains pressed is recognized as a
single valid key depression.

B. N Key Rollover:
In this case, the debounce circuit waits for two scans after the first key press. Then checks
whether key is still in the pressed condition or not. If yes, then the data corresponding to the key
press is taken into RAM of 8279. No limit is there to the number of key presses. For
simultaneous key presses, data are entered according to the order of key press.
If within a single debounce cycle, two keys are found pressed, the error flag is set and data
entry into the RAM is prohibited. The error flag can be read from the FIFO STATUS word and
can be cleared by a CLEAR command (CF = 1).

2. Scanned Sensor Matrix Mode:


In the Scanned Sensor Matrix Mode of operation, the keys are arranged in the form of a
matrix, with the scan lines (SL0 SL2) forming the columns and return lines (RL0 RL7) forming
the rows. The open/closed condition of the key is stored in a RAM location. The size of the matrix be
8 8 or 4 8 for encoded and decoded scan lines respectively.
The data entering via the RL lines are admitted into eight columns of the sensor RAMthus
each RAM position corresponds to a specific switch position. Apart from switches, other logic
circuit output lines can be connected to the RL lines.

3. Strobed Input Mode:
In this mode, data are placed on the return lines (RLs). The source of data may be an
encoded keyboard or a switch matrix. The data so entering go to FIFO RAM and are accepted on
the rising edge of a CNTL/STB pulse.

- Display / Output Modes:
1. Left Entry Mode(Type Writer type)
In this mode, the first entry goes to the left most display position. The second entry to the
just right of the earlier one (the first entry goes to address 0, the second entry to address 1 and so on,
and the 16th entry goes to 15th address position). It is to be remembered that the 17th entry goes to
the RAM address 0 again, 18th entry goes to RAM address 1 and so on.
2. Right Entry Mode (Calculator type)
In this mode, the characters are entered from the right most position. As characters are
entered one after another, the present data occupies the right most position; just the earlier one
occupies the left of the right most position.

The options available in the display mode are:
Display format Left entry or Right entry.
Number of display characters 8 or 16.
Organization of characters Single 8-bit or dual 4-bit.

- Scanning Modes:
The four scan lines (SL0 SL3) can be operated in two modes: encoded and decoded mode.
Encoded mode:
In this, 16 lines are generated using the 4 scan lines and a 4 16 external decoder. And 8
decoded scan lines are possible with SL0 SL2 lines and a 3 8 decoder. These 8 lines, along with
eight return lines (RL0 RL7) can form an 8 8 keyboard matrix. Thus it leads to 64 different
character definitions.
With SHIFT and CONTROL input lines taken as two additional input lines, total character
definitions possible = 64 22 = 256.
Decoded mode:
Using the internal decoder present in 8279, SL0SL3 lines are decoded.
With SHIFT and CONTROL lines along with RL0 RL7 lines, total character definition
now possible is = 4 8 4 = 128.

M B Rajpara

8255A Programmable Peripheral Interface

Features / Boasts:
It is widely used IC and compatible with most other MPUs.
Basically there are three 8-bit
But Port C can be divided into C
Thus 8255 can be viewed with four P
PPI 8255 can operate in 4 modes.
selected by the control word register (bit D7).

I / 0 Modes: (Mode 0, Mode 1, and Mode 2
Mode 0: Basic or simple I/O mode,
- All ports can be programmed i
- Sixteen possible input/output configurations are possible.
- Ports dont have handshake or interrupt capability.

Mode 1: Transferring of data is carried out by the help of handshaking signals, also known as strobe signals
(because it is used for synchronization).
- Ports A and B can function as 8
either as input or output port.
- In this mode, Port C is called status port.
- Interrupt logic is supported.
- Handshake signals are
check or Interrupt. In the
becomes ready, while interrupts overcome this.)
- There are two groups in this mode
group consists of an 8-bit port and a 4

Mode 2: In this mode, Port A can be set up for bidirectional data transfer using handshake signals from Port
C. Port B can be set up either in mode 0 or mode 1.

8255A Programmable Peripheral Interface (PPI)
It is widely used IC and compatible with most other MPUs.
bit Ports in 8255, A, B and C, each having 8 pins.
Port C can be divided into C
UPPER
and C
LOWER
, each having four pins (a nibble).
Thus 8255 can be viewed with four PortsPort A, Port B, Port C
UPPER
and Port C
modes. (a) Mode 0 (b) Mode 1 and (c) Mode 2. These are I/O operations and
selected by the control word register (bit D7). And another mode is BSR mode (Bit Set/Reset mode).
Mode 0, Mode 1, and Mode 2)
: Basic or simple I/O mode, features are:
can be programmed in either input or output mode. - Outputs are latched.
Sixteen possible input/output configurations are possible. - Inputs are not latched.
Ports dont have handshake or interrupt capability.
rring of data is carried out by the help of handshaking signals, also known as strobe signals
(because it is used for synchronization). Its features are,
Ports A and B can function as 8-bit I/O ports, with the help of Port C.
either as input or output port.
In this mode, Port C is called status port.
Interrupt logic is supported.
Handshake signals are used to data transfer. (Handshake signals can be used either with
. In the status check, the CPU gets tied up in a loop until the status of the I/O
becomes ready, while interrupts overcome this.)
There are two groups in this modegroup A and group B. They can be configured separately. Each
bit port and a 4-bit port. This 4-bit port is used for handshaking in each group.
: In this mode, Port A can be set up for bidirectional data transfer using handshake signals from Port
C. Port B can be set up either in mode 0 or mode 1.
28

, each having four pins (a nibble).
and Port C
LOWER
.
Mode 0 (b) Mode 1 and (c) Mode 2. These are I/O operations and
BSR mode (Bit Set/Reset mode).
Outputs are latched.
Inputs are not latched.
rring of data is carried out by the help of handshaking signals, also known as strobe signals
A and B can be configured
Handshake signals can be used either with status
, the CPU gets tied up in a loop until the status of the I/O
group A and group B. They can be configured separately. Each
bit port is used for handshaking in each group.
: In this mode, Port A can be set up for bidirectional data transfer using handshake signals from Port


BSR (Bit Set Reset) Mode: characteristics of BSR
- BSR mode is selected only when D
7
= 0 in CWR.
- Concerned with bits of port C. Individual bits of
Port C can either be Set or Reset.
- At a time, only a single bit of port C can be Set
or Reset.
- Is used for control or on/off switch.
- BSR control word doesnt affect ports A and B
functioning.

Signals for Modes:

Used in both (Input & Output) Control Signal
- INTR: Interpret request
- INTE: Interpret Enable

Input Control Signal
- SIB
: Strobe Input, is a signal generated by input device to inform the CPU that data to be read is
already sent on the port lines of 8255. So 8255 loads the data in to input buffer of appropriate port
from its port lines.
- IBF: Input Buffer Full, is a acknowledgement signal (in response to SIB
) generated by MPU to inform

the input device that input latch has received the data byte. It reset when the MPU reads the data.

Output Control Signal
- 0BF
: Output Buffer Full, is a signal generated by MPU to inform the input device that data is sent
from output latch of MPU. This signal goes high after receiving the ACK
signal from device.

- ACK
: Acknowledgement, is a signal generated by device to acknowledge the 0BF
signal of MPU, that

data will received by device.

Fig : Control Word Register (CWR) in I/O Mode
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

0 X X X S/R

D
3
D
2
D
1
Bit of Prot C
Selected
0 0 0 Bit 0
0 0 1 Bit 1
0 1 0 Bit 2
0 1 1 Bit 3
1 0 0 Bit 4
1 0 1 Bit 5
1 1 0 Bit 6
1 1 1 Bit 7

Fig: CWR in BSR Mode
Note:
Mode 0:
Simple I/O for all three ports.

Mode 1:
Handshake I/O for Port A &
Port B. Port C bits are used
for handshake signal.

Mode 2:
Bidirectional data bus only for
Port A. Port B can be used in
either mode 0 or mode 1.
Handshake signals derived
from Port C.
X Dont Care
Condition

S/R
1 = Set,
0 = Reset
M B Rajpara

8253 / 8254 Programmable
Fig: 8253 PIT Functional Block and Diagram & Pin Diagram

8254 is a successor version of 8253, with few
- 8254 works on 0 10 MHz
- 8254 has Read Back Command

Features / Boasts:
It can generates accurate time delays
Counter, a Square Wave Generator, and a Complex Wave Form Generator.
Three 16 bit independent counters
Counters are identical and
Having READ BACK command

Control Word Format:
D
7

SC
1

SC
1
SC
2

0 0 Select Counter 0
1 1 Read Back Command in 8254
(See Read Operations)
Not works in 8253

RW
1
RW
0
Read / Write
0 0 Counter Latch Command
0 1 R/W Least Significant byte only
1 0 R/W Most Significant
1 1 R/W Least Significant byte first,
Then most significant byte.


Programmable Interval Timer (PIT)
version of 8253, with few enhancements as mentioned below.
10 MHz (8253 works on 0 2.6 MHz)
Read Back Command (can letch the count and the status of the counter)
It can generates accurate time delays and can used for application like Real Time
Counter, a Square Wave Generator, and a Complex Wave Form Generator.
counters, with six different Modes.
Counters are identical and programmable for either BCD or Binary count.
Having READ BACK command facility.
D
6
D
5
D
4
D
3
D
2
D
1

SC
0
RW
1
RW
0
M
2
M
1
M
0

M
2
M
0 0
0 0
X 1
X 1
1 0
1 0

Select Counter 0
Select Counter 1
Select Counter 2
Read Back Command in 8254
(See Read Operations)
Not works in 8253
Read / Write
Counter Latch Command
R/W Least Significant byte only
R/W Most Significant byte only
R/W Least Significant byte first,
Then most significant byte.
BCD
0 Binary Counter 16
1 BCD Counter (4 Decades)

30

as mentioned below.
(can letch the count and the status of the counter).
and can used for application like Real Time Clock, an Event

D
0

BCD
1
M
0

0 Mode 0
1 Mode 1
0 Mode 2
1 Mode 3
0 Mode 4
1 Mode 5
Binary Counter 16 bit
BCD Counter (4 Decades)


Modes: It has six different modes
A. Mode 0: Interrupt on terminal count
B. Mode 1: Hardware Retriggerable One Shot
C. Mode 2: Rate Generator
D. Mode 3: Square Wave Rate Generator
E. Mode 4: Software Triggered Strobe
F. Mode 5: Hardware Triggered Strobe (Retriggerable)

Read Back Command:
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0

1 1 C0uNI
SIAIuS
CNT 2 CNT 1 CNT 0 0

D5: 0 Latch Count of Selected Counter(s) A
0
, A
1
= 11
D4: 0 Latch Status of Selected Counter(s) CS
= 0
D3: 1- Select counter 2 RB
= 1
D2: 1- Select counter 1 WR
= 0
D1: 1- Select counter 0
D0: Reserved for Future Expansion; Must be 0

Fig: Read Back Command Format

READ BACK command allows the user to read the count and the status of the counter. The
command is written in the control register, and the count of specified counter can be latched if C0uNI
is
0. This command eliminates the need of writing separate latch commands for different counters.

M B Rajpara

8259A Programmable Interrupt Controller
Features / Boasts:
Can manage eight priority interrupts
equivalent to providing 8 interrupt pins on processor in place of INTR pin.
8259 can be cascaded to have 64 levels of vectored priority interrupts in a microprocessor system.
The priority modes can be changed or reconfigured dynami
It can be operated in various interrupt modes
8259 supports both edge and level triggered mode of interrupts.
The CALL address can be programmed to have a
The data bus is buffered.
8259 can be used with either 8080/8085 or 8086/8088 microprocessor.
The AEOI (Automatic End

- PIC 8259 can accept a maximum of 8 interrupts from 8 differen
regard to servicing the interrupts and issues an INT output signal, which is connected to INTR input pin.

- PIC 8259 has four different functional blocks.
1. Interrupt and Control logic block
This block consists of
(b) In Service Register (ISR)
(d) Interrupt Mask Register (IMR)
2. Data bus buffer
3. Read/Write control logic block
4. Cascade buffer/comparator section.

- 8259 can be operated through OCW (Operation Comman
In the following four categories of
1. Fully Nested Mode (FNM)
This mode is a default mode (auto
IR0 is assigned the highest priority and IR7 the lowest priority (priority 7).
When 8259 acknowledges an interrupt request via its INTR pin, it finds out the highest priority
and the corresponding bit in the ISR (Interrupt Service Register).
It is further enhanced with, Special Full Nested Mode
interrupt request. Because the FNM

8259A Programmable Interrupt Controller (PIC)
Can manage eight priority interrupts according to the instruction written in it
equivalent to providing 8 interrupt pins on processor in place of INTR pin.
The priority modes can be changed or reconfigured dynamically at any time during the main program.
It can be operated in various interrupt modesfully nested, rotating priority, special mask and polled.
8259 supports both edge and level triggered mode of interrupts.
The CALL address can be programmed to have a spacing of either 4 or 8 memory locations.
8259 can be used with either 8080/8085 or 8086/8088 microprocessor.
The AEOI (Automatic End of Interrupt) can be programmed.
PIC 8259 can accept a maximum of 8 interrupts from 8 different I/O devices, resolves the priority with
ifferent functional blocks.
Interrupt and Control logic block
consists of: (a) Interrupt Request Register (IRR)
(b) In Service Register (ISR) (c) Priority Resolver
(d) Interrupt Mask Register (IMR) (e) Control Logic Block.
ad/Write control logic block
Cascade buffer/comparator section.
ed through OCW (Operation Command Word).
categories of Interrupt Modes:
(FNM):
This mode is a default mode (auto-set after initialization).
and the corresponding bit in the ISR (Interrupt Service Register).
enhanced with, Special Full Nested Mode (SFNM): It supports the cascading systems
interrupt request. Because the FNM acknowledge only one interrupt at a time
32

according to the instruction written in its control register. It is

cally at any time during the main program.
fully nested, rotating priority, special mask and polled.
spacing of either 4 or 8 memory locations.
t I/O devices, resolves the priority with
(a) Interrupt Request Register (IRR)
(e) Control Logic Block.
It supports the cascading systems
interrupt at a time from the same level,


after that it disable from that line. The SFNM supports one more interrupt request from slave after
acknowledging the request of master in cascading system.

2. Rotating Priority Mode: it is categorized in two parts.
A. Automatic Rotation
When a peripheral is serviced, all other equal priority peripherals should be given a chance
to be serviced before the original peripheral is serviced a second time around.
This is accomplished by automatically assigning a peripheral the lowest priority after
being serviced. Thus a device, presently being serviced, would have to wait until all other
devices are serviced.
Automatic rotation is further categorized in two types:
(a) Rotate on non-specific EOI Command.
(b) Rotate on automatic EOI Mode.
B. Specific Rotation.
In this mode, after the service of peripheral; the user can be assigned any of the IR levels
(between 0 and 7) for the lowest priority by specifying OCW2 by user.
This mode is independent of EOI command.

3. Special Mask Mode:
This mode enables interrupts from all levels except the level presently in service. Its done
by masking the level that is in service and then issuing the special mask mode command and this
mask remains in effect until reset.

4. Polled Mode:
In this the interrupting devices seeking services from 8085 are polled one after another to
detect which device issued interrupt request.

- EOI (End of Interrupt) Command:
This command updates the ISR bit of service, after the completion of that particular interrupt service.
In the cascade mode (two ICs are Interfaces with each other), the EOI command must be issued twice
(one for master IC and one for slave IC).
It has three formats:
A. Automatic EOI: Automatically done by 8259 PIC. (Ex. In FNM mode.)
B. Non-Specific EOI Command: Resets the highest priority ISR bit.
C. Specific EOI Command: Specifies which ISR bit to reset.

- 8259 is programmed and initialized by a set of four ICW (Initialization Command Words).
ICWs (ICW1, ICW2, ICW3, and ICW4) perform the following jobs:
Specifying the vectoring addresses for the individual interrupts.
Specifying single or cascaded mode of operation.
Level or edge triggering mode of operation.

- Operation Sequence for programming 8259
1. Write ICW1.
2. Write ICW2.
3. If not in the cascade mode of operation, go to Step 5.
4. Write ICW3.
5. IF ICW4 is not needed, then go to Step 7.
6. Write ICW4.
7. Ready to accept interrupts sequence.



8237 DMA Controller

Features / Boasts:
It is a 4-channel interface, which allows data transfer between memory and up to 4 I/O devices,
bypassing CPU.
A maximum of 16 KB of data can be transferred by DMA sequentially at a time.
Initialization of the DMAC is done under program control for each channel.
DMAC can be operated in three modes:
DMA Read (reading from memory, writing into peripheral)
DMA Write (writing into memory, reading from peripheral)
DMA verify.
Priority for each of the 4 channels can be set in (a) fixed priority, (b) rotating priority.
A Terminal Count Register exists for each of 4 channels. The number of bytes of data to be transferred
is stored in the D
13
D
0
positions of the 16-bit Terminal Count Register.

Initialization of DMA: Its done by MPU
By loading the starting address of a DMA block for an I/O device in the 16-bit address register.
By loading D
13
D
0
bits i.e., lower 14-bits of Terminal Count Register (TCR) with the number of
bytes of data to be transferred.
By loading D
15
and D
14
of TCR appropriately to set the mode of operation of 8257.
By loading the Mode Set Register appropriately.

Two classes of to data transfer in DMA:

Sequential DMA: In this, the DMA controller reads a data byte from memory and then writes the same
into I/O or vice-versa. For each of these read or write operations, 2 to 4 CLK cycles are required.

Simultaneous DMA: It is the fastest transfer process. Here Read and Write operations are performed at
the same time. Thus both HEHR
& I0w
(or I0R
& HEHw
) are active at the same time. Thus a

speed improvement of twice the sequential DMA class is possible in this case.

Sequential DMA is used to be transfer bulk data and Simultaneous is used for moderate data transfer.

- The peripherals which are granted DMA transfer are called enabled peripherals and the ones who are
denied DMA transfer are called disabled peripherals. It is done by Mode Set Register.



8251A USERT (Universal Synchronous/Asynchronous Receiver Transmitter)

Features / Boasts:
28 DIP package with TTL compatibility.
It has built in baud rate generator, and it also provides different baud rate for transmitter and receiver.
It supports standard asynchronous and synchronous protocol.
Provide double buffering of data.
Do error detection with parity.
It is compatible with many INTEL MPUs



Fre#$e%&l' A"( )$e"&io%"

1. What is microprocessor?
It is a program controlled semi conductor device (IC), which fetches, decodes and execute
instructions.
Or
The microprocessor is a programmable integrated device that has computing and decision
making capability similar to CPU.
Or
A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic
device that reads binary instruction from a storage device called memory, accepts binary data as input
and processes data according to those instructions, and provides results as output.

2. Which type of architecture/model 8085 has?
Its Von Neumann architecture and was derived after the mathematician John Von Neumann.

3. What are the basic units of microprocessor?
The basic units or blocks of microprocessor are ALU, an array of registers and control unit.

4. Why a microprocessor based system is called a sequential machine?
It can perform the jobs in a sequential manner, one after the other. That is why it is called a
sequential machine.

5. Why a microprocessor based system is called a synchronous one?
All activities pertaining to the MPU takes place in synchronism with the clock. Hence it is called
a synchronous device.

6. Does the ALU have any storage facility?
No, it does not have any storage facility. For this reason, the need for temporary data registers
arise in ALUit has two inputs: one provided by the accumulator and the other from the temporary data
register. The result of summation is stored in the accumulator.

7. How an assembler translates programs written in mnemonic form to binary?
An assembler has a translation dictionary, which is stored in its memory. Mnemonics entered
via keyboard is compared with this dictionary, which then retrieves its binary equivalent from the same
place (dictionary).

8. Write down the difference between a compiler and an interpreter.
Difference between a compiler and an interpreter lies in the generation of the machine code or
object code. A compiler reads the entire program first and then generates the corresponding object code.
Whereas, an interpreter reads an instruction at a time, produces the corresponding object code
and executes the same before it starts reading the next instruction. A program from a compiler runs some
5 to 25 times faster than a program from an interpreter.

9. Differentiate between a compiler/interpreter and an assembler.
No. Compiler/Interpreter Assembler
1
2
3
4
Debugging easier
Less efficient
Requires large memory space
Use when the prog. is big
Debugging relatively tougher
More efficient
Requires less memory space
Use when the prog. is small


10. What is a bus?
Bus is a group of conducting lines that carries data, address and control signals.

11. Defile: Instruction.
Instruction is a binary bit pattern / set designed to perform a specific tack in microprocessor.

12. What is a mnemonic?
It is very difficult to understand a program if it is written in either binary or hex code. Thus the
manufacturers have devised a symbolic code for each instruction, called a mnemonic.

13. Why data bus is bi-directional?
The microprocessor is to fetch (read) the data from memory or input device for processing and
after processing it has to store (write) the data to memory or output devices. Hence the data bus is bi-
directional.

14. What is meant by word length of a computer?
The number of bits that a computer recognizes and can process at a time is calls word length.

15. What is an editor?
An editor is a program and is used for creation and modification of source programs or text. The
editor program includes commands which can delete, insert or change lines/ characters. An editor stores
in ASCII form in successive RAM locations of the typed letters/ numbers.

16. What is a linker?
A linker is a program that links several small object files to produce one large object file. A large
program is usually divided into several small programs. They are written separately, tested and
debugged. The large program is then produced by linking these debugged programmers.
A linker has a link file and a link map. The former contains the binary codes of all the modules
which have been combined while the link map stores in it the addresses of all the link files. A linker
assigns relative addressing instead of absolute addressing which helps in putting a linker program
anywhere in the memory.

17. What is a locator?
A locator is a program which is used to assign specific address when object code is to be loaded
into the memory.

18. What is a coprocessor?
A coprocessor or an arithmetic coprocessor, as it is so called, performs operations like
exponentiation, trigonometric functions, etc. To implement these functions in CPU hardware is a costly
one and the software implementation of the above slows down the processor. A coprocessor overcomes
these difficulties.
The coprocessor has its own instruction set. The CPU and the coprocessor execute their
respective instructions from the same program. The instructions belonging to the coprocessor are fetched
and decoded by the CPU but executed by the coprocessor.

19. Why address bus is unidirectional?
The address is an identification number used by the microprocessor to identify or access a
memory location or input/output device. It is an output signal from the processor. Hence the address bus
is unidirectional.

20. What is meant by Bus Idle Machine cycle?
There are a few situations in which machine cycles are neither Read nor Written into. These are
called Bus Idle Machine cycle. Such situations arise when the system executes a DAD or during the


internal opcode generation for the RST or TRAP interrupts. The ALE signal changes state during T1 of
each machine cycle, but in Bus Idle Machine cycles, ALE does not change state.

21. Define machine cycle?
Machine cycle is defined as the time required to complete one operation of accessing memory
input/output, or acknowledging an external request. This cycle may consist of three to six T-states.

22. Describe in brief the timing and control circuitry of 8085.
The T&C section is a part of CPU and generates timing and control signals for execution of
instructions. This section includes Clock signals, Control signals, Status signals, DMA signals as also the
Reset section. This section controls fetching and decoding operations. It also generates appropriate
control signals for instruction execution as also the signals required to interface external devices.

23. Define T-state?
T-state is defined as one subdivision of operation performed in one clock period. These
subdivisions are internal states synchronized with the system clock, and each T-state is precisely equal to
one clock period.

24. What should be the size of the Instruction Register if an arbitrary microprocessor has only 25
instructions?
The length of the Instruction Register would be 5-bits, since 25 = 32, since a 5-bit Instruction
Register can decode a maximum of 32 instructions.
25. What is an instruction cycle?
The sequence of operations that a processor has to carry out while executing the instruction is
called instruction cycle. Each instruction cycle of processor contains a number of machine cycles.

26. What is fetch and execute cycle?
The instruction cycle is divided in to fetch and execute cycles. The fetch cycle is executed to
fetch the opcode from memory. The execute cycle is executed to decode the instruction and to perform
the work instructed by the instruction.

27. What does memory-mapping mean?
The memory mapping is the process of interfacing memories to microprocessor and allocating
addresses to each memory locations.

28. What is opcode fetch cycle?
The opcode fetch cycle is a machine cycle executed to fetch the opcode of an instruction stored
in memory. Each instruction starts with opcode fetch machine cycle.

29. What are the instructions used to control the interrupts?
EI, DI, RIM, SIM

30. What is polling?
In polling, the microprocessors software simply checks each of the I/O devices every so often.
During this check, the microprocessor tests to see if any device needs servicing.

31. What are the different types of interrupts?
Hardware interrupts- The interrupts where the CPU pins are used to receive interrupt requests are
called hardware interrupts.
Software interrupts This interrupt is caused by the execution of the instruction. These are special
instructions supported by the microprocessor.

32. Difference between memory mapped I/o and I/O mapped I/o?



Memory mapped I/O I/O mapped I/O
In this device address is 16- bit. Thus A0 to
A15 lines are used to generate the device
address.
In this device address is 8-bit. Thus A0
to A7 or A8 to A15 lines are used to
generate device address.
MEMR and MEMW control signals are
used to control read and write I/O
operations.
IOR and IOW control signals are used to
control read and write I/O operations.
Instructions available are LDA,STA,MOV
R,M , ADD M etc
Instructions available are IN and OUT.
Data transfer is between any register and
I/O device.
Data transfer is between accumulator and
I/O device.
Decoding 16-bit address may require more
hardware.
Decoding 8-bit address will require less
hardware.

33. Describe the function of the following pins in 8085? i. READY ii. ALE iii. IO/M
iv. HOLD v. SID and vi. SOD
READY It is used by the microprocessor to sense whether a peripheral is ready or not for data
transfer. If not, the processor waits. It is thus used to synchronize slower peripherals to the
microprocessor.
ALE In 8085, AD0 to AD7 lines are multiplexed and lower half of address (Ao to A7) is
available only during T1 of the machine cycle. The latching of lower half address from the multiplexed
address lines by using ALE signal.
IO/M - indicates whether I/O operation or memory operation is being carried out.
HOLD This signal indicates that another master is requesting for the use of address bus, data
bus and control bus.
SID(Serial Input Data) This input signal is used to accept serial data bit by bit from the
external device.
SOD(Serial Output Data) This is an output signal which enables the transmission of serial data
bit by bit to the external device.

34. Comparison between full address decoding and partial address decoding?

Full Address Decoding Partial Address decoding
1. All higher address lines are decoded to
select the memory or I/O device.
1. Few higher address lines are decoded
to select the memory or I/O device.
2. More hardware is required to design
decoding logic.
2. Hardware required to design
decoding logic is less and sometimes it
can be eliminated.
3. Higher cost for decoding circuit. 3. Less cost for decoding circuit.
4. No Multiple addresses. 4. It has a advantage of multiple
addresses.
5. Used in large systems 5. Used in small systems

35. What is ALE?
The ALE (Address latch enable) is a signal used to demultiplex the address and data lines using
an external latch. It is used to enable the external latch.

36. Where is the READY signal used?
READY is an input signal to the processor, used by the memory or input/output devices to get
extra time for data transfer or to introduce wait states in the bus cycles.

37. Give some examples of port devices used in 8085 microprocessor based system?


The various port devices used in 8085 are: 8212, 8155, 8156, 8255, 8355, 8755.

38. What is the need for timing diagram?
The timing diagram provides information regarding the status of various signals, when a
machine cycle is executed. The knowledge of timing diagram is essential for system designer to select
matched peripheral devices like memories, latches, ports etc from a microprocessor system.

39. What operation is performed during first T-state of every machine cycle in 8085?
In 8085, during the first T-state of every machine cycle the low byte address is latched into an
external latch using ALE signal.

40. In an interrupt driven system, EI instruction should be incorporated at the beginning of the
program. Why?
A program, written by a programmer in the RAM location, is started first by system reset and
loading the PC with the starting address of the program. Now, with a system reset, all Maskable
interrupts are disabled. Hence, an EI instruction must be put in at the beginning of the program so that
the Maskable interrupts, which should remain unmasked in a program, remain so.

41. How the system can handle multiple interrupts?
Multiple interrupts can be handled if a separate interrupt is allocated to each peripheral. The
programmable interrupt controller IC 8259 can also be used to handle multiple interrupts when they are
interfaced through INTR

42. What is interrupt acknowledge cycle?
The interrupt acknowledge cycle is a machine cycle executed by 8085 processor to get the
address of the interrupt service routine in order to service the interrupt device.

43. When an interrupt is acknowledged, Maskable interrupts are automatically disabled. Why?
This is done so that the interrupt service subroutine (ISS) to which the program has entered on receiving
the interrupt has a chance to complete its own task.

44. What is vectored and non-vectored interrupt?
When an interrupt is accepted, if the processor control branches to a specific address defined by
the manufacturer then the interrupt is called vectored interrupt. In Non-vectored interrupt there is no
specific address for storing the interrupt service routine. Hence the interrupted device should give the
address of the interrupt service routine.

45. Can the microprocessor be interrupted before completion of existing Interrupt Service Subroutine
(ISS)?
Yes, the microprocessor can be interrupted before the completion of the existing ISS. Let after
acknowledging the INTR, the microprocessor is in the ISS executing instructions one by one. Now, for a
given situation, if the interrupt system is enabled (by inserting an EI instruction) just after entering the
ISS, the system can be interrupted again while it is in the first ISS. If an interrupt service subroutine be
interrupted again then this is called nested interrupt.

46. When returning back to the main program from Interrupt Service Subroutine (ISS), the software
instruction EI is inserted at the end of the ISS. Why?
When an interrupt (either via RST 7.5, RST 6.5, RST 5.5, INTR) is acknowledged by the
microprocessor, any interrupt acknowledge signal resets the interrupt enable F/F. It thus disables RST
7.5, RST 6.5, RST 5.5 and INTR interrupts. Thus any future interrupt coming via RST 7.5, RST 6.5,
RST 5.5 or INTR will not be acknowledged unless the software instruction EI is inserted which thereby
sets the interrupt enable F/F.

47. What is meant by nested interrupts? What care must be taken while handling nested interrupts?


Interrupts occurring within interrupts are called nested interrupts. While handling nested
interrupts, care must be taken to see that the stack does not grow to such an extent as to foul the main
programin that case the system program fails.

48. Bring out one basic difference between SIM and DI instructions.
While by using SIM instruction any combinations or all of RST 7.5, RST 6.5 and RST 5.5 can be
disabled, on the other hand DI disables RST 7.5, RST 6.5, RST 5.5 and in addition INTR interrupt also.

49. What is TRAP?
The TRAP is a non-Maskable interrupt of 8085. It is not disabled by processor reset or after
recognition of interrupt.

50. A RIM instruction should be performed immediately after TRAP occurs. Why?
This is so as to enable the pre-TRAP interrupt status to be restored with the implementation of a
SIM instruction.
51. How clock signals are generated in 8085 and what is the frequency of the internal clock?
The 8085 has the clock generation circuit on the chip but an external quartz crystal or LC circuit
or RC circuit should be connected at the pins X1 andX2. The maximum internal clock frequency of 8085
is 3.03MHz.

52. Define stack.
Stack is a sequence of RAM memory locations defined by the programmer.

53. Why stack is used in a program?
The stack is used to store information temporarily during the execution of a program. Also the
stack is used in subroutine calls to store the return address. As an example, data generated at a certain
point in a program may be needed later in the program. This data is stored in the stack and retrieved
when needed. Because the number of general purpose registers (GPRs) in a microprocessor is limited
hence not all the temporary data can be stored in them and this is where the stack plays its part.

54. Comment on the size of the stack.
It depends on the size of the R/W memory, as well as the program length. Since for a given
system, the size of the R/W memory is fixed, thus smaller the size of the program, more would be the
size of the stack.

55. Is initialization of stack a must in a program?
No, it is not a must. If for programs for which any temporary data that are generated can be
stored in GPRs and which dont require subroutine calls, there is no need to initialize the stack by the SP.

56. Who uses the stack?
The stack is used by both the programmer and the system. Programmer uses the stack for
storage/retrieval of data by using the PUSH/POP instructions respectively. On the other hand, the system
uses the stack to store return address whenever subroutine CALL is used.

57. What is program counter? How it is useful in program execution?
The program counter keeps track of program execution. To execute a program the starting
address of the program is loaded in program counter. The PC sends out an address to fetch a byte of
instruction from memory and increments its content automatically.

58. Why a subroutine is used in a program?
Since a subroutine is called more than once by the main program, thus, use of subroutines saves
precious memory space. The more the number of times a subroutine is called by the main program, the
more is the saving of memory space.



59. Define opcode and operand?
Opcode (operation code) is the part of an instruction that identifies a specific operation. Operand
is a part of instruction that represents a value on which the instruction acts.

60. How the 8085 processor differentiates a memory access and I/O access?
The memory access and I/O access is differentiated using IO/M signal. The 8085 processor
asserts IO/M low for memory operation and high for I/O operations.

61. Give some examples of subroutines.
Some examples of subroutines called by main program are: multiplication program, time delay
subroutine, hexadecimal converter subroutine, display subroutine, apart from any user specific
subroutines that may be needed by a programmer.

62. Where do subroutines reside?
Standard subroutines like display program, time delay program, hexa-decimal conversion
programs are supplied by the manufacturers of microcomputer in monitor ROM, while any user specific
programs are written in the R/W memory.

63. What is meant by parameter passing?
Subroutines are scattered at many places in the memory and that they may be called from
different locations in the main program. In such cases, various types of information/data are exchanged
between the main program and the subroutine. This technique goes by the name parameter passing.

64. When the 8085 processor checks for an interrupt?
In the second T-state of the last machine cycle of every instruction, the 8085 processor checks
whether an interrupt request is made or not.

65. Why interfacing is needed for I/O devices?
Generally I/O devices are slow devices. Therefore the speed of I/O devices does not match with
the speed of microprocessor. And so an interface is provided between system bus and I/O devices.

66. What is interrupt I/O?
If the I/O devices initiate the data transfer through interrupt then the I/O is called interrupt driven
I/O.

67. What is a port?
The port is a buffered I/O, which is used to hold the data transmitted from the microprocessor to
I/O devices and vice versa.

68. What is the need for interrupt controller?
The interrupt controller is employed to expand the interrupt inputs. It can handle the interrupt
request from various devices and allow one by one to the processor.

69. What is synchronous & asynchronous data transfer scheme?
For synchronous data transfer scheme, the processor does not check the readiness of the device
after a command has been issued for read/write operation. For this scheme the processor will request the
device to get ready and then read/write to the device immediately after the request.
In asynchronous data transfer scheme, first the processor sends a request to the device for
read/write operation. Then the processor keeps on polling the status of the device. Once the device is
ready, the processor executes a data transfer instruction to complete the process.



Peripheral Questions

1. What are the internal devices of 8255?
The internal devices of 8255 are port-A, port-B, port-C. The ports can be programmed for either
input or output function in different operating modes.

2. What is USART?
The device which can be programmed to perform Synchronous or Asynchronous serial
communication is called USART (Universal Synchronous Asynchronous Receiver Transmitter). Eg:
INTEL 8251

3. What is scanning in keyboard and what is scan time?
The process of sending a zero to each row of a keyboard matrix and reading the columns for key
actuation is called scanning. The scan time is the time taken by the processor to scan all the rows one by
one starting from first row and coming back to the first row again.

4. What is programmable peripheral device?
If the function performed by the peripheral device can be altered or changed by a program
instruction then the peripheral device is called programmable device. It has control register. The device
can be programmed by sending control word in the prescribed format to the control register.

5. What is baud rate?
The baud rate is the rate at which the serial data are transmitted. Baud rate is defined as (The
time for a bit cell). In some systems one bit cell has one data bit, then the baud rate and bits/sec are same.

6. How many possible combinations of 8255 would be there when it is operated in mode 2?
Only Port A can be operated in mode 2 and Port B in either mode 0 or mode 1. Thus, there
would be 4 possible combinations:
(a) Mode 2 and Mode 0 (input) (b) Mode 2 and Mode 0 (output)
(c) Mode 2 and Mode 1 (input) (d) Mode 2 and Mode 1 (output)

7. What are the tasks involved in keyboard interface?
The tasks involved in keyboard interfacing are sensing a key actuation, Debouncing the key and
generating key codes( Decoding the key). These tasks are performed software if the keyboard is
interfaced through ports and they are performed by hardware if the keyboard is interfaces through 8279.

8. How a keyboard matrix is formed in keyboard interface using 8279?
The return lines, RL0 toRL7 of 8279 are used to form the columns of keyboard matrix. In
decoded scan lines SL0 t0SL3 of 8279 are used to form the rows of keyboard matrix. In encoded scan
mode, the output lines of external decoder are used as rows of keyboard matrix.

9. What is GPIB?
GPIB is the General Purpose interface Bus. It is used to interface the test instruments to the
system controller.

10. Advantages of differential data transfer?
1. Communication at high data rate in real world environment.
2. Differential data transmission offers superior performance.
3. Differential signals can help induced noise signals.

11. Features of INTEL 8259?
1. It manage 8 interrupt request.


2. The interrupt vector addresses are programmable.
3. The priorities of interrupts are programmable.
4. The interrupt can be masked or unmasked individually.

12. What is meant by micro controller?
A device which contains the microprocessor with integrated peripherals like memory, serial
ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is
called micro controller.

13. What are the different types of Address decoding Techniques?
I. Absolute decoding/Full decoding II. Linear decoding / Partial decoding.

14. Comparison between full address decoding and Partial address decoding?
Full address decoding Partial address decoding
1. All higher address lines are decoded to
1. Few higher address lines are decoded to
2. More hardware is required to design
decoding logic.
2. Hardware required to design decoding
logic is less and sometimes it can be
eliminated.
3. Higher cost for decoding circuit. 3. Less cost for decoding circuit.
4. No multiple addresses. 4. It has a disadvantage of multiple
addresses. (Shadow addresses)
5. Used in large systems. 5. Used in small systems.

15. What is the significance of wait state generator?
This is used to transfer data between slower I/O device and the microprocessor. In some applns,
the speed of I/O systems is not compatible with the microprocessors timings. So the microprocessor has
to confirm whether the peripheral is ready or not. If READY pin is high, the peripheral is ready
otherwise 8085 enters in to wait state.

16. What is a Non-Maskable interrupt?
It is unaffected by any mask or interrupt enable. Eg: TRAP

17. What is meant by contact bounce? How it is eliminated?
When an electromechanical switch is switched over from an off to on condition, the contact does
not become firm on the first count. It loses contact and then makes itthis process repeats itself for a
number of times before the contact is firmly placed. This occurs for a very small duration of time.
This thus leads to erroneous operation in digital circuits. This problem can be eliminated by a
hardware circuitcalled contact debouncers or by software technique (by a delayed reading so that the
transient period is over) in microprocessor based systems.

18. What is a Data pointer register?
The data pointer register (DPTR) consists of a high byte(DPH) and a low byte (DPL) functions
to hold 16 bit address. It may be manipulated as a 16-bit data register or as independent 8-bit registers. It
serves as a base register in indirect jumps, look up table instructions and external data transfer.

19. What are the operating modes of 8279?
1. Input modes
Scanned keyboard Scanned sensor matrix Strobed input
2. Display modes
Left entry (Type writer mode) Right entry (Calculator mode)

20. What are the different functional units in 8279?


CPU interface section, Keyboard section, Display section, Scan section.

21. What are the priority modes in 8259?
a. Fully nested mode b. Special fully nested mode
c. Rotating Priority mode d. Special Masked mode
e. Polled mode

22. What is IMR(Interrupt mask register)?
IMR stores the masking bits of the interrupt lines to be masked. This register can be programmed
by an operation command word (OCW).

23. What is priority resolver?
It determines the priorities of the bits set in the Interrupt request register (IRR).The bit
corresponding to the highest priority interrupt input is set in the ISR during INTA input.

24. What is the use of IRR?
The interrupt request register is used to store all the interrupt levels which are requesting the
service. The eight interrupt inputs sets corresponding bits of the Interrupt Request Register upon the
service request.

25. What is Interrupt service register(ISR)?
The interrupt service register stores all the levels that are currently being serviced.

26. What is the difference between SHLD and LHLD?
SHLD- Store HL register pair in memory. This instruction is used to store the contents of H and
L register directly in to memory.
LHLD- Load HL register pair from memory. This instruction copies the contents of memory
location given with in the instruction in to the L register and the contents of next memory location in to
the H register.

27. What is the difference between STAX and LDAX?
STAX rp Store the contents of Accumulator register (A) in memory location whoseb address is
specified by BC or DE register pair.
LDAX rp Load Accumulator register (A) with the contents of memory location whose address
is specified by BC or DE register pair.

28. What are the types of branching instructions?
1. Jump instructions
2. Call and Return instructions
3. Restart instructions

29. Explain the instruction LXI rp, data (16)?
LXI rp, data (16) Load 16 bit immediate data to specified register pair or stack pointer. The rp
is 16 bit register pairs such as BC, DE, HL or stack pointer.

30. Write the difference between LDA and STA instruction?
LDA Load data in to Accumulator register (A) directly from the address specified within the
instruction.
STA Store the contents of Accumulator register (A) to the address specified within the
instruction.

31. What are the operating modes of 8255?
1. Bit set/Reset mode


2. I/O modes
a) Mode 0: Simple input/output
b) Mode 1: Input/output with handshake
c) Mode 2: Bi-directional I/O data transfer

32. What are the priority modes in 8259?
1. Fully nested mode 2. Special fully nested mode
3. Rotating priority mode 4. Special mask mode
5. Poll mode



Few Fat Model Questions (and hints to deal with that.)

1. Using diagram illustrate logic pin out of the 8085 Microprocessor.
Draw the pin diagram of 8085 and explains pins of it.

2. With Neat diagram, explain the Architecture of 8085?
Or Draw the functional block diagram of internal architecture of IC 8085 and explain its working.
Draw Block diagram and Explanation

3. Explain demultiplexing of AD7 - AD0.
Explain the ALE signal and show the use with diagram.

4. Discuss the flags in flag register of 8085.

5. List and Explain categories of 8085 instructions that manipulate data.
Only explain the Logic and Bit manipulation class of instruction ex. ANA, CMP, XRI

6. Explain the instruction sets of 8085?
Describe the classification of instruction. (Data Transfer, Arithmetic, Logical, )

7. What is stack and stack pointer? Explain working of PUSH and POP instruction with suitable
example.

8. Explain the timing diagram of the memory write cycle.
Draw the memory write cycle and explain it.

9. Distinguish between Hardware and Software interrupt and explain the interrupt vector diagram.

10. Write a detailed note on Interrupts of 8085. Or Explain the interrupt structure of 8085?
TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Detail description of all of this

11. Assume that microprocessor does not support interrupts. What limitations do put on your design of
general purpose system?

12. What are the different means to control the interrupts in 8085 by enabling and disabling them? Show
all the ways and effects on each other.

13. Explain the interrupt acknowledgement cycle.

14. Draw the timing diagram of STA address?
Four machine cycles. (Opcode, Memory Read / Write, IO Read)

15. Explain about Memory interfacing?

16. Explain the rotate instruction with example.

17. Draw and explain the timing diagram of the instruction IN 00 H

18. Compare (CALL & RET) instructions with (PUSH & POP) instructions.

19. What are break points? Show its usefulness and method of implementation.



20. With neat block diagram, explain the Architecture of 8279? (or any of chip)
Or Explain the keyboard interfacing
Explanation with Block Diagram

21. With neat block diagram, explain the Architecture of PPI?
Explanation with Block Diagram of 8255A

22. With neat block diagram, explain the Architecture of USART?

23. Explain the operating modes of 8279?
Describe input and display modes

24. Illustrate designing a square wave generator using the 8155 timer [Assume necessary required data]

25. Compare slave and master mode of 8257.

26. Explain the 8254 Timer alone with die waveforms for various modes.

27. Explain the operating modes of PPI?
Describe the modes of 8255A with diagram.

28. Explain the Bi-directional data transfer - mode for 8255A along with Control word, Status Words &
timing diagrams.

29. Explain the BSR of 8255.

30. Describe 2-key lockout and N-Key roll over.

31. Explain the operating modes of USART?

32. Explain the receiver and transmitter section of 8251? or Explain the receiver and transmitter section
of USERT?

33. Explain how the 8237 DMA controller transfers 64K bytes of data per channel.

34. Explain the operating modes of 8259?

35. Explain the initialization process of the 8259 interrupt controller.

36. What is EOI? Explain it with its different techniques.

37. Discuss in detail different working modes of IC 8254Programmable interval timer.

38. List major components of the 8259A interrupt controller and explain their functions.
Or With neat diagram discuss the working of IC 8259A Programmable interrupt controller.

39. Explain keyboard controller. Or explain the circuit diagram of 16-key keyboard.
Describe 8279 with block diagram.

40. How stepper motor is interfaced with 8085?

41. Explain the Addressing modes of 8085?



42. Explain Debounce.

43. Explain RIM and SIM

44. Compare A/D and D/A interfacing?

45. Discuss in detail memory mapped I/O and I/O mapped I/O.

46. Write instructions to set up the 8155 timer in Mode 3 with count 33CD H.

47. Design an output port with the help of decoder and gates using port address XX H.

48. Show how to connect one input port and one output port on same port address with the help of circuit
diagram.

M B Rajpara Appendix A (Instructions) I


Appe%*i+ , A
8085 I%"&r$!&io% Se&

Notations R Register Rp Register Pair
Used in: Rd Destination Register M HL Register Pair
Rs Source Register addr A 16-bit Address

NOTE
If the Opcode
contains :

A
M
I
D
L
X

Then
- You are dealing with Accumulator
- Doing copy / transferring of something without alter the source content
- Shows Immediate addressing mode
- Shows Direct addressing mode
- Load data or address.
- If X is the first character then its exchange of data
If X is in between the opcode then it shows register pair

* MC Machine Cycle *TC T-state

Data Transfer Instructions

To move / copy data
MOV Rd, Rs
M, Rs
Rd, M
Copy the data from source to destination register without changing the
content of source register.
Ex. MOV C,B MOV C,A

To move / copy 8-bit data Immediately
MVI Rd, data
M, data
8-bit data is stored / load in the destination register or memory with
immediate addressing mode. Or if there is a M in instruction, so its HL Pair;
which contains the address of the data. The data will be fetched from there.
Ex. MVI B, 23H MVI M, 89H

Load Data into Accumulator
LDA addr. (Direct)

LDAX Rp (Indirect)
The contents at memory location, specified in 16- bit address will be copied
to the accumulator.
Ex. LDA 2312H

It copies the contents of the memory location whose 16-bit address is stored
in designated register pair, into the accumulator.
Ex: LDAX B

Load Register Pair Immediately
LXI Rp, 16-bit data 16-bit data is stored in the register pair. It is just like MVI.
Ex. LXI H, 2386H

M B Rajpara Appendix A (Instructions) II


Store the Content of Accumulator
STA addr. (Direct)

STAX Rp (Indirect)
It copies (store) the content of the accumulator to the specified address.
Ex: STA 4390H

The contents of the accumulator are copied into the memory location
specified in the Register pair.
Ex: STAX D

Load HL Register Pair Direct
LHLD addr. It copies the contents of the given (16-bit address) memory location into
register L and copies the contents of the next memory location into register H.
The contents of source memory locations are not altered.
Ex: LHLD 2340H

Store HL Register Pair Direct
SHLD addr. The content of register L is stored into the specified memory location (the 16-
bit address in the operand) and the content of register H is stored into the next
memory location by incrementing the operand.
Ex: SHLD 2170H

Exchange HL with DL Register pair
XCHG The contents of register H are exchanged with the contents of register D, and
the contents of register L are exchanged with the contents of register E.
There is no operand in this instruction.

Initialize stack pointer with HL pair
SPHL It loads (copy) the contents of HL register pair into the stack pointer register
(SP), the contents of the H register provide the high-order address and the
contents of the L register provide the low-order address.

Exchange HL with SP
XTHL The contents of the L register are exchanged with the stack location pointed
out by the contents of the stack pointer register. The contents of the H register
are exchanged with the next stack location (SP+1); however, the contents of
the stack pointer register are not altered.

Data Transfer with the Stack
PUSH Rp

POP Rp
The contents of the register pair specified in the operand are copied onto the
stack. The stack pointer register is decremented and the contents of the high-
order register (B, D, H, A) are copied into that location. The stack pointer
register is decremented again and the contents of the low-order register (C, E,
L, flags) are copied to that location.
Ex: PUSH D or PUSH PSW

The contents of the memory location pointed out by the stack pointer register
are copied to the low-order register (C, E, L, status flags) of the operand. The
stack pointer is incremented by 1 and the contents of that memory location
are copied to the high-order register (B, D, H, A) of the operand. The stack
pointer register is again incremented by 1.
Ex: POP B or POP PSW

M B Rajpara Appendix A (Instructions) III


Data Transfer with Port
OUT port no.

IN port no.
The contents of the accumulator are copied into the I/O port specified by the
operand.
Ex: OUT C3H

The contents of the input port designated in the operand are read and loaded
into the accumulator.
Ex: IN 8AH

Arithmetic Instructions

Add Data into the Content of the Accumulator
ADD R
M

ADI 8-bit data
It adds the contents of register or memory in the contents of the accumulator
and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers.
The flag register will be modified, with the reflection of result.
Ex: ADD C or ADD M

The 8-bit data (operand) is added to the contents of the accumulator and the
result is stored in the accumulator.
Ex: ADI 45H

Add Data into the Content of the Accumulator with Carry
ADC R
M

ACI 8-bit data
It adds the contents of register or memory with carry to the content of the
accumulator and the result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents of the HL registers.
Ex: ADC B or ADC M

The 8-bit data (operand) and the Carry flag are added to the contents of the
accumulator and the result is stored in the accumulator.
Ex: ACI 45H

Add data of any Register Pair to HL Register Pair
DAD Rp The 16-bit contents of the specified register pair are added to the contents of
the HL register and the result is stored in the HL register. The contents of the
source register pair are not altered. If the result is larger than 16 bits, the CY
flag is set. No other flags are affected.
Ex: DAD H

Subtract from the Content of the Accumulator
SUB R
M

SUI 8-bit data
It subtracts the contents of register or memory from the contents of the
accumulator and the result is stored in the accumulator If the operand is a
memory location, its location is specified by the contents of the HL registers.
Ex: SUB B or SUB M

The 8-bit data (operand) is subtracted from the contents of the accumulator
and the result is stored in the accumulator.
Ex: SUI A5H

M B Rajpara Appendix A (Instructions) IV


Subtract from the Content of the Accumulator with Borrow
SBB R
M

SBI 8-bit data
The contents of the operand (register or memory) and the Borrow flag are
subtracted from the contents of the accumulator and the result is placed in the
accumulator. If the operand is a memory location, its location is specified by
the contents of the HL registers. All flags are modified to reflect the result of
the subtraction.
Ex: SBB B or SBB M

The 8-bit data (operand) and the Borrow flag are subtracted from the contents
of the accumulator and the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.
Ex: SBI 45H

Increment Data by 1
INR R / M

INX R
The contents of the designated register or memory are incremented by 1 and
the result is stored in the same place. If the operand is a memory location, its
location is specified by the contents of the HL registers.
Ex: INR B or INR M

The contents of the designated register pair are incremented by 1 and the
result is stored in the same place.
Ex: INX H

Decrement Data by 1
DCR R / M

DCX R
The contents of the designated register or memory are decremented by 1 and
the result is stored in the same place. If the operand is a memory location, its
location is specified by the contents of the HL registers.
Ex: DCR B or DCR M

The contents of the designated register pair are decremented by 1 and the
result is stored in the same place.
Ex: DCX H

Decimal adjust accumulator
DAA The contents of the accumulator are changed from a binary value to two 4-bit
binary coded decimal (BCD) digits. This is the only instruction that uses the
auxiliary flag to perform the binary to BCD conversion, and the conversion
procedure is described below. S, Z, AC, P, CY flags are altered to reflect the
results of the operation.
If the value of the low-order 4-bits in the accumulator is greater than 9 or if
AC flag is set, the instruction adds 6 to the low-order four bits.
If the value of the high-order 4-bits in the accumulator is greater than 9 or if
the Carry flag is set, the instruction adds 6 to the high-order four bits.

M B Rajpara Appendix A (Instructions) V


Logic & Bit Manipulation Instructions

Compare with the Content of Accumulator
CMP R
M

CPI 8-bit data
Compare data of register / Memory with accumulator and set PSW.
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Ex: CMP C or CMP M

You can compare data immediately with accumulator.
Ex: CPI A7H

Logical AND Operation with the Content of Accumulator
ANA R
M

ANI 8-bit data
It do AND operation between accumulator and given memory/register data.
Ex. ANA B or ANA M

To do immediate AND operation with accumulator and 8-bit data.
Ex. ANI 45H

Logical OR Operation with the Content of Accumulator
ORA R
M

ORI 8-bit data
It do OR operation between accumulator and given memory/register data.
Ex. ORA D or ORA M

To do immediate OR operation with accumulator and 8-bit data.
Ex. ORI 23H

Exclusive OR (XOR) Operation with the Content of Accumulator
XRA R
M

XRI 8-bit data
It does Exclusive OR operation between accumulator and given
memory/register data.
Ex. XRA C or XRA M

To do immediate Exclusive OR operation with accumulator and 8-bit data.
Ex. XRI 89H

Rotate the content of the Accumulator
RLC
(Rotate Left without carry)

RAL
(Rotate Left with carry )

RRC
(Rotate Right without
carry)

RAR
(Rotate Right with carry)

Each binary bit of the accumulator is rotated left by one position. Bit D7 is
placed in the position of D0 as well as in the Carry flag.

Each binary bit of the accumulator is rotated left by one position through the
Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in
the least significant position D0.CY is modified according to bit D7.

Each binary bit of the accumulator is rotated right by one position. Bit D0 is
placed in the position of D7 as well as in the Carry flag. CY is modified
according to bit D0.

Each binary bit of the accumulator is rotated right by one position through the
Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in
the most significant position D7. CY is modified according to bit D0.

Compliment Accumulator
CMA The content of the accumulator is complimented. No flag are affected.

M B Rajpara Appendix A (Instructions) VI


Compliment Carry
CMC Carry flag is complimented. No other flag is affected.

Set Carry
STC Carry flag is set to 1. No other flag is affected.

Branch Instructions

Jump
Jump Unconditionally
JMP addr.

Jump Conditionally

JC addr.
JNC addr.
JZ addr.
JNZ addr.
JPE addr.
JPO addr.
JM addr.
JP addr.

The program sequence is transferred to the memory location specified by the
16-bit address given in the operand.
Ex. JMP 2022H

16-bit address given in the operand based on the specified flag of the PSW.
Jump on Carry (Carry Flag CY = 1)
Jump on No Carry (Carry Flag CY = 0)
Jump on Zero (Zero Flag Z = 1)
Jump on No Zero (Zero Flag Z = 0)
Jump on Even Parity (Parity Flag P = 1)
Jump on Odd Parity (Parity Flag P = 0)
Jump on Minus (Sign Flag S = 1)
Jump on Positive (Sign Flag S = 0 )

Subroutine Calls
Call Unconditionally
CALL addr.

Call Conditionally
The conditions are just like
Jump. Put C instead of J.
16-bit address given in the operand. Before the transfer, the address of the
next instruction after CALL (the contents of the program counter) is pushed
onto the stack.
Ex. CALL 2356H

The program sequence is transferred based on the specified flag of the PSW.
Ex. For carry JC -> CC so CC 2040H
And on odd parity JPO -> CPO so CPO 2020H

Subroutine Returns
Return Unconditionally RET
The program sequence is transferred from the subroutine to the calling
program. The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
So no need of address requires.

Return Conditionally R(condition) just like Jump. Ex. JC-> RC

M B Rajpara Appendix A (Instructions) VII


Machine Control & I/O Instructions

All Machine and I / O Control instructions are 8-bit instruction
No Operation
NOP
The instruction is fetched and decoded but no operation is executed

Halt or End of the Program
HLT To stop (or put on waiting state) the execution we can use this instruction.
To exit from this state, an interrupt or reset signal is used.

Disable Interrupt
DI Without affecting any flag, this will reset the interrupt enable flip-flop and;
that will disable all interrupt accept TRAP

Enable Interrupt
EI It will set the interrupt enable flip-flop, so all interrupt will be enabled.

M B Rajpara Appendix B (Sample Programs) VIII


Appe%*i+ , -
Sample A""embl' La%g$age Program"

1s complement

LDA 2200H ; Get the number
CMA ; Complement number
STA 2300H ; Store the result
HLT ; Terminate program execution

2s complement

LDA 2200 H ; Get the number
CMA ; Complement the number
ADI 01H ; Add one in the number

Addition of Two Hexadecimal Numbers Including Carry

LXI H, 2000H ; HL Points 2000H
MOV A, M ; Get first operand
INX H ; HL Points 2001H
ADD M ; Add second operand
MOV M, A ; Store the lower byte of result at 2002H
MVI A, 00H ; Initialize higher byte result with 00H
ADC A ; Add carry in the high byte result
MOV M, A ; Store the higher byte of result at 2003H

Addition of Two Hexadecimal Numbers
LXI H, 2000H ; HL points 2000H
INX H ; HL points 2001H
ADD M ; Add second operand
MOV M, A ; Store result at 2002H

Adding Two Hexadecimal Numbers without Carry
M B Rajpara Appendix B (Sample Programs) IX


LDA 2200H ; Load data from 2200H
MOV C, A ; Initialize counter
SUB A ; sum = 0
LXI H, 2201H ; Initialize pointer
BACK: ADD M ; SUM = SUM + data
INX H ; Increment pointer
DCR C ; Decrement counter
JNZ BACK ; if counter 0 repeat
STA 2300H ; store sum
HLT ; stop the execution

Adding Two Hexadecimal Numbers With Carry

SUB A ; Sum low = 0
MOV B, A ; Sum high = 0
BACK: ADD M ; Sum = sum + data
JNC SKIP ; Jump it not carry
INR B ; Add carry to MSB of SUM
SKIP: INX H ; Increment pointer
JNZ BACK ; Check if counter 0 repeat
STA 2300H ; Store lower byte
MOV A, B ; copy B to accumulator
STA 2301H ; Store higher byte

Add Two 16-Bit Numbers

LHLD 2000H ; Get first 16-bit number
XCHG ; Save first 16-bit number in DE
LHLD 2002H ; Get second 16-bit number in HL
DAD D ; Add DE and HE
SHLD 2004H ; Store 16-bit result in memory locations 2004H and 2005H

Subtract Two 16-Bit Numbers Including a Carry from D7 Bit to D8 Bit

LHLD 2000H ; Get first 16-bit number in HL
MOV A, E ; Get lower byte of the first number
SUB L ; Subtract lower byte of the second number
MOV L, A ; Store the result in L register
MOV A, D ; Get higher byte of the first number
SBB H ; Subtract higher byte of second number with borrow
MOV H, A ; Copy accumulator to H
M B Rajpara Appendix B (Sample Programs) X



Add Two 16-Bit Numbers Including a Carry from D7 Bit to D8 Bit

LHLD 2000H ; Get first 16-bit number in HL
MOV A, E ; Get lower byte of the first number
ADD L ; Add lower byte of the second number
MOV L, A ; Store result in L register
MOV A, D ; Get higher byte of the first number
ADC H ; Add higher byte of the second number with carry
MOV H, A ; Store result in H register

Adding Two BCD Numbers without Carry

MOV A, L ; Get lower 2 digits of no. 1
ADD E ; Add two lower digits
DAA ; Adjust result to valid BCD
STA 2300H ; Store partial result
MOV A, H ; Get most significant 2 digits of no. 2
ADC D ; Add two most significant digits
DAA ; Adjust result to valid BCD
STA 2301H ; Store partial result

Decimal Addition of Numbers

MOV A, M ; Get the first number
INX H ; Increment the pointer
ADD M ; Add two numbers
DAA ; Convert HEX to valid BCD

Adding the 4 Most Significant Bit to a Hexadecimal Number
LDA 2201H ; Get the Most significant BCD digit
RLC ; Rotate accumulator left without carry
RLC ; Adjust the position
MOV C, A ; store the partial result
LDA 2200H ; Get the lower BCD digit
ADD C ; Add lower BCD digit
Store the Numbers in a Memory Location in the Reverse Order
M B Rajpara Appendix B (Sample Programs) XI


MVI C, 0AH ; Initialize counter
LXI H, 2200H ; Initialize source memory pointer
LXI D, 2309H ; Initialize destination memory pointer
BACK: MOV A, M ; Get byte from source memory block
STAX D ; Store byte in the destination memory block
INX H ; Increment source memory pointer
DCX D ; Decrement destination memory pointer
JNZ BACK ; If counter 0, repeat

Search for a Number in the List If Found Store Address Where It Is Found Else Store 0000H

LXI H, 2000H ; Initialize memory pointer
MVI B, 52H ; Initialize counter
BACK: MOV A, M ; Get the number
CMP C ; Compare with the given byte
JZ LAST ; Go last if match occurs
INX H ; Increment memory pointer
DCR B ; Decrement counter
JNZ BACK ; If not zero, repeat
LXI H, 0000H ; Load HL pair with 0000H
SHLD 2200H ; Store HL to 2200H
JMP END ; Store 00 at 2200H and 2201H
LAST: SHLD 2200H ; Store memory address
END: HLT ; Stop

In A Set of Numbers, Do Addition of Only Odd Numbers
LDA 2200H ;
MVI E, 00 ; Sum low = 0
MOV D, E ; Sum high = 0
ANI 01H ; Mask Bit1 to Bit7
JZ SKIP ; Do not add if number is even
MOV A, E ; Get the lower byte of sum
ADD M ; Sum = sum + data
MOV E, A ; Store result in E register
JNC SKIP ; Jump to skip if Carry flag is not set
INR D ; Add carry to MSB of SUM
JNZ BACK ; Check if counter 0 repeat
MOV A, E ; Copy E to A
STA 2300H ; Store lower byte
MOV A, D ; Copy D to A
STA 2301H ; Store higher byte

Block Data Transfer
M B Rajpara Appendix B (Sample Programs) XII


MVI C, 0AH ; Initialize counter
LXI H, 2200H ; Initialize source memory pointer
LXI D, 2300H ; Initialize destination memory pointer
INX H ; Increment source memory pointer
INX D ; Increment destination memory pointer

Block Data Transfer of 15 Numbers

MVI C, 0FFH ; Initialize counter
LXI H, 20FFH ; Initialize source memory pointer
LXI D, 214FH ; Initialize destination memory pointer
DCX H ; Decrement source memory pointer
DCX D ; Decrement destination memory pointer
HLT ; Stop execution

Addition of Two Numbers in 6 Different Memory Locations, And Store it in 6 Other Memory Location

LXI H, 2200H ; Initialize memory pointer 1
LXI B, 2300H ; Initialize memory pointer 2
LXI D, 2400H ; Initialize result pointer
BACK: LDAX B ; Get the number from array 2
ADD M ; Add it with number in array 1
STAX D ; Store the addition in array 3
INX H ; Increment pointer1
INX B ; Increment pointer2
INX D ; Increment result pointer
MOV A, L ; Copy L to A
CPI 0H ; Check pointer1 for last number
JNZ BACK ; If not, repeat
HLT ; Stop

Decimal Addition of Two Numbers in 6 Different Memory Locations, And Store in 6 Other Memory
Location

LXI H, 2000H ; Initialize pointer1 to first number
LXI D, 2100H ; Initialize pointer2 to second number
LXI B, 2200H ; Initialize pointer3 to result
STC ; Set Carry flag
CMC ; Carry = 0
BACK: LDAX D ; Get the digit
ADD M ; Add two digits
M B Rajpara Appendix B (Sample Programs) XIII


DAA ; Adjust for decimal
STAX B ; Store the result
INX H ; Increment pointer1
INX D ; Increment pointer2
INX B ; Increment result pointer
MOV A, L ; Copy L to A
CPI 06H ; Check for last digit
JNZ BACK ; If not last digit repeat

Transfer 5 Numbers in Memory Pointed By Location Value in another Memory Location

LXI H, 2200H ; Initialize lookup table pointer
LXI D, 2100H ; Initialize source memory pointer
LXI B, 2000H ; Initialize destination memory pointer
BACK: LDAX D ; Get the number
MOV L, A ; A point to the square
MOV A, M ; Get the square
STAX B ; Store the result at destination memory location
INX D ; Increment source memory pointer
INX B ; Increment destination memory pointer
MOV A, C ; Copy C to A
CPI 05H ; Check for last number
JNZ BACK ; If not repeat
HLT ; End of program

In A List of 50 Numbers Separate the Even Numbers and Store Them

LXI H, 2200H ; Initialize memory pointer1
LXI D, 2300H ; Initialize memory pointer2
MVI C, 32H ; Initialize counter
ANI 01H ; Check for even number
JNZ SKIP ; If ODD, dont store
MOV A, M ; Get the number
STAX D ; Store the number in result list
INX D ; Increment pointer 2
SKIP: INX H ; Increment pointer1
HLT ; Stop

Separate the Digits of a Hexadecimal Numbers and Store It in Two Different Locations

LDA 2200H ; Get the packed BCD number
ANI F0H ; Mask lower nibble
RRC ; Rotate accumulator right
RRC ; Adjust higher BCD digit as a lower digit
STA 2300H ; Store the partial result
M B Rajpara Appendix B (Sample Programs) XIV


LDA 2200H ; Get the original BCD number
ANI 0FH ; Mask higher nibble

Subtraction of Two Numbers in Memory

LXI H, 2000H ; HL points 2000H
SUB M ; Subtract second operand
MOV M, A ; Store result at 2002H

Multiplication of Two 8 Bit Numbers

MOV E, A ; Copy accumulator to E
MVI D, 00 ; Get the first number
LXI H, 0000H ; Result = 0
BACK: DAD D ; Result = result + first number
DCR C ; decrement count
JNZ BACK ; If count 0 repeat
SHLD 2300H ; Store result

Division of Two 8 Bit Numbers
LHLD 2200H ; Get the dividend
MOV C, A ; Get the divisor
LXI D, 0000H ; Quotient = 0
BACK: MOV A, L ; Copy L to A
SUB C ; subtract C from A
MOV L, A ; Save partial result
JNC SKIP ; if CY 1 jump
DCR H ; Subtract borrow of previous subtraction
SKIP: INX D ; Increment quotient
MOV A, H ; Copy H to A
CPI 00 ; Check if dividend
JNZ BACK ; < divisor
MOV A, L ; if no repeat
CMP C ; Compare A with C
JNC BACK ; jump to BACK if no carry
SHLD 2302H ; Store the remainder
XCHG ; Exchange HL with DE
SHLD 2300H ; Store the quotient
Negative Numbers in the List of Hexadecimal Numbers
M B Rajpara Appendix B (Sample Programs) XV


MOV C, A ; Initialize count
MVI B, 00H ; Negative number = 0
ANI 80H ; Check for MSB
JZ SKIP ; If MSB = 1
INR B ; Increment negative number count
DCR C ; Decrement count
JNZ BACK ; If count 0 repeat
MOV A, B ; Copy B to A

Maximum Number in the List of Hexadecimal Numbers

LDA 2200H ;
XRA A ; Maximum = Minimum possible value = 0
BACK: CMP M ; Is number > maximum
JNC SKIP ; jump on carry to SKIP
MOV A, M ; Yes, replace maximum
SKIP: INX H ; increment pair HL
DCR C ; Decrement C by 1
JNZ BACK ; jump on zero flag to BACK
STA 2300H ; Store maximum number

Swapping the Numbers

LDA 2000H ; Get the contents of memory location 2000H into accumulator
MOV B, A ; save the contents in B register
LDA 2200H ; Get the contents of memory location 2200H into accumulator.
STA 2000H ; Store the contents of accumulator at address 2000H.
MOV A, B ; Get the saved contents back into A register
STA 2200H ; Store the contents of accumulator at address 2200H

Complement the Flag Content
LXI SP, 2700 ; Initialize Stack
PUSH PSW ; Save flags on stack
POP H ; Retrieve flags in L
MOV A, L ; Flags in accumulator
CMA ; Complement accumulator
MOV L, A ; Accumulator in L
PUSH H ; Save on stack
POP PSW ; Back to flag register
Bubble Sort of 10 Numbers
M B Rajpara Appendix B (Sample Programs) XVI


MVI B, 09 ; Initialize counter 1
START: LXI H, 2200H ; Initialize memory pointer
MVI C, 09H ; Initialize counter 2
INX H ; Increment memory pointer
CMP M ; Compare number with next number
JC SKIP ; If less, dont interchange
JZ SKIP ; If equal, dont interchange
MOV D, M ; Copy HL to DE pair
MOV M, A ; Copy accumulator to desired address in HL pair
DCX H ; Decrement register pair HL with 1
MOV M, D ; Copy DE to HL
INX H ; Interchange two numbers
SKIP: DCR C ; Decrement counter 2
DCR B ; Decrement counter 1
JNZ START ; If not zero, repeat

Convert the set of numbers to odd parity if the no is even parity

LXI H, 2040H ; Load HL pair with 2040H
MOV C, M ; Counter for character
REPEAT: INX H ; Memory pointer to character
MOV A, M ; Char. in accumulator
ORA A ; OR ing with itself to check parity
JPO PAREVEN ; if odd parity generated jump to PAREVEN
ORI 80H ; If odd parity place even parity in D7 (80)
PAREVEN: MOV M, A ; Store converted even parity character
JNZ REPEAT ; If not zero go for next character.

Bibliography
[1] Ramesh Gaonkar, Microprocessor Architecture,
Programming, and Application with the 8085, 5
th

edition, Mumbai: Penram International Publishing,
1999. [ISBN: 81-87972-09-2]
[2] A. P. Godse and D. A. Godse, Microprocessor &
Interfacing, 2
nd
edition, Pune: Technical
Publications, 2011. [ISBN: 978-93-5038-096-3]
[3] John E. Uffenbeck, Microcomputers and
Microprocessors: The 8080, 8085, and Z-80
Programming, Interfacing, and Troubleshooting, 3
rd

edition, NY: Prentice Hill, 1999. [ISBN: 978-
0132091985]
[4] Charles M. Gilmore, Microprocessors: Principles
and Applications, 2
nd
edition, NY: McGrow-Hill
science, 1995. [ISBN: 0028018370]
[5] Kumar, The 8085 Microprocessor: Architecture,
Programming And Interfacing, 2
nd
edition, Pearson
Education India, 2008. [ISBN: 9788177584554]
[6] Abhishek Yadav, Microprocessor 8085,8086, 2
nd

edition, Delhi: Firewall Media, 2008. [ISBN:
9788131803561]
[7] Triebel, The 8088 And 8086 Microprocessors:
Programming, Interfacing, Software, Hardware and
Applications, 4
th
edition, New Delhi: Pearson
Education India, 2007. [ISBN: 8177584812]
[8] K. A. Krishnamurthy, Ten Days with 8085
Microprocessor, 1
st
edition, New Delhi: PHI
Learning Pvt. Ltd, 2010. [ISBN: 8120338545]
[9] Functional and block diagram figures of
Programmable Peripherals: Courtesy of Intel
Corporation, Santa Clara, California.
[10] 8051 Microcontroller - Kenneth Ayala
[11] Programming manual for 8080/8085 based
development system, Intel Corporation, 1976.
[12] Evolutionary Test Program Induction for
Microprocessor Design Verification By. Matteo
Sonza Reorda, Giovanni Squillero

Web References

[13] http://www.8085microprocessor.com/
[14] http://www.8085projects.info/
[15] http://microprocessor-8085.blogspot.in/
[16] http://en.wikipedia.org/wiki/Intel_8085
[17] http://www.cpu-world.com/CPUs/8085
[18] http://www.romux.com/tutorials/8085-
microprocessor
[19] http://www.dynalogindia.com/products/education-
solutions/8085-microprocessor-262.html

Closing Words

Microprocessor is the heart and brain of the computer. So, its an important thing to study and
understand for the Engineering students.
I have made this document through sort of experience and references, for the quick reference of
microprocessor 8085; to help out the students in their academic session and can deal with exam questions.
The short questions will helpful in viva and interviews. The person who wants dive deep in this subject, they
should go with the reference books.
You are free to use and share this quick book accept selling. I will be grateful to get reviews and
suggestions from the readers to improvise this vade mecum. Feel free to send e-mail with your queries and
reviews.

- M B Rajpara
mbrajpara@indiatimes.com
April 1
st
, 2012.

Web Site: www.vidyanuragi.wordpress.com
About me: http://en.gravatar.com/mbrajpara

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Fundamentals, Peripherals & Problems

: Read Signal actives LOW. To read/ fetch data

: Write Signal actives LOW. To write data into

: If it is high operation is doing with IO. If it

: Program Counter is set to 0. (Address goes to 0000H ) MPU is reset.

(bar) on any signal shows that it works in LOW signal.

This signal is use to insert the RST instruction through

(Interrupt Acknowledge) to acknowledge the interrupt.

) generated by MPU to inform

signal from device.

: Acknowledgement, is a signal generated by device to acknowledge the 0BF

signal of MPU, that

CNT 2 CNT 1 CNT 0 0

) are active at the same time. Thus a

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