1

Unit 7
8279 Programmable Keyboard/Display Controller and Interfacing
The Keyboard/Display Controller 8279
Intels 8279 is a general purpose Keyboard Display controller that simultaneously
drives the display of a system and interfaces a Keyboard ith the !"U# $he Keyboard
Display interface scans the Keyboard to identify if any %ey has been pressed and sends
the code of the pressed %ey to the !"U# It also transmits the data received from the !"U&
to the display device#
'oth of these functions are performed by the controller in repetitive fashion ithout
involving the !"U# $he Keyboard is interfaced either in the interrupt or the polled mode#
In the interrupt mode& the processor is re(uested service only if any %ey is pressed&
otherise the !"U can proceed ith its main tas%#
In the polled mode& the !"U periodically reads an internal flag of 8279 to chec% for a %ey
pressure# $he Keyboard section can interface an array of a ma)imum of *+ %eys ith the
!"U# $he Keyboard entries ,%ey codes- are debounced and stored in an 8.byte /I/0
123& that is further accessed by the !"U to read the %ey codes# If more than eight
characters are entered in the /I/0 ,i#e# more that eight %eys are pressed-& before any
/I/0 read operation& the overrun status is set# If a /I/0 contains a valid %ey entry& the
!"U is interrupted ,in interrupt mode- or the !"U chec%s the status ,in polling- to read
the entry#
0nce the !"U reads a %ey entry& the /I/0 is updated& i#e# the %ey entry is pushed out of
the /I/0 to generate space for ne entries# $he 8279 normally provides a ma)imum of
si)teen 7.seg display interface ith !"U It contains a 1*.byte display 123 that can be
used either as an integrated bloc% of 1*)8.bits or to 1*)+.bit bloc% of 123# $he data
entry to 123 bloc% is controlled by !"U using the command ords of the 8279#
Architectre and !ignal Descriptions of 8279
$he Keyboard display controller chip 8279 provides
1# 2 set of four scan lines and eight return lines for interfacing %eyboards#
2# 2 set of eight output lines for interfacing display#
2
I/" Control and Data #ffer
$he I40 control section controls the flo of data to4from the 8279# $he data buffer
interface the e)ternal bus of the system ith internal bus of 8279# the I40 section is
enabled only if D is lo#
8279 Internal Architectre
$he pin 2o& 1D and 51 select the command& status or data read4rite operations carried
out by the !"U ith 8279#
Control and Timing $egister and Timing Control
$hese registers store the %eyboard and display modes and other operating
conditions programmed by !"U# $he registers are ritten ith 2o61 and 51 67# $he
timing and control unit controls the basic timings for the operation of the circuit# 8can
!ounter divide don the operating fre(uency of 8279 to derive scan %eyboard and scan
display fre(uencies#
!can Conter
$he 8can !ounter has to modes to scan the %ey matri) and refresh the display#
In the 9ncoded mode& the counter provides a binary count that is to be e)ternally decoded
:
to provide the scan lines for %eyboard and display ,four e)ternally decoded scan lines
may drive up to 1* displays-#
In the decoded scan mode& the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of + scan on 8;%.8;& ,four internally decoded scan lines may
drive up to + Displays-# $he Keyboard and Display both are in the same mode at a time#
$etrn #ffers and Keyboard Debonce and Control
$his section scans for a Key closure ro.ise# If it is detected& the Keyboard
debounce unit debounces the %ey entry ,i#e# ait for 17 ms-# 2fter the debounce period& if
the %ey continues to be detected# $he code of the Key is directly transferred to the sensor
123 along ith 8<I/$ and !0=$10; %ey status#
'I'"/!ensor $A( and !tats )ogic
In Keyboard or strobed input mode& this bloc% acts as 8.byte first.in.first.out
,/I/0- 123# 9ach %ey code of the pressed %ey is entered in the order of the entry& and
in the meantime& read by the !"U& till the 123 becomes empty# $he status logic
generates an interrupt re(uest after each /I/0 read operation till the /I/0 is empty#
In scanned sensor matri) mode& this unit acts as sensor 123# 9ach ro of the sensor
123 is loaded ith the status of the corresponding ro of sensors in the matri)# If a
sensor changes its state& the I1> line goes high to interrupt the !"U#
Display Address $egisters and Display $A(*
$he Display address registers hold the addresses of the ord currently being
ritten or read by the !"U to or from the display 123# $he contents of the registers are
automatically updated by 8279 to accept the ne)t data entry by !"U# $he 1*.byte display
123 contains the 1*.byte of data to be displayed on the si)teen 7.seg displays in the
encoded scan mode#
Pin Diagram of 8279
D#% + D#7 ,
$hese are bidirectional data bus lines# $he data and command ords to and from the !"U
are transferred on these lines#
+
C)K ,
$his is a cloc% input used to generate internal timings re(uired by 8279#
$-!-T ,
$his pin is used to reset 8279# 2 high on this line resets 8279# 2fter resetting 8279& its in
si)teen 8.bit display& left entry encoded scan& 2.%ey loc% out mode# $he cloc% prescaler is
set to :1#
C! chip select,
2 lo on this line enables 8279 for normal read or rite operations# 0therise this pin
should be high#
Ao ,
2 high on the 2o line indicates the transfer of a command or status information# 2 lo
on this line indicates the transfer of data# $his is used to select one of the internal
registers of 8279#
?
$D. /$ ,
,Input40utput- 192D451I$9 input pins enable the data buffer to receive or send data
over the data bus#
I$0,
$his interrupt output line goes high hen there is data in the /I/0 sensor 123# $he
interrupt line goes lo ith each /I/0 123 read operation# <oever& if the /I/0 123
further contains any Key.code entry to be read by the !"U& this pin again goes high to
generate an interrupt to the !"U#
1ss. 1cc ,
$hese are the ground and poer supply lines for the circuit#
!)%+!)& 2 !can )ines,
$hese lines are used to scan the %eyboard matri) and display digits# $hese lines can be
programmed as encoded or decoded& using the mode control register#
$)%+$)7 2 $etrn )ines ,
$hese are the input lines hich are connected to one terminal of %eys& hile the other
terminal of the %eys are connected to the decoded scan lines# $hese are normally high&
but pulled lo hen a %ey is pressed#
!3I'T ,
$he status of the 8hift input line is stored along ith each %ey code in /I/0 in the
scanned %eyboard mode# $ill it is pulled lo ith a %ey closure it is pulled up internally
to %eep it high#
C4T)/!T#+C"4T$")/!T$"#-D I/P (ode ,
In the Keyboard mode& this line is used as a control input and stored in /I/0 on a %ey
closure# $he line is a strobe line that enters the data into /I/0 123& in the strobed input
mode# It has an internal pull up# $he line is pulled don ith a Key closure#
#D 2 #lan5 Display ,
*
$his output pin is used to blan% the display during digit sitching or by a blan%ing
command#
"6TA% 2 "6TA& and "6T#% 2 "6T#& ,
$hese are the output ports for to 1*)+ ,or one 1* ) 8- internal display refresh registers#
$he data from these lines is synchroni@ed ith the scan
lines to scan the display and %eyboard# $he to +.bit ports may also be used as one 8.bit
port#
(odes of "peration of 8279
$he 3odes of operation of 8279 are
i# Input ,Keyboard- modes
ii# 0utput ,Display- modes
Inpt 7Keyboard8 modes ,
8279 provides three input modes& they are A
9* !canned Keyboard (ode ,
$his mode allos a %ey matri) to be interfaced using either encoded or decoded scans# In
the encoded scan& an 8 ) 8 %eyboard or in decoded scan & a + ) 8 Keyboard can be
interfaced# $he code of %ey pressed ith 8<I/$ and !0=$10; status is stored into
the /I/0 123#
2* !canned !ensor (atri:,
In this mode& a sensor array can be interfaced ith 8279 using either encoder or decoder
scans# 5ith encoder scan 8 ) 8 sensor matri) or ith decoder scan + ) 8 sensor matri)
can be interfaced # $he sensor codes are stored in the !"U addressable sensor 123#
&* !trobed Inpt ,
In this mode& if the control line goes lo& the data on return lines& is stored in the /I/0
byte by byte#
"tpt 7Display8 (odes ,
7
8279 provides to output modes for selecting the display options#
9* Display !can,
In this mode& 8279 provides 8 or 1* character multiple)ed displays those can be
organi@ed as dual +.bit or single 8.bit display units#
2* Display -ntry,
$he Display data is entered for display either from the right side or from the left side#
Details of (odes of "peration
Keyboard (odes
9* !canned Keyboard (ode ;ith 2 Key )oc5ot
In this mode of operation& hen a %ey is pressed& a debounce logic comes into
operation# $he Key code of the identified %ey is entered into the /I/0 ith 8<I/$ and
!=$; status& provided the /I/0 is not full#
2* !canned Keyboard ;ith 4+5ey $ollo<er
In this mode& each %ey depression is treated independently# 5hen a %ey is
pressed& the debounce circuit aits for 2 %eyboard scans and then chec%s hether the %ey
is still depressed# If it is still depressed& the code is entered in /I/0 123# 2ny number of
%eys can be pressed simultaneously and recogni@ed in the order& the Keyboard scan
record them#
&* !canned Keyboard !pecial -rror (ode
$his mode is valid only under the =.Key rollover mode# $his mode is
programmed using end interrupt/error mode set command# If during a single debounce
period ,to Keyboard scan- to %eys are found pressed& this is considered a simultaneous
depression and an error flag is set# $his flag& if set& prevents further riting in /I/0 but
allos generation of further interrupts to the !"U for /I/0 read#
&* !ensor (atri: (ode
In the 8ensor 3atri) mode& the debounce logic is inhibited the 8.byte memory
matri)# $he status of the sensor sitch matri) is fed directly to sensor 123 matri) $hus
the sensor 123 bits contains the ro.ise and column.ise status of the sensors in the
sensor matri)#
Display (odes
8
$here are various options of data display $he first one is %non as left entry mode or
type riter mode# 8ince in a type riter the first character typed appears at the left.most
position& hile the subse(uent characters appears successively to the right of the first one#
$he other display format is %non as right entry mode& or calculator mode& since the
calculator the first character entered appears at the right.most position and this character
is shifted one position left hen the ne)t character is entered#
9* )eft -ntry (ode
In the ;eft entry mode& the data is entered from the left side of the display unit# 2ddress
7 of the display 123 contains the leftmost display character and address 1? of the
123 contains the rightmost display character#
2* $ight -ntry (ode
In the right entry mode& the first entry to be displayed is entered on the rightmost
display# $he ne)t entry is also placed in the right most display but after the previous
display is shifted left by one display position#
Command /ords of 8279
2ll the !ommand ords or status ords are ritten or read ith 2o 6 1 and !8 6 7 to or
from 8279#
a* Keyboard Display mode set
$he format of the command ord to select different modes of operation of 8279 is
given belo ith its bit definitions#
9
b* Programmable Cloc5
$he cloc% for operation of 8279 is obtained by dividing the e)ternal cloc% input signal
by a programmable constant called prescaler#
""""" is a ?.bit binary constant# $he input fre(uency is divided by a decimal constant
ranging from 2 to :1& decided by the bits of an internal prescalar& """""#
c* $ead 'I'"/!ensor $A(
$he format of this command is given as shon belo
B . dont care
2I . 2uto increment flag
222 . 2ddress pointer to 8 bit /I/0 123
$his ord is ritten to set up 8279 for reading /I/048ensor 123# In scanned %eyboard
mode& 2I and 222 bits are of no use# $he 8279 ill automatically drive data bus for
each subse(uent read& in the same se(uence& in hich the data as entered#
17
17
d* $ead Display $A(
$his command enables a programmer to read the display 123 data
$he !"U rites this command ord to 8279 to prepare it for display 123 read
operation# 2I is auto incremented flag and 2222& the +.bit address& points to the 1*.byte
display 123 that is to be read# If 2I 6 1& the address ill be automatically& incremented
after each read or rite to the display 123#
e* /rite Display $A(
$he format of this command is given as shon belo
2I . 2uto increment flag
2222 . +.bit address for 1*.bit display 123 to be ritten
0ther details of this command are similar to the C1ead Display 123 !ommand#
f* Display /rite Inhibit/#lan5ing
$he I5 ,Inhibit rite flag- bits are used to mas% the individual nibble <ere Do and D2
corresponds to 0U$'o D 0U$': hile D9 and D& corresponds to 0U$2o.0U$2: for
blan%ing and mas%ing respectively#
g* Clear Display $A(
11
11
$he !D2& !D9& !Do is a selectable blan%ing code to clear all the ros of the display
123 as given belo# $he characters 2 and ' represents the output nibbles#
!D !D9 !Do
1 7 ) 2ll Eeros ,) dont care- 2' 6 77
1 1 7 2&.2o 6 2,7717- and '&.'o 6 77,7777-
1 1 1 2ll ones ,2' 6 //-& i#e# clear 123
<ere& !2 represents clear 2ll and !/ represents !lear /I/0 123
-nd Interrpt/-rror (ode !et
/or the sensor matri) mode& this command loers the I1> line and enables further
riting into the 123# 0therise& if a charge in sensor value is detected& I1> goes high
that inhibits riting in the sensor 123#
Key+code and stats Data 'ormats
$his briefly describes the formats of the Key.code48ensor data in their respective modes
of operation and the /I/0 8tatus 5ord formats of 8279#
Key+code Data 'ormats ,
2fter a valid Key closure& the %ey code is entered as a byte code into the /I/0
123& in the folloing format& in scanned %eyboard mode# $he Keycode format contains
:.bit contents of the internal ro counter& :.bit contents of the column counter and status
of the 8<I/$ and !=$; Keys $he data format of the Keycode in scanned %eyboard
mode is given belo#
12
12
In the sensor matri) mode& the data from the return lines is directly entered into an
appropriate ro of sensor 123& that identifies the ro of the sensor that changes its
status# $he 8<I/$ and !=$; Keys are ignored in this mode# 1; bits represent the return
lines#
1n represents the sensor 123 ro number that is e(ual to the ro number of the sensor
array in hich the status change as detected# Data /ormat of the sensor code in sensor
matri) mode
'I'" !tats /ord ,
$he /I/0 status ord is used in %eyboard and strobed input mode to indicate the
error# 0verrun error occurs& hen an already full /I/0 is attempted an entry& Underrun
error occurs hen an empty /I/0 read is attempted# /I/0 status ord also has a bit to
sho the unavailability of /I/0 123 because of the ongoing clearing operation#
In sensor matri) mode& a bit is reserved to sho that at least one sensor closure indication
is stored in the 123& $he 849 bit shos the simultaneous multiple closure error in
special error mode# In sensor matri) mode& a bit is reserved to sho that at least one
sensor closure indication is stored in the 123& $he 849 bit shos the simultaneous
multiple closure error in special error mode# $he /I/0 status ord format is as shon
belo A
1:
1:
Interfacing and Programming 8279
Problem ,
Interface %eyboard and display controller 8279 ith 878* at address 7787<# 5rite an
2;" to set up 8279 in scanned %eyboard mode ith encoded scan& =.Key rollover mode#
Use a 1* character display in right entry display format# $hen clear the display 123
ith @eros# 1ead the /I/0 for %ey closure# If any %ey is closed& store its code to register
!;# $hen rite the byte ?? to all the displays& and return to D08# $he cloc% input to
8279 is
23<@& operate it at 177K<@#
!oltion ,
$he 8279 is interfaced ith loer byte of the data bus& i#e# Do.D7 # <ence the 2o
input of 8279 is connected ith address line29#
$he data register of 8279 is to be addressed as 7787<& i#e#2o67#
/or addressing the command or status ord 2o input of 8279 should be 1#
$he ne)t step is to rite all the re(uired command ords for this problem#
'igre sho;s the interfacing schematic
1+
1+
Keyboard/Display (ode !et C/ ,
$his command byte sets the 8279 in 1*.character right entry and encoded scan =.Key
rollover mode#
Program cloc5 selection ,
$he cloc% input to 8279 is 23<@& but the operating fre(uency is to be 177K<@& i#e# the
cloc% input is to be divided by 27 ,17177-# $hus the prescalar value is 17177 and trhe
command byte is set as given#
Clear Display $A( ,
$his command clears the display 123 ith the programmable blan%ing code#
$ead 'I'" ,
$his command byte enables the programmer to read a %ey code from the /I/0
123
/rite Display $A( ,
1?
1?
$his command enables the programmer to rite the addressed display locations of the
123 as presented belo#
Program gi<es the A)P re=ired to initiali>e the 8279 as re=ired,
2ssume !8 A !ode
!ode 8egment
8tart A 30F 2;& 12< G 8et 8279 in 9ncoded scan&
0U$ 82<& 2; G = Key rollover& 1* display& 1ight entry mode#
30F 2;& :+< G 8et cloc% prescalar to
0U$ 82<& 2; G 177K<@
30F 2;& 7D:< G !lear display ram
0U$ 82<& 2; G command
30F 2;& +7< G 1ead /I/0 command
0U$ 82<& 2; G for chec%ing display 123
5ait A I= 2;& 82< G 5ait for clearing of
2=D 2;& 87< G Display 123 by reading
!3" 2<& 87< G /I/0 Du bit of the status ord i#e#
H=E 5ait G If Du bit is not set ait& else proceed#
30F 2<& +7< G 1ead /I/0 command
0U$ 82<& 2; G for chec% %ey closure
I= 2;& 82< G 1ead /I/0 status
2=D 2<& 77< G 3as% all bits e)cept the
!3" 2<& 77 G number of characters bits
H=E Key code G if any %ey is pressed& ta%e
5armA 30F 2;& 97< G re(uired action& otherise
0U$ 82<& 2; G "roceed to rite display
30F 2;& ??< G 123 by using rite display
30F !;& 17< G command# 5rite the byte
=e)tA 0U$ 87<& 2; G ??< to all display 123
D9! !; G ;ocations
H=E =e)t G
H3" 8top G
Key codeA !all 1ead code G !all routine to read the %ey
H3" 5arm G !ode of the pressed %ey is
assumed available
8top 30F 2<& +!< G stop
I=$ 21<
!ode 9=D8
9=D 8$21$
Programmable timer de<ice 82?&
Intels programmable counter4timer device ,82?:- facililitates the
generation of accurate time delays# 5hen 82?: is used as timing and
delay generation peripheral& the microprocessor becomes free from the
tas%s related to the counting process and e)ecute the programs in
memory& hile the timer device may perform the counting tas%s# $his
minimi@es the softare overhead on the microprocessor#
Architectre and !ignal Descriptions
$he programmable timer device 82?: contains three independent
1*.bit counters& each ith a ma)imum count rate of 2#* 3<@# It is thus
possible to generate three totally independent delays or maintain three
independent counters simultaneously# 2ll the three counters may be
independently controlled by programming the three internal command
ord registers#
$he 8.bit& bidirectional data buffer interfaces internal circuit of
82?: to microprocessor systems bus# Data is transmitted or received by
the buffer upon the e)ecution of I= or 0U$ instruction# $he read4rite
logic controls the direction of the data buffer depending upon hether it
is a read or a rite operation# It may be noted that I= instruction reads
data hile 0U$ instruction rites data to a peripheral# $he internal bloc%
diagram and pin diagram of 82?: are shon in /ig# 1 and l#1 respectively#
1*
17
17
/ig1#1 "in !onfiguration of 82?:
$he three counters available in 82?: are independent of each other in
operation& but they are identical to each other in organi@ation# $hese are
all 1*.bit presettable& don counters& able to operate either in '!D or in
he)adecimal mode# $he mode control ord register contains the
information that can be used for riting or reading the count value into or
from the respective count register using the 0U$ and I= instructions# $he
specialty of the 82?: counters is that they can be easily read on line
ithout disturbing the cloc% input to the counter# $his facility is called as
Ion the flyI reading of counters& and is invo%ed using a mode control
ord#
2
7
& 2
l
pins are the address input pins and are re(uired internally for
addressing the mode control ord registers and the three counter registers#
2 lo on !8 line enables the 82?:# =o operation ill be performed by
82?: till it is enabled# $able 1 shos the selected operations for various
control inputs#
C! $D /$ A
9
A
%
!elected "perations
7 1 7 7 7 5rite !ounter 7
7 1 7 7 1 5rite !ounter 1
7 1 7 1 7 5rite !ounter 2
7 1 7 1 1 5rite control 5ord
7 7 1 7 7 1ead !ounter 7
7 7 1 7 1 1ead !ounter 1
7 7 1 1 7 1ead !ounter 2
7 7 1 1 1 =o 0peration
7 1 1 B B =o 0peration
1 B B B B Disabled
18
18
$able 1#8elected operations for various control inputs of 82?:
2 control ord register accepts the 8.bit control ord ritten by the
microprocessor and stores it for controlling the complete operation of the
specific counter# It may be noted that& the control ord register can only be
ritten and cannot be read as it is obvious from $able 1. $he !;K, J2$9
and 0U$ pins are available for each of the three timer channels# $heir
functions ill be clear hen e study the different operating modes of
82?:#
Control /ord $egister
$he 82?: can operate in anyone of the si) different modes# 2 control ord
must be ritten in the respective control ord register by the
microprocessor to initiali@e each of the counters of 82?: to decide its
operating mode# 9ach of the counters or%s independently depending upon
the control ord decided by the programmer as per the needs# In other
ords& all the counters can operate in anyone of the modes or they may be
even in different modes of operation& at a time# $he control ord format is
presented& along ith the definition of each bit& in /ig# 1#2
5hile riting a count in the counter& it should be noted that& the count
is ritten in the counter only after the data is put on the data bus and a
falling edge appears at the cloc% pin of the peripheral thereafter# 2ny
reading operation of the counter& before the falling edge appears may result
in garbage data#
5ith this much information& on the general functioning of 82?:& one
may proceed further for the details of the operating modes of 82?:#
D%
#CD
"peration
7 <e)adecimal !ount
1 '!D !ount
19
19
<oever& the concepts shall be clearer after one goes through the interfacing
e)amples and the related assembly language programs#
CONTROL BYTE D7 - D0
D7 D6 D5 D4 D3 D2
D1 D0
SC1 SC0 RL1 RL0 M2 M1
M0 BCP
D5
RL1
D4
RL0
R / L Definition
0 0
Counter value is latce!. "is #eans
tat te selecte! counter as its
contents trans$erre! into a te#%orar&
latc, 'ic can ten (e rea! (& te CP).
0 1 Rea! * loa! least+si,ni$icant (&te onl&.
1 0 Rea! * loa! #ost+si,ni$icant (&te onl&.
1 1 Rea! * loa! least+si,ni$icant (&te $irst,
ten #ost+si,ni$icant (&te.
D7
SC1
D6
SC0
Counter Select
0 0
counter 0
0 1
counter 1
1 0
counter 2
1 1
ille,al value
27
27
D3
M2
D2
M1
D
M0
!o"e #$lue
0 0
0 #o!e 0- interru%t on ter#inal count
0 0 1 #o!e 1- %ro,ra##a(le one+sot
. 1 0 #o!e 2- rate ,enerator
. 1 1 #o!e 3- s/uare 'ave ,enerator
1 0 0 #o!e 4- so$t'are tri,,ere! stro(e
1 0 1 #o!e 5- ar!'are tri,,ere! stro(e
/ig1#2#!ontrol 5ord /ormat and 'it Definitions
"perating (odes of 82?&
9ach of the three counters of 82?: can be operated in one of the folloing
si) modes of operation#
1#3ode7 ,Interrupt on terminal count-
2# 3odel ,"rogrammable monoshot-
:# 3ode2 ,1ate generator-
+# 3ode: ,8(uare ave generator-
?#3ode+ ,8oftare $riggered robe-
*#3ode? ,<ardare triggerred strobe-
In this section& e ill discuss all these modes of operation of 82?: in brief#
("D- % $his mode of operation is generally called as interrupt on terminal
count# In this mode& the output is initially lo after the mode is set# $he
output remains lo even after the count value is loaded in the counter# $he
counter starts decrementing the count value after the falling edge of the
cloc%& if the J2$9 input is high# $he process of decrementing the counter
continues at each falling edge of the cloc% till the terminal count is reached&
i#e# the count becomes @ero# 5hen the terminal count is reached& the output
goes high and remains high till the selected control ord register or the
corresponding count register is reloaded ith a ne mode of operation or a
ne count& respectively# $his high output may be used to interrupt the
processor henever re(uired& by setting suitable terminal count# 5riting a
count register hile the previous counting is in process& generates the
folloing se(uence of response#
$he first byte of the ne count hen loaded in the count register&
stops the previous count# $he second byte hen ritten& starts the ne
count& terminating the previous count then and there#
$he J2$9 signal is active high and should be high for normal
counting# 5hen J2$9 goes lo counting is terminated and the current
count is latched till the J2$9 again goes high# /igure 1#: shos the
operational aveforms in mode7#
/ig1#:# 5aveforms 51& 0U$ and J2$9 in 3ode 7
("D- 9 $his mode of operation of 82?: is called as programmable one.shot
mode# 2s the name implies& in this mode& the 82?: can be used as a
monostable multivibrator. $he duration of the (uasistable state of the
monstable multivibrator is decided by the count loaded in the count
register# $he gate input is used as trigger input in this mode of operation#
=ormally the output remains high till the suitable count is loaded in the
count register and a trigger is applied# 2fter the application of a trigger ,on
the positive edge-& the output goes lo and remains lo till the count
becomes @ero# If another count is loaded hen the output is already lo& it
does not disturb the previous count till a ne trigger pulse is applied at the
J2$9 input# $he ne counting starts after the ne trigger pulse# /igure 1#+
shos the related aveforms for mode 1#
21
/ig1#+# 51& J2$9 and 0U$ 5aveforms in 3ode 1
("D- 2 $his mode is called either rate generator or divide by = counter# In
this mode& if = is loaded as the count value& then& after = pulses& the
output becomes lo only for one cloc% cycle# $he count N is reloaded and
again the output becomes high and remains high for N cloc% pulses# $he
output is normally high after initialisation or even a lo signal on J2$9
input can force the output high# If J2$9 goes high& the counter starts
counting don from the initial value# $he counter generates an active lo
pulse at the output initially& after the count register is loaded ith a count
value# $hen count don starts and henever the count becomes @ero
another active lo pulse is generated at the output# $he duration of these
active lo pulses are e(ual to one cloc% cycle# $he number of input cloc%
pulses beteen the to lo pulses at the output is e(ual to the count
loaded# /igure 1#? shos the related aveforms for mode 2# Interestingly&
the counting is inhibited hen J2$9 becomes lo#
/ig1#?#5aveforms at pin 51 and 0U$ in 3ode 2
("D- & In this mode& the 82?: can be used as a s(uare ave rate
generator# In terms of operation this mode is somehat similar to mode 2#
5hen& the count N loaded is even& then for half of the count& the output
remains high and for the remaining half it remains lo# If the count loaded
is odd& the first cloc% pulse decrements it by 1 resulting in an even count
value ,holding the output high-# $hen the output remains high for half of
the ne count and goes lo for the remaining half# $his procedure is
repeated continuously resulting in the generation of a s(uare ave# In case
of odd count& the output is high for longer duration and lo for shorter
duration# $he difference of one cloc% cycle duration beteen the to
periods is due to the initial decrementing of the odd count# $he aveforms
for mode : are shon in /ig# 1#*# In general& if the loaded count value 'N
is odd& then for ,=Kl-42 pulses the output remains high and for ,=.l-42
pulses it remains lo#
22
/ig1#*#5aveforms for 3ode :
("D- @ $his mode of operation of 82?: is named as softare triggerred
strobe# 2fter the mode is set& the output goes high# 5hen a count is loaded&
counting don starts# 0n terminal count& the output goes lo for one cloc%
cycle& and then it again goes high# $his lo pulse can be used as a strobe&
hile interfacing the microprocessor ith other peripherals# $he count is
inhibited and the count value is latched& hen the J2$9 signal goes lo# If a
ne count is loaded in the count register hile the previous counting is in
progress& it is accepted from the ne)t cloc% cycle# $he counting then
proceeds according to the ne count# $he related aveforms are shon in
/ig# 1#7#
!;K
51
0U$
51
J2$9
0U$
/ig1#7#51& J2$9& and 0U$ 5aveforms for 3ode +
("D- ? $his mode of operation also generates a strobe in response to the
rising edge at the trigger input# $his mode may be used to generate a delayed
strobe in response to an e)ternally generated signal# 0nce this mode is
programmed and the counter is loaded& the output goes high# $he counter
starts counting after the rising edge of the trigger input ,J2$9-# $he output
goes lo for one cloc% period& hen the terminal count is reached# $he output
ill not go lo until the counter content becomes @ero after the rising edge of
any trigger# $he J2$9 input in this mode is used as trigger input# $he related
aveforms are shon in /ig# 1#8#
/ig1#8# 5aveforms in 3ode ?
Programming and Interfacing 82?&
2s it is evident from the previous discussion& there may be to types of rite
operations in 82?:& vi@# ,i- riting a control ord into a control ord register
and ,ii- riting a count value into a count register# $he control ord register
accepts data from the data buffer and initiali@es the counters& as re(uired# $he
control ord register contents are used for ,a- initialising the operating modes
,mode7.mode+- ,b- selection of counters ,counter7.counter2- ,c- choosing
binary '!D counters ,d- loading of the counter registers# $he mode control
register is a rite only register and the !"U cannot read its contents#
0ne can directly rite the mode control ord for counter 2 or
counter 1 prior to riting the control ord for counter7# 3ode control
ord register has a separate address& so that it can be ritten
independently# 2 count register must be loaded ith the count value& in the
same byte se(uence that as programmed in the mode control ord of that
counter& using the bits 1;
7
and 1;
1
# $he loading of the count registers of
different counters is again se(uence independent# 0ne can directly rite
the 1*.bit count register for count 2 before riting count 7 and count 1& but
the to bytes in a count must be ritten in the byte se(uence programmed
using 1;
7
and 1;
1
bits of the mode control ord of the counter# 2ll the
counters in 82?: are don counters& hence their count values go on
decrementing if the !;K input pin is applied ith a valid cloc% signal# 2
ma)imum count is obtained by loading all @eros into a count register& i#e#
2
1*
for binary counting and 17
+
for '!D counting# $he 82?: responds to
the negative cloc% edge of the cloc% input# $he ma)imum operating cloc%
fre(uency of 82?: is 2#* 3<@# /or higher fre(uencies one can use timer
82?+& hich operates up to 17 3<@& maintaining pin compatibility ith
82?:# $he folloing $able *#2 shos the selection of different mode
control ords and counter register bytes depending upon address lines 2
o
and 2
1
$able 1#2 8election of !ount 1egisters and !ontrol 5ord 1egister ith 2
1
and 2
7#
In most of the practical applications& the counter is to be read and
depending on the contents of the counter a decision is to be ta%en# In case
of 82?:& the 1*.bit contents of the counter can simply be read using
successive 8.bit I= operations# 2s stated earlier& the mode control register
cannot be read for any of the counters# $here are to methods for reading
82?: counter registers# In the first method& either the cloc% or the counting
procedure ,using J2$9- is inhibited to ensure a stable count# $hen the
contents are read by selecting the suitable counter using 2
7
& 2
l
and
e)ecuting using I= instructions# $he first I= instruction reads the least
significant byte and the second I= instruction reads the most significant
byte# Internal logic of 82?: is designed in such a ay that the programmer
has to complete the reading operation as programmed by him& using 1;
7
and 1;
l
bits of control ord#
In the second method of reading a counter& the counter can be read
hile counting is in progress# $his method& as already mentioned is called
as reading on fly. In this method& neither cloc% nor the counting needs to be
inhibited to read the counter# $he content of a counter can be read Lon flyL
using a nely defined control ord register format for online reading of
the count register# 5riting a suitable control ord& in the mode control
register internally latches the contents of the counter# $he control ord
format for Lread on flyL mode is given in /ig# 1#9 along ith its bit
definitions# 2fter latching the content of a counter using this method& the
programmer can read it using I= instructions& as discussed before#
!elected $egister A
9
A
%
3ode !ontrol 5ord !ounter7 1 1
3ode !ontrol 5ord !ounter1 1 1
3ode !ontrol 5ord !ounter2 1 1
!ounter 1egister 'yte !ounter 2 ;8' 1 7
!ounter 1egister 'yte !ounter 2 38' 1 7
!ounter 1egister 'yte !ounter 1 ;8' 7 1
!ounter 1egister 'yte !ounter 1 38' 7 1
!ounter 1egister 'yte !ounter 7 ;8' 7 7
$able1#2# 8election of count registers and !ontrol 5ord 1egister ith
2
1
and 2
7
CONTROL BYTE D
7
- D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SC
1
SC
0
0 0 0 0 0 0
D7.D* 6 8!1&8!7 . 8pecify the counter to be selected
D?.D+ 6 77 . Designate counter latching operation
B .Dont !are . 2ll other bits are neglected
/ig1#9 3ode !ontrol 5ord for ;atching !ount
-:ample,
Design a programmable timer using 82?: and 878*# Interface 82?: at an
address 77+7< for counter 7 and rite the folloing 2;"s# $he 878* and 82?:
run at * 3<@ and 1#? 3<@ respectively&
1# $o generate a s(uare ave of period 1 ms#
2# $o interrupt the processor after 17 ms#
:# $o derive a monoshot pulse ith (uasistable state
duration ? ms#
Assembly langage program
SC
1
SC
0
RL
1
RL
0
M
2
M
1
M
0
BCD
0 0 1 1 0 1 1 1
Solution: =eglecting the higher order address lines ,2
1*
.2
8
- the interfacing circuit
diagram is shon in /ig# 1#17# $he 82?: is interfaced ith loer order data bus
,D
7
.D
7
-& hence 2
7
is used for selecting the even ban%# $he 2
7
and 2
1
of the 82?:
are connected ith 2
1
and 2
2
of the processor# $he counter addresses can be
decoded as given belo# If 2
7
is 1& the 82?: ill not be selected at all#
27 2* 2? 2+ 2: 22 21 27
7 1 7 7 7 7 7 7 6 +7< !ounter 7
7 1 7 6 +2< !ounter 7
1 7 7 6 ++< !ounter 7
1 1 7 6 +*< !51
i# /or generating a s(uare ave& 82?: should be used in mode :#
;et us select counter 7 for this purpose& that ill be operated in '!D mode ,may
even be operated in <9B mode-# =o suitable count is to be calculated for
generating 1 ms time period#
f61#?3<@&
$6141#?B17
.*
67#**M s
If = is the number of $ states re(uired for 1ms&
=61B17
.:
47#**)17
.*
61#?)17
:
61?77 states
$he control ord is decided as belo
1372
/ig1#17 Interfacing 82?: ith 878*
SC
1
SC
0
RL
1
RL
0
M
2
M
1
M
0
BCD
0 1 1 1 0 0 0 0
!0D9 89J39=$
288U39 !8A!0D9
8$21$A 30F 2;&:7< GInitialise 82?: ith
0U$ +*<&2; G!ounter7 in mode:
30F 2;&77 G5rite 77 decimal
0U$ +7<&2; GIn ;8' of count reg and
30F 2;&1? G1? decimal in 38' as a
0U$ +7<&2; Gcount
30F 2<&+!< G1eturn to D08
I=$ 21<
!0D9 9=D8
9=D 8$21$
ii# /or generating interrupt to the processor after 17ms& the 82?: is to be used in
mode 7# $he 0U$1 pin of 82?: is connected to interrupt input of the processor#
;et us use counter 1 for this purpose& and operate the 82?: in <9B count mode#
=umber of $ states re(uired for 17ms delay
617B17
.:
47#**)17
.*
61#?)17:
61?77 states
6:298<
$he control ord is decided as belo
1 702
Assembly langage program
!0D9 89J39=$
288U39 !8A!0D9
8$21$A 30F 2;&77< GInitialise 82?: ith
0U$ +*<&2; G!ounter1 in mode7
30F 2;&98< G;oad 98< as ;8' of count
0U$ +2<&2; GIn count reg of counter1
30F 2;&:2< G1? decimal in 38' as a
0U$ +2<&2; Gof counter1
30F 2<&+!< G1eturn to D08
I=$ 21<
!0D9 9=D8
9=D 8$21$
SC
1
SC
0
RL
1
RL
0
M
2
M
1
M
0
BCD
1 0 1 1 0 0 1 0
iii# /or generating a ?ms (uasistable state duration& the count re(uired is calculated
first# $he counter 2 of 82?: is used in mode1& to count in binary# $he 0U$2 signal
normally remains high after the count is loaded& till the trigger is applied# 2fter the
application of trigger signal& the output goes lo in the ne)t cycle& count don
starts and henever the count goes @ero the output again goes high#
=umber of $ states re(uired for 7?ms delay
6?B17
.:
47#**)17
.*
67?77 states
61D+! <
$he control ord is decided as belo
1B22
Assembly langage program
!0D9 89J39=$
288U39 !8A!0D9
8$21$A 30F 2;&'2< GInitialise 82?: ith
0U$ +*<&2; G!ounter2 in mode1
30F 2;&+!< G;oad +!< ,;8' of count-
0U$ ++<&2; GInto count register
30F 2;&1D< G;oad1D< ,38' of count-
0U$ ++<&2; GInto count register
30F 2<&+!< G1eturn to D08
I=$ 21<
!0D9 9=D8
9=D 8$21$
P$"A$A((A#)- I4T-$$6PT C"4T$"))-$ 82?9A
$he processor 878? had five hardare interrupt pins# 0ut of these five
interrupt pins& four pins ere allotted fi)ed vector addresses but the pin
I=$1 as not allotted any vector address& rather an e)ternal device as
supposed to hand over the type of the interrupt& i#e# ,$ype 7 to 7 for 18$7
to 18$7-& to the microprocessor# $he microprocessor then gets this type
and derives the interrupt vector address from that# !onsider an application&
here a number of I40 devices connected ith a !"U desire to transfer
data using interrupt driven data transfer mode# In these types of
applications& more number of interrupt pins are re(uired than available in a
:7
:7
typical microprocessor# 3oreover& in these multiple interrupt systems& the
processor ill have to ta%e care of the priorities for the interrupts&
simultaneously occurN ring at the interrupt re(uest pins#
$o overcome all these difficulties& e re(uire a programmable
interrupt controller hich is able to handle a number of interrupts at a time#
$his controller ta%es care of a number of simultaneously appearing
interrupt re(uests along ith their types and priorities# $his ill relieve the
processor from all these tas%s# $he programmable interrupt controller
82?92 from Intel is one such device# $he predecessor 82?9 as designed to
operate only ith 8.bit processors li%e 878?# 2 modified version& 82?92
as later introduced that is compatible ith 8.bit as ell as 1*.bit
processors#
Architectre and !ignal Descriptions of 82?9A
$he architectural bloc% diagram of 82?92 is shon in /ig# 1#1# $he
functional e)planation of each bloc% is given in the folloing te)t in brief#
Interrpt $e=est $egister 7I$$8 $he interrupts at I1> input lines are
handled by Interrupt 1e(uest 1egister internally# I11 stores all the
interrupt re(uests in it in order to serve them one by one on the priority
basis#
In+!er<ice $egister 7I!$8 $his stores all the interrupt re(uests those are
being served& i#e I81 %eeps a trac% of the re(uests being served#
Priority $esol<er $his unit determines the priorities of the interrupt re(uests
appearing simultaneously# $he highest priority is selected and stored into
the corresponding bit of I81 during I=$2 pulse# $he I1
7
has the highest
priority hile the I1
7
has the loest one& normally in fi)ed priority mode#
$he priorities hoever may be altered by programming the 82?92 in
rotating priority mode#
:1
:1
/ig1#1# 82?92 'loc% Diagram
Interrpt (as5 $egister 7I($8 $his register stores the bits re(uired to mas%
the interrupt puts# I31 operates on I11 at the direction of the "riority
1esolver#
Interrpt Control )ogic $his bloc% manages the interrupt and interrupt
ac%noledge sigD8ls to be sent to the !"U for serving one of the eight
interrupt re(uests# $his also accepts interrupt ac%noledge ,I=$2- signal
from !"U that causes the 82?92 to release vector address on to the data
bus#
Data #s #ffer $his tristate bidirectional buffer interfaces internal 82?92
bus to the microprocessor system data bus# !ontrol ords& status and vector
information pass through buffer during read or rite operations#
$ead ;rite Control )ogic $his circuit accepts and decodes commands from
the !"U# $his also allos the status of the 82?92 to be transferred on to the
data bus#
Cascade #ffer/Comparator $his bloc% stores and compares the IDLs of all
the 82?92s used in the system# $he three I40 pins !287.2 are outputs
:2
:2
hen the 82?92 is used as a master# $he same pins act as inputs hen the
82?92 is in slave mode# $he 82?92 in master mode sends the ID of the
interrupting slave device on these lines# $he slave thus selected& ill send
its pre programmed vector address on the data bus during the ne)t I=$2
pulse#
/igure 1#2 shos the pin configuration of 82?92& folloed by their
functional description of each of the signals in brief#
/ig#1#2# 82?9 "in Diagram
C! $his is an active.lo chip select signal for enabling 1DO and 51O
operations of 82?92#I=$2O function is independent of !8O#
/$B $his pin is an active.lo rite enable input to 82?92# $his enables
it to accept command ords from !"U#
$DB $his is an active.lo read enable input to 82?92# 2 lo on this line
enables 82?92 to release status onto the data bus of !"U#
D
7
.D
7
$hese pins form a bidirectional data bus that carries 8.bit data either
to control ord or from status ord registers# $his also carries interrupt
vector information#
CA!
o
+CA!
2
!ascade ;ines 2 single 82?92 provides eight vectored
interrupts# If more interrupts are re(uired& the 82?92 is used in cascade
::
::
mode# In cascade mode& a master 82?92 along ith eight slaves 82?92
can provide up to *+ vectored interrupt lines# $hese three lines act as
select lines for addressing the slaves 82?92#
P!B/-4B $his pin is a dual purpose pin# 5hen the chip is used in buffered
mode& it can be used as buffer enable to control buffer transreceivers# If this
is not used in buffered mode then the pin is used as input to designate
hether the chip is used as a master ,8" 6 1- or a slave ,9= 6 7-#
I4T $his pin goes high henever a valid interrupt re(uest is asserted# $his
is used to interrupt the !"U and is connected to the interrupt input of !"U#
I$
%
+I$
7
79nterrpt re=ests8 $hese pins act as inputs to accept interrupt
re(uests to the !"U# In edge triggerred mode& an interrupt service is
re(uested by raising an I1 pin from a lo to a high state and holding it high
until it is ac%noledged& and Pust by latching it to high level& if used in level
triggered mode#
I4TAB 7Interrpt ac5no;ledge8 $his pin is an input used to strobe.in 82?92
interrupt vector data on to the data bus# In conPunction ith !8& 51& and
1D pins& this selects the different operations li%e& riting command ords&
reading status ord& etc#
$he device 82?92 can be interfaced ith any !"U using either polling or
interrupt# In polling& the !"U %eeps on chec%ing each peripheral device in
se(uence to ascertain if it re(uires any service from the !"U# If any such
service re(uest is noticed& the !"U serves the re(uest and then goes on to
the ne)t device in se(uence# 2fter all the peripheral devices are scanned as
above the !"U again starts from the first device# $his type of system
operation results in the reduction of processing speed because most of the
!"U time is consumed in polling the peripheral devices#
In the interrupt driven method& the !"U performs the main
processing tas% till it is interrupted by a service re(uesting peripheral
device# $he net processing speed of these type of systems is high because
the !"U serves the peripheral only if it receives the interrupt re(uest# If
more than one interrupt re(uests are received at a time& all the re(uesting
peripherals are served one by one on priority basis# $his method of
interfacing may re(uire additional hardare if number of peripherals to be
interfaced is more than the interrupt pins available ith the !"U#
Interrpt !e=ence in an 8%8C !ystem
:+
:+
$he interrupt se(uence in an 878*.82?92 system is described as follosA
1# 0ne or more I1 lines are raised high that set corresponding I11 bits#
2# 82?92 resolves priority and sends an I=$ signal to !"U#
:# $he !"U ac%noledges ith I=$2 pulse#
+# Upon receiving an I=$2 signal from the !"U& the highest priority I81
bit is set and the corresponding I11 bit is reset# $he 82?92 does not drive
data bus during this period#
?# $he 878* ill initiate a second I=$2 pulse# During this period 82?92
releases an 8.bit pointer on to data bus from here it is read by the !"U#
*# $his completes the interrupt cycle# $he I81 bit is reset at the end of the
second I=$2 pulse if automatic end of interrupt ,290I- mode is
programmed# 0therise I81 bit remains set until an appropriate 90I
command is issued at the end of interrupt subroutine#
Command /ords of 82?9A
$he command ords of 82?92 are classified in to groups& vi@#
initiali@ation command ords ,I!5s- and operation command ords
,0!5s-Initiali@ation !ommand 5ords ,I!5s- 'efore it starts functioning& the
82?92 must be initiali@ed by riting to to four command ords into the
respective command ord registers# $hese are called as initiali@ation
command ords ,I!5s-# If 2
7
6 7 and D
+
6 1& the control ord is recogni@ed
as I!5
1
It contains the control bits for edge4level triggered mode& sin.
gle4cascade mode& call address interval and hether I!5
+
is re(uired or
not& etc# If 2
7
6 1& the control ord is recogni@ed as I!5
2
# $he I!5
2
stores
details regarding interrupt vector addresses# $he initialisation se(uence of
82?92 is described in from of a flo chart in /ig# 1#:# $he bit functions of
the I!51 and I!52 are self e)planatory as shon in /ig# 1#+#
0nce I!5
1
is loaded& the folloing initiali@ation procedure is carried out
internally#
,a- $he edge sense circuit is reset& i#e# by default 82?92 interrupts are edge
sensitive#
,b- I31 is cleared#
,c- I17 input is assigned the loest priority#
,d- 8lave mode address is set to 7#
,e- 8pecial mas% mode is cleared and status read is set to I11#
,f- If I!
+
6 7& all the functions of I!5
+
are set to @ero# 3aster4slave bit in
I!5
+
is used in the buffered mode only#
:?
:?
3C4
3C4
567S358L911:
3n
Casca
!e!
5673C
4
10:
3C4
3s
3C44
;9S7S358L910:
;9S73C
4
11:
3C4
Rea!& to acce%t
3nterru%t re/uest
/ig1#:# Initialisation 8e(uence of 82?92
In an 878? based system& 2
1?
D 2
8
of the interrupt vector address are the
respective bits of I!52# In 878*488 based system 2
1?
D 2
11
of the interrupt
vector address are inserted in place of $
7
. $: respectively and the
remaining three bits ,2
8
& 2
9
and 2
17
- are selected depending upon the
interrupt level& i#e# from 777 to 111 for I1
7
to I1
7
#
I!5
1
and I!5
2
are compulsory command ords in initiali@ation
se(uence of 82?92 as is evident from /ig# 1#:& hile I!5
:
and I!5
+
are
optional# $he I!5
:
is read only hen there are more than one 82?92s in
the system& i#e# cascading is used ,8=J; 6 7-# $he 8=J; bit in I!5
1
D
0
D
1
113C4
4
5ee!e!
015o 3C4
4
5ee!e!
11Sin,le
01Casca!e!
<
7
+<
5
o$ 3nterru%t vector a!!ress
MCs =0*=5 #o!e onl&
D
2
Call <!!ress 3nterval
113nterval o$ 4 (&tes
013nterval o$ = (&tes
D
3
11Level "ri,,ere!
019!,e "ri,,ere!
D
D
indicates hether the 82?92 is in cascade mode or not# $he I!5
:
loads an
8.bit slave register# Its detailed functions are as follos#
In master mode Qi#e# 8" 6 1 or in buffer mode 348 6 1 in I!5
+
R& the 8.bit
slave register ill be set bit.ise to L1L for each slave in the system& as
shon in /ig# 1#?# $he re(uesting slave ill then release the second byte of
a !2;; se(uence#
In slave mode Qi#e#8"67 or if 'U/61 and 34867 in I!5
+
R bits D
2
to D
7
identify the slave& i#e 777 to 111 for slave 1 to slave 8# $he slave compares
the cascade inputs ith these bits and if they are e(ual& the second byte if
the !2;; se(uence is released by it on the data bus#
%C&

<
0
D
7
6 D
5 D
4
D
3
D
2
D
1
D
0
0 '
7
'
6
'
5
L%T! 'D%
SN(L
%C
4
%C&
2
<
0
D
7
6 D
5 D
4
D
3
D
2
D
1
D
0
T
7
T
6
T
5
T
4
T
3
'
0
'
)
'
*
"
7
+"
3
are <
3
> <
0
o$ 3nterru%t vector a!!ress
<
10
> <
?
, <
=
> Selecte! accor!in, to 3nterru%t re/uest level.
"e& are not te a!!ress lines to #icro%rocessor
<
0
> 1 Selects 3C4
2
@i,1.4. 3nitialisation Co##an! 4or!s 3C4
1
an! 3C4
2
D
!$+ter %C&
3
<
0
D
7
D
6
D
5 D
4
D
3
D
2
D
1
D
0
S
7
S
6
S
5
S
4
S
3
S
2
S

S
0
S
n
1 1 > 3R
n
3n%ut as a slave
10 > 3R
n
3n%ut !oes not ave a slave
Sl$#e %C&
4
<
0
D
7
6
D
5 D
4
D
3
D
2
D
1
D
0
0 0 0 0 0 %D
2
%D

%D
0
D
2
D
1
D
0
> 000 to 111 $or 3R
0
to 3R
7
or slave 1 to slave =
@i,1.5. 3C4
3
in Master an! Slave Mo!e
IC/
@
$he use of this command ord depends on the I!
+
bit of I!5
1
# If I!
+
6 1& I!5
+
is used& otherise it is neglected# $he bit functions of I!5
+
are
described as follosA
8/=3 8pecial fully nested mode is selected& if 8/=3 6 1#
'U/ If 'U/ 6 1& the buffered mode is selected# In the buffered mode&
!P/-4 acts as enable output and the master4slave is determined using the
348 bit of I!5
+
#
(/! If 348 6 1& 82?92 is a master# If 348 6 7& 82?92 is a slave# If 'U/ 6
7& 348 is to be neglected#
A-"I If 290I 6 1& the automatic end of interrupt mode is selected#
M "3 If the M "3 bit is 7& the 3cs.8? system operation is selected
and if4M "3 61& 878*488 operation is selected#
@i,1#* shos the I!5
+
bit positions
D
"peration Command /ords
0nce 82?92 is initiali@ed using the previously discussed command ords for
initialisation& it is ready for its normal function& i#e# for accepting the interrupts but
82?92 has its on ays of handling the received interrupts called as modes of
operation# $hese modes of operations can be selected by programming& i#e# riting
three internal registers called as operation command ord registers. $he data
ritten into them ,bit pattern- is called as operation command ords. In the three
operation command ords 0!5
l
&0!5
2
and 0!5
:
every bit corresponds to
some operational feature of the mode selected& e)cept for a fe bits those are
either L1L or L7L# $he three operation command ords are shon in /ig# 1#7 ,a-& ,b-
and ,c- ith the bit selection details# 0!5
1
is used to mas% the unanted interrupt
re(uests# If the mas% bit is L1L& the corresponding interrupt re(uest is mas%ed& and if
it is L7L& the re(uest is enabled# In 0!5
2
the three bits& vi@# 1& 8; and 90I control
the end of interrupt& the rotate mode and their combinations as shon in /ig# 1#7
,b-& $he three bits ;
2
& ;
1
and ;
7
in 0!5
2
determine the interrupt level to be
selected for operation & if the 8; bit is active& i#e# L1L# $he details of 0!5
2
are
shon in /ig# 1#7,b-#
In operation command ord : ,0!5:-& if the 9833 bit& i#e# enable special mas%
mode bit is set to L1L& the 833 bit is enabled to select or mas% the special mas%
mode. 5hen 9833 bit is L7L& the 833 bit is neglected# If the 833 bit& i#e#
special mas% mode bit is L1L& the 82?92 ill enter special mas% mode provided
9833 6 1#
If 9833 6 1 and 833 6 7& the 82?92 ill return to the normal mas% mode# $he
details of bits of 0!5
:
are given in /ig# 1#7 ,c- along ith their bit definitions#
OC&

<
0
D
7
6
D
5 D
4
D
3
D
2
D
1
D
0
0 !
7
!
6
!
5
!
4
!
3
!
2
!

!
0
M
0
+M
7
1 + MasA Set
@i,1.7.a.
@i,1.7.(
@i,1.7.c.
:9
+7
+7
"perating (odes of 82?9
$he different modes of operation of 82?92 can be programmed by setting or
resting the appropriate bits of the I!5s or 0!5s as discussed previously# $he
different modes of operaN tion of 82?92 are e)plained in the folloing te)t#
'lly 4ested (ode $his is the default mode of operation of 82?92# I1
7
has the
highest priority and I1
7
has the loest one# 5hen interrupt re(uests are noticed&
the highest priority re(uest amongst them is determined and the vector is placed
on the data bus# $he corresponding bit of I81 is set and remains set till the
microprocessor issues an 90I command Pust before returning from the service
routine or the 290I bit is set# If the I81 ,in service- bit is set& all the same or
loer priority interrupts are inhibited but higher levels ill generate an interrupt&
that ill be ac%noledged only if the microprocessorLs interrupt enable flag ,I/- is
set# $he priorities can afterards be changed by programming the rotating priority
modes#
-nd of Interrpt 7-"I8 $he I81 bit can be reset either ith 290I bit of I!5
1
or
by 90I command& issued before returning from the interrupt service routine# $here
are to types of 90I commands specific and non.specific# 5hen 82?92 is
operated in the modes that preserve fully nested structure& it can determine hich
I81 bit is to be reset on 90$# 5hen nonspecific 90I command is issued to 82?92
it ill automatically reset the highest I81 bit out of those already set#
5hen a mode that may disturb the fully nested structure is used& the 82?92
is no longer able to determine the last level ac%noledged# In this case a specific
90I command is issued to reset a particular I81 bit# 2n I81 bit that is mas%ed by
the corresponding I31 bit& ill not be cleared by a non.specific 90I of 82?92& if
it is in special mas% mode#
Atomatic $otation $his is used in the applications here all the interrupting
devices are of e(ual priority# In this mode& an interrupt re(uest ,I1- level receives
loest priority after it is served hile the ne)t device to be served gets the highest
priority in se(uence# 0nce all the devices are served li%e this& the first device again
receives highest priority#
Atomatic -"I (ode $ill 290I 6 1 in I!5
+
& the 82?92 operates in 290I
mode# In this mode& the 82?92 performs a non.specific 90I operation at the
trailing edge of the last I=$2 pulse automatically# $his mode should be used only
hen a nested multilevel interrupt structure is not re(uired ith a single 82?92#
!pecific $otation In this mode a bottom priority level can be selected& using ;
2
&
;
1
and ;
7
in 0!5
2
and 1 61& 8; 6 1& 90I 6 7# $he selected bottom priority fi)es
other priorities# If I1
?
is selected as a bottom priority& then I1
?
ill have least
+1
+1
priority and I1
+
ill have a ne)t higher priority# $hus I1
*
ill have the highest
priority# $hese priorities can be changed during an 90I command by
programming the rotate on specific 90I command in 0!5
2
!pecial (as5 (ode In special mas% mode& hen a mas% bit is set in 0!5
l
& it
inhibits further interrupts at that level and enables interrupt from other levels&
hich are not mas%ed#
-dge and )e<el Triggered (ode $his mode decides hether the interrupt should
be edge triggered or level triggered# If bit ;$I3 of I!5
l
6 7& they are edge
triggered& otherise the interrupts are level triggered#
$eading 82?9 !tats $he status of the internal registers of 82?92 can be read
using this mode# $he 0!5
:
is used to read I11 and I81 hile 0!5
l
is used to
read I31# 1eading is possible only in no polled mode#
Poll Command In polled mode of operation& the I=$ output of 82?92 is
neglected& though it functions normally& by not connecting I=$ output or by
mas%ing I=$ input of the microprocessor# $he poll mode is entered by setting " 6
1 in 0!5
:
# $he 82?92 is polled by using softare e)ecution by microprocessor
instead of the re(uests on I=$ input# $he 82?92 treats the ne)t 1D pulse to the
82?92 as an interrupt ac%noledge# 2n appropriate I81 bit is set& if there is a
re(uest# $he priority level is read and a data ord is placed on to data bus& after
1D is activated# $he data ord is shon in /ig# 1#8#
/ig# 1#8# Data 5ord of 82?9
2 poll command may give you more than *+ priority levels# =ote that this has
nothing to do ith the 878* interrupt structure and the interrupt priorities#
!pecial 'lly 4ested (ode $his mode is used in more complicated systems&
here cascading is used and the priority has to be programmed in the master using
I!5
+
# $his is somehat similar to the normal nested mode# In this mode& hen an
interrupt re(uest from a certain lave is in service& this slave can further send
re(uests to the master& if the re(uesting device connected to the slave has higher
priority than the one being currently served# In this mode& the master interrupts the
+2
+2
!"U only hen the interrupting device has a higher or the same priority than the
one currently being served# In normal mode& other re(uests than the one being
served are mas%ed out#
5hen entering the interrupt service routine the softare has to chec%
hether this is the only re(uest from the slave# $his is done by sending a non.
specific 90I command to the slave and then reading its I81 and chec%ing for @ero#
If its @ero& a non.specific 90I can be sent to the master& otherise no 90I should
be sent# $his mode is important& since in the absence of this mode& the slave ould
interrupt the master only once and hence the priorities of the Llave inputs ould
have been disturbed#
#ffered (ode 5hen the 82?92 is used in the systems here bus driving buffers
are used on data buses ,e#g# cascade systems-# $he problem of enabling the buffers
e)ists# $he 82?92 sends buffer enable signal on 8" 49= pin& henever data is
placed on the bus#
Cascade (ode $he 82?92 can be connected in a system containing one master
and eight laves ,ma)imum- to handle up to *+ priority levels# $he master controls
the slaves using !28
7
.!28
2
hich act as chip select inputs ,encoded- for slaves#
In this mode& the slave I=$ outputs are connected ith master I1 inputs# 5hen a
slave re(uest line is activated and ac%noledged& the master ill enable the slave
to release the vector address during second pulse of I=$2 se(uence# $he cascade
lines are normally lo and contain slave address codes from the trailing edge of
the first I=$ 2 pulse to the trailing edge of the second I=$ 2 pulse# 9ach 82?92
in the system must be separately initiali@ed and programmed to or% in different
modes# $he 90I command must be issued tice& one for master and the other for
the slave# 2 separate address decoder is used to activate the chip select line of each
82?92#
/igure 1#9 shos the details of the circuit connections of 82?92s in cascade
scheme#
+:
0 0 0 0
D
Interfacing and programming 82?9
9)ampleA
8ho 82?92 interfacing connections ith 878* at the address 77+)# 5rite an 2;"
to initiali@e the 82?92 in single level triggered mode# $hen set the 82?92 to
operate ith I1* mas%ed& I1+ as bottom priority level& ith special 90I mode# 8et
special mas% mode of 82?92# 1ead I11 and I81 into registers '< and ';
respectively#
8olutionA
;et the starting address is 7777A7717# $he interconnections of 82?92 ith
878* are as shon in /ig 1#17# $he 82?9 is interfaced ith loer byte of the 878*
data bus& hence 27 line of the microprocessor system is abondened and 21 of the
microprocessor system is connected ith 27 of the 82?92# 'efore going for an
2;"& all the initialisation command ords ,I!58- and 0peration command ord
,0!58- must be decided# I!51 decides single level triggered& address interval of
+ as given belo#
<
0
D
7
6 D
5 D
4
D
3
D
2
D
1
D
0
6 1/<
D
0
3C4
4
5ee!e!
D
1
Sin,le =25?<
D
2
Call <!!ress 3nterval 4
D
3
Level "ri,,ere!
D
4
<l'a&s set to 1
D
5
D
6
D
7
DonBt care $or =0=6 s&ste#
<
0
<l'a&s set to 0
++
$7 $* $? $+ $: 217 29 28
1 7 7 7 7 7 1 1
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 0 0 0 0 0 0 0
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 0 0 0 0 0 0 1
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0 0 0 0 0 0
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 1 1 1 0 0 1 0 0
3C4
2
Cector a!!ress1 0000-0010 $or 3R
3
1=32
<
=
<
?
<
10
3R3 selecte!
"ere is no slave ence te 3C43 is as ,iven (elo'
3C4
3
1002
2ctually I!5: is not at all needed& because in I!51 the 82?92 is set for single mode#
$he I!5+ should be set as shon beloA
3C4
4
1012
D7 /or 878* system
D1 =ormal 90I
D2 D: =on buffered mode
D+ /or special fully nested mode mas%ing
0!51 8ets the mas% of I1* as shon belo
6C4
1
1402
I1* is mas%ed
0!52 8ets the modes and rotating priority as shon belo
6C4
2
1942
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 0 1 1 0 1 0 1 0
<
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 0 1 1 0 1 0 1 1
D7 D2 'ottom priority ;evel set at I1+
D? D7 8pecific 90I !ommand ith rotating priority
0!5: 8ets the special mas% mode and reads
I81 and I11 using the folloing control ords#
/or reading I11
D7 D1 1ead I11
D2 =o "oll command
D? D7 8pecial mas% mode
6C4
3
16<2
/or reading I81
D7 D1 1ead I81
D2 =o "oll command
D? D7 8pecial mas% mode
6C4
3
16B2
/ig1#17# Interfacing 82?92 ith 878*
Assembly langage program
!0D9 89J39=$
288U39 !8A!0D9
8$21$A 30F 2;&1/< G 8et the 82?92 in single& level
30F DB&77+7<
0U$ DB&2; Gtriggered mode ith call
30F DB&77+2< Gaddress of interval of +
30F 2;&8:< G8elect vector address 7717<
0U$ DB&2; Gfor I1:,I!52-
30F 2;&71< AI!5+ for 878* system& normal
0U$ DB&2; G 90I& non.buffered& 8/=3 mas%ed
30F 2;&+7<
0U$ DB&2; G0!51 for I1* mas%ed
30F 2;&9+< G8pecific 90I ith rotating
30F DB&77+7<
0U$ DB&2; G "riority and bottom level of
30F 2;&*2< GI1+ ith 0!52 5rite 0!5: reading
0U$ DB&2; G I11 and store in '<
I= 2;&DB
30F '<&2;
30F 2;&*'< G 5rite 0!5: to read
0U$ DB&2; G I81 and store in ';
I= 2;&DB
30F ';&2;
30F 2<&+!< G 1eturn to D08
I=$ 21<
!0D9 9=D8
9=D 8$21$