Analog Integrated Circuits and Signal Processing, 38, 161–174, 2004

c 2004 Kluwer Academic Publishers. Manufactured in The Netherlands.

A Differential CMOS Current-Mode Variable Gain Amplifier with Digital dB-Linear

Gain Control

ARUN RAVINDRAN,1 EVA VIDAL,2 SEOUNG-JAE YOO,1 KISHORE RAMARAO1

AND MOHAMMED ISMAIL1
1
Analog VLSI Lab, The Department of Electrical Engineering, The Ohio State University, 2015 Neil Ave, Columbus, OH-43201, USA
2
Department d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, Gran Capità s/n, Mòdul C4, 08034 Barcelona, Spain
E-mail: ravindra@ee.eng.ohio-state.edu

Received June 15, 2002; Revised January 7, 2003; Accepted February 14, 2003

Abstract. A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is
presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current
signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the
desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at
the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for
designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of
the presented approach.

Key Words: current-mode circuits, variable gain amplifier

1. Introduction
Variable gain amplifiers (VGAs) find use in a number
of automatic gain control applications used in diverse
areas such as communication, control, consumer elec-
tronics etc [1–4]. In most such applications, they serve
to provide a constant dynamic range to the accompany-
ing analog to digital converter (ADC). As an example,
Fig. 1 shows the use of a VGA in a typical wireless
communication receiver chain [5]. As shown in Fig. 1,
the VGA is controlled by a digital signal processor
(DSP) which performs gain control based on the re-
ceived signal strength. Hence it is desirable that the
gain of the VGA is directly controlled digitally thus
avoiding the use of auxiliary digital to analog convert-
ers (DACs in grey in Fig. 1 ). Also a dB-linear control
is often required so that a large gain control range can
be achieved.
A continued scaling of devices and the accompany-
ing reduction in supply voltage has led to a demand for
new circuit techniques capable of low voltage operation
[6]. Current-mode signal processing enjoys a distinct
advantage for low voltage operation as current-mode
circuits are characterized by low impedance nodes with
low voltage swing [7]. This allows for a reduced sup-
ply since the supply range is limited only by the need
to keep the devices in the active region of operation.
An accompanying advantage is that, such circuits allow
for the use of technologies with high threshold voltages
(for reduced leakage) optimized for digital circuits. The
low impedance nodes also render the circuit nodes less
sensitive to a noisy supply, an important requirement
for mixed signal operation where analog circuits have
to operate in conjunction with noisy digital circuits.
Even in traditional applications where signals are pro-
cessed as voltages such as the receiver chain shown in
Fig. 1, current-mode signal processing finds use as the
outputs of the mixer are best thought of as current sig-
nals owing to the high output impedance of the mixer
stage [8]. As a result, there is an effort to develop ana-
log signal processing circuits such as amplifiers, filters,
analog to digital converters (ADC) etc that are capable
of processing current domain signals.
In this work, a novel CMOS current-mode variable
gain amplifier with a dB-linear gain control is pre-
sented. The VGA is conceptually shown in Fig. 2. A
digitally controlled circuit generating exponentially
varying currents serves as the control signal. The input
162 Ravindran et al.

VGA
LPF A/D
GSM DCS1800
BPF LNA
Antenna
a

90o
DAC
DECT
BPF DECT
LNA D
LO S
P
DAC
WCDMA WCDMA
BPF LNA

LPF A/D

VGA

Fig. 1. A typical multi-standard wireless receiver chain for GSM, DECT and WCDMA wireless standards.

I+in I-in
Iref

From DSP Ithru

Current
Division Buffer
Network Idum
I+out I-out

Offset cancellation

I+VGA I-VGA
A A

Fig. 2. Block diagram of the variable gain amplifier.

signal is then multiplied by this control current using 2. Exponential Generator

a current multiplier to generate a dB-linear output. A
current amplifier at the output then sets the gain to the
desired level. More than one circuit realization of the
exponential generator, current multiplier and current
amplifier is presented that allows for designs capable
of meeting different design specifications. The circuits
are analyzed for their advantages and limitations.
The next section presents the exponential generator
required to generate the control signal. Following
this, implementation details of the current multiplier
are described. This is followed by a brief description
of the current amplifier. The paper concludes with
simulation and experimental results showing validity
of the presented approach.
2.1. Circuit Realization
In bipolar technology, the inherent exponential V-I
characteristics can be used to realize an exponential
current. Though weak inversion MOS transistors ex-
hibit an exponential behavior, a lack of sufficient cur-
rent drive limits the use of circuits based on weak
inversion of MOS transistors. Previous attempts in
generating the exponential function using MOS tran-
sistors operating in saturation regions have focused
on implementing an approximation of the exponen-
tial function based on either a truncated Taylor’s se-
ries [9] or an approximation given by the following
 A Differential CMOS Current-Mode Variable Gain Amplifier 163

function [1–3] a dynamic range given by

n
nx ∼ 1+x DR = 2n+1 (3)
e = (1)
1−x
with a percentage error given by
The Taylor series approximation is valid with an er-
ror less than 5% for a limited range of the x signal, 1
Error = 100 ∗ (4)
−0.575 ≤ x ≤ 0.815, [2] whereas Eq. (1) is valid 2n+1
for −0.24 ≤ x ≤ 0.24, with a 2% error with n = 2.
In this work, an alternative approach based on the Thus a 6 bit implementation results in a dynamic range
direct digital synthesis of the exponential function is of 36 dB.
implemented. Points on an exponential curve (normal- Figure 4 shows the digitally synthesized exponen-
ized to unity) are represented as binary numbers, with tial control curve. The exponential control shown in
the number of bits used depending on the accuracy re- Fig. 4 (Eq. (2)) can be realized using a R-2R ladder.
quired. Such a binary number is generated by a digital The number of bits employed depends on the accuracy
signal processor (DSP) as a binary word. The algorithm of the resistors that can be realized in a given tech-
required to generate the binary numbers is presented in nology being 6–8 bits possible in most technologies.
[10]. The binary word then controls a reference current However, the R-2R ladder consumes a large chip area.
source thus generating an exponential curve as the dig- Also, the switch resistance has to kept sufficiently low
ital word is varied. This operation can be represented in order to preserve the accuracy of the division. An al-
mathematically as ternative compact realization using a MOS-only R-2R
ladder, also known as current division network (CDN),
 

n is shown in Fig. 5 [11]. Although a current division
Iexp = Iref bi 2 i
(2) network employs MOS devices, its performance is in-
i=1 dependent of the region of operation of the device and
hence does not constitute a limitation for low voltage
where bi are the bits constituting the binary number applications. Moreover, the switches are part of the net-
and n is the number of bits used in the digital represen- work and their aspect ratios can be kept small. However,
tation of the exponential curve points. Figure 3 shows CDNs are very sensitive to the offset voltages between
representative points on an exponential curve, the cor- their “thru” and “dump” current terminals (see Fig. 5)
responding digital word and values of the exponential and the binary division may get distorted as a result.
current signal obtained upon attenuating a reference Even so, 10 bit CDNs have been reported [12]. Note
current source of 10 µA. The percentage error for a 6- that it is possible to pre-distort the digital codes such
bit implementation is also included. In general, an n-bit that the inaccurate division, if known in advance, can
implementation of a current division network results in be corrected for. As will be seen later, the choice of the
reference current value depends on the signal handling
Steps e-x 6-bit Error Simulated Error
capabilities of the multiplier.
(dB) approx (%) values(µA) (%) In either realization of Eq. (2), a current buffer is
b1-b6 Iref=10µA required to extract the current out of the CDN/R-2R
ladder. The current buffer circuit used in this work
-1 0.8914 111001 0.0741 8.904 0.10
-2 0.7945 110011 -0.2341 7.967 -0.22 is shown in Fig. 6. The requirement to keep the off-
-5 0.5627 100100 0.0205 5.625 0.02 set voltage minimum between the Ithru and Idump ter-
-10 0.3166 010100 0.4137 3.126 0.40 minals (Fig. 4) necessitates the use of two identical
-15 0.1782 001011 0.6298 1.721 0.07
-20 0.1003 000110 0.6509 0.939 0.64 branches of the current buffer (Fig. 6) so that Ithru and
-25 0.0564 000100 -0.6084 0.626 -0.62 Idump are connected to the same voltage. Not that Ithru
-30 0.0317 000010 0.0496 0.314 0.03 is the required control current Iexp . Three additional
-36 0.0159 000001 0.0298 0.158 0.01
copies of Iexp are required (as will be seen in the next
Fig. 3. Digital representation of the exponential curve by a 6-bit section) that are easily generated by mirroring the Ithru
approximation. thrice.
164 Ravindran et al.

Fig. 4. Digitally synthesized exponential curve.

Iref Iref /2 Iref /6

Vbias
Iref /2 Iref /6

B1/ B6 B6/
B1

Ithru Idump

Fig. 5. A 6-bit current division network.

The buffer is based on a Sackinger current mirror
[13] with a low impedance terminal realized at the
source of the cascode transistor and a high impedance
terminal realized at the drain of the cascode transistor.
The input resistance of the buffer is given by
1
Rin ≈
A p gm3
and the output impedance is given by
Rout ≈ An gm2r02r01  A p gm3r03r04
where A p and An are the booster amplifier gains (M5
and M6 ) and the others parameters have their usual
meaning. Note that use of Sackinger current mirrors in
the realization of the buffer constraints the minimum
supply voltage to at least
(5) Vdd = 4Vov + Vtn + |Vtp | (7)
where Vtn and Vtp are the threshold voltages of the
NMOS and the PMOS transistors respectively and Vov
(6) is the overdrive voltage.
 A Differential CMOS Current-Mode Variable Gain Amplifier 165

code of this circuit is not critical. A bandwidth of 10

kHz should be sufficient for most applications.
The R-2R ladder can  be thought of as an equivalent
Vbias2
M4 resistor of value R/( bi 2 −i ) [15]. Thus the ladder
contributes a thermal noise current of
Ithru
2
M6 Irms 4kTR
Idump = n (9)
Hz 
M3 bi 2−i
i=1
Ibias2
where k is the Boltzman’s constant, T is the tempera-
Ibias2
To gnd
Iexp ture, R is the resistor value of the R-2R ladder.
M2 In the case of CDN, assuming the transistors are in
the linear region, a similar noise expression holds with
M5 the equivalent resistance given by

1
Vbias1 M1 Req = (10)
µn Cox (W/L)Vov

where Vov is the overdrive voltage of the transistors

constituting the CDN.
Fig. 6. A current buffer circuit based on Sackinger current mirrors.
The current buffer based on the Sackinger current
mirror (Fig. 6) has transistors M1 and M4 as the most
significant noise contributors. The total noise current
A modification of the Sackinger current mirror using at the output of the current buffer (thermal + flicker
a level shifting circuit capable of low voltage operation noise) is
is show in Fig. 7 [14]. The minimum supply voltage for
a current buffer incorporating low voltage-level shifted 2
Irms 8kT
Sackinger current mirror circuit is ≈ (gm1 + gm4 )
Hz 3
K n gm1 K p gm4
Vdd = 2Vov + |Vtp | − |Vtn | (8) + + (11)
(WL)1 Cox f n (WL)4 Cox f p

2.2. Frequency Response and Noise Analysis where f n and f p are the flicker noise corners of the
NMOS and PMOS transistors respectively. A similar
Since the control signal of the VGA does not vary noise analysis holds for the low voltage-level shifted-
rapidly frequency response as regards to the digital Sackinger current mirror [14] based current buffer.

Ibias2 Ibias2
Iin Ibias1
Ibias1
Iout

Fig. 7. A modified low voltage Sackinger current mirror.

166 Ravindran et al.

3. Multiplier and Iexp − Idiff ,

3.1. Circuit Realization 2Iexp Idiff

Having generated an exponentially varying control cur-
rent, our next objective is to multiply this current signal
with the input differential current signal to obtain a dif-
ferential output current that is a scaled version of the
input differential signal. This is mathematically repre-
sented as
+ (Idiff ) · Iexp − (Idiff ) · Iexp
Iout = Iout =−
Iα Iα
where Iα is a constant scaling factor having units of
Amperes.
The differential input signal Idiff = Iin+ − Iin− (Iin+ =
−Iin− ) is thus scaled to a determined amplitude differ-
+ −
ential output signal Iout and Iout by the exponentially
controlled signal Iexp hence realizing a VGA. In a VGA
control loop any variation in the output signal Iout level
is detected by the DSP which in turn varies the con-
trol current Iexp by changing the digital control word
(bi ).
A number of current-mode multiplier circuits ca-
pable of realizing the product of two currents exist
in the literature [16–19]. Here we consider a multi-
plier circuit based on [19]. This circuit uses a min-
imum number of devices and shows an excellent
linearity. Figure 8 shows the multiplier core cell. As-
suming the MOS transistors are operating in the satu-
ration region and a square-law based operation, it can
be shown that for inputs to the multiplier Iexp + Idiff
+
Iout = −Iexp +
K (VDD − |Vtp | − Vtn )2
− 2Iexp Idiff
Iout = −Iexp − (13)
K (VDD − |Vtp | − Vtn )2
where K = K n = µn Cox W/L = K p = µ p Cox W/L
and all parameters have their usual meanings.
Equation (13) differs from the ideal Eq. (12) by the
dc offset current −Iexp . By adding the copies of the cur-
(12) + −
rent Iexp to Iout and Iout , the dc offset can be eliminated.
Incomplete offset cancellation results in an offset cur-
rent at the output.
While the core cell in Fig. 8 is simple, deviations
from Eq. (13) results due to the imperfect current mir-
ror. The performance of the core cell can be improved
by replacing the current mirror with a Sackinger current
mirror [13]. The improved current multiplier is shown
in Fig. 9. The input resistance of the multiplier is given
by


1 1 1
Rin ≈  · (14)
gm1 gm7 Ap
and Rout is given by an expression similar to Eq. (6).
Thus the use of Sackinger current mirror not only im-
proves the current copying accuracy but also the output
impedance. The multiplier based on the Sackinger cur-
rent mirror has a supply requirement as given by Eq. (7).
Similar to the current buffer a low voltage realization
can be realized using a level shifted Sackinger current
mirror [14] with a minimum supply voltage given by
Eq. (8).
Another problem suffered by the core cell is
the requirement that K n be equal to K p (see
Eq. (13)). If K = K n − K p , it can be shown that for
(K /K )2 << 1, the resulting deviation from the ideal
output of the multiplier by I is given by [19]

+ − 4Iexp Idiff
Io = Iout − Iout ≈
K (VDD − |Vtp | − Vtn )2
4Iexp Idiff K
+
K (VDD − |Vtp | − Vtn )2 K
Idiff K
+ (15)
Fig. 8. Multiplier core cell. 2 K
 A Differential CMOS Current-Mode Variable Gain Amplifier
Fig. 9. Improved multiplier based on the Sackinger current mirror.
This can be written as
4Iexp Idiff
Io ≈
K (VDD − |Vtp | − Vtn )2


K K K
× 1+ +
K 8(VDD − |Vtp | − Vtn )2 Iexp K
(16)
showing two error terms proportional to K /K . The
mismatch limits the number of bits that can be used in
the exponential generator thus determining the control
range of the VGA. For a n bit accuracy, K /K must
be at least less that 1/2n . Though µn and µ p values
vary in the same fashion with process and temperature,
practically, the mismatch in K values limits the accu-
racy to10%. An alternative multiplier realization that
eliminates this requirement (K n = K p ) is described in
[20].
3.2. Frequency Response and Noise Analysis
The frequency response of the multiplier based on
the Sackinger current mirror is dominated by the high
impedance node at the output of the current mirror. The
3-dB frequency of the pole associated to this node is
167
given by
1
f 3dB ≈ (17)
2π (Rout  R L )(C L  Cgdn  Cgdp )
where Rout is given by an expression similar to Eq. (6),
R L is the load resistance, C L is the load capacitance
and Cgdn and Cgdp are the gate-drain capacitances of
the NMOS and PMOS cascode transistors respectively.
Since the multiplier is composed of current mirrors,
the output noise current is similar to the noise expres-
sion derived for the current buffer.
4. Current Amplifier
4.1. Circuit Implementation
A current amplifier is required for scaling to the desired
+ −
gain level the current signals Iout and Iout . A realization
of the current amplifier based on the current conveyor
(CCII) [21] is shown in Fig. 10. The CCII is a three
terminal device, with a voltage buffer between the X
and Y terminals and a current buffer between the X and
Z terminals. A voltage Vy applied to the Y terminal is
168 Ravindran et al.

ii V y transistor M5 reduces the input resistance into the drain

Y io of M6 and M7 (X terminal) to a value given by
Ry ix Z 1
X Rx ≈ (21)
gm1 gm5 (r02  r04 )
Rx
The voltage at the X input tracks that of the Y input
due to feedback provided by the buffer. The output
Fig. 10. Current amplifier based on CCII. impedance of the CCII (Z terminal) is given by

Rz ≈ r09 gm10r10  ro12 gm 11 ro11 (22)

converted to a current Ix at the X terminal.
Vy Instead of using two separate current amplifiers a
Ix = (18) single current amplifier based on a fully differential
Rx
current conveyor can be employed [23]. This circuit
This current is then copied on to the Z terminal (Iz = uses a differential difference amplifier instead of a sin-
Ix ). The multiplier output current is converted to a volt- gle ended amplifier. The resulting circuit is more com-
age Vy by passing through a resistor R y . Thus the cur- plex and requires a common mode feedback to define
rent gain realized is output common mode levels.
Iz Ry
A= = (19) 4.2. Frequency Response and Noise Analysis
Iout,multiplier Rx

Two such current amplifiers are used to provide iden- The frequency response of the current amplifier is dom-
+
tical current gains to the outputs of the multiplier Iout inated by a pole at the output of the current amplifier
−
and Iout . Thus the final differential output of the VGA (Z terminal of the CCII) and a pole at the output of first
shown in Fig. 2 is stage of the buffer. The 3-dB frequencies of the poles
associated with these nodes are given by
+ + A · 2Iexp Idiff
IVGA = AIout = 1
K (VDD − |Vtp | − Vtn )2 f out ≈
(20) 2π Rz C L
− − A · 2Iexp Idiff 1
IVGA = AIout =− f buffer ≈ (23)
K (VDD − |Vtp | − Vtn )2 2π (r02  r04 )Cgs5

The circuit implementation of the CCII is shown in Assuming C L  Cgs5 , and since Rz  ro2 //ro4 the f out
Fig. 11. The circuit enjoys a rail-to-rail swing capability is the dominant pole. No additional compensation is
at the output and an excellent linearity [22]. Transistors necessary since the load serves as the compensation
M1, M2, M3 and M4 in Fig. 11 constitute the voltage capacitor.
buffer. The feedback due to the buffer around the PMOS The noise current at the output of the amplifier is
dominated by transistors M5 and M6 connected at the
low impedance input of the current amplifier (terminal
X of the CCII). The noise current at the output of the
current amplifier is given by
2
Irms 8kT(gm5 + gm8 )
=
Hz 3
K p gm5 K n gm8
+ + (24)
(WL)5 Cox f n (WL)8 Cox f p

5. Simulation Results

In the implementation of the prototype VGA, as pre-

Fig. 11. Circuit realization of CCII. sented above, several circuit choices are available. The
 A Differential CMOS Current-Mode Variable Gain Amplifier
target technology was three metal, two poly, AMI 0.5µ
CMOS process available through MOSIS. This process
has Vtpo = 0.95 V and Vtno = 0.65 V. A high resistance
layer of sheet resistance 1 k/sq is available for real-
izing large resistors. The large threshold voltages con-
straints the supply to be ±1.5 V upon using Sackinger
current mirrors for the various circuit blocks. A lower
supply voltage of ±0.9 V is however possible if the
Sackinger current mirrors are replaced by the low volt-
age Sackinger current mirrors (see Fig. 7). Since the
conceptual VGA shown in Fig. 2 is independent of the
supply voltage, a supply voltage of ±1.5 V was used
in the prototype implementation. The exponential gen-
erator was implemented using a 6-bit current division
network for a targeted dynamic range of 36 dB. How-
ever, as pointed out earlier, the actual dynamic range
is dependent on the mismatch between the K n and K p
values. The current buffer was realized using the circuit
shown in Fig. 6. In the multiplier implementation, the
circuit of Fig. 9 based on the Sackinger current mirror
was employed. Two separate but identical current am-
plifiers based on the CCII circuit of Fig. 11 were used
in the final amplifier stage.
Fig. 12. DC response of multiplier based on Sackinger current mirror.
169
A reference current of 50 µA was chosen for the cur-
rent division network. The Rx and Ry values of the cur-
rent amplifier were chosen to be 1 k and 25 k respec-
tively. The VGA was simulated using Cadence Spectre
with BSIMv3 models. Figure 12 shows the simulated
DC response of the multiplier. The static power con-
sumption of the VGA was found to be less than 5 mW.
6. Experimental Results
A photograph of the prototype chip is given in Fig. 13.
A pair of external resistors of 100 k were used to gen-
erate the input differential current signal required for
the circuit. The reference current for the current divi-
sion network was generated using an external resistor
of 30 k. The output current signals were converted to
a voltage signal using two external resistors of 10 k
each. No internal or external buffers were used in inter-
facing the circuit with the probes and test equipment. As
a result, the circuit drives an estimated load capacitance
of more than 60 pF. The measured AC response of the
circuit for different gain settings is shown in Fig. 14.
170 Ravindran et al.

Fig. 13. A photograph of the prototype chip.

Fig. 14. Measured AC response for selected gain steps.

 A Differential CMOS Current-Mode Variable Gain Amplifier 171

As seen from Fig. 14, the VGA shows a dynamic range
of 28 dB with a 3 dB bandwidth of 5 MHz. The step
response of the circuit at maximum gain setting for an
input step of a 10 kHz fundamental frequency is shown
in Fig. 15. In order to measure the DC response of the
circuit, a semiconductor parameter analyzer was em-
ployed. Since this instrument is capable of generating
and monitoring current signals directly the external re-
sistors mentioned above were not used. The measured
dc response of the circuit is shown in Fig. 16.

Fig. 15. Output response for a 100 kHz step input. Vertical scale is 100 mV/div.

Fig. 16. Measured DC response.

172 Ravindran et al.
7. Conclusions
The paper presents a novel current-mode CMOS VGA
with a dB-linear gain control. The use of current-
mode signal processing enables low voltage opera-
tion. Different circuit implementations of the various
blocks are described for different design specifications.
A brief estimation of the dominant poles and noise
contributions for the chosen circuit implementation
have also been included. A prototype circuit was fab-
ricated and tested in order to experimentally verify the
technique.
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22. H.O. Elwan and A.M. Soliman, “Low-voltage, low-power
CMOS current conveyors.” IEEE Transactions on Circuits and
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23. H.A. Alzaher, H.O. Elwan, and M. Ismail, “CMOS fully-
differential second generation current conveyor.” Electronics
Letters, vol. 36, no. 13, June 2000.
Arun Ravindran received the B.Eng. and M.Eng.
degrees from the Birla Institute of Technology and Sci-
ence, Pilani in 1996 and 1997 respectively and M.S. in
Physics from The Ohio State University in 2000. He
is currently a Ph.D. student in the Analog VLSI Lab
at The Ohio State University. His research interests
are in the areas of low voltage design of analog base-
band circuits, data converters and wireless transceiver
architectures.
 A Differential CMOS Current-Mode Variable Gain Amplifier
Eva Vidal (S’94, M’99, IEEE) received her
M.S. and Ph.D. degrees (both with honors) in electrical
and electronics engineering (master in Telecommuni-
cations) from the Universitat Politècnica de Catalunya
in Barcelona, Spain, in 1993 and 1998, respec-
tively. During the period 1993–1994 she was an As-
sistant Professor at the Department of Electronics
Engineering of the Universitat Rovira i Virgili of
Tarragona. From 1994 to 1998 she was an Assistant
Professor at the Department of Electronics Engineer-
ing of the Telecommunication Engineering School of
Barcelona, where she became full-time Associate Pro-
fessor in December 1998. She was a visiting scholar
with the Analog VLSI Lab at the Ohio State Uni-
versity’s Electrical Engineering Department in 2001.
She has participated in five Spanish national research
projects. Her research focuses in the area of ana-
log circuit design with emphasis in analog microelec-
tronics and particular interest in current-mode design,
automating tuning design, analog baseband circuits,
wireless transceiver architectures and nonlinear anal-
ysis of oscillators. She has authored or co-authored
about forty scientific papers in journals and conference
proceedings.
Seoung-Jae Yoo was born in Seoul, Korea, on March
6, 1971. He received the B.Sc. and M.Sc degrees from
the Ohio State University, Ohio, USA, in 1998 and
2000, where he is currently working toward the Ph.D.
degree. His research is focused on the low voltage
CMOS analog circuits.
173
Kishore Rama Rao was born in Chennai, India,
in 1974. He received the B.E. degree in electronics
and communication engineering from Anna University,
India in 1995 and the M.S. degree in electrical engi-
neering from the Ohio State University at Columbus,
OH in 1998, where he is currently pursing the Ph.D.
degree in the area of radio frequency integrated circuits
for telecommunication. His current research interests
include design and analysis of RF transceiver blocks in
CMOS and communication system architectures.
Mohammed Ismail (S’80-M’82-SM’84-F’97) re-
ceived the B.S. and M.S. degrees in electronics and
telecommunications engineering from Cairo Univer-
sity in 1974 and 1978, and the Ph.D. in electrical engi-
neering from the University of Manitoba in 1983. He is
a professor with the Department of Electrical Engineer-
ing, The Ohio State University and is the founder and
director of the Analog VLSI Lab. He has held several
positions previously in both industry and academia and
has served as a corporate consultant to nearly 30 com-
panies in the United States and abroad. He held visiting
appointments at the Norwegian Institute of Technol-
ogy, University of Oslo, University of Twente, Tokyo
Institute of Technology, Helsinki University of Tech-
nology and the Swedish Royal Institute of Technology.
He has authored many publications on VLSI circuit de-
sign and signal processing and has been awarded sev-
eral patents in the area of analog VLSI. He has coedited
and coauthored several books including a text on Ana-
log VLSI Signal and Information Processing, (McGraw
174 Ravindran et al.
Hill, 1994). He advised the work of 24 Ph.D. students,
55 M.S. students, and 25 visiting scholars. His current
interests include low-voltage/low-power VLSI circuits,
RF and mixed signal VLSI circuits for wireless commu-
nications, statistical computer-aided design and opti-
mization, integrated circuits for image, video and mul-
timedia applications and VLSI information processing
systems. He gives intensive courses to industry in these
areas.
Dr. Ismail has been the recipient of several awards in-
cluding the IEEE 1984 Outstanding Teacher Award, the
NSF Presidential Young Investigator Award in 1985,
the OSU Lumley Research Award in 1993, 1997, and
2002, the SRC Inventor Recognition Awards in 1992
and 1993, and a Fulbright/Nokia fellowship Award
in 1995. He is the founder of the International Jour-
nal of Analog Integrated Circuits and Signal Process-
ing and serves as the Journal’s Editor-In-Chief (North
America). He has served the IEEE in many editorial
and administrative capacities, including General Chair
of the 29th Midwest Symposium CAS, member of the
CAS Society Board of Governors, chair of the CAS
Analog Signal Processing Technical Committee, the
Circuits and Systems (CAS) Society’s editor of the
IEEE Circuits and Devices Magazine, founder and co-
editor of The Chip, a column in the magazine, and
associate editor of the IEEE Transactions on Circuits
And Systems, IEEE Transactions on Neural Networks,
IEEE Transactions on VLSI Systems and IEEE Trans-
actions on Multimedia. Dr. Ismail is a Fellow of IEEE.