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2. ANALOG DESIGN METHODOLOGY
The design of analog integrated circuits requires exten-
sive design practice with a given technology to correctly
size transistors in order to achieve the required performance.
Analytical knowledge-based equations describe the relations
between the transistors (design parameters), design spec-
ifications (e.g. slew-rate more than 10V /μs) and design
objectives (such as minimum power, area, noise, etc, or a
combination thereof). These equations are topology-specific
and can be used within an automatic synthesis methodol-
ogy, which must perform the resolution of a system of non-
linear equations. This system usually has more independent
variables than equations, returning a wide solution space.
The search for an optimum design, however, is often made
by extensive simulation practice, by expert heuristics and,
to a much lesser extent, by optimization algorithms. The
simulated annealing (SA) algorithm was implemented as an
option to optimize the design, since it exploits the entire
design space, including different transistor lengths. In most
devices these are kept fixed by the tools or the designer. SA Figure 1: Measured gm/ID x In curve for NMOS
is a well known random-search technique which exploits an 0.35μm CMOS technology.
analogy between the way in which a metal cools and freezes
into a minimum energy crystalline structure (the annealing
process) and the search for a minimum of a cost function in a where αi is the weighting coefficient for performance param-
more general system. It forms the basis of an optimization eter p̂i (X) , which is a normalized function of the vector of
technique for combinatorial and other problems [12]. The independent design parameters X. This function allows the
use of simulated annealing in the synthesis of analog circuits designer to set the relative importance of competing perfor-
was reported in previous works [7]. SA’s major advantage mance parameters, such as, for example, a weighted relation
over other methods is the ability to avoid becoming trapped between power and area. The parameter ĉj (X) is a con-
in local minima in the parameter space. The algorithm em- straint normalized function, which shrinks the design space
ploys a random search which does not only accept solutions to feasible solutions of design specifications. The coefficient
that decrease the objective cost function fc (assuming a βj indicates how closely the specification must be pursued.
minimization problem), but also some changes that increase If ĉj (X) is inside a given specification, it is set to zero. The
it. In the design procedure herein proposed, a methodology correct design space exploration is directly related to the
called gm/ID is used for the circuit performance evaluation. cost function formulation [4]. Figure 2 shows the proposed
This methodology considers the relationship between the ra- design flow. The user enters the design specifications, tech-
tio of the transconductance gm over DC drain current ID nology parameters and configures the cost function accord-
and the normalized drain current In = ID /(W/L) as a fun- ing to the required design objectives and specifications. The
damental design parameter [13], such as the measured curve optimization loop performs a random perturbation on the
shown in figure 1. The gm/ID characteristic is directly re- design variables, whose amplitude is defined by the ”tem-
lated to the performance of the transistors, gives a clear in- perature”. These variables are defined by the user, and are
dication of the device operation region and provides a way always related to the transistor geometry, large and small-
for straightforward estimation of transistors dimensions. signal parameters, such as W , L, ID , gm and gm/ID . Fol-
The main advantage of this method is that the gm/ID lowing, the design properties evaluation is performed by the
x In curve is unique for a given technology, reducing the calculation of the circuit characteristics such as gain, cut-
number of electrical parameters related to the fabrication off frequency, phase margin, power, common-mode range,
process. Additionally, its analytical form covers all tran- etc. This is done using circuit-specific analytical equations,
sistor operation regimes, from weak to moderate to strong the gm/ID versus In curve and the ACM model for calcula-
inversion. In the LIT tool, the gm/ID x In curve is auto- tion of transconductances, drain-source saturation voltages
matically evaluated by electrical simulation using the ACM and currents. If the circuit is feasible, i.e., transistor sizes
compact MOSFET model [3], which is also implemented in are within an allowed range, the cost function can be eval-
the commercial simulator SMASH. An automatic parameter uated and the solution is accepted if the cost decreased or
conversion procedure from BSIM3 to ACM is reported [2], else if the cost increased with a given probability to avoid
warranting the compatibility with most technology kits pro- trapping in a local minima. The final solution returns the
vided by silicon foundries. The analog circuit modeling for devices dimensions. The entire automatic optimization flow
simulated annealing is straightforward. The design objec- is implemented in the LIT tool. The tool returns a spice-
tive, or its cost function, has to be formulated appropriately like description of the sized circuit and the evaluated perfor-
and then minimized. In this work we propose and use the mance. External electrical simulations are then evaluated at
following cost function: this stage, in order to verify the solution integrity. The phys-
ical synthesis can also be performed in the LIT tool, which
X
n X
m generates the layout according to specific criteria of tran-
fc = αi p̂i (X) + βj ĉj (X) (1) sistor pair matching, transistor folding/splitting, and even
i=1 j=1 more complex associations of transistors.
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Figure 3: Schematics of a two-stage operational am-
plifier
Figure 2: Proposed design flow
where In1 is the normalized current given by the gm/ID
3. DESIGN EXAMPLE: MILLER AMPLIFIER x In curve. The same approach is done for the remaining
transistors. For example, the size of the transistors in the
The proposed algorithm and design methodology were im-
current mirror load is:
plemented and applied to the synthesis of a two-stage oper-
ational amplifier, shown in figure 3. This amplifier is com- “W ”
posed by an input differential pair with active load in the ID1
= (7)
first stage, an inverter amplifier in the second stage, and L 3 In3
a compensation capacitor for stability, connecting nodes 4
“W ”
and 5 between first and 2nd stages. The analytical equations
W3 = · L3 (8)
that describe the behavior of this circuit are well-known [1]. L 3
In this example, we want to size the transistors in order to The design characteristics calculation is straightforward.
achieve the design specifications given in Table 1. The de- The low-frequency gain, for example, is given by
sign objective (fc ) is to minimize the relative area and total
DC current, and to maximize the low-frequency gain Av , in “ gm ” “ gm ”
the following way: Av = · (V A1 + V A3 ) · · (V A5 + V A6 ) (9)
ID 1 ID 5
A IDD Av0 Our LIT tool implements the ACM model source code and
fc = + + (2) can estimate the Early voltage (V A) according to the tran-
A0 IDD0 Av
sistor length. In this example, the technology used is CMOS
Here, A is the silicon area occupied by all transistors, in- 0.35μm, the power supply voltage is ±1.65V and the load
cluding drain and source regions (estimated), A0 is a refer- capacitance is 10pF . The independent variables subjected
ence area for normalization, IDD is the total supply current to perturbations by the simulated annealing algorithm are:
and Av is the low-frequency gain. The gate transconduc- L1 = L2 , L3 = L4 , L5 , L6 , L7 = L8 , (gm/ID )1 = (gm/ID )2 ,
tance of the input differential pair is set by the GBW and (gm/ID )3 = (gm/ID )4 , (gm/ID )5 , (gm/ID )6 , (gm/ID )7 ,
Miller cap, as: and the dependent parameters are W1 = W2 , W3 = W4 ,
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implemented in the LIT tool and provides a reasonable solu-
tion in a short CPU time. The main advantage is the simple
sizing method based on the transistor inversion coefficient,
which is calculated by a single technology-specific charac-
teristic curve gm/ID versus In . The design space is not
limited to strong inversion region, but also to moderate and
weak inversion, allowing low-power optimum design. Com-
paring with a typical human-made design procedure, the
advantages of using an automated design methodology are
the reduced design time, better performance and the possi-
bility of even non-expert analog designers to achieve good
solutions for non-critical applications.
5. REFERENCES
[1] P. E. Allen and D. R. Holberg. CMOS Analog Circuit
Design. Oxford University Press, Oxford, second
edition, 2002.
[2] R. M. Coitinho, L. H. Spiller, M. C. Schneider, and
Figure 4: Cost function evolution C. Galup-Montoro. A simplified methodology for the
extraction of acm most model parameters. In 14th
Table 2: Transistors sizes obtained by the optimiza- Symposium on Integrated Circuits and Systems Design,
tion method for the Miller amplifier pages 136–141, Brası́lia, Brazil, September 2001.
Transistor L(μm) W (μm) gm/ID (V −1 ) [3] A. I. A. Cunha, M. C. Schneider, and
M1 , M2 1.2 74.8 16.5 C. Galup-Montoro. An MOS transistor model for
M3 , M4 6.6 15 4.7 analog circuit design. IEEE Journal of Solid-State
M5 0.6 147 15.7 Circuits, 33(10):1510–1519, October 1998.
M6 6 10.7 0.7 [4] B. de Smedt and G. G. E. Gielen. Watson: Design
M7 , M8 0.8 5.5 3.1 space boundary exploration and model generation for
analog and rf ic design. IEEE Transactions on
Computer-Aided Design of Integrated Circuits and
W5 , W6 , W7 = W8 , Cf and bias current. The constraints Systems, 22(2):213–224, Feb 2003.
L ≥ Lmin , W ≥ Wmin and (gm/ID )min ≤ (gm/ID ) ≤ [5] M. Degrauwe, O. Nys, E. Dukstra, J. Rijmenants,
(gm/ID )max avoid infeasible solutions, with Lmin = 0.3μm, S. Bitz, B. L. A. G. Goffart, E. A. Vittoz, S. Cserveny,
Wmin = 0.6μm, (gm/ID )min = 0.1 and (gm/ID )max = 25 C. Meixenberger, G. V. der Stappen, and H. J. Oguey.
in our technology. The range of gm/ID is well known from IDAC: An interactive design tool for analog CMOS
device physics and behaves smoothly over a wide range of circuits. IEEE Journal of Solid-State Circuits,
transistor biases, which is advantageous for the search ro- SC-22(6):1106–1116, December 1987.
bustness. Moreover, the design space is limited by values [6] F. El-Turky and E. E. Perry. BLADES: An artificial
of gm/ID less than about 28V −1 , which is the theoretical intelligence approach to analog circuit design. IEEE
maximum gm/ID of bulk MOS transistors. Design objec- Transactions on Computer-Aided Design,
tives and design specifications are evaluated in terms of free 8(6):680–692, June 1989.
variables (gm/ID )i and Li . The same occurs with the de- [7] G. E. Gielen, H. C. C. Walscharts, and W. M. C.
pendent variables such as Wi and IDi . The optimization Sansen. Analog circuit design optimization based on
process for the example took 158 iterations and mere 91 symbolic simulation and simulated annealing. IEEE
million floating point operations. The final transistors sizes Journal of Solid-State Circ., 25(3):707–713, June 1990.
obtained by the iterations with the analytical models are [8] G. G. E. Gielen, H. C. C. Walscharts, and W. M. C.
shown in table 2. The third column of table 1 shows the Sansen. ISAAC: A symbolic simulator for analog
performance of the optimized solution obtained by electri- integrated circuits. IEEE Journal of Solid-State
cal simulations of the sized circuit with SMASH. Figure 4 Circuits, 24(6):1587–1597, December 1989.
shows the evolution of the cost function after each iteration, [9] A. Girardi and S. Bampi. Lit - an automatic layout
converging to a minimum value, reaching stability as the generation tool for trapezoidal association of
cool-down proceeds. transistors for basic analog building blocks. In
Proceedings of the Design Automation and Test in
4. CONCLUSION Europe, March 2003.
The proposed methodology combines the SA algorithm, [10] R. Harjani, R. A. Rutenbar, and L. R. Carley. OASYS:
the gm/ID characteristics and the ACM MOSFET model A framework for analog circuit synthesis. IEEE
in the same environment in order to optimize the design of Transactions on Computer Aided Design, 8(12), 1989.
analog circuits based on the transistor inversion coefficient. [11] M. D. M. Hershenson, S. P. Boyd, and T. H. Lee.
The main advantage of using the SA over the crude gm/ID Optimal design of a CMOS op-amp via geometric
technique is that the design space is explored in a more effec- programming. IEEE Trans. on Computer-Aided
tive way, combining operation in weak and strong inversion Design of Integrated Circuits and Systems, 20(1):1–21,
to achieve optimum low-power design. The methodology is January 2001.
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[12] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. [13] F. Silveira, D. Flandre, and P. G. A. Jespers. A
Optimization by simulated annealing. Science, gm/ID based methodology for the design of CMOS
220(4598):671–680, May 1983. analog circuits and its application to the synthesis of a
silicon-on-insulator micropower OTA. IEEE Journal of
Solid-State Circuits, 31(9):1314–1319, September 1996.
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