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Power Constrained Design Optimization of Analog Circuits

Based on Physical gm/ID Characteristics

Alessandro Girardi and Sergio Bampi


Federal University of Rio Grande do Sul - UFRGS
PGMICRO, Informatics Institute
Caixa Postal 15.064 - Zip 91.501-970
Porto Alegre-RS, Brazil
{girardi, bampi}@inf.ufrgs.br

ABSTRACT tives (multiple and complex performance specifications to be


This paper presents a transistor optimization methodology met, like bandwidth, gain, power, maximum offset voltage,
for low-power analog integrated CMOS circuits, relying on power supply rejection ratio, etc.) and the large number of
the physics-based gm/ID characteristics as a design opti- design variables (transistor sizes and bias currents) to be set.
mization guide. Our custom layout tool LIT implements Previous work has been done in the field of analog design
and uses the ACM MOS compact model in the optimiza- automation to enable fast design at the block level. Different
tion loop. The methodology is implemented for automation strategies and approaches have been used, such as symbolic
within LIT and exploits all design space through the sim- simulation [8], artificial intelligence [6], manually derived de-
ulated annealing optimization process, providing solutions sign equations [5], hierarchy and topology selection [10] and
close to optimum with a single technology-dependent curve geometric programming [11]. The main difficulty encoun-
and accurate expressions for transconductance and current tered for widespread use of these tools is that they require
valid in all operation regions. The compact model itself appropriate modeling of both the devices (technology de-
contributes to convergence and to optimized implementa- pendence) and of the circuit in order to achieve the design
tions, since it has analytic expressions which are continuous objectives in a reasonable processing time. The choice of the
in all current regimes, including weak and moderate inver- different circuit topologies to support in a method or tool is
sion. The advantage of constraining the optimization within also a problem, since most approaches work with topology-
a power budget is of great importance for low-power CMOS. based equations, which limits the application range. The
As examples we show the optimization results obtained with addition of new block topologies has to be supported, and
LIT, resulting in significant power savings, for the design of requires again expert analog designer knowledge. The use
a two-stage Miller operational amplifier. of optimization algorithms combined with physical models
seems to be a good solution when applied to specific appli-
cations, since a general solution most often proves to have
Categories and Subject Descriptors shortcomings for fully exploiting the capabilities of the ana-
B.7.1 [Integrated Circuits]: Types and Design Styles; log CMOS technology. The main requirements of an analog
B.7.2 [Integrated Circuits]: Design Aids—Layout, Sim- synthesis tool are: user interactivity, flexibility for multi-
ulation ple topologies, connection to automatic layout generation,
and reasonable response time. The interface with an elec-
General Terms trical simulator is also convenient. This paper describes a
methodology for analog design automation that combines
Performance, Design, Reliability the simulated annealing optimization technique, a physics-
based transconductance-to-current ratio characteristics and
Keywords the electrical simulation integrated in the LIT layout gen-
simulated annealing, analog design, synthesis eration tool [9], providing even to a non-expert user a very
flexible tool that is able to size analog circuits, including
a broad range of analog constraints, including total power
1. INTRODUCTION dissipation. The paper is organized as follows: Section 2
The design of CMOS analog integrated circuits is demand- describes the proposed methodology and explains how the
ing due to the complex relations between the design objec- simulated annealing algorithm, the gm/ID characteristics
and the ACM MOSFET model are used to search optimized
designs; Section 3 shows the synthesis of a two-stage Miller
operational amplifier, in order to demonstrate the capabil-
Permission to make digital or hard copies of all or part of this work for ities of the methodology; finally, Section 4 summarizes the
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies main contributions.
bear this notice and the full citation on the first page. To copy otherwise, to
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permission and/or a fee.
SBCCI’06, August 28–September 1, 2006, Minas Gerais, Brazil.
Copyright 2006 ACM 1-59593-479-0/06/0008 ...$5.00.

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2. ANALOG DESIGN METHODOLOGY
The design of analog integrated circuits requires exten-
sive design practice with a given technology to correctly
size transistors in order to achieve the required performance.
Analytical knowledge-based equations describe the relations
between the transistors (design parameters), design spec-
ifications (e.g. slew-rate more than 10V /μs) and design
objectives (such as minimum power, area, noise, etc, or a
combination thereof). These equations are topology-specific
and can be used within an automatic synthesis methodol-
ogy, which must perform the resolution of a system of non-
linear equations. This system usually has more independent
variables than equations, returning a wide solution space.
The search for an optimum design, however, is often made
by extensive simulation practice, by expert heuristics and,
to a much lesser extent, by optimization algorithms. The
simulated annealing (SA) algorithm was implemented as an
option to optimize the design, since it exploits the entire
design space, including different transistor lengths. In most
devices these are kept fixed by the tools or the designer. SA Figure 1: Measured gm/ID x In curve for NMOS
is a well known random-search technique which exploits an 0.35μm CMOS technology.
analogy between the way in which a metal cools and freezes
into a minimum energy crystalline structure (the annealing
process) and the search for a minimum of a cost function in a where αi is the weighting coefficient for performance param-
more general system. It forms the basis of an optimization eter p̂i (X) , which is a normalized function of the vector of
technique for combinatorial and other problems [12]. The independent design parameters X. This function allows the
use of simulated annealing in the synthesis of analog circuits designer to set the relative importance of competing perfor-
was reported in previous works [7]. SA’s major advantage mance parameters, such as, for example, a weighted relation
over other methods is the ability to avoid becoming trapped between power and area. The parameter ĉj (X) is a con-
in local minima in the parameter space. The algorithm em- straint normalized function, which shrinks the design space
ploys a random search which does not only accept solutions to feasible solutions of design specifications. The coefficient
that decrease the objective cost function fc (assuming a βj indicates how closely the specification must be pursued.
minimization problem), but also some changes that increase If ĉj (X) is inside a given specification, it is set to zero. The
it. In the design procedure herein proposed, a methodology correct design space exploration is directly related to the
called gm/ID is used for the circuit performance evaluation. cost function formulation [4]. Figure 2 shows the proposed
This methodology considers the relationship between the ra- design flow. The user enters the design specifications, tech-
tio of the transconductance gm over DC drain current ID nology parameters and configures the cost function accord-
and the normalized drain current In = ID /(W/L) as a fun- ing to the required design objectives and specifications. The
damental design parameter [13], such as the measured curve optimization loop performs a random perturbation on the
shown in figure 1. The gm/ID characteristic is directly re- design variables, whose amplitude is defined by the ”tem-
lated to the performance of the transistors, gives a clear in- perature”. These variables are defined by the user, and are
dication of the device operation region and provides a way always related to the transistor geometry, large and small-
for straightforward estimation of transistors dimensions. signal parameters, such as W , L, ID , gm and gm/ID . Fol-
The main advantage of this method is that the gm/ID lowing, the design properties evaluation is performed by the
x In curve is unique for a given technology, reducing the calculation of the circuit characteristics such as gain, cut-
number of electrical parameters related to the fabrication off frequency, phase margin, power, common-mode range,
process. Additionally, its analytical form covers all tran- etc. This is done using circuit-specific analytical equations,
sistor operation regimes, from weak to moderate to strong the gm/ID versus In curve and the ACM model for calcula-
inversion. In the LIT tool, the gm/ID x In curve is auto- tion of transconductances, drain-source saturation voltages
matically evaluated by electrical simulation using the ACM and currents. If the circuit is feasible, i.e., transistor sizes
compact MOSFET model [3], which is also implemented in are within an allowed range, the cost function can be eval-
the commercial simulator SMASH. An automatic parameter uated and the solution is accepted if the cost decreased or
conversion procedure from BSIM3 to ACM is reported [2], else if the cost increased with a given probability to avoid
warranting the compatibility with most technology kits pro- trapping in a local minima. The final solution returns the
vided by silicon foundries. The analog circuit modeling for devices dimensions. The entire automatic optimization flow
simulated annealing is straightforward. The design objec- is implemented in the LIT tool. The tool returns a spice-
tive, or its cost function, has to be formulated appropriately like description of the sized circuit and the evaluated perfor-
and then minimized. In this work we propose and use the mance. External electrical simulations are then evaluated at
following cost function: this stage, in order to verify the solution integrity. The phys-
ical synthesis can also be performed in the LIT tool, which
X
n X
m generates the layout according to specific criteria of tran-
fc = αi p̂i (X) + βj ĉj (X) (1) sistor pair matching, transistor folding/splitting, and even
i=1 j=1 more complex associations of transistors.

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Figure 3: Schematics of a two-stage operational am-
plifier
Figure 2: Proposed design flow
where In1 is the normalized current given by the gm/ID
3. DESIGN EXAMPLE: MILLER AMPLIFIER x In curve. The same approach is done for the remaining
transistors. For example, the size of the transistors in the
The proposed algorithm and design methodology were im-
current mirror load is:
plemented and applied to the synthesis of a two-stage oper-
ational amplifier, shown in figure 3. This amplifier is com- “W ”
posed by an input differential pair with active load in the ID1
= (7)
first stage, an inverter amplifier in the second stage, and L 3 In3
a compensation capacitor for stability, connecting nodes 4
“W ”
and 5 between first and 2nd stages. The analytical equations
W3 = · L3 (8)
that describe the behavior of this circuit are well-known [1]. L 3
In this example, we want to size the transistors in order to The design characteristics calculation is straightforward.
achieve the design specifications given in Table 1. The de- The low-frequency gain, for example, is given by
sign objective (fc ) is to minimize the relative area and total
DC current, and to maximize the low-frequency gain Av , in “ gm ” “ gm ”
the following way: Av = · (V A1 + V A3 ) · · (V A5 + V A6 ) (9)
ID 1 ID 5

A IDD Av0 Our LIT tool implements the ACM model source code and
fc = + + (2) can estimate the Early voltage (V A) according to the tran-
A0 IDD0 Av
sistor length. In this example, the technology used is CMOS
Here, A is the silicon area occupied by all transistors, in- 0.35μm, the power supply voltage is ±1.65V and the load
cluding drain and source regions (estimated), A0 is a refer- capacitance is 10pF . The independent variables subjected
ence area for normalization, IDD is the total supply current to perturbations by the simulated annealing algorithm are:
and Av is the low-frequency gain. The gate transconduc- L1 = L2 , L3 = L4 , L5 , L6 , L7 = L8 , (gm/ID )1 = (gm/ID )2 ,
tance of the input differential pair is set by the GBW and (gm/ID )3 = (gm/ID )4 , (gm/ID )5 , (gm/ID )6 , (gm/ID )7 ,
Miller cap, as: and the dependent parameters are W1 = W2 , W3 = W4 ,

gm1 = GBW · Cf (3)


The drain current for these transistors can be calculated Table 1: Specifications and simulated results for the
with the information about the transconductance-to-current Two-Stage Amplifier
ratio, which is an independent variable: Specification Required Simulated
Total current (μA) ≤ 200 102
gm1 Phase margin (◦ ) ≥ 60
ID1 = “ ” (4) 60
gm
ID
Low-frequency gain (dB) ≥ 90 95
1 GBW (M Hz) ≥ 15 15
So, the aspect ratio for the input transistors is: Slew-rate (V /μs) ≥ 15 15
“W ” ICMR− (V ) ≤ −1 -0.8
=
ID1
(5) ICMR+ (V ) ≥1 1.4
L 1 In1 Total area (μm2 ) minimize 9064
“W ” Offset (μV ) ≤ 200 160
W1 = · L1 (6) Cost function minimize 1.62
L 1

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implemented in the LIT tool and provides a reasonable solu-
tion in a short CPU time. The main advantage is the simple
sizing method based on the transistor inversion coefficient,
which is calculated by a single technology-specific charac-
teristic curve gm/ID versus In . The design space is not
limited to strong inversion region, but also to moderate and
weak inversion, allowing low-power optimum design. Com-
paring with a typical human-made design procedure, the
advantages of using an automated design methodology are
the reduced design time, better performance and the possi-
bility of even non-expert analog designers to achieve good
solutions for non-critical applications.

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