A CMOS Variable Gain Amplifier with Wide

Dynamic Range and Accurate dB-Linear

Characteristic
Ji-Hun Kim, Chang-Seok Chae, Young-Jin Woo, and Gyu-Hyeong Cho
Division of Electrical Engineering Department of Electrical Engineering & Computer Science
Korea Advanced Institute of Science and Technology
373-1 Guseong-dong, Yuseong-gu, Daejeon 305-701. Republic of Korea
Tel:+82-42-869-5424, Fax:+82-42-869-8024
E-mail: klcallgkaist.ac.kr

Abstract -A novel CMOS variable gain amplifier (VGA) with realize an exponential or logarithmic function because the
high frequency, wide dynamic range and accurate dB-linear gain normal operation of MOS transistor is the square law transfer
control for WCDMA Direct-Conversion Receiver is proposed. characteristic. However, it is easily obtained in bipolar
To achieve conflicting performances such as high linearity and technology. Unfortunately, the bipolar process for VGA and
wide dynamic range with constraints of low power dissipation, it AGC are not compatible for monolithic low voltage
is necessary for VGA to have an accurate gain control
characteristic and a wideband gain cell (VGA cell) with high gain
at low voltage. Therefore, a new VGA cell is proposed to achieve
cM se anal nd me signaleciBG.
.
process solution may not be cost effective.
both high dynamic range and wideband at low supply voltage. The trend towards fully integrated wireless transceivers for
Wideband operation is also achieved using novel active load with low power consumption makes it desirable to realize low
gain boosting. In a proposed exponential voltage function voltage VGA in CMOS technology. Specifications for the
generator using parasitic bipolar transistor, it is possible to linearity of the VGA are generally very tight in order to
compensate some deviation of its slope against temperature and maintain good overall system linearity.
process variations. This paper describes a novel VGA that exploits variable
The VGA has a controllable gain range of-20dB-55dB which triode bias technique to achieve high linearity and wide
can be controlled by adjusting the external control voltage and bandwidth simultaneously with very low power supply
enhanced operating frequency range up to 150 Elllz.
voltage and accurate dB linear control using parasitic bipolar
Keywords - linear-in-dB, temperature compensation, transistor in CMOS process. Section 2 describes the VGA
automatic gain control (AGC), parasitic BJT, variable Architecture. Section 3 describes the circuit implementation of
amplifiger (VGA). the proposed VGA. Simulation results are reported in section 4
and conclusion is given in section 5.
1. Introduction 2. VGA Architecture
Variable gain amplifier (VGA) is an indispensable key ----------------------
building block in many applications, such as disk drives [1], canceller
hearing aids [2], and wireless communication systems [3], in Amp ;
order to maximize the dynamic range of the overall system. In
wireless communication receiver, VGA is typically employed , +=-==-================-_-_--
in a feedback loop to realize an automatic gain control (AGC), vV+ . + VGA
to provide constant signal power to baseband analog-to-digital cel - cel vc_
converter (ADC) for unpredictable received signal strengths. -Gain stage
Since a close-loop operation is used in the AGC circuit, -
stability and settling time must be considered. In AGC loop, ---------------'I Vc_int
to maintain its settling time independent of the input signal LL.
levels and a large dynamic control range, exponential gain AD-
control characteristic is required [4]. kExjyVenerator_-__--, -

Therefore, how to make a VGA with a linear in dB -- --

characteristic has become a research topic, especially in V:GclV I
CMOS technology. As for CMOS VGAs, it is difficult to lVcex GA -S A
linea
dB
/
tGalin Controller _
ref ________

The work is supported by C&S Lab, funded by IT-SoC of KIPA(Korea

Invention Promotion Association) Figure 1. Block diagram of proposed VGA

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 This paper proposes a novel circuit scheme for achieving VC intl of NMOS transistor (M7, M8) goes up, the gain is
accurate dB-linear gain control, wide bandwidth and wide
dynamic~~ ~~~~.
dynamic range using CMOS ragusntechnology.m
MStehooy ncreased. On the contrary, when gate voltage Vc t2 of inner
in,

A block diagram of the proposed VGA with a
voltage-controlled exponential gain characteristic is shown in
Figure 1. It comprises exponential function voltage generator
with temperature compensation and wide dB-linear range, a
dB-linear gain controller for accurate dB-linear gain control
and a gain stage block with DC offset canceller. Next section
describes the circuit implementation of the proposed VGA
3. Circuit Implementation
3.1 VGA cell
The gain stage is composed of two VGA cells which are
cascaded to obtain wide dynamic range. The each VGA cell is
controlled by internal control voltage which is made by means
of dB-linear gain controller to have linear gain characteristic in
decibel domain.
MOS transistor (M5, M6) goes up, the gain is decreased. In the
VGA cell, an inverting amplifier is used to make properly
amplitude of control voltage because VC intl and VC_i.t2
should inversely operate. Namely, inner NMOS transistor (M5,
M6) play an important role to increase the dynamic range of
gain.
It is difficult for a VGA cell with simple resistor load to
operate with comparable performance at low voltage since
there is no more headroom for output voltage swing. Therefore,
a new active load scheme is exploited as output load instead of
a resistive load for wideband characteristic and sufficient gain
in low voltage applications. Figure 3. shows equivalent circuit
of active load and output impedance ZO according to
operating frequency region.
V
,
Mp I

V_DI Zo" i DuetoL-eff Due to Cp

I c I c I I vR2 1
mg mg Cc RI CRIIJ? g

RI Rl
i ~~~~~~~~~~~~~~~~~Leff(in highferquency Y9.~~~~~~~~~~~~
C,[ HR21w
|R+D/1
-C VoLlt + VoutE _______________Vmu_
__,---------------- __ -- a) Equivalent circuit b) Output impedance
DE>-4-
Vc_i [Itt I
M7
Il
M8 k" R4
Figure 3. Active load with gain boosting in high frequency

Cascode M Active load in this VGA cell is obtained by combining two

Input Stage
+ E: M1 M2
Vbias
Figure 2. Proposed VGA cell
A new VGA cell is proposed as shown in Figure 2. It has
several features; cascode differential structure for low
distortion and wideband, input stage MOS biased in triode
region for good linearity and high dynamic range [8], active
load for wideband and low supply voltage operation.
The VGA cell utilizes a differential pair of the cascode
amplifiers, as shown in Figure 2. This suppresses even
harmonics, rejects common-mode noises and doubles the
signal swing for a given supply voltage. The differential
cascode configuration can extend the bandwidth due to
reduction of Miller effect and suppress the signal distortion.
To increase linearity, the NMOS transistors (MIVM4) of
input stage are operated in the triode region. A variable gain
can be achieved by controlling the gate voltage ( Vc
,1V int
C transistors, two resistors, a current source and a capacitor. In
; ; ref this Figure 3, NMOS transistors M10 play a role for this circuit
: lto be in low supply voltage operation and in stable DC
operation with negative feedback. In the low frequency region,
the out impedance of this circuit can roughly be about a
reciprocal of transconductance of PMOS transistors M9 in
saturation region. So, if we want to get higher voltage gain, we
have to decrease the value of l/gm Mp by tuning the value of
RI and R2. In this circuit, another key point to improve
frequency characteristic as a wideband operation is for active
load to have characteristic of inductance. It is possible to
control the -3dB frequency by tuning boost capacitor Cc. With
large output impedance of MOS transistor instead of using
resistor load, high gain and wide bandwidth are sufficiently
achieved.
Theoutputimpedance Z0ofVGAcellwiththisactiveload
circuit in low operation frequency region is expressed by
following (1).
RO RO R )1
at DC
Z
Z R IR (1)
-

intlU R
Vcint2 ) of transistor M7, M8 and M5, M6 because
trans-conductance of MOS biased in the triode region is At high frequency region near the -3dB frequency of the
changed according to drain-source voltage VDS . If the inner gain, the output impedance of VGA cell can be approximated
MOS transistor (M5, M6) do not exist, when gate voltage a

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 process is used. It can achieve very high dB output voltage
Z at high frequency range. Figure 4. shows exponential function voltage generator
(+ R2Lg [ r1 + circuit with parasitic bipolar transistor for dB-linear gain
C1
C,
R2L] n S+ +() 2 control.
9p4n C, 1, ~~~~l/gn + R2

where gn and gp is each trans-conductance of NMOS and

PMOS and S = jw . In the negative feedback consisted of M9 R3 + A -R2
and M10, loop gain is expressed by following (3). A4 +

Loop Gain 4X , -X ITEMP RI Exp V IREF

(~V-)%+S SCRI)~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ .3
~~ ~~~~~~g
,)SI A, A \N
~~ ~ S+~~7~1gj+R2j~~~+kJ A~3 M4 ILoop i1
(
+ R2) _
A
M

Output impedance is increased due to the effect of feedback Q3 Q1 Q2

loop in the high frequency region, is decreased due to effect of 16X A X
parasitic capacitance Cp in the further high frequency. The
zero frequency where gain is increased by inductance Figure 4. Exponential function voltage generator
characteristic is expressed by (4) because the pole of feedback
loop is to be zero in the frequency response of output The control voltage V, is scaled and inverted for a proper
impedance. polarity and amplitude by control voltage scaler. This scaled
voltage is applied to the emitter of QI that is parasitic BJT in
1 + (4) CMOS transistor because Al play a roll as a buffer. The
z Cc 11g" + R2 JR ' ' Emitter current of Q I can be generated using relation between
emitter current IE and base-emitter voltage VBE of bipolar
It shows that this active load effectively acts like an transistor Ql. The current from BJT are converted to output
inductive load in the high frequency region. The effective exponential voltage through the output resistor RI.
inductance Leff of the active load forms a parallel resonance
circuit associated with parasitic capacitance Cp at the output IE = IS * exp VBE (6)
node. The resonant frequency wi0 of equivalent L-C resonance VT
circuit with Q can be expressed by following (5)
Equation (6) shows emitter current Where Is is the
w= 1/ ECp saturation current, VT(= KT/q) is thermal voltage. These
(5)
parameters are affected by the absolute temperature T
Thus, by adjusting the size of capacitor Cc, it is possible to Therefore some variations such as temperature or process
deviation can cause a poor performance of exponential
exostend -3dB togharequency boosting thegainthighfequenexponential
frequency somewhathigherfunction voltage. In this circuit, to achieve a temperature stable
function generator, temperature compensation
3.2 Exponential function voltage generator technique adopted based on negative feedback.
is
The feedback loop 1 consisted of Q2, A6, A7 and M2
The exponential function is required to make a VGA with a provides voltage on base of Ql which is compensated for
linear in dB characteristic. Several methods were proposed to temperature change. Another compensation technique is
provide solutions for a linear-in-dB VGA in CMOS implemented by means of feedback loop 2.
tecnolgy.The ex onential function for control voltage1is In this proposed controlofvoltage it. is possible
implemented bye
technology, exponential
by using function
a "pseudo for control
exponential" voloage[5] compensate
generator the deviation its slopescaler,
by adjusting to
the ratio
R4/R3 against temperature variation. Variable resistor R4
or "Taylor series expansion" [6], or "MOS transistor in
sub-threshold region" [7] so as to accomplish the linear-in-dB dpce nfgr .scnitdo w eitr n n O
transistor whose gate voltage iS controlled by output voltage of
characteristic. However, these previously reported approaches A ooeaei roergo.We eprtr scagd
show very small dB-linear output range of less than 20dB. In colco curn of Q4i lee.TeA nteNgtv
this paper to achieve an exponential function according to the febc opsne hne urn n hncnrl h
coto olae aastcbpla rniso tlze nCO gate voltage of MOS in the R4. Namely, the negative feedback

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 loop 2 compensates the output current of exponential function Figure 5. DC offset canceller scheme
voltage generator by adjusting the gain factor R2/R1 (R4/R3) The alternative is to use the DC-coupled stage with a
through A4 according to temperature variation. The output feedback configuration as depicted in figure 5. The circuit of
voltage independent of the process and temperature has the DC offset canceller is shown in Figure 6. It consists of Gm cell
exponential function as represented by and a amplifier which extract DC components from the
outputs of the last VGA. The offset of VGA output is detected
VOep eneraor,and
= K1L]Exp(-K2V') (7) by the Gm cell, and cancelled at the VGA inputs via feedback
is K,is
loop with Gm cell and amplifier. The dc-offset cancellation
where K1 where
gain of generator, and K2
gai of
is voltage scaling
Kisvoltaescaling
scheme is implemented with the very low high-pass cutoff
factor. frequency and a smaller area than required by a simple
This exponential voltage is applied to the inputs of VGA coupling capacitor.
cell which has gain Av and then amplified by VGA cell as
shown in the figure 1. A constant voltage VR is generated by C
an external current source and then subtracted from the output Vi+ Vo+
of VGA cell. Therefore, if VGA gain is Av , then the output of Vi- Gm Vo-
VGA can be expressed as (8)
C
V.
ti, OPA =VO _eAV-VR=Kl.exp(-K2.Vc).AV-VR (8)

This output voltage of VGA cell is amplified by amplifier, and

then the output voltage Vci,_ of the amplifier is fed back to
the control node of the VGA cell. In the steady state, the input iV VOUT+ Vb VOUT-
voltage ViK_OPA of amplifier becomes almost zero due to V2
negative feedback loop. Therefore, the VGA gain can be C C
expressed by (9) M5 M6 M 8

V,,
AV = VR Kl Exp(K2 VC) (9) DE]M1M24l<M4 V
M3 v]
~~~~~~~~~~IN-
V2

Equation (10) shows that the gain of VGA has exponential

function for the control voltage Vc .
Operation of dB-linear gain controller which generates
internal control voltage Vc intl refer to [9]

3.3 DC offset canceller Figure 6. Exponential function voltage generator

Although there are several obstacles in a direct-conversion The offset canceller is tuned for a cutoff frequency of about
transceiver implementation, the DC offset problem is the most 50 KHz, which does not significantly degrade the BER of the
serious one. A small DC offset can be amplifier by the VGA to DCR.
a level what saturates the following stages or may cause the
output signal to be clipped. Thus, active compensation of the 4. Simulation Results
DC offset is an important part of VGA circuit design. In the
proposed VGA, two cascaded gain cells may have DC voltage The proposed VGA with wide dynamic range and accurate
problem due to device mismatch. While the AC-coupling dB-linear gain characteristic was designed and simulated
method may be regarded as an intuitive solution, it requires using Cadence Spectre with process parameter from a
huge capacitor area and accompanies unavoidable in-band Samsung 0.18um CMOS technology. The circuit was
loss. designed to operate with a single 1 .8V power supply voltage.
Figure 7. shows inductance characteristic of active load. Gain
Vill v V<ut Cainii error of exponential function generator within ± of 0.6dB over
0 - A A / temperature variation from -20 to 80 is also achieved. Figure 9.
Vi \8 ,' \shows the simulated AC frequency response of the proposed
\/ \ VGA when varying control voltage. A linear-in-dB gain
. ER
_ R'
_7 _ RC/i \Wp control over a dynamic range of about 75dB (from
-20~±55dB) is achieved via the proposed VGA. The -3dB
- Doffset canceIIation -GClGR - -/ bandwidth of 1 50MHz can be obtained.

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 [2] J. Duque-Carrillo et al., "VERDI: An acoustically programmable and
adjustable CMOS mixed-mode signal processor for hearing aid
applications", IEEE J. Solid-State Circuits, May 1996, vol.31, pp.
634-645.
[3] M. Mostafa, H. Elwan, "A 1 10MHz 70dB CMOS variable gain amplifier",
in Proc. IEEE Int. Symp. Circuits and Systems, May 1999, pp.628-63 1.
[4] John M., Khoury, "On the Design of Constant Settling Time AGC
Gain Boostin effect Circuit" Circuits and Sys. I: Analog and Digital Signal Processing,
IEEE Transactions on, March 1998, vol .45, issue.3,1.
[5] A. Motanemd, C. Hwang and M. Ismail, "CMOS exponential current to
voltage converter", Elect. Letter, June1997, vol.33, no.12, pp.998-1000.
[6] C. Lin, T. Pimenta, M. Ismail, "Universal exponential function
3K X X k.r ffi A. W Mfi k X...... a A ..mm implementation using highly-linear CMOS V-I converters for dB-linear
(AGC) application", Proc.1998, IEEE Midwest Simp. Circuits and Sys.,
1999, pp.360-363
Figure 7. Gain boostinf effect of active load. [7] Takafumi Yamaji, Nobou Kanou, and Tetsuro Itakura, "A Temperature
Stable CMOS Variable Gain Amplifier with 80dB Linearly Controlled
Gain Range", IEEE J. Solid-State Circuit, June 1996, vol. 37, no.6.
ExpI[uA][dB] [8] Kwon, J.K., Kim, K.D., Song, W.C., and Cho, G.H., "Wide high dynamic
range CMOS variable gain amplifier for low voltage and low power
ogo, V t Vc =k V. _13
vu=EW
.J- V= | ,,,Vc =,*kW VSB> .1
}ikg wireless applications", Electron. Lett., 2003, 39,(10),pp.759-760
--------- -fifi;..fi -
[9] Song, W.C., Oh, C.J., CHO, G.H., and Jung, H.B., "High frequency/high
dynamic range CMOS VGA", Electron. Lett., 2000, 36, (13),
---- --- -- ...... .........
pp. 1096-1098.

S ...h p.10 so 6 10 9 0 8.

Figure 8. output current of exponential function enerator for

temperature deviation.

5 7dB ~Vc=1L8V
VcVc Vc

~~Vc c= 5~dB20(((VF("/net0129") VF(/net0 -

50
40A
40

20 ~

20

7 B~c .8'
-20 0.0
-10

-40-2 -OdI3 ~Vc= CV

1K M 1iG 0.0 90 16,

Figure 9. Frequency response of VGA

ISN8-559194 8i135 - Feb 2-22, 206 A020
5. Conclusion
A CMOS VGA with wide dynamic range and accurate
dB-linear gain characteristic is proposed. A new VGA cell for
wide dynamic range, exponential function generator using
parasitic BJT for accurate dB-linear control is proposed. Also,
wideband and low supply voltage operation is achieved
through new active load.

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