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RFIT2007-IEEE International Workshop on Radio-Frequency Integration Technology, Dec. 9-11, 2007, Singapore

A Wideband CMOS Variable Gain Amplifier with a Novel

Linear-in-dB Gain Control Structure
Zhiqun Li, Feng Guo, Dongdong Chen, Haisong Li, Zhigong Wang

(Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China)

Abstract — In this paper, a novel structure of linear-in-dB
gain control is introduced. Based on this structure, a
wideband variable gain amplifier has been designed and
implemented in TSMC 0.18-μm RF CMOS process. On-
chip measured results show a good linear-in-dB gain
control characteristic with 12.8 dB dynamic gain range of
-3.3~9.5 dB. It can operate in the frequency range of 430~
2330 MHz and consumes 16.2 mW at 1.8 V supply. The
noise figure is 6.2 dB at maximum gain and the input P 1dB
at minimum gain is -9 dBm.
Index Terms — VGA, wideband, linear-in-dB, CMOS
I. INTRODUCTION
Among most wireless communication systems, the
intensity of the received RF signal is always unstable.
Therefore, an automatic gain control (AGC) is required.
The variable gain amplifier (VGA) is the main part of
an AGC. It is employed for adjusting the gain of
receiver path to stabilize the intensity of received
signal, so that the received signal can be accurately and
easily processed by the following circuits.
According to the category of gain-control signal,
there are two options in realizing a VGA. One is
digitally controlled. Such a VGA comprises a series of
switched gain stages. It can create digitally
programmable gain and is often called PGA
(programmable gain amplifier). The other is controlled
by an analog signal and has a continuously gain change.
For the most real time processing systems, smooth gain
transitions is required in order to avoid the demodulated
error caused by gain saltation. Consequently, the
implementation of a PGA requires a large number of
capacitors and tight controls on mismatch. The analog
control scheme, on the other hand, efficiently provides a
continuously and monotonic characteristic which is free
from gain saltation. For this reason, analog gain control
was chosen instead of a switched-C implementation.
In practical VGA design, especially in the RF system,
the linear characteristic between logarithmic gain and
control voltage is required or preferred. Traditionally,
bipolar devices are used to implement VGA because of
their exponential voltage-current characteristic.
However, CMOS transistor shows an exponential
relationship between gate voltage and drain current only
when it works in weak inversion region. But
considering its critical requirement to bias circuits and
sensitiveness to the threshold voltage, this methodology
is not practical. Therefore, there is no intrinsic
logarithmic characteristic which can be exploited to
generate the desired linear-in-dB characteristic. An
alternate methodology, being presented here, is to use
the exponential gain control behavior presented by the
function.
II. CIRCUIT DESIGN
The topology of the VGA is shown in Fig. 1. It
consists of three blocks. The input stage has an active
voltage-shunt negative feedback which presents a
wideband characteristic, a good input impedance
matching and noise figure performance. The variable
gain stage adopts the signal-summing structure to
achieve gain control. A novel exponential converting
circuit is added to make the gain become linear-in-dB
along with the control voltage Vc.
Fig. 1 Topology of the VGA
A. Variable Gain Stage Design
VGA has been studied for many years. The signal-
summing VGA is the one of superior VGAs which are
advantageous in terms of low-noise and low-distortion
[1]
characteristics . Fig. 2 shows the structure of signal-
summing VGA. In this circuit, common-source
transistors M1 and M2 operate in saturation region.
They transform RF voltage signal to RF current signal
and offer a gain. The signal-summing VGA realizes the
gain adjusting from changing the control voltage Vcont.
The signal-summing VGA also has a good
performance at high frequencies owning to the gain-
control stages M3~M6 operating as common-base
transistors. This structure can make good operation at
high frequency.

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When x<0.2, there is an approximation equation:

Vcc
1/(1+x)≈1-x. Hence, when we set appropriate
parameters of transistors M1 and M2 to have

W2 (Vcont − VS − VTH2 )
RFout- RFout+ ⋅ < 0.2 (3)
W1 (Vref − VS − VTH1 )
Vcont M3 M4 M5 M6
Eqn (2) becomes
Vref
W2 (Vcont − VS − VTH2 )
GI ≈ 1− ⋅
RFin+ M1 M2 RFin-
W1 (Vref − VS − VTH1 )
W2
= ⋅ (VCC − Vcont )
Iss
W1 (Vref − VS − VTH1 )
W2 (VCC − VS − VTH2 )
+1− ⋅
W1 (Vref − VS − VTH1 )
Fig. 2 Signal-summing variable gain amplifier When appropriate parameters of M1 and M2 are set
as follow:
When Vcont is adjusted, the voltage-difference between
reference voltage Vref and control voltage Vcont will W2 (VCC − VS − VTH2 )
⋅ =1 (4)
change, which will result in the change of the signal W1 (Vref − VS − VTH1 )
current distribution among differential pair M3-M4 and
M5-M6. Afterwards, the continuous gain adjusting has The current gain GI is approximately expressed by:
achieved. The Fig. 3 shows the signal-summing
G I ≈ α (VCC − Vcont ) > 0 (5)
variable gain structure. Its current gain is expressed by
[1]
: where α = W2 /[W1 (Vref − VS − VTH1 )]
I out g m,M1
GI = = (1) Eqn (5) indicates a linear relationship between GI
I in g m,M1 + g m,M2 and Vcont. In order to make the gain become linear-in-dB
along with the control voltage Vc, an exponential
Vcc
function circuit is required.
B. Design of Exponential Converting Circuit
Iout
In this sector, a novel control-voltage converting
Vcont M2 M1 Vref
circuit with exponential function aiming at signal-
summing VGA’s characteristic is presented. Fig. 4
Vs shows the structure of the exponential converting
circuit.
Iin Vcc
Vc
Fig. 3 Signal-summing variable gain structure
R1
The transconductances of transistors M1 and M2 M0
operating in saturation region are expressed by: R2
Vcont
W
g m,M1 = μ n Cox 1 (Vref − VS − VTH1 ) , R3
L1
W2
g m,M2 = μ n Cox (Vcont − VS − VTH2 )
L2 Fig. 4 Exponential converting circuit
μC μC
When n ox = n ox , Eqn (1) becomes Transistor M0 is a PMOS transistor operating in
L1 L2 linear region and in common-source configuration. The
1 transconductance gm,M0 and dVcont/dVC of M0 are
GI = (2)
W2 (Vcont − VS − VTH2 ) expressed by:
1+ ⋅
W1 (Vref − VS − VTH1 ) W
g m,M0 = μ p Cox 0 (VCC − Vcont )
L0

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dVcont R2 Vin+ 1/g m3 +R1 +RL 1

=− ⋅ g m,M0 ⋅ R3 Z in = = // (9)
dVC R1 + R2 (6) I in+ 1+g m1 ⋅ RL jωC gs1
= K 2 (Vcont − VCC )
So, when (1/g m3 +R1 +RL )/(1+g m1 ⋅ RL ) << 1/(ωCgs1 ) 㧘
RR W 50 Ω impedance matching could be achieved easily
where K 2 = 2 3 ⋅μ p Cox 0 > 0 .
R1 + R2 L0 through choosing appropriate gm1, gm3, R1 and RL.

From Eqn (6), we can write The noise performance is another significant target
d (VCC − Vcont ) that we focus to. For most simple wideband amplifiers,
= K 2 dVC there is a severe conflict between input impedance
(VCC − Vcont )
matching and noise figure [3]. The reason for this is that
ln(VCC − Vcont ) = K 2VC + C the transconductance of the input transistor is given by
and the input impedance, leaving no freedom to optimize it
for low-noise. The active feedback structure used here
has overcome this issue. The noise figure of the input
VCC − Vcont = e K2VC + C (7) stage is given by [2]
Combining Eqns (5) and (7), we have
¦v n
2
§ 1 ·
2
γ1
GI = αe K 2VC + C F= ≈ 1 + ¨1 + ¸ ⋅
+ ⋅ ⋅ Rin
2
(8) vn, Rs © 1 AV ¹ 4 g m1 (10)
GI (dB) = K 3 + K 4VC
γ2 RL
+ +
where K 3 = 10 lg α + 10C lg e , K 4 = 10 K 2 lg e . 4(1 + AV ) 4 ⋅ Rin (1 + AV )2
From the deductions above, conclusion could be where 1 and  2 are the noise factors of M1and M2. The
received: After the exponential converting circuit has second term represents the noise contribution from M1,
been added, the logarithmic gain of circuit becomes which equivalent input noise voltage is partly cancelled
linear along with the control voltage as long as the through the feedback loop. The third term represents the
appropriate parameters of transistors are set. noise contribution from M2, which can be ignored if AV
C. Design of Input Stage is high enough. The last term represent noise
contribution from resistor RL. From Eqns (9) and (10)
As the first stage of VGA, a wideband matching we have seen that the input impedance is determined by
design and a low-noise performance are required. the feedback transistor M3, while the noise figure is
Therefore, the structure of active voltage-shunt negative determined by the input transistors M1 and M2.
feedback has been adopted in the input stage. Fig. 5 Therefore, input impedance matching and noise figure
shows the schematic of input stage. Transistors M1 and could be optimized independently, and good
M2 compose a cascode amplifier, and the common-gate performances could be achieved simultaneity in this
transistor M2 is used for reducing the Miller effect. The structure.
common-drain transistor M3 is imported as an active
negative feedback.
Vcc III. MEASURED RESULTS
Vbias Vbias
3
The VGA was fabricated in TSMC 0.18-μm RF
2 RL RL
CMOS process. A micrograph of the VGA is shown in
M3 M6
Fig. 6. The die size is 757μm×540 μm. The chip was
C AC Vbias1 C AC
measured in the test room of Institute of RF- & OE-ICs,
M2 M5
Southeast University, and adopted the On-Wafer Test
R1 R2
scheme. The major test equipments include Cascade
I in+ + - - probe-station, high frequency probes, Agilent network
V in V in I in
M1 M4 analyzer E5071B and spectrum analyzer E4440A.
Cgs1 Cgs4 Fig. 7 shows the measured result of relationship
between logarithmic gain and control voltage, when the
signal frequency is 1220 MHz. It presents an excellent
linear-in-dB variable-gain characteristic with a dynamic
Fig. 5 Input stage circuit gain rang from -3.3 to 9.5 dB. Fig. 8 shows the gain
performance of the VGA at different frequencies. The
By using this feedback stage a wideband impedance
measured result indicates that the amplifier has an
matching to 50 Ω is achieved. The input impedance is
outstanding wideband characteristic. Its 3dB bandwidth
expressed by
covers 430~2330 MHz.

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Fig. 8 Frequency response of amplifier

The measured performances of the VGA are
Fig. 6 Micrograph of the chip summarized in TABLE I.

IV. CONCLUSION
A linear-in-dB gain control technique for CMOS
process is introduced. Based on the novel structure, a
VGA circuit was implemented using TSMC 0.18-μm
RF CMOS process. Measured results show an
outstanding linear-in-dB gain control characteristic with
12.8 dB dynamic gain range. It has a 3dB bandwidth
from 430 to 2330 MHz and consumes 16.2 mW at 1.8 V
supply.

Fig. 7 Plot of gain (dB) versus control voltage

TABLE I
MEASURED RESULTS
Temperature (°C) 27
Supply Voltage (V) 1.8
Power Consumption (mW) 16.2
Frequency (MHz) 430~2330
Control-voltage Range (V) 0.1~1.7
Gain Range (dB) -3.3~9.5

NF(dB) At Maximum Gain 6.27@1220MHz

At Minimum Gain 7.85@1220MHz
Input P1dB (dBm) At Maximum Gain -7@1220MHz
At Minimum Gain -9@1220MHz
Differential Input Impedance (Ω) 50
Differential Output Impedance (Ω) 100

REFERENCES
[1] Shoji Otaka, Gaku Takemura, and Hiroshi Tanimoto, [3] F.Bruccoleri, E.A.M. Klumperink, B. Nauta, Noise
Member, IEEE A Low-Power Low-Noise Accurate Canceling in Wideband CMOS LNAs, IEEE
Linear-in-dB Variable-Gain with 500MHz Bandwidth International Solid-Stare Circuits Conference., Feb.
IEEE JOURNAL SOLID-STATE CIRCUIT., VOL.35, 2002, pp. 406-407.
NO.12, DECEMBER 2000, pp 1942-1948.
[2] B. Razavi, Design of Analog CMOS Integrated Circuits,
Xian Jiaotong University Press, ISBN 7-5605-1606-8.,
pp. 312, 2003-2-1.

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