A High-linearity, 80-dB CMOS VGA with DC-offset Cancellation
for DAB Application
Cui Yike* Li Yongming Wang Zhihua
Institute of Microelectronics, Tsinghua University, Beijing 100084, China
* Email: cuiyk04@mails.tsinghua.edu.cn
Abstract: A three-stage cascaded variable gain amplifier
(VGA) with continuous exponential voltage tuning
characteristics in 0.18um 3.3V UMC process is
presented for COFDM-based DAB/DVB system. The
novel methods to improve the linearity of this circuit and
to automatically cancel DC-offset are introduced. The
operation frequency is only 38.912MHz, but the circuit
maintains 3dB-bandwidth wider than 70MHz throughout
its gain range as wide as 80dB. It provides nearly
2.7dB/10mV slope in 0.3V control voltage range, which
leads to fast settling-time and high accuracy for AGC
loop. At the worst case, the THD of the VGA is -50dB
low, the IIP3 is about -4dBm; the simulated equivalent
input density of while noise is 7 nV / HZ . The overall
dimension of freedom for linearizing these VGA circuits
which used to have poor linearity. Furthermore, since 53
dB voltage gain (maximum) of the open-loop three-stage
cascaded VGA will lead to large DC-offset, this paper
introduces a suitable cancellation circuit to attenuate it.
High performance is attained by carefully analyzing the
influencing facts of the circuit’s parameters.
2. Circuit Description
2.1 Conventional circuit
It is hard to realize exponential gain control function
in CMOS. Here a pseudo-exponential equation is used to
approximate the exponential function according to:
n n
§1 x · §
1
2x ·
| exp  2 nx  (1)
¨ ¸ ¨ ¸
current consumption is only 4mA. ©1 x ¹ © 1 x ¹
Keywords: VGA, AGC, CMOS, linear, DC-offset, IF This approximation is suitable for cascade circuit cells.
Here n is the number of stages.
1. Introduction
In most communication system, automatic gain
control (AGC) circuits are often employed to maximize CMFB

the dynamic range of the whole system, since the a b OUT

received signal power of all the communication systems Vref M7 M8 M1 M3 M4 M2

IN
is unpredictable. Moreover, because AGC may control VC
Ib+Ivar Ib-Ivar
the amplitude of output signal within a fairly small range, M9 M10 M5 M6

it will relax the demand on the accuracy of following

ADC as well as adequately utilize its efficiency.
Fig.1 Simplified VGA cell circuit schematic
In AGC, VGA is a pivotal circuit. When digitally
Fig.1 shows a single-stage VGA cell[2][3].The cell
controlled VGA has disadvantages in stability, accuracy
consists of a differential pair with diode-connected
and has additive digital circuits, continuous gain tuning
NMOS loads. A common-mode feedback (CMFB)
VGA with exponential characteristic is always preferred
circuit is used to stabilize DC output voltages against
for its high accuracy and relatively constant dynamic
process, temperature, and supply variation. The gain of
-process in AGC. There are two main approaches to
the VGA cell is controlled by varying the current (Ivar)
realize an exponential function circuit using MOSFETs.
through the differential pair. The current is in terms
Compared with using the exponential characteristic in
controlled by the difference between Vc (control voltage
the weak inversion[l], using the square-law characteristic
from the IF output peak detector circuit) and Vref (the
in the saturation region to approximate an exponential
reference set point correspondence to the final IF output
function by specific circuits [2][7]is more suitable for
signal level to be maintained) according to:
high-speed applications, which is adopted in this paper.
Since AGC is always near to the output of receivers, g m1 W1 I b  I var W1 1  I var / I b 1  F (2)
A 1 ˜ ˜ K˜
the linearity of VGA is significant for that of the system. g m3 W3 I b  I var W3 1  I var / I b 1 F
However, compared with digitally controlled VGA [4], I var E g m 8 Vref  Vc  (3)
the current based, continuous gain tuning VGA is short Here, E W/ L / W/ L W/ L / W/ L
in linearity.[3][7].This paper proposes a novel method to 5 10 6 9
n/2
improve the linearity of versatile pseudo-exponential § 1 F · (4)
An _ dB v 20 log ¨ ¸ v nF
VGA structure[2][3]. This method improved the IIP3 to © 1 F ¹
-4dBm compared with circuit proposed in [2].What is Eqn.(4) shows that the gain is approximately exponential
more significant is that the method provides an extra characteristic as mentioned in Eqn(1).In order to increase

1-4244-0161-5/06/$20.00 ©2006 IEEE

Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on October 15, 2008 at 02:01 from IEEE Xplore. Restrictions apply.
 the accuracy of the AGC, it is necessary to increase
either n or F . According to Eqn(2)(3)(4), Vref  Vc is just M5 M3 M4 M6

the output range which controls the large input range. INn
M1 M2
INp

Note that the impedances at node a and node b will R1 R2

change with the variation of gain, so the bandwidth will C1 M7 C2

VB
be smallest when the gain is maximum and vice versa.
2.2 Linearity improved circuit
There are three main distortion sources in Fig.1. First, Fig.3 DC-offset cancellation circuit schematic
the practical gain of the diode connection amplifier is not Fig.3 shows a proposed offset cancellation circuit [6],
exactly the ratio of the two transconductances. Second which consists of a differential negative feedback loop
the difference of currents between M1&M2 and M3&M4 with a low pass filter (consists of R and C). Note that the
will introduce extra distortion. Third, the deviation of capacitor in DCOC should not be too large, or it will
transistor M5&M6 from ideal saturation region will also limit the VGA’s bandwidth. DCOC detects the difference
deduce serious distortion. It is obvious that the facts of the VGA output signals at DC level and removes the
cause the distortion by affecting the transconductances DC-offset. In Fig.3, differential DC-offset voltages at the
both of the differential input transistors and the diode VGA output are sensed and passed through LPF, while
transistors. Among various linearization methods, the other higher frequency voltages are blocked. The
source-degeneration technique is the most natural differential pair M1 and M2 turns the input into different
high-frequency linearization scheme. DC currents through M3 and M4, then mirrored by M5
and M6. The offset correction currents are injected back
to the VGA in Fig. 2.As a result, the DC-offset current in
the VGA is adjusted. With the DCOC, the closed over all
INn DCO INp
CMFB
C transfer function of the VGA can be derived to be
OUT jZ
1 (6)
Vref M7 M8 M1 M3
M16
M4 M2 g m1Ro Z 3 dB , f
IN H w 2
VC M15
Ib-Ivar
1  g m 2 Ro
1
jZ

Ib+Ivar
M14
M9 M10 M5 M11 M13
VB
Fig.2 Improved VGA cell circuit schematic
The circuit in Fig.2 adopts the technique of using
drain-source conductance of CMOS transistors biased in
the linear region as source-degeneration resistors[5].
Compared with fixed bias drain-source conductance as
source-degeneration resistors, this method is preferable
for an additional internal feedback which increases the
transconductances for large signals to increases the linear
range of this topology. The circuit in Fig. 2 has:
I b  I var E1 (5)
g m1 n1 1
n 1 (V G S 1  V T )
According to Eqn(5), because of the reduction factor n1 ,
HD3 of the differential input transistors will be reduced
by n12 ,while the diode load transistors M3,M4 are also
linearized by application of linear transistors M16,M15.
The gain equation result and control function are the
same to Eqn.(2)(3)(4).
2.3 DC-cancellation method
The proposed three-stage VGA consists three cells to
achieve as large as 53dB DC gain. Due to mismatch of
input transistors, each cell has its own offset voltage,
typically as large as 10mV. Thus, the offset voltage
would be amplified to about 4V, large enough to saturate
the circuit. Therefore a DC-offset cancellation circuit
(DCOC) is necessary for each cell.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on October 15, 2008 at 02:01 from IEEE Xplore. Restrictions apply.
 jZ 
Z oQ Z o2
M12 M6
Zo
Q
Zo (1  g m 2 R o )Z  3 dB ,VG A Z  3 dB , f Z  3 dB ,VG A  Z  3 dB , f
,
g m 1 is the transconductance of M1,2 in Fig.2. g m 2 is the
transconductance of M1,2 in Fig.3. It is clear from Eqn(6)
that the VGA with DCOC is band-pass. Note that VB in
Fig3 is not fixed but adjusted by VGA bias. When the
VGA operates at maximum gain, the attenuation of DC-
offset is also maximum for the bias is largest at that time,
otherwise the DCOC operated with less current. This
method further reduces the DCOC’s negative effects on
the whole circuit performance.
2.4 VGA chain optimization
4 E 14
Based on the analysis of the above circuit cells, it is
not difficult to optimize the three-stage VGA chain to
achieve design goal.( Fig4)
Fig4 VGA Chain
In order to attain 53dB gain and 70MHZ bandwidth,
4mA current and three-stage VGA is necessary. To
control the output voltage within smaller range, a large
size (W/L=400u/0.5u) of M7 and M8 in Fig. 1 and Fig. 2
is adopted. The tradeoff between noise and linearity is
carefully made. Since the circuit in Fig.2 has a bad noise
 performance and good linearity compared with circuit in
Fig.1, the first stage adopts the configuration in figure 1.
The last two stages adopt circuits in Fig.2. Here, the
V V
value of c ref from -0.175 to 0.125 can control 80dB
input signal range from -98dBm to -18dBm. Since the
DCOC and CMFB circuits are close-loop, inspection of
stability of them is also critical.
3. Simulation Results
The proposed VGA is designed in UMC mix-signal
0.18um technology. Lots of simulations were made on
the variation of power supply voltage, temperature and
process corner. At last a series of trade-off results are got.
The VGA shows exponential voltage control in Fig. 5.
(Sweep AC response). Fig.6 illustrates the gain response
for the whole dynamic range of 80dB with 0.025V VC a
step. The 3dB-bandwidth of the VGA is 70MHZ over the
entire gain range. When the VGA operates at maximum
gain, the DC attenuation is about 0.8dB, that is 52 dB
compared to the gain. The simulated equivalent input
density of while noise is 7.7nV/ HZ at 52.5dB gain and
309nV/ HZ at 27.5 dB attenuation.(Fig.7). The integrate
noise power of both meet the signal to noise ratio
requirement of DAB system .And the range of VGA gain
is much bigger than the ratio between the maximum and
minimum equivalent input noise, which means all the
operation situations of VGA satisfy the SNR requirement.
Fig.8 shows the IIP3 of two extreme situations, in the
worst case(27.5 attenuation), the IIP3 is about -4dBm.
The THD of maximum gain is 0.15%(-98dBm input),
while the THD of minimum gain is 0.4%(-18dBm input).
THD of all the operation situations are below -50dBc.
4. Summary
This paper presents a three-stage cascaded VGA with
continuous exponential tuning characteristics. Based on
a versatile exponential voltage control VGA, it proposes
a new method to improve the linearity of this circuit.
This method has significant meaning to provide a new
dimension of freedom to linearize these VGA circuits.
This paper also introduces DC-offset cancellation circuit
to reduce effects of input transistors’ mismatch and 1/f
noise. The VGA operates at 38.912MHz under 3.3 V
supply voltage and consumes about 4 mA DC current.
The gain range is 80dB tuned by 0.3V output range.
Table 1. comparison prior design
[4] [7] ours
process 0.35um 0.6um 0.18um
mode digital analog analog
bandwidth 95MHZ 110MHZ 70MHZ
linearity IIP3-2dBm THD-50dBc -4dBm -50dBc
input noise 16nV/ HZ 7.7nV/ HZ
power 32.7mW 18mW 13mW
range 70dB 70dB 80dB
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on October 15, 2008 at 02:01 from IEEE Xplore. Restrictions apply.
Fig.5exponential character Fig.6 different VC-AC
Fig. 7 equivalent input noise Fig.8 IIP3
Acknowledgments
This research was partly supported by the National
Natural Science Foundation of China (No. 90407006)
References
[1] T.Yamaji, N.Kanou, T.Itakura: “A Temperature Stable
CMOS Variable Gain Amplifier with 80-dB Linearly
Controlled Gain Range”, 2001 symposium on VLSI
Circuit Design of Technical Papers, pp.77-80,2001.
[2]P-C.Huang,L-Y.Chiou,C-K.Wang:“A 3.3-V Wideband
Exponential Control Variable-Gain-Amplifier,” IEEE
International Symposium on Circuits and Systems, 1, pp.
285-288, 1998.
[3] R. Harjani: “A Low -Power CMOS VGA for 50 Mb/s
Disk Drive Read Channel,” IEEE Trans. on Circuits and
System, pt 11, vol. 42, no. 6, pp.370-376, June 1995.
[4]Chua-Chin Wang; Ching-Li Lee; Li-Ping Lin;
Yih-Long Tseng “Wideband 70dB CMOS digital
variable gain amplifier design for DVB-T receiver's
AGC” Circuits and Systems, 2005. ISCAS 2005. IEEE
International Symposium on 23-26 2005
[5] F. Krummenacher and N. Joehl, “A 4-MHz CMOS
continuous-time filter with on-chip automatic tuning,”
IEEE J. Solid-Slate Circuits, vol. 23, pp. 750-757, 1988.
[6] Anh-Tuan Phan; Chang-Wan Kim; Moon-Suk Jung;
Yun-A Shim; Jae-Yung Kim; Sang-Gug Lee;ĀA novel
1.5V DC offset cancellation CMOS down conversion
mixer” Circuits and Systems, 2005. ISCAS 2005. IEEE
International Symposium on 23-26 May 2005
[7] M. Mostafa, H. Elwan, A. Bellaour, B. Kramer, and S.
H. K. Embabi, “A 110 MHz 70 dB CMOS variable gain
amplifier” ,1999 IEEE Inter. Symp. on Circuits and
Systems (ISCAS'99), May 1999.