Low-Power GPS Receiver Design

Invited Paper
Teresa H. Meng
Department of Electrical Engineering
Stanford University

Abstract: This paper describes the design of a low-power Global

Positioning System (GPS) receiver implemented in the CMOS tech-
nology. The primary GPS ranging signal is broadcast at the fre-
quency of 1.575 GHz, modulated by a pseudo-noise sequence at a
chip rate of 1 MHz. The design of this low-power GPS receiver
emphasizes the circuit techniques and architectural trade-offs
employed in minimizing the energy needed for each position esti-
mate.

1.0 Introduction
The Global Positioning System, first proposed in 1973 with a total of 24 satel-
lites, uses one-way ranging from the satellites that are also broadcasting their esti-
mated positions. Ranges are measured to four satellites simultaneously in view by
matching the incoming signal with a user-generated replica signal and measuring
the received phase against the user’s clock. With four satellites and appropriate
geometry, four unknowns can be determined: latitude, longitude, altitude, and a
correction to the user’s clock.
The GPS ranging signal is broadcast at two frequencies: a primary signal at
1575.42 MHz and a secondary broadcast at 1227.6 MHz. These signals are gener-
ated synchronously, so that a user who receives both signals can directly calibrate
the ionospheric group delay and apply appropriate corrections. However, most
civilian users will only use the primary frequency at 1575.42 MHz [ 11.
There are two modulations on the primary frequency: a course acquisition code (C/
A code) and a precise code (P code). The CIA code is a short pseudo-noise (PN)
binary sequence of 1023 chips broadcast at a chip rate of 1.023 MHz. The same PN
code is repeated 20 times for each data bit, to accommodate a data rate of 50 bps of
broadcast satellite data. The P code, on the other hand, is a very long code (seg-
ments of a 200-day code) that is broadcast at ten times the rate of the CIA code,
10.23 MHz. Because of its higher modulation bandwidth, the P code ranging signal
is somewhat more precise. The military has encrypted this signal in such a way that
renders it unavailable to the unauthorized users. We focus on using the CIA code
for position estimates in this paper.
Currently the US government intentionally degraded the accuracy of the CIA code
by desynchronizing the satellite clock. This degradation is called selective avail-

1
ability (S/A). The magnitude of these ranging errors is typically 20 meter, resulting
in horizontal position errors of about 50 meters rms. A technique known as differ-
ential GPS (DGPS) can overcome this limitation by providing a fixed position ref-
erence. Without S/A, the ranging accuracy of a GPS receiver using non-coherent
detection can be less than a few meters.
2.0 Overview of GPS Operation
The GPS signal can be viewed as carrying an instantaneous reading of the
position and clock of the satellites in view (Chapter 2 of [l]). Assume that the user
is stationary and that the user’s clock is synchronizedwith the satellite clock. At the
instant that the GPS signal is received, the user local time is recorded. By compar-
ing the local time and the satellite time and position carried by the GPS signal, we
can calculate the measured delay caused by the finite speed of light and a range D
to the satellite. Therefore, the receiver’s location is somewhere on a sphere of radius
D centered at the satellite. Clearly if we were able to perform the same type of mea-
surement with three satellites simultaneously, we could locate the user position in
three dimensions at the intersection of three spheres. However, most user clocks are
not perfectly synchronized with satellites, and therefore a fourth ranging measure-
ment is necessary to account for the local clock bias.
2.1. Calculation of Position Accuracy
The current GPS uses 24 satellites, each assigned a CIA code so that the signal from
each satellite can be individually decoded. Most recent GPS receivers are equipped
with 12 correlators to decode 12 satellite signals concurrently. Four of the strongest
signals are selected for ranging measurements. Figure 1 illustrates the GPS ranging
measurements using a delay-lock-loop (DLL). Satellite data are modulated with a
PN code of 1023 chips that has a distinct beginning, called the epoch. The DLL cre-
ates an internal replica of the known code sequence and adjusts the internal epoch
until it exactly matches the received signal in delay. The clock time of the satellite
at the time of transmission is then subtracted from the user clock time to recover the
measured pseudo-range.
Positioning accuracy reflects the final capability of most GPS receivers. Positioning
accuracy is a function of the ranging accuracy and the geometry of the selected sat-
ellites, called the dilution of precision (DOP).For the current nominal constella-
tion, the worldwide median position DOP is approximately 2.5. To calculate the
positioning accuracy, for example, assume that the satellite geometry produces an
position DOP of 3. We also know that the speed of light is 0.3 d n s . To achieve a
position accuracy of 10 meters would require a ranging accuracy of 11 ns (10 m = 3
* 11 ns * 0.3 d n s ) , which i s about 1% of a chip interval.
2.2. User-Received Signal-to-NoiseRatio
The receiver antenna output is fed to a bandpass filter, followed by a low-
noise amplifier (LNA). Because of the potential for line losses, the LNA is gener-
ally kept in close physical proximity to the antenna. The bandpass filter must simi-

2
larly have low loss but provide adequate filter selectivity to attenuate adjacent
channel interference.

I GPS Code Filter & Satellite Time

I Generators 4

Figure 1.GPS tracking operation.

Assuming that the LNA noise figure is 2 dB, then the receiver noise temperature is
167 OK. For a typical filter loss of 1.1 and an antenna temperature of 130 OK, the
receiver noise density (one-sided) is -203.66 dBW/Hz. The CIA signal power den-
sity for the specified -160 dBW and a signal bandwidth of 1.023 MHz is -220.1
dBW/Hz. Thus, the CIA signal spectrum is 16.4 dB below the noise power spectral
density. Therefore the GPS signal normally is not visible to a spectrum analyzer.
This relatively low signal power will be amplified by the processing gain of 43 dB
at the receiver due to the use of the spreading PN code.
In the next two sections, we will describe a low-power GPS receiver implemented
in the CMOS technology as a design example.

3.0 GPS Receiver Front-End Design

To achieve the goals of integration and low power consumption, one can
employ a low-IF receiver architecture [2]. The low-IF approach is well-suited for
use in a GPS receiver due to the inherent properties of the GPS signal spectrum, as
illustrated in Figure 2.
The GPS spectrum consists of the CIA code, whose main-lobe occupies
approximately a 2 MHz band, and the P code, whose main-lobe occupies approxi-
mately a 20 MHz band, with both bands centered at 1.575 GHz. Although most
receivers will be used for detection of the CIA code, the presence of the P code
serves as a buffer zone which guarantees that the nearest broadcast interferer will be
no closer than 10 Mhz from the center of the band. Assuming a local oscillator fre-

3
quency of 1.573 GHz, the IF frequency becomes 2 MHz. Since we only need the
main lobe of the CIA code, spanning 1-3 MHz, the lower end of the transition band
of the IF filter can start at 3 MHz. Furthermore, since the P code from the spectrum
centered at -2 MHz extends up to 8 MHz, the transition band can extend up to 8
MHz. This relatively wide transition band allows us to implement filtering on-chip.
A 5th order elliptical filter in the signal path should provide sufficient rejection of
out of band interference.
Received GPS signal

.........................................................................................................................
Thermul Noise

- I7dB

1.575 GHz

Signal after conversion to low-IF using an LO at 1.573GHz

................................................................................................
Thermal Noise including Receiver Noise
t
Imnge Rejection Filter removes this signal
--A,' -i -23dB I
,

GPS U A Code

Figure 2. GPS signal spectrum before and after low-IF conversion.

The received GPS signal is around 17 dB below the thermal noise floor. A process-
ing gain of around 43 dB is available through the de-spreading of the GPS spread
spectrum signal. Given that we desire a signal-to-noise ratio of around 20 dB after
de-spreading, we will need a signal to noise ratio of around -23 dB at the output of
the IF stage. This means that the overall noise figure of the front-end should not
exceed 6 dB .
Figure 3 shows a block diagram of the front-end architecture [2]. The signal passes
through a bandpass filter (BPF), used to reduce out of band noise, and is then fed to
a low noise amplifier (LNA) centered at 1.575 GHz. The signal splits into the in-

4
phase (I) and quadrature (Q) branches at the two mixers [3] and is then amplified at
the IF frequency before being low-pass filtered to remove out of band interferers.
Following this, an amplifier with an automatic gain control (AGC) is used to bring
the IF signal up to an acceptable level before undergoing A/D conversion. The out-
puts of the A/D can now be processed by DSP to decode position and time informa-
tion. The I and Q paths allow image rejection to be carried out in the digital domain
so that the lobes of the CIA signal spectrum centered at -2 MHz does not interfere
with the desired one at 2 MHz.
2MHz
IF amp
I-mixer

Ibl

LPF
BPF

LNA
1.575GHz Q[nl
Q-mixer
IF amp IAGC I

Figure 3. Low-IF receiver front-end architecture.

A summary of the performance of the proposed GPS receiver front-end design is
presented in Table 1 [2][3].

Table 1. GPS Receiver Front-End Chip

Signal Path Performance I
LNA Noise Figure 2.4 dB
Overall Receiver Noise Figure 5.4 dB
Peak SFDR (Spurious Free Dynamic Range) 57 dB
Filter Cutoff Frequency 3.5MHz
Filter Stopband Attenuation > 50dB @ 8MHz
> 66dB @ lOMHz
Pre-filter Power Gain 19 dB
Pre-filter Voltage Gain 32 dB
Total Power Gain (limiting amplifier limits on - 82 dB
system thermal noise)
Total Voltage Gain - 107 dB
Technology 0.5 pm CMOS
Signal Path Power 79 mW
PLUVCO Power 36 mW

5
4.0 Low-Power Baseband Processing Design
The GPS baseband processing consists of two parts: a signal processor block
for data acquisition and a data processor block for position calculation,as shown in
Figure 4. The signal processor receives the digitized low-IF signal from the RF
front-end. The digital frequency-locked-loop(FLL) removes the Doppler frequency
and converts the IF signal down to the baseband. This baseband signal is then corre-
lated with locally generated C/A spreading code. The path between the satellite and
the receiver which the incoming signal travels through introduces a phase delay in
the spreading code. The phase delay can be very accurately measured by a DLL and
converted to the pseudo-range which is then used by the navigation data processor
to compute the user's position. By removing the Doppler frequency and the C/A
spreading code, the signal processor also recovers the SO bps navigation data which
contains the satellite orbital information, health status and error correction parame-
ters. The data processor decodes the raw data and computes the position of the sat-
ellite. Based on the information of the satellite position and the pseudo-range
between the satellite and receiver, the navigation data processor obtains an estimate
of the user position and time fix,

SIGNALPROCESSOR : DATAPROCESSOR

DATA PROCESSINO
0

Figure 4. Block diagram of GPS base-band processing.

4.1. Baseband System Architecture
Most commercial GPS receivers employ an ASIC and a general purpose DSP pro-
cessor to achieve reaI-time position calculation. While this approach offers the
designer flexibility, it is power inefficient and unsuitable for single-chip integration.
Since the rate of position calculation can be very low, only one navigation solution

6
updated at every few seconds, implementing both the data acquisition and position
calculation in single hardware allows the use of low-power custom design for data
acquisition and a low-speed processor core for position calculation. This approach
substantially reduces both the size and complexity of the receiver design.
4.2. Signal Acquisition and ’hacking
To achieve low power, we reduce the duty cycle through fast synchronization.
Since position and time update is required at every few seconds in our applications,
rapid acquisition and tracking speed allows the receiver to spend more time in the
power-down mode, reducing total power consumption. Thus, an important goal in
our synchronization scheme is to minimize the acquisition time. Furthermore, to
achieve single-chip integration, the synchronizer must be made as simple as possi-
ble.
Almost all existing GPS receivers correlate the received signal with a reference
pseudo-noise code by employing a code generator that is clocked by a numerically
controlled oscillator (NCO). The frequency of the NCO is adjusted so that the local
reference code is generated at the same frequency as the incoming signal frequency,
which has been altered by the Doppler frequency. In these architectures, rapid reac-
quisition is attained by operating several of these correlators at different time off-
sets in parallel. The complexity in the receiver grows rapidly with increasing degree
of parallelism since separate adders are required for each correlator.
To reduce the hardware complexity with an increasing number of parallel correla-
tors, a passive correlator is illustrated in Figure 5. Unlike the conventional correla-
tion approach discussed above, the received code is convolved with a “stationary”
set of a local reference code [4].
Assume that M parallel correlators are necessary and that we take two samples per
chip. In Figure 5, the ith baseband signal b(i) is passed through a tapped delay line
consisting of M-1 registers. Every two consecutive taps are multiplied by a single
reference PN code, since b(i consists of two samples per chip. In Fi ure 5 , b(i)and

3 (7 4
b(i-1) are multiplied by x k- , b(i-2) and b(i-3) by x k - + 1 , and so on.
~ ( jis)thejth chip of the reference PN code and k is an integer value. After every
M clock cycles, k is incremented by one. The multiplied values, which are imple-
M
mented by XOR’s, are combined by a tree adder network. If N = - , the result-
2
ing sum is dumped for further processing. Otherwise, it is integrated with the sum
N
M cycles earlier, which is stored in a FIFO. This integration is performed -
M/2
times to achieve the effect of correlating N chips. The result is then output for fur-
ther processing. Since the reference code is “stationary” in this approach, the
received signal is re-sampled by using a digital interpolator at a frequency consis-
tent with that of the “stationary” taps of the reference local code.

7
 Adder Network

Adder Network

Figure 5. Low-power architecture of M parallel correlators.

Once the received signal is convolved with the local reference code, the position of
the largest correlation value represents, in general, a coarse estimate of the time off-
set between the reference and received signal. If the received signal power is low,
post-detection integration might be necessary to ensure that this coarse estimate is
accurate with high probability. The correlation peak and its two adjacent correlation
values are used to estimate the phase offset. With an appropriate state-space repre-
sentation of the phase error, the code frequency error is also readily estimated. The
interpolated frequency and phase are then appropriately adjusted by an NCO, as
shown in Figure 6.
A GPS receiver that performs the functions described above has been implemented
in 0.5 pm CMOS technology. This chip accepts a two-bit IF signal, whose exact
frequency is programmable. It mixes the IF samples to baseband and performs cor-
relation and synchronization as described above. The chip outputs decoded data and
pseudo-range estimates of five channels. At lSV, the chip operates up to 25 MHz.
Each channel searches seven chips in parallel for rapid reacquisition. The estimated
power consumption when all five channels are fully operational is under 30 mW.

8
 Baseband
Receive-
Signal Digital
Interpolator-

I NCO PhaseFreq Error Est. I

Figure 6. Simplified synchronizer architecture.
To facilitate a single-chip design, we propose to leverage on the properties of
CDMA embedded in GPS signals. Due to the substrate coupling and other leakage
paths, the switching noise produced by the digital part of the design can desensitize
analog components on the same die, especially the RF front-end devices which usu-
ally operate at a signal level 6 orders of magnitude below that of the digital ones.
We propose to avoid mixed-signal coupling by interleaving the operation of the
analog and digital parts in the time domain, which introduces negligible perfor-
mance degradation and a modest increase in power consumption [5].
To further improve the accuracy of position estimates, an averaging process, such
as a Kalman filter, is often used. Though optimal in the sense of minimizing mean
square error of position estimates, Kalman filters suffer from a sluggish response to
highly dynamic user maneuvers. To address this problem, we have derived a self-
regulated algorithm to improve the tracking ability without degradation in steady-
state position accuracy [6].

5.0 Conclusions
In this paper, we reported the design of an all CMOS GPS receiver. Measure-
ments made on our receiver match or exceed the performance metrics of all other
GPS chip sets, but at substantially lower power levels. This low-cost, low-power
design enables the implementation of numerous new applications, especially of the
portable/wearable variety, that are simply impractical with existing solutions.
The design of this GPS receiver chipset is yet another example of the power-perfor-
mance trade-offs that can be achieved by an integrated design approach. Our ability
to integrate all of the RF circuitry with the digital processing has given us the
unique opportunity to implement a philosophy of RF and digital co-design. Imple-
menting this philosophy has allowed us to minimize unwanted interaction between
the two domains, while simultaneously reducing power consumption, to achieve a
level of performance associated with much more sophisticated technologies.

9
~cknowl~dgment
The author would like to acknowledge the members of the Stanford GloMo Project
for their contribution to the work reported in this paper. This research was sup-
ported by DARPA.
References

B. W. Parkinson, J. J. Spilker, P. Axelrad, and P. Enge, editor, Global

Positioning System: Theory and Application, AIAA, 1996.
D. K. Shaeffer, A. R. Shahani and T. H. Lee, “A 115 mW GPS Front-End
Receiver Chip,” ISSCC Digest of Technical Papers, February 1998.
A. R. Shahani, D. K. Shaeffer and T. H. Lee, “A 12 mW Wide Dynamic
Range CMOS Front-End for a Portable GPS Receiver,” ISSCC Digest of
Technical Papers, February 1997.
W. Namgoong and T. H Meng, “Power Comparison of Parallel Spread
Spectrum Correlator Architectures,” Proc. International Symposium on Low
Power Electronics and Design, August 1998.
S. Reader and T. H. Meng, “Partitioning Analog and Digital Processing in a
Single-Chip GPS Receiver,” IEEE Workshop on Signal Processing Systems,
October 1998.
H. W. Lee and T. H. Meng, “Self-ReguIated GPS Navigation Algorithm”,
IEEE Workshopon Signal Processing Systems, October 1998.

10