1414 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.

7, JULY 2005

A 19-mW 2.6-mm2 L1/L2 Dual-Band

CMOS GPS Receiver
Jinho Ko, Jongmoon Kim, Student Member, IEEE, Sanghyun Cho, and Kwyro Lee, Senior Member, IEEE

Abstract—This paper presents the design and implementa-

tion of an L1/L2 dual-band global positioning system (GPS)
receiver. Dual-conversion with a low-IF architecture was used for
dual-band operation. The receiver is composed of an RF pream-
plifier, down-conversion mixers, a variable-gain channel filter, a
2-bit analog-to-digital converter, and the full phase-locked-loop
synthesizer including an on-chip voltage controlled oscillator.
Fabricated in a 0.18- m CMOS technology, the receiver exhibits
maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for
L1 and L2, respectively. An on-chip variable-gain channel filter
provides IF image rejection of 20 dB and gain control range over
60 dB. The receiver consumes 19 mW from a 1.8-V supply while Fig. 1. GPS L1/L2 band spectrum.
occupying a 2.6-mm2 die area including the ESD I/O pads.
Index Terms—CMOS RF receiver, global positioning Traditionally, GPS radios were implemented in bipolar pro-
system (GPS), image-rejection complex filter, low IF, satellite cesses [1]–[3]. However, in order to satisfy the increasing de-
communications, wireless communications. mand of low cost and higher level of integration, CMOS imple-
mentation becomes more and more popular and important. Sev-
I. INTRODUCTION eral successful implementations of integrated L1-band GPS re-
ceivers in CMOS processes were reported in [4]–[9]. This paper

G LOBAL positioning system (GPS) is a satellite broad-

cast system, providing the fundamental physical quanti-
ties of the absolute position, velocity, and time information to
users. Although GPS was originally developed for military pur-
poses, its civil use has greatly been increased after the end of the
cold war. Satellite-based navigation and positioning will have an
ever-increasing influence on our daily lives in the future, espe-
cially for location-based service.
The main drawback of the current GPS system is its poor
sensitivity performance in a multipath environment. Recently,
to overcome this limit, the GPS modernization plan, adding a
new modernized civil code called L2 C/S on L2 band, was an-
nounced. The L2 C/S code achieves better tracking performance
in multipath environment. As a result, the L2 C/S is likely to be-
come the signal of choice for applications like E911 positioning
inside buildings, personal navigation in wooded areas, or ve-
hicle navigation along tree-lined roads. If this prediction comes
true, embedded GPS in wireless phones will make the L1/L2
dual-band receiver the most widely used of all GPS applications
until nearly every satellite has the L2 civil signal and require a
low-cost, highly integrated chip solution.
Manuscript received November 10, 2004; revised January 27, 2005.
J. Ko is with the Department of Electrical Engineering and Computer Science,
Korea Advanced Institute of Science and Technology (KAIST), Daejeon 305-
701, Korea, and also with PHYCHIPS, Inc., Daejeon 305-701, Korea (e-mail:
jhko@dimple.kaist.ac.kr; jhko@phychips.com).
K. Lee is with the Department of Electrical Engineering and Computer Sci-
ence, Korea Advanced Institute of Science and Technology (KAIST), Daejeon
305-701, Korea (e-mail: krlee@ee.kaist.ac.kr).
J. Kim and S. Cho are with PHYCHIPS, Inc., Daejeon 305-701, Korea
(e-mail: jmkim@phychips.com; shcho@phychips.com).
Digital Object Identifier 10.1109/JSSC.2005.847326
0018-9200/$20.00 © 2005 IEEE
describes the design and implementation of a single chip L1/L2
dual-band GPS receiver in a 0.18- m CMOS process that can
receive both L1 and L2-band signals.
Section II describes the GPS fundamentals and advantages of
dual-band operation. Section III provides the GPS receiver re-
quirements that are not well defined yet and slightly different
from other wireless communications systems such as cellular
phone or wireless local area network (WLAN). Receiver archi-
tecture and circuit details are presented in Sections IV and V,
respectively. Section VI presents experimental results of the fab-
ricated IC, and the paper concludes in Section VII.
II. GLOBAL POSITIONING SYSTEM
The GPS signal from the satellite uses two RF bands: a pri-
mary signal at 1575.42 MHz (L1 band) and a secondary signal
at 1227.6 MHz (L2 band). The GPS utilizes a direct-sequence
spread spectrum (DSSS) technique and a binary phase-shift
keying (BPSK) modulation. The minimum received signal
power at the antenna port is about 130 dBm for L1 and
133 dBm for L2 which is 19 and 22 dB below the thermal
noise level, respectively, as seen in Fig. 1. By despreading and
integrating over a long time period, a receiver can exploit the
inherent spread-spectrum processing gain of the navigation
signals to get the proper postcorrelation signal-to-noise ratio
(SNR).
The L1 band signal from each satellite is spreaded by two
pseudo random codes, the coarse acquisition (C/A) code and
the precision (P) code. The P-code is intended for military use
and hence encrypted, with the encrypted version of the P-code
referred as the Y-code. Currently, the L2 signal is modulated

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 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER
TABLE I
L1 AND L2 SIGNAL CHARACTERISTICS
by the P-code only. However, according to the GPS moderniza-
tion plan, in the near future, a new civil code called L2 C/S will
be added in the L2-band signal, which will enhance the current
GPS navigation performance significantly [10]. Signal charac-
teristics of the L1 and L2 bands are summarized in Table I.
The primary need of L2 C/S was to eliminate the unaccept-
able 21-dB cross-correlation performance of the C/A code,
which allows a strong GPS signal to interfere with weak GPS
signals. The L2 C/S signal achieves this by having a worst-case
cross-correlation performance of 45 dB. Furthermore, L2 C/S
lowers the data demodulation threshold, making it possible to
read the message when barely tracking the signal and hence can
improve the sensitivity performance in multipath environment
as well as the first-time-to-fix performance [10]. Moreover,
one can easily compensate for the ionospheric group delay
variation, a dominant source of ranging error, by measuring
two delays from two different carrier frequencies [11]. In order
to exploit the L2 C/S benefits as well as the stable L1 C/A GPS
signal with reasonable cost and moderate power consumption,
a novel highly integrated, low-power receiver suitable for
dual-band operation should be introduced.
III. RECEIVER REQUIREMENT
To satisfy the stringent power and area requirements, it is
necessary to properly specify and optimize the receiver require-
ment. Unlike other wireless communications systems such as
GSM [12], Bluetooth [13], or WPAN [14], however, the GPS
requirements were not well defined yet nor specified in the lit-
erature until now. One remarkable difference between the GPS
standard and a conventional wireless standard is that GPS has
only one RF channel in each band; there is no strong in-band
interferer that is common in a cellular or WLAN system; wider
bandwidth than necessary was reserved; the channel selectivity
might be even looser than that in the others, and so forth, these
factors give us a very important implication to build a low-power
GPS receiver. For example, by trading the selectivity, including
linearity, phase noise, and channel filter attenuation, one can im-
prove both sensitivity and area (cost) for a given power con-
sumption [15]. In the following section, we present some fun-
damental requirements of a GPS receiver.
A. Gain Dynamic Range
As mentioned before, a GPS signal from the satellite is far
below the thermal noise level at a GPS receiver input, so the
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1415
thermal noise always dominates. In principle, the signal dy-
namic range at the GPS antenna is almost static and is uniquely
determined by the only one factor, which is the antenna temper-
ature.
(1)
where is the total input power at a receiver front-end,
is the wanted signal power from the th satellite, is the number
of visible satellites, is the available noise power, is the
Boltzman constant, and is the absolute antenna temperature.
Signal dynamic range due to the temperature variation is very
small. If we consider a temperature range from 45 C to
85 C, then the signal dynamic range is calculated by
dB
(2)
Now, suppose a practical GPS receiver, as depicted in Fig. 2, in-
corporating an external active antenna, an external RF image re-
jection filter, and an integrated GPS receiver. The gain required
for an integrated receiver is
(3)
where is the wanted IF output power determined from
the full scale of the analog-to-digital converter (ADC). Thus,
the required gain dynamic range of the integrated receiver can
be defined as
dB (4)
where is the required gain control range of the integrated
GPS receiver, is the gain variation of external components,
and the margin is a headroom for possible gain variation of
the integrated receiver due to process, temperature, and supply
voltage variation. If we assume that is about 25 dB and the
worst gain variation of the receiver is about 6 dB, then we can
conclude that the automatic gain control (AGC) range of 40 dB
is sufficient for GPS applications. It is worth noting that, if a
strong jamming signal exists in the GPS band, then the lower
bound of gain should be lowered to handle the large interfering
signal.
B. Noise Performance
The ultimate goal of a GPS receiver is to extract the accu-
rate position and time information from the weak satellite sig-
nals. Although the position error can be considered as a figure
of merit, there exist various sources of position error. One is
from the satellite itself, another is due to a propagation delay
variation, and the other is from the receiver impairments such
as noise and jitter. In order to account for the radio impairment
only and to compare the GPS RF receivers fairly, it is desirable
to use a normalized version of noise metric such as an SNR.
However, the signal bandwidth of spread-spectrum signals like
that of the GPS is varying with the position in the receiver under
 1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005

Fig. 2. Block diagram of the entire GPS receiver.

TABLE II
GAIN AND NOISE BUDGET (L1 BAND)

consideration. Precorrelation SNRs are negative whereas post-

correlation SNRs are positive. It is convenient to normalize the
SNR to a 1-Hz bandwidth. This result is referred to as the “car-
rier-to-noise density” ratio [16]. The carrier-to-noise density can
be easily converted into or , commonly used in
communications system analysis using the following equation:

(5)

where is a raw data rate of 50 b/s for L1 C/A and 25 b/s for
L2 C/S.
Once the minimum required or is given by a
digital correlator to maintain the wanted tracking or acquisition
performance, the receiver sensitivity is uniquely determined by
(6) without any confusion caused by the bandwidth ambiguity.
Fig. 3. Effect of image rejection ratio on C=N performance.
Sensitivity in dBm
dBm C. Image Rejection
dB Hz dB
Hz With a finite image rejection ratio (IMRR), image band noise
dB dB Hz can contribute a substantial portion at the receiver output. Fortu-
nately, in GPS RF bands, even wider bandwidth than necessary
dBm for the C/A code was reserved for P code, and hence we can ex-
dB (6) ploit the low-IF architecture. This choice of low IF causes the
Hz
image signal to lie within the same GPS band; thus the receiver
where is the thermal noise power density at the antenna port need only to reject thermal noise of the unwanted side band. The
which equal to 174 dBm/Hz at typical room temperature and effective is related to the IMRR in the following equation:
NF is the noise figure of the receiver. For example, if a dig-
ital correlator requires of 25 dB Hz, in other words,
of 8 dB, and a radio has an NF of 4 dB, then the re-
ceiver sensitivity can go down to 145 dBm. In our work, an (7)
active antenna system composed of an antenna, prefilter, and a
low-noise amplifier (LNA) followed by an image rejection filter The loss due to a finite image rejection ratio is plotted in
was assumed as depicted in Fig. 2. Table II summarizes the gain Fig. 3. The result shows that an IMRR of 16 dB yields just a
and noise distribution in this work. 0.1-dB loss, which is negligible for most cases.

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 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1417

Fig. 4. Reciprocal mixing of the in-band thermal noise and phase noise.

Fig. 6. Channel filter requirement.

TABLE III
GPS RECEIVER REQUIREMENTS

Fig. 5. Effect of phase noise on C=N performance.

D. Phase Noise
The phase noise of a local oscillator also corrupts the spec-
trum and degrades the . The phase-noise requirement orig-
inates from the reciprocal mixing of the phase-noise spectrum
by the in-band thermal noise itself, as seen in Fig. 4. Multipli- or
cation in the time domain corresponds to convolution in the fre-
quency domain, and hence the added noise density due to the
phase noise is calculated by
(11)
To obtain less than 0.1-dB loss, the averaged phase noise should
be lower than 80 dBc/Hz, as seen in Fig. 5. This number is
(8) quite loose. From this fact, it can be inferred that a small-sized
ring voltage-controlled oscillator (VCO) is a promising solution
for a low cost, as presented in [7]. However, in the viewpoint of
where is the phase noise of an LO. Interestingly, the last power consumption, an LC resonator-based VCO is still advan-
integral term is equivalent to the absolute rms jitter of the local tageous.
oscillator, normalized to its period, thus,
E. Filter Bandwidth and ADC Bit Resolution
(9) Determining the filter bandwidth and the attenuation require-
ment is very straightforward. From the anti-aliasing and the
Similar to (7), the effective at the mixer output can be image rejection requirement, illustrated in Fig. 6, a simple sixth-
written by order (third-order in baseband-equivalent) band-pass filter with
2-MHz bandwidth fulfills both requirements. The degradation
of due to the ADC is dependent on three factors: the
number of quantization levels, the IF filter bandwidth, and the
(10) ratio of the maximum A/D threshold to the rms noise level [15].

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 1418 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005

Fig. 7. Block diagram of the GPS receiver.

Fig. 8. Dual-band GPS application. (a) L1/L2 selectable receiver. (b) Full dual-band receiver.

The effective at the output of a quantizer can be expressed where denotes the quantization noise power, and is the
as bandwidth of the IF filter. The typical degradation intro-
duced by a limiter is approximately 2 dB. For a 2-bit ADC with
an optimal AGC, the minimum loss of 0.7 dB can be reachable
(12) [17]. The loss is marginally worse. The receiver requirements
discussed in this section are summarized in Table III.

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 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1419

Fig. 10. Schematic of the RF mixer.

Fig. 9. Simplified schematic of the low-noise RF preamplifier.

IV. RECEIVER ARCHITECTURE

A block diagram of the L1/L2 dual-band GPS receiver is

shown in Fig. 7. Excluding a low-noise amplifier and a RF filter,
the complete analog building blocks are integrated, including
the RF preamplifier, a RF mixer, IF mixers, a variable-gain
channel-select filter, a 2-bit ADC, and a phase-locled loop
(PLL). A dual-conversion with a final low-IF architecture was
chosen based on the following reasons.
1) Both L1 and L2 frequencies can be translated into the
same first IF frequency with a LO centered at the two
frequencies.
2) This choice of the first IF causes the first IF image signal
to lie within the alternate GPS band. Thus, the required
image rejection for first the IF is quite low.
3) With a low second IF, the second IF image signal also
lies within its own GPS band. Thus, the required image
rejection for the second IF is also quite low.
4) All of the building blocks are identical for both band op-
erations
5) All LO signals for L1 and L2 can be coherently generated
from a single PLL.
The L1 or L2 signal is received by an active antenna and fil-
tered with a band-select prefilter to remove strong out-of-band
signals, which may overload the following blocks. The signal
is amplified by about 20 dB in an LNA, followed by an image
rejection filter which eliminates the first IF image noise lying at
the alternate GPS band, and then fed into the integrated receiver.
The receiver frequency plan is also presented in Fig. 7.
Thanks to the fact that in a GPS satellite the L1 and L2 fre-
quencies are generated from a single reference clock and is
an integer multiple of the chip rate (1.023 MHz), a novel
frequency plan allowing the simplest possible PLL architecture
could be proposed. The signal is first mixed down to the first
IF centered at (173.91 MHz) by the first LO signal
of (1401.51 MHz), which equals exactly the center
frequency of L1 and L2 and then down-converted to the second
IF signal centered at (1.278 75 MHz) by the second LO
signal of (175.188 75 MHz), a 1/8-divided version
of the first LO signal.
Fig. 11. Schematic of the IF mixer.
The final low-IF signal is fed into a variable-gain complex
channel filter, offering channel selection, second IF image rejec-
tion, and anti-aliasing as well as gain control. Finally, the signal
is quantized and sampled in an ADC. The ADC provides 2-bit
outputs, coded as Sign (SIGN) and Magnitude (MAG) bits to a
digital correlator chip. A charge pump-based AGC loop regu-
lates the ADC input signal such that the duty cycle of the MAG
bit is kept 33% in average by monitoring the MAG signal and
adjusting the gain of the variable-gain channel filter.
Fig. 8 shows two possible configurations of dual-band appli-
cations using the receiver architecture presented in this paper.
As seen in Fig. 8(a), this work is applicable to an L1/L2 band-se-
lectable application as well as the L1 or L2 single-band ap-
plication. Simultaneous reception of L1 and L2 with just one
receiver branch is also possible but not practical because the
noise floor increases by 3 dB due to the noise from the alter-
nate GPS (image) band. So, two independent receiver paths are
required for simultaneous reception without sensitivity degra-
dation, as depicted in Fig. 8(b). Weaver architecture, having
post-image-rejection capability, must be a possible candidate
for a full dual-band application [23]. However, it still requires a
complex hardware incorporating a quadrature RF LO, a quadra-
ture IF LO, two RF mixers, and four IF mixers.

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 1420 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005

Fig. 12. Block diagram of the IF strip.

V. CIRCUIT IMPLEMENTATION
A. RF Section
The low-noise preamplifier depicted in Fig. 9 uses a single-to-
differential architecture based on the following two reasons.
First, because we adopted a dual conversion architecture, the
first mixer should be a double-balanced mixer in order to mini-
mize the LO feed-through that will cause an unacceptably large
dc offset at the second mixer output. Second, alternatively, we
can exploit a fully differential amplifier with an external balun.
However, the external balun causes an extra gain loss and NF
increase of about 1 dB. By adopting a single-to-differential am-
plifier, we can eliminate the need of an external balun and its
performance loss.
In Fig. 9, the input stage M1 is an inductively degenerated
common source stage. M3 forms a common gate amplifier while
M2 forms a common source amplifier. If the transconductance
of M3 is equal to that of M2, then the drain current of M3 is
equal in magnitude and different in polarity to the drain current
of M2. A high-voltage gain is necessary to sufficiently reduce
the noise contribution of the following mixers. The voltage gain Fig. 13. Complex filter unit cell. (a) Gm-C implementation. (b) Pole location.
(c) Frequency response.
is
provide a gain control function. A - based complex filter
(13)
as shown in Fig. 13 was adopted. The transfer function of the
unit filter cell is
The gain of the low-noise preamplifier was specified as 21 dB,
while the requirements for both the noise figure and IIP3 were
quite moderate, with values of 6 dB and 10 dBm, respectively.
Fig. 10 shows the RF mixer. A conventional Gilbert-type (14)
mixer, with a source-grounded input stage and a current where is the midband voltage gain,
bleeding technique at the load, is used to support a high gain is the real part of the complex pole, and
as well as a low-voltage operation. The IF mixer, shown in is the image part of the complex pole. It can
Fig. 11, is almost identical to the RF mixer except that it pro- be inferred from (14) that, by controlling , we can adjust
vides quadrature outputs. Due to the high gain in the preceding the filter gain without affecting the pole location. To reduce
circuits of about 32 dB, the second mixer limits the receiver the current consumption and the number of cascaded stages,
linearity. The RF section provides total gain of 44 dB, cascaded we proposed a unit filter cell as depicted in Fig. 14. In this
noise figure of 7 dB, and IIP3 of 30 dBm. circuit, , built by nMOS transistors, and and ,
built by pMOS transistors, are sharing the dc bias current. One
B. IF Section important design consideration in a fully differential complex
Fig. 12 shows a block diagram of the IF strip. The IF strip filter is the common mode stability. In common-mode opera-
consists of four cascaded stages. The first three stages make tion, the polarity of is changed to positive. This leads
three complex poles and the two variable-transconductor stages to an unwanted positive feedback loop. Applying a negative

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 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1421

Fig. 14. Proposed variable-gain complex filter cell.

Fig. 15. Schematic of the complex load.

common mode feedback or reducing the common mode gain
[18], can help to avoid this problem. In our work, we adopt
the later method. Fig. 15 shows the final complex load circuit,
including the extra transistors for common-mode gain reduc-
tion. The common-mode rejection ratio is given by the ratio
of the common-mode conductance to the differential-mode
conductance
(15)
(16)
Fig. 16 shows a linear cell used in the first stage. A replica
circuit technique is used. The transconductance of the slave cell
is a copy of the very linear master circuit and is equal to .
The final stage in the receiver signal path is a 2-bit ADC
as illustrated in Fig. 17. Using a 2-bit converter results in a
slightly improved performance compared to that of a 1-bit con-
verter. The quantizer has a nominal input range of 500 mV
and provides a 2-bit output coded as Sign (SIGN) and Magni-
tude (MAG) bits. The AGC feedback loop, used in our work, is
similar to that used in [3].

CMRR C. Synthesizer
The synthesizer provides two LO frequencies for mixers and
a master clock signal for a digital correlator. The frequencies
(17)
are generated by an on-chip PLL including an LC VCO, a di-
vider chain, a phase-frequency detector, and a charge pump. As
Equation (17) ensures that the CMRR is far greater than 1 for seen in Figs. 7 and 18, by choosing a PLL reference frequency
the frequency band of interest. of (10.9493 MHz), the whole divider chain could

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 1422 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005

Fig. 18. Block diagram of a PLL.

Fig. 16. Schematic of the linear G cell.

Fig. 19. LC VCO topology.

Fig. 17. 2-bit ADC.

be composed of scaled version of an identical differential di-

vide-by-2 circuit.
The total current consumption of the synthesizer is 5.5 mA.
Figs. 19–21 show the LC VCO topology used in this PLL, the
measured VCO output frequency versus tuning voltage, and the
closed-loop phase-noise spectrum, respectively. The frequency Fig. 20. Measured VCO frequency.
tuning range is about 14%. Considering a possible process vari-
ation in mass production, some kind of VCO center frequency
in Fig. 22. The layout consumes 2.6 mm including the ESD
trimming should be added.
protection pads. A standard 40-pin MLF package is used. The
Although a loop filter was not integrated in this version, it
entire signal path of the chips is differential configuration ex-
will be also possible to integrate a passive loop filter on a chip,
cluding the RF preamplifier, and careful attention is paid to sym-
because the reference frequency is relatively high, that allows a
metry throughout the layout. The RF input is matched with S11
small RC time constant suitable for on-chip integration.
better than 20 dB. The measured maximum voltage gain of
the GPS receiver is 95 dB, as seen in Fig. 23, and the noise
VI. EXPERIMENTAL RESULTS figure is 8.5 dB for L1 and 7.5 dB for L2, which is slightly
The L1/L2 dual-band GPS receiver is implemented in a 1P6M higher than the simulated values, while the input third-order
0.18- m CMOS process, and a die microphotograph is shown intercept point is 30 dBm. In Fig. 23, the linear-in-decibel

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 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1423

Fig. 21. Measured VCO phase noise.

Fig. 24. Measured final IF spectrum.

Fig. 22. Die microphotograph of the complete CMOS receiver front-end chip
occupying 2.6 mm die area.

Fig. 25. Measured frequency response of the entire receiver.

TABLE IV
RADIO PERFORMANCE SUMMARY

Fig. 23. Measured AGC characteristics.

range of the VGA is just a small portion of whole control range.

Linear-in-decibel characteristics, which guarantee constant set-
tling time and stability over all gain settling, are favorable es-
pecially for a burst-mode communications receiver. However, a
GPS receiver operates continuously over several seconds after it
is powered on. Therefore, the settling time issue is less crucial.
Fig. 24 shows a typical output spectrum at the final IF stage,
the bandpass filtered signal centered at 1.279 MHz. Fig. 25
shows the frequency response of the entire radio. The signal
extends from 250 kHz to 2.25 MHz and the average image re-
jection ratio is about 20 dB. Due to a substantial dc offset pre-
sented in the IF strip, an unwanted in-band gain ripple of about
1.5 dB was observed. This receiver operates over a supply
voltage from 1.5 to 2.5 V and temperature range from 40 C

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 1424
to 90 C. It drains 10.5 mA from a 1.8-V supply at room tem-
perature. Table IV summarizes the experimental results of the
presented work.
VII. CONCLUSION
In this paper, the receiver requirements for GPS was derived
and newly specified with an appropriate metric, in a uni-
fied way, and then an integrated CMOS receiver chip based on
the dual-conversion with a low-IF architecture was implemented
for use in a L1/L2 dual-band GPS system with an external ac-
tive antenna. All required IF signal processing functions, in-
cluding gain control, image rejection, channel selection, and
anti-aliasing are successfully merged into the proposed com-
plex filter cell, reducing power consumption and die area signif-
icantly. Fabricated in a 0.18- m CMOS technology, the receiver
consumes 19 mW from a 1.8-V supply and 2.6-mm die area.
ACKNOWLEDGMENT
The authors would like to thank M. Son for her circuit layout.
They would also like to thank W. Oh for test as well as layout
assistance.
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Jinho Ko received the B.S. degree and the M.S.
degree in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1994 and 1996, re-
spectively, where he is currently working toward the
Ph.D. degree.
From 1996 to 1998, he was with the R&D Center,
SK Telecom, Daejeon, where he was involved in
designing a CMOS baseband analog processor for
CDMA cellular phones. Between 1999 and 2002,
he was with Havin’ Company, Ltd, Daejeon, where
he worked on developing a low-power CMOS Bluetooth and GPS RF-IC. In
2002, he founded PHYCHIPS Inc., Daejeon, which is focused on developing
low-power RF system-on-a-chip (SoC) solutions. His research interests include
low-power, low-cost CMOS RF-SoC for WPANs and wireless sensor networks.
Jongmoon Kim (S’00) received the B.S. degree
and the M.S. degree in electrical engineering from
Chungnam National University, Daejeon, Korea, in
1998 and 2000, respectively.
From 2000 to 2002, he was with Havin’ Company,
Ltd., Daejeon, where he was involved in designing a
CMOS Bluetooth and GPS receiver. Since 2002, he
has been with PHYCHIPS Inc., Daejeon, where he is
developing CMOS transceivers for WPANs and GPS
receivers. His research interests are in low-power RF
integrated-circuits for wireless applications.
Sanghyun Cho received the B.S. degree in electrical
engineering from Chungnam National University,
Daejeon, Korea, in 1999, where he is currently
working toward the M.S. degree in electrical engi-
neering.
From 1999 to 2002, he was with Havin’ Company,
Ltd., Daejeon, where he was involved in designing
PLL systhesizers for Bluetooth and GPS receivers.
Since 2002, he has been with PHYCHIPS Inc.,
Daejeon, where he is developing low-power PLLs
for wireless applications. His research interests
include low-power PLL architecture and circuit.
 KO et al.: 19-mW 2.6-mm L1/L2 DUAL-BAND CMOS GPS RECEIVER 1425

Kwyro Lee (S’79–M’80–SM’90) received the B.S.

degree in electronics engineering from Seoul Na-
tional University, Seoul, Korea, in 1976 and the M.S.
and Ph.D. degrees from the University of Minnesota,
Minneapolis, in 1981 and 1983, respectively.
While at the University of Minnesota, he ac-
complished a great deal of pioneering work for
characterization and modeling of AlGaAs–GaAs
heterojunction field-effect transistors. After gradua-
tion, he worked as an Engineering General Manager
with GoldStar Semiconductor, Inc., Gumi, Korea,
from 1983 to 1986, where he was responsible for development of the first
polysilicon CMOS products in Korea. He joined the Korea Advanced Institute
of Science and Technology (KAIST), Daejon, Korea, in 1987 as an Assistant
Professor with the Department of Electrical Engineering, where he is now
a Professor. He has authored and coauthored more than 150 publications in
major international journals and conferences. He is the principal author of the
book Semiconductor Device Modeling for VLSI (Englewood Cliffs, NJ: Pren-
tice-Hall, 1993) and one of the co-developers of AIM-Spice, the world’s first
SPICE run under windows. Since 1997, he has been working as the Director
of MICROS (Micro Information and Communication Remote Object-oriented
Systems) Research Center, an Engineering Center of Excellence supported by
the Korea Science and Engineering Foundation.
Prof. Lee is a Life Member of IEEK. From 1990 to 1996, he served as the Con-
ference Co-Chair of the International Semiconductor Device Research Sympo-
sium, Charlottesville, VA. From 1998 to 2000, he served as the KAIST Dean
of Research Affairs as well as the Dean of Institute Development and Cooper-
ation. During the same periods, he also served as the Chairman of IEEE Korea
Electron Device Chapter and is currently serving as the elected member of EDS
AdCom.

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