A Fast Compact CMOS Feedforward

Automatic Gain Control Circuit

J. P. Alegre, B. Calvo, S. Celma
Electronic Design Group (I3A)
University of Zaragoza
Zaragoza, Spain
{juanpa, becalvo, scelma}@unizar.es

Abstract— This paper presents a fast settling compact

feedforward automatic gain control (AGC) suitable for use in
wireless communication systems such as WLAN or Bluetooth Vin Vout
VGA
receivers where the use of traditional closed loop feedback
amplifiers forms a boundary due to the stringent settling time
constraints. The AGC has been implemented in a 0.35 μm VC
standard CMOS technology. Supplied at 1.8 V, it operates with
a power consumption of 1.6 mW at frequencies as high as 100
MHz, while its gain ranges from 0 to 18 dB. The settling time of
the circuit is below 0.25 μs.

I. INTRODUCTION
Automatic gain control (AGC) is an essential function in
modern wireless communication systems. Therefore, many
automatic gain control circuits have been proposed to date,
with attention currently being focused on their development in
CMOS technologies to attain large integration and chip-cost
reduction.
The AGC circuitry adjusts the output signal of a variable
or programmable gain amplifier to the optimal level, for
different input signal strengths. Conventional AGCs use a
closed-loop feedback technique to settle the desired output
signal amplitude, as shown in Fig. 1. However, in applications
such as WLAN or Bluetooth receivers timing constraints
preclude the use of such closed-loop AGC schemes.
Meanwhile, novel feedforward techniques have been found to
be adequate to shorten the settling time and reduce the
acquisition time of AGCs [1-3].
This paper presents an automatic gain control circuit based
on a feedforward approach. The proposed AGC circuitry
consists of a digitally programmable gain amplifier, a peak
detector and a 3-bit comparator bank. It offers low-voltage
low-power operation, low-distortion and an inherent rapid
convergence of the amplifier gain. Section II describes the
proposed AGC architecture and the circuit design of the key
function blocks. The main performances are summarized in
Section III. Finally, some preliminary conclusions are drawn
in Section IV.
Loop
Filter Vref
Figure 1. Conventional feedback AGC loop.
II. SYSTEM ARCHITECTURE
The automatic gain control described in this paper is just
the last stage of the full AGC shown in Fig. 2. The full
background AGC consists of several fixed gain amplifiers A1,
A2, … controlled by simple pass-switches with a digitally
programmable gain amplifier (PGA) at the end. Thus, the total
input dynamic range in the last stage is no more than the gain
of one of the previous amplifiers. Considering 0.4 VP-P as a
typical output voltage and 18 dB fixed gain amplifiers, the
expected input dynamic range extends from -22 to -4 dBm.
The proposed AGC is based on a feedforward technique,
which allows very fast convergence of the amplifier gain. The
circuit has a peak detector PD that extracts the signal
amplitude at the input of the PGA. This signal amplitude is
then introduced in a simple comparator array –like a flash
ADC– that directly generates the digital word to control the
PGA gain.
The following offers the circuit description and
implementation of the main blocks of the proposed AGC.

This work has been partially supported by MEC (AP-2004-5895), DGA-

FSE (T51/2005), DGA-FSE (PIP187/2005) and MEC-FEDER (TEC2005-
00285/MIC).

978-1-4244-1684-4/08/$25.00 ©2008 IEEE 1504

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 IF 71MHz 18/36/54 dB
0 to 18 dB
This work
Vin Channel Vout
PGA PGA
Filter

Mixer RMS D
D
Peak
VCO Detector Comparator
Digital Word Generator Bank
Vref

Figure 2. IF 71 MHz strip.

1.8 V

R0
IB IB ai
RL 10 kΩ 40 μ A 40 μ A 10 kΩ RL a0

+
Vout 1
VCM + vin VCM - 1 vin Vout
(W/L) (W/L)
2 M1 M1 2 MSi MSi
a1 Ri 2
10/0.5 10/0.5
Ri 4 Ri 4
M3 Vcas Vcas M3 2(W/L) 2(W/L)
IQ 2R IQ
10 μ A a2
10 μA M2 M2
M2 M2
4/0.5 4/0.5 4/0.5 4/0.5
4(W/L) 4(W/L)

(a) (b)
Figure 3. Programable gain amplifier cell: (a) Amplifier core and (b) Programmable degeneration resistance

A. Programable Gain Amplifier With respect to the degeneration resistance, we settled

for an approach which combines, in equal parts, HRP
The employed PGA, shown in Fig. 3, is based on a very resistors and MOS transistors biased in the triode region, in
simple gm-boosted source degenerated differential pair with order to preserve good linearity, moderate area
resistive loads [4]. Focusing on the transconductor core, consumption and, at the same time, facilitate digital gain
transistors M1-M2 form a two-pole negative-feedback loop control. These act simultaneously both as resistors and
that reduces the equivalent source resistance of the input switches. Following this strategy, the degeneration scheme
voltage buffer M1 down to 50 Ω [5]. Consequently, for a is shown in Fig. 3 (b). The minimum gain setting is
source-degenerated pair exploiting this approach, the imposed by a fixed high resistivity polysilicon (HRP)
differential transconductance can be expressed as Į/R, resistor Ro. The gain is then digitally increased by adding in
where Į denotes the M1 gate-to-source DC voltage gain, parallel a new linear resistor in series with two MSi NMOS
which is somewhat less than unity due to the body effect, switches biased in the triode region, whose on-resistance is
and R denotes one-half the degeneration resistance. Next, one half of the total conversion impedance. Fine gain
the linearized differential signal current, copied out by tuning can, if necessary, be performed through slight MS
loading each M2 gate terminal with a matched NMOS
gate voltage variations to improve accuracy.
device, is converted to voltage through load resistors RL.
Thereby, the differential gain of this stage is given by Į· This PGA cell, supplied at a single voltage of 1.8 V
(RL/R). with a common-mode voltage of 1.3 V, dissipates less than
The gain can be adjusted by using a variable 0.5 mW. Transistor sizes and biasing conditions are shown
degeneration resistor while maintaining a constant load in Fig. 3. The programmable degeneration impedance
resistor. This choice, adopted in this work, results in a fixed consists of a 3-bit array of hybrid NMOS-HRP resistors in
dominant pole at the PGA output nodes, and therefore a parallel, which are weighted to obtain a logarithmic gain
constant bandwidth is maintained throughout all the gain distribution ranging from 0 to 18 dB in 6 dB steps through
stages [6]. For high-frequency applications, noise a thermometer code control. Finally, to guarantee a
specifications limit the value of the load and degeneration convenient common-mode output signal, biasing currents
IQ are added to the two output nodes.
resistors to the kΩ range. Hence, a high-resistive
polysilicon (HRP) load resistor RL = 10 kΩ has been
chosen.

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 1.8 V

M4 M5 M5 M4 IB IB
IB IB IB IB
80uA 5/0.4

5/0.4 Vout
Vin+ Vin-
M1 M1 M1 M1

5/0.5
CL IL
M2 CL M2
M2 M3 1.5pF 0.5uA M3 M2
3/0.35 3/0.35

Figure 4. Peak detector cell.

B. Peak Detector III. SIMULATION RESULTS

The structure of the peak detector cell shown in Fig. 4, is a The proposed AGC has been simulated in the AMS 0.35
differential positive peak detector where, instead of a diode, a μm CMOS technology using SPECTRE. Its main
unidirectional current mirror is employed together with a performances are summarized in Table 1. The circuit
transconductor to implement the rectifier [7]. One detector is consumes 1.6 mW from a single 1.8 V supply voltage. The
employed for each balanced signal adding both signals at a gain can be varied linearly in dB from 0 to 18 dB in 6 dB
single output. The circuit works by introducing the excess steps. Higher accuracy would be easily obtained just by
current flowing through current mirrors and charging the hold increasing the bit number of the comparator bank. The
capacitor C when the Vin is larger than the Vpeak. bandwidth is kept constant around 100 MHz assuming
As can be seen in the schematic, rather than using a simple capacitive loads of 150 fF at the two outputs, see Fig. 6.
transconductor as in [7], we employ a high performance Gm
cell, based on the same core cell as the reported PGA, so that TABLE I. SUMMARY OF AGC PERFORMANCES
the peak detector exhibits higher linearity at higher
frequencies with lower power consumption. In addition, this Parameter Value
leads to very compact design. Technology 0.35 μm CMOS
Supply voltage 1.8 V
C. Gain Computation Block AGC ouput Voltage 400 mVpp,diff
Once the input signal level has been detected, the output of Frequency response 100 MHz
the envelope detector is carried to a comparator bank where it
AGC gain range 0 to 18 dB in 6 dB steps
is contrasted with a reference level, Fig. 5. In order to take into
account any change in the input common-mode DC level, and AGC settling time 0.25 μs
since the peak detector is not balanced, the reference level is THD@ 10MHz, 0.2 Vp-p out < –70 dB
generated with respect to the common-mode voltage. The
current circuit is implemented for a 3-bit gain adjustment, but In-band noise @ 0 dB 51 nV/√Hz
by simply increasing the number of comparators it is possible Power consumption 1.6 mW
to increase the number of bits. The comparators are simple
differential pairs supplied with a single 1.8 V supply voltage.
24
Vref +VCM V peak
a0 '111'
18
Comp
'011'
12

'001'
a1 6
Comp
Gain
'000'
(dB) 0

a2 -6
Comp

-12

-18 6 7 8 9
10 10 10 10
VCM frequency (Hz)

Figure 5. Comparator bank cell. Figure 6. PGA frequency response.

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 18 dB

Signal Amplitude (V)

-50
0.2
12 dB 0.1
-55
6 dB 0
THD, 10 MHz (dB)

0 dB -0.1
-60
-0.2
-65 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t (us)
-70

Signal Amplitude (V)

0.2
-75
0.1
0
-80
-0.1
0 0,2 0,4 0,6 0,8
-0.2
Vout (Vpp)
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t (us)
Figure 7. THD levels at 10 MHz for all gain settings versus output voltage
Vout. Figure 9. AGC convergence performance with an 18 dB stepwise change
input signal at 71 MHz. Input and envelope signal (up), AGC output (down).

0.09
Ideal
IV. CONCLUSIONS
0.08 Simulated This paper presents an automatic gain control circuit based
on a feedforward approach which offers very fast settling
0.07 time. The proposed architecture is very simple and can be
implemented with basic cells, obtaining at the same time high
0.06
performance characteristics. This AGC can be very useful in
Vout (V)

0.05 applications such as WLAN or Bluetooth receivers where the

0.04
0.03
0.02
0.01
0.05 0.1 0.15 0.2 0.25 0.3 0.35
Vin,p-p (V)
Figure 8. Input-output linearity of the peak detector.
The total harmonic distortion (THD) behaviour for a signal
frequency of 10 MHz is depicted in Fig. 7 considering
constant differential output levels. Figures are below –70 dB
over all the gain setting range with a differential output signal
level of 0.2 Vp-p, value that increases to –60 dB for 0.4 Vp-p.
The performance of the envelope detector is shown in Fig.
8. Deviations from ideal behaviour are below ±0.5 dB for all
the input range, so if necessary, it is possible to obtain a
similar accuracy with the AGC.
Finally, the convergence of the AGC was tested
introducing an 18 dB stepwise signal which is the maximum
change the AGC can observe due to the switch off of one of
the fix gain amplifiers just before the PGA. The results are
shown in Fig. 9. Since the AGC has a feedforward loop, the
settling time required by the AGC is equal to the one required
by the envelope detector, so the settling time is below 0.25 μs.
use of traditional closed loop feedback amplifiers forms a
boundary due to the stringent settling time constraints.
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0.4
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