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V pd = Peak (Vout ) (3) If ω e is relatively small when compared with ω gmVref / VT , the
where Peak( ) is the peak extraction function. The output of the envelope of Vout,ss1 can be approximated to Vref (steady-state
gm-C filter, which acts as a loop filter, can also be described as value), which means the overall AGC can settle within a very
short time. If ω e is large, (9) implies that the AGC cannot keep
t
1 (4) the output amplitude constant.
Vctrl = ∫ g m (Vref −Vpd )dt
C −∞
where Vctrl is integrated from the error term Vref-Vpd. II. AGC CIRCUIT SECOND-ORDER LARGE SIGNAL MODEL
Combining (1)-(4), we have A. Peak Detector Delay Model
dVctrl g m (5) The analysis in the previous section was concerned only with
= (Vref − A (1 + m cos ω et ) × α × eVctrl / VT ) the first-order (single-pole) approximation, where the pole is
dt C
only determined by the gm-C filter and there are no delays
Equation (5) describes the transient behavior of Vctrl of the anywhere else in the circuit. However, as the input frequency
first-order AGC circuit. It is a nonlinear first-order differential increases, other poles in the circuit become more important [10].
equation and is difficult to solve directly. However, (5) can be Therefore, a second-order large-signal model is proposed here,
simplified by substituting u = eVctrl / VT and then: which takes into account the other poles associated with the peak
detector.
1 du g m Vref 1 g A × α (1 + m cos ωet ) (6)
− =− m Consider the peak detector delay model in Fig. 2, where the
u 2 dt C VT u C VT
input signal is A cos(ω t ) and ω p is the angular frequency of the
Equation (6) is known as the Bernoulli Equation [9] and can
be solved as associated pole. In steady state, the output of the peak detector
delay block, Vdout(t), can be calculated by the Inverse Laplace
−1
Transform of Vdout(s) as follows:
ωgmVref
(7)
ω A × α m cos(ωet − φ ) Aα − t Aω p ω (10)
u = gm + + Pe VT Vdout (t ) = cos(ωt − ϕd ),φd = tan−1 ( )
VT ω V Vref
2
ω + ωp
2 2 ωp
ωe2 + gm ref
VT
g m and P is the integration constant. B. Second-order Steady-state Behavior
where φ = tan −1 CVT ωe , ω =
gm
C If we insert the above delay block between the output of the
g mVref
PD and the input to gm-C filter to model the delay associated
Finally, the control voltage Vctrl can be obtained by applying with the PD, as shown in Fig. 3, the input of gm-C filter can be
Vctrl = VT ln u and solved explicitly as calculated by combining (2) and (3), and be re-written as
mω p cos(ωet − ϕd )
(11)
Vgmc = Aα evctrl / VT u (t ) − e p +
−ω t
(8)
ω gm A × α
ωgmVref
t
ω 2
+ ω 2
m cos(ωe t − φ ) Aα −
VT e p
Vctrl = −VT ln + + Pe
VT ω V Vref
2
−ω t
ωe 2 + gm ref In steady state, the e p term can be ignored. By substituting Vpd
VT with Vgmc and solving (1), (2), (4), and (11), the steady-state
value of Vctrl can be obtained as:
B. First-order Steady-state Behavior
ω gmVref ω gmω p mA α
− t (12)
In steady state, the Pe V term in (8) can be neglected and
T
ωe VT ωe + ω p A α
2 2
Vout can also be solved explicitly by combining and substituting Vctrl ,ss 2 = −VT ln [cos(ωet − ϕt )] +
ωgmVref
2 Vref
Vctrl of (8) into (1) and (3). + 1
ωeVT
(9)
(1 + m cos ωet )
Vout , ss1 = V cos ωct
m cos(ωe t − φ ) ref
1+
2
ωeVT Aω p cos(ωt − ϕd )
+ 1 Vdin (t ) = A cos(ωt ) Vdout (t ) =
ω gmVref
Delay Block
ω 2 + ωp2
ωp
A× s A× s ωp
Vdin ( s ) = s + ωp Vdout ( s ) = 2
s2 + ω2 s + ω2 s + ωp
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III. AGC LOOP SETTLING TIME
Vctrl
Vgmc Vin = A1 (1 + k × u (t ))cos ωct (13)
Gm
Vref
Where u(t) is the unit-step function and k is the input amplitude
C
variation factor. The first-order Vctrl transient response with
respect to input unit-step response is
Fig.3. Second-order AGC circuit block diagram. The dotted area represents the Vref k −(
ω gmVref
t)
(14)
new peak detector model including the delay of the peak detector. Vctrl , sr1 = VT ln( ) − ln(1 − ( )e VT )
A1 (1 + k )α 1+ k
where ϕ = tan −1 ωeVT + tan −1 ( ωe ) . When ω p is much greater and Vout can be solved by substituting (14) into (1)
t
ωgmVref ωp Vref cos ωc t (15)
Vout ,sr1 =
than ω e , (12) reduces to (8) as expected. k −(
ωgmVref
t)
1− ( )e VT
In a similar manner to Section II, Vout and Vpd can also be 1+ k
expressed explicitly by combining and substituting Vctrl of (12) Then the 1% settling time Ts [12] of the Vout,sr1’s envelope can
into (1) and (3). Equation (12) also shows that the loop’s overall be solved as
response could be severely impeded by a low ω e (corresponding VT k + 100 (16)
Ts = ln
to excessive loop delay). To validate our theory, the Vpd root ωgmVref k + 1
mean square error percentage with respect to (ωe/ ωp), from Not surprisingly, (16) shows that the settling time is not only
SPICE simulation and calculation, is shown in Fig. 4. It can be a function of ω gmVref / VT , but also a function of input amplitude
seen that the error percentage increases when (ωe/ ωp) increases, variation ratio k.
and calculation and simulation results agree closely.
B. Second-order AGC Circuit Settling Time Calculation
Similarly, the second-order AGC circuit settling time can
also be calculated by applying a unit step response to the circuit
in Fig.3. The second-order Vctrl transient response with respect to
80
input unit-step response can be shown as follows:
Root mean square error (%)
60
(17)
Theory
(wgm=40MHz)
Simulation Vref
(wgm=40MHz)
A1α (1 + k )
Vctrl , sr 2 (t ) = VT ln
40 ω VT
p
Vref ωgm
−ω t
e p ωgmVref 1 − VT t
1 + ω V − − e
ωV 1+ k
p T
−1 p T −1
20 ω gmVref ωgmVref
Theory
Simulation
where ωp represents the pole angular frequency of peak detector.
(wgm=80MHz)
(wgm=80MHz) Substituting (17) into (1) and (3), the envelope of Vout, Vpd , then
0 becomes
0.001 0.01 0.1 1
we/wp
Fig.4. Second-order AGC circuit root mean square error percentage vs.
(ωe/ωp) from SPICE simulation and theory . The error percentage increases
when ωe increases. Simulation parameters: VT=0.6V, ωc=2GHz, Vref=0.24V,
A=1mV, gm=0.5mS and 1mS, C=2pF, α=0.1, m=0.9.
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(18) V. CONCLUSION
Vref An exact dynamic model of linear-in-dB Automatic Gain
Vpd , sr 2 (t ) = Control (AGC) circuit is proposed and validated. The explicit
ω pVT
−ω p t
ω V
Vref ωgm steady-state behavior and the overall loop settling time are
1 + e 1 − t
− ( gm ref − )e VT calculated for first-order and second-order AGC loops. The
ω pVT ω pVT 1+ k
ω V − 1 ω V −1 analysis shows that the overall loop settling time depends on the
gm ref gm ref input amplitude ratio, phase detector delay, and other loop
The settling time Ts is difficult to be expressed explicitly from parameters. This exact large-signal model can also be used for
(18) but it can be solved iteratively. Equation (18) shows that the the design of wideband closed-loop polar transmitters.
transient behavior is a function of ω gmVref / VT , input amplitude
variation ratio k and peak detector pole ωp. If ωp is very low, the REFERENCES
Vpd settling response is dominated by ωp rather than ω gmVref / VT .
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Settling Time Ts (ns)
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