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Data Sheet
64/80-Pin High-Performance,
256 Kbit to 1 Mbit Enhanced Flash
Microcontrollers with A/D
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
64-Pin TQFP
RE7/CCP2(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE2/CS
RE3
RE4
RE5
RE6
VDD
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RE1/WR 1 48 RB0/INT0
RE0/RD 2 47 RB1/INT1
RG0/CCP3 3 46 RB2/INT2
RG1/TX2/CK2 4 45 RB3/INT3
RG2/RX2/DT2 5 44 RB4/KBI0
RG3/CCP4 6 43 RB5/KBI1/PGM
MCLR/VPP 7 PIC18F6520 42 RB6/KBI2/PGC
RG4/CCP5 8 41 VSS
PIC18F6620
VSS 9 40 OSC2/CLKO/RA6
PIC18F6720 OSC1/CLKI
VDD 10 39
RF7/SS 11 38 VDD
RF6/AN11 12 37 RB7/KBI3/PGD
RF5/AN10/CVREF 13 36 RC5/SDO
RF4/AN9 14 35 RC4/SDI/SDA
RF3/AN8 15 34 RC3/SCK/SCL
RF2/AN7/C1OUT 16 33 RC2/CCP1
31
18
17
29
30
32
19
20
21
22
23
24
25
26
27
28
RF0/AN5
RF1/AN6/C2OUT
RA5/AN4/LVDIN
RC1/T1OSI/CCP2(1)
RC6/TX1/CK1
RC7/RX1/DT1
RA3/AN3/VREF+
RC0/T1OSO/T13CKI
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
AVSS
VSS
AVDD
VDD
RA4/T0CKI
80-Pin TQFP
RE7/CCP2/AD15(2)
RD0/PSP0/AD0(3)
RD1/PSP1/AD1(3)
RD2/PSP2/AD2(3)
RD3/PSP3/AD3(3)
RD4/PSP4/AD4(3)
RD5/PSP5/AD5(3)
RD6/PSP6/AD6(3)
RD7/PSP7/AD7(3)
RE2/CS/AD10(3)
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RH0/A16
RH1/A17
RJ0/ALE
RJ1/OE
VDD
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RH2/A18 1 60 RJ2/WRL
RH3/A19 2 59 RJ3/WRH
RE1/WR/AD9(3) 3 58 RB0/INT0
RE0/RD/AD8(3) 4 57 RB1/INT1
RG0/CCP3 5 56 RB2/INT2
RG1/TX2/CK2 6 55 RB3/INT3/CCP2(1)
RG2/RX2/DT2 7 54 RB4/KBI0
RG3/CCP4 8 53 RB5/KBI1/PGM
MCLR/VPP 9 PIC18F8520 52 RB6/KBI2/PGC
RG4/CCP5 10 51 VSS
VSS
PIC18F8620 OSC2/CLKO/RA6
11 50
VDD 12 PIC18F8720 49 OSC1/CLKI
RF7/SS 13 48 VDD
RF6/AN11 14 47 RB7/KBI3/PGD
RF5/AN10/CVREF 15 46 RC5/SDO
RF4/AN9 16 45 RC4/SDI/SDA
RF3/AN8 17 44 RC3/SCK/SCL
RF2/AN7/C1OUT 18 43 RC2/CCP1
RH7/AN15 19 42 RJ7/UB
RH6/AN14 20 41 RJ6/LB
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RF0/AN5
RF1/AN6/C2OUT
RJ4/BA0
RA2/AN2/VREF-
RJ5/CE
RA5/AN4/LVDIN
RC1/T1OSI/CCP2(1)
RC6/TX1/CK1
RC7/RX1/DT1
RA3/AN3/VREF+
AVSS
VSS
AVDD
VDD
RA4/T0CKI
RH5/AN13
RH4/AN12
RA1/AN1
RA0/AN0
RC0/T1OSO/T13CKI
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer<21> Data Latch
21 RA2/AN2/VREF-
8 8 RA3/AN3/VREF+
Data RAM RA4/T0CKI
21 inc/dec logic
RA5/AN4/LVDIN
Address Latch RA6
21 PCLATU PCLATH 12 PORTB
RB0/INT0
Address<12>
PCU PCH PCL RB1/INT1
Program Counter 4 12 4 RB2/INT2
BSR
RB3/INT3
Address Latch FSR0 Bank0, F
RB4/KBI0
31 Level Stack FSR1 RB5/KBI1/PGM
Program Memory FSR2
12 RB6/KBI2/PGC
RB7/KBI3/PGD
Data Latch
inc/dec
Decode logic
Table Latch PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
16 8
RC2/CCP1
ROM Latch
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
IR
RC6/TX1/CK1
RC7/RX1/DT1
8
PORTD
PRODH PRODL
RD7/PSP7:RD0/PSP0
Instruction
Decode & 8 x 8 Multiply
Control 3 8
PORTE
RE0/RD
BITOP WREG RE1/WR
Power-up 8 8
OSC2/CLKO 8 RE2/CS
Timer
OSC1/CLKI RE3
Timing Oscillator 8 RE4
Generation Start-up Timer RE5
Power-on ALU<8> RE6
Reset RE7/CCP2
Watchdog 8 PORTF
Timer
Precision RF0/AN5
Band Gap Brown-out
RF1/AN6/C2OUT
Reference Reset
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
MCLR/VPP VDD, VSS RF6/AN11
RF7/SS
PORTG
Synchronous Data RG0/CCP3
Serial Port USART1 USART2 EEPROM RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
BOR
Timer0 Timer1 Timer2 Timer3 Timer4
LVD
10-bit
Comparator CCP1 CCP2 CCP3 CCP4 CCP5
A/D
RB1/INT1
Address<12>
PCU PCH PCL RB2/INT2
Program Counter 4 12 4 RB3/INT3/CCP2
BSR
RB4/KBI0
Address Latch FSR0 Bank0, F
RB5/KBI1/PGM
31 Level Stack FSR1 RB6/KBI2/PGC
Program Memory FSR2
12 RB7/KBI3/PGD
Data Latch PORTC
inc/dec RC0/T1OSO/T13CKI
Decode logic RC1/T1OSI/CCP2
Table Latch
RC2/CCP1
RC3/SCK/SCL
16 8
RC4/SDI/SDA
ROM Latch
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
IR
AD15:AD0, A19:A16(1) PORTD
8 RD7/PSP7/AD7:
RD0/PSP0/AD0
PORTJ
RJ0/ALE
RJ1/OE
BOR RJ2/WRL
Timer0 Timer1 Timer2 Timer3 Timer4 RJ3/WRH
LVD
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
In XT, LP, HS or HS+PLL Oscillator modes, a crystal or 2: When operating below 3V VDD, or when
ceramic resonator is connected to the OSC1 and using certain ceramic resonators at any
OSC2 pins to establish oscillation. Figure 2-1 shows voltage, it may be necessary to use high
the pin connections. gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.
The PIC18FXX20 oscillator design requires the use of
a parallel cut crystal. 3: Since each resonator/crystal has its own
characteristics, the user should consult
Note: Use of a series cut crystal may give a fre- the resonator/crystal manufacturer for
quency out of the crystal manufacturer’s appropriate values of external
specifications. components, or verify oscillator
performance.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)
C1(1) OSC1
To
Internal
XTAL Logic
RF(3)
Sleep
RS(2)
C2(1) OSC2 PIC18FXX20
Phase
OSC2 Comparator
FIN
Loop VCO
Crystal FOUT Filter
Osc
SYSCLK
MUX
OSC1 Divide by 4
PIC18FXX20
Main Oscillator
OSC2
TOSC/4
Sleep 4 x PLL
TOSC TSCLK
MUX
OSC1
Timer1 Oscillator
TT1P
T1OSO
T1OSCEN Clock
Enable Source
T1OSI Oscillator
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
TT1P
T1OSI 1 2 3 4 5 6 7 8
TSCS
OSC1
Internal TOSC
System
Clock TDLY
SCS
(OSCCON<0>)
Program PC PC + 2 PC + 4
Counter
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switch- If the main oscillator is configured for an external
ing from the Timer1 oscillator to the main oscillator will crystal (HS, XT, LP), then the transition will take place
depend on the mode of the main oscillator. In addition after an oscillator start-up time (TOST) has occurred. A
to eight clock cycles of the main oscillator, additional timing diagram, indicating the transition from the
delays may take place. Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
TT1P
T1OSI
OSC1 1 2 3 4 5 6 7 8
TOST TSCS
OSC2
TOSC
Internal
System Clock
SCS
(OSCCON<0>)
Program
PC PC + 2 PC + 6
Counter
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T1OSI
OSC1
TOST
TPLL
OSC2
TOSC TSCS
PLL Clock
1 2 3 4 5 6 7 8
Input
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter PC PC + 2 PC + 4
If the main oscillator is configured in the RC, RCIO, EC indicating the transition from the Timer1 oscillator to the
or ECIO modes, there is no oscillator start-up time-out. main oscillator for RC, RCIO, EC and ECIO modes, is
Operation will resume after eight cycles of the main shown in Figure 2-11.
oscillator have been counted. A timing diagram,
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TT1P
T1OSI TOSC
OSC1 1 2 3 4 5 6 7 8
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program
Counter PC PC + 2 PC + 4
RESET Instruction
External Reset
MCLR WDT
Time-out
WDT Reset
Module
Sleep
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter R Q
OSC1
PWRT
On-chip
10-bit Ripple Counter
RC OSC(1)
Enable PWRT
Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
HS with PLL enabled(1) 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC + 2 ms
+ 2ms + 2 ms + 2 ms
HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms(2) + 1024 TOSC 1024 TOSC
(2)
EC 72 ms 1.5 µs 72 ms 1.5 µs(3)
(2)
External RC 72 ms — 72 ms —
Note 1: 2 ms is the nominal time required for the 4xPLL to lock.
2: 72 ms is the nominal power-up timer delay, if implemented.
3: 1.5 µs is the recovery time from Sleep. There is no recovery time from oscillator switch.
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program RCON
Condition RI TO PD POR BOR STKFUL STKUNF
Counter Register
Power-on Reset 0000h 0--1 1100 1 1 1 0 0 u u
MCLR Reset during normal 0000h 0--u uuuu u u u u u u u
operation
Software Reset during normal 0000h 0--0 uuuu 0 u u u u u u
operation
Stack Full Reset during normal 0000h 0--u uu11 u u u u u u 1
operation
Stack Underflow Reset during 0000h 0--u uu11 u u u u u 1 u
normal operation
MCLR Reset during Sleep 0000h 0--u 10uu u 1 0 u u u u
WDT Reset 0000h 0--u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 u--u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0--1 11u0 1 1 1 1 0 u u
(1)
Interrupt wake-up from Sleep PC + 2 u--u 00uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
IINTERNAL POR
TPWRT
PLL TIME-OUT
INTERNAL RESET
PC<20:0>
CALL,RCALL,RETURN 21
RETFIE,RETLW
Stack Level 1
•
•
•
Stack Level 31
01FFFFh
020000h
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value after erase ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
External
Program Reads
Memory ‘0’s
External External
Program Program
Memory Memory
Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes(1)
Available
Device Boot Boot+1 Boundary Boundary+1
Memory Mode(s)
PIC18F6520 0007FFh 000800h 007FFFh 008000h MC
PIC18F6620 0001FFh 000200h 00FFFFh 010000h MC
PIC18F6720 0001FFh 000200h 01FFFFh 020000h MC
PIC18F8520 0007FFh 000800h 007FFFh 008000h MP, MPBB, MC, EMC
PIC18F8620 0001FFh 000200h 00FFFFh 010000h MP, MPBB, MC, EMC
PIC18F8720 0001FFh 000200h 01FFFFh 020000h MP, MPBB, MC, EMC
Note 1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC+2 PC+4
OSC2/CLKO
(RC mode)
Execute INST (PC-2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+2)
Fetch INST (PC+4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
4.7 Instructions in Program Memory word boundaries, the data contained in the instruction
is a word address. The word address is written to
The program memory is addressed in bytes. Instruc- PC<20:1>, which accesses the desired byte address in
tions are stored as two bytes or four bytes in program program memory. Instruction #2 in Figure 4-5 shows
memory. The Least Significant Byte of an instruction how the instruction “GOTO 000006h” is encoded in the
word is always stored in a program memory location program memory. Program branch instructions, which
with an even address (LSB = 0). Figure 4-5 shows an encode a relative address offset, operate in the same
example of how instruction words are stored in the pro- manner. The offset value stored in a branch instruction
gram memory. To maintain alignment with instruction represents the number of single-word instructions that
boundaries, the PC increments in steps of 2 and the the PC will be offset by. Section 24.0 “Instruction Set
LSB will always read ‘0’ (see Section 4.4 “PCL, Summary” provides further details of the instruction
PCLATH and PCLATU”). set.
The CALL and GOTO instructions have an absolute
program memory address embedded into the
instruction. Since instructions are always stored on
Word Address
LSB = 1 LSB = 0 ↓
Program Memory 000000h
Byte Locations → 000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
00h 000h
= 0000 Access RAM
05Fh
Bank 0 060h
FFh GPRs
0FFh
00h 100h
= 0001 GPRs
Bank 1
FFh 1FFh
00h 200h
= 0010
Bank 2 GPRs
FFh 2FFh
= 0011 00h 300h
• Bank 3
• GPRs
•
to
Bank 6
= 0110 Access Bank
FFh 6FFh 00h
00h 700h Access RAM Low
= 0111 5Fh
Bank 7 GPRs
FFh Access RAM High 60h
7FFh (SFRs)
800h FFh
= 1000
00h 000h
= 0000 Access RAM
05Fh
Bank 0 060h
FFh GPRs
0FFh
00h 100h
= 0001 GPRs
Bank 1
FFh 1FFh
00h 200h
= 0010
Bank 2 GPRs
FFh 2FFh
00h 300h
= 0011
Bank 3 GPRs
FFh 3FFh
400h
= 0100
Bank 4 GPRs Access Bank
4FFh 00h
500h Access RAM Low
= 0101 5Fh
Access RAM High 60h
(SFRs) FFh
• Bank 5
• to
Bank 13
• GPRs
When a = 0,
the BSR is ignored and the
= 1101 Access Bank is used.
The first 96 bytes are General
DFFh Purpose RAM (from Bank 0).
00h E00h The second 160 bytes are
= 1110
Bank 14 GPRs Special Function Registers
FFh EFFh (from Bank 15).
00h F00h
= 1111 Unused F5Fh
Bank 15 F60h
FFh SFRs
FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
LATJ(3) Read PORTJ Data Latch, Write PORTJ Data Latch xxxx xxxx 35, 125
LATH(3) Read PORTH Data Latch, Write PORTH Data Latch xxxx xxxx 35, 122
LATG — — — Read PORTG Data Latch, Write PORTG Data Latch ---x xxxx 35, 120
LATF Read PORTF Data Latch, Write PORTF Data Latch xxxx xxxx 35, 117
LATE Read PORTE Data Latch, Write PORTE Data Latch xxxx xxxx 35, 114
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 35, 111
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 35, 109
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 35, 106
LATA — LATA6(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 35, 103
PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 36, 125
PORTH(3) Read PORTH pins, Write PORTH Data Latch xxxx xxxx 36, 122
PORTG — — — Read PORTG pins, Write PORTG Data Latch ---x xxxx 36, 120
PORTF Read PORTF pins, Write PORTF Data Latch xxxx xxxx 36, 117
PORTE Read PORTE pins, Write PORTE Data Latch xxxx xxxx 36, 114
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 36, 111
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 36, 109
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 36, 106
PORTA — RA6(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 36, 103
TMR4 Timer4 Register 0000 0000 36, 148
PR4 Timer4 Period Register 1111 1111 36, 148
T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 36, 147
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 36, 151,
152
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 36, 151,
152
CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 0000 0000 36, 149
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 36, 151,
152
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 36, 151,
152
CCP5CON — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 0000 0000 36, 149
SPBRG2 USART2 Baud Rate Generator 0000 0000 36, 205
RCREG2 USART2 Receive Register 0000 0000 36, 206
TXREG2 USART2 Transmit Register 0000 0000 36, 204
TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 36, 198
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 36, 199
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.
• Intermediate computational values BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
• Local variables of subroutines
writes will have no effect.
• Faster context saving/switching of variables
A MOVLB instruction has been provided in the
• Common variables
instruction set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
The Access Bank is comprised of the upper 160 bytes read will return all ‘0’s and all writes are ignored. The
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0. Status register bits will be set/cleared as appropriate for
These two sections will be referred to as Access RAM the instruction performed.
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas. Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in A MOVFF instruction ignores the BSR, since the 12-bit
the Access Bank. This bit is denoted by the ‘a’ bit (for addresses are embedded into the instruction word.
access bit). Section 4.12 “Indirect Addressing, INDF and FSR
When forced in the Access Bank (a = 0), the last Registers” provides a description of indirect address-
address in Access RAM Low is followed by the first ing, which allows linear addressing of the entire RAM
address in Access RAM High. Access RAM High maps space.
the Special Function Registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
Direct Addressing
BSR<3:0> 7 From Opcode(3) 0
Data
Memory(1)
0h
RAM
Instruction
Executed
Opcode Address
FFFh
12
BSR<3:0> 12 12
Instruction
4 8
Fetched
Opcode File FSR
Indirect Addressing
11 FSR Register 0
Location Select
0000h
Data
Memory(1)
0FFFh
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Instruction: TBLRD*
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Instruction: TBLWT*
Program Memory
Holding Registers
Table Pointer(1) Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5 “Writing to Flash Program Memory”.
5.2 Control Registers The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
Several control registers are used in conjunction with operation is initiated on the next WR command. When
the TBLRD and TBLWT instructions. These include the: FREE is clear, only writes are enabled.
• EECON1 register The WREN bit, when set, will allow a write operation.
• EECON2 register On power-up, the WREN bit is clear. The WRERR bit is
• TABLAT register set when a write operation is interrupted by a MCLR
• TBLPTR registers Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
5.2.1 EECON1 AND EECON2 REGISTERS WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EECON1 is the control register for memory accesses.
EEADR), due to Reset values of zero.
EECON2 is not a physical register. Reading EECON2
The WR control bit, initiates write operations. The bit
will read all ‘0’s. The EECON2 register is used
cannot be cleared, only set, in software; it is cleared in
exclusively in the memory write and erase sequences.
hardware at the completion of the write operation. The
Control bit EEPGD determines if the access will be a inability to clear the WR bit in software prevents the
program or data EEPROM memory access. When accidental or premature termination of a write
clear, any subsequent operations will operate on the operation.
data EEPROM memory. When set, any subsequent
operations will operate on the program memory. Note: Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
Control bit CFGS determines if the access will be to the
be cleared in software.
configuration/calibration registers, or to program
memory/data EEPROM memory. When set, subse-
quent operations will operate on configuration regis-
ters, regardless of EEPGD (see Section 23.0 “Special
Features of the CPU”). When clear, memory selection
access is determined by EEPGD.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD* TBLPTR is not modified
TBLWT*
TBLRD*+ TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*- TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+* TBLPTR is incremented before the read/write
TBLWT+*
ERASE – TBLPTR<20:6>
WRITE – TBLPTR<21:3>
READ – TBLPTR<21:0>
Program Memory
TABLAT
Write Register
8 8 8 8
Program Memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
D<7:0>
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
PIC18F8X20
AD<7:0> 373 A<20:1> JEDEC Word
A<x:0>
EPROM Memory
D<15:0>
D<15:0>
CE OE WR(1)
AD<15:8>
373
ALE
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
PIC18F8X20
A<20:1>
AD<7:0> 373 A<x:1> JEDEC Word
Flash Memory
D<15:0>
D<15:0>
AD<15:8> 138 CE
373 A0
ALE BYTE/WORD OE WR(1)
A<19:16>
OE
WRH
WRL A<20:1>
A<x:1> JEDEC Word
BA0 SRAM Memory
I/O
D<15:0>
CE D<15:0>
LB LB
UB UB OE WR(1)
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
FIGURE 6-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Apparent Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q4 Q4 Q4
Actual Q Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BA0
ALE
OE
CE ‘0’ ‘0’
1 TCY Wait
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A<19:16> 0Ch
CE
ALE
OE
Instruction
INST(PC-2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW
Execution
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
CE
ALE
OE
Memory
Opcode Fetch Opcode Fetch Sleep Mode, Bus Inactive
Cycle
SLEEP MOVLW 55h
from 007554h from 007556h
Instruction
Execution INST(PC-2) SLEEP
The EEPROM data memory allows byte read and write. Control bits, RD and WR, initiate read and write opera-
When interfacing to the data memory block, EEDATA tions, respectively. These bits cannot be cleared, only
holds the 8-bit data for read/write. EEADR and set, in software. They are cleared in hardware at the
EEADRH hold the address of the EEPROM location completion of the read or write operation. The inability
being accessed. These devices have 1024 bytes of to clear the WR bit in software prevents the accidental
data EEPROM with an address range from 00h to or premature termination of a write operation.
3FFh. The WREN bit, when set, will allow a write operation.
The EEPROM data memory is rated for high erase/ On power-up, the WREN bit is clear. The WRERR bit is
write cycles. A byte write automatically erases the loca- set when a write operation is interrupted by a MCLR
tion and writes the new data (erase-before-write). The Reset or a WDT Time-out Reset during normal opera-
write time is controlled by an on-chip timer. The write tion. In these situations, the user can check the
time will vary with voltage and temperature, as well as WRERR bit and rewrite the location. It is necessary to
from chip to chip. Please refer to parameter D122 (see reload the data and address registers (EEDATA and
Section 26.0 “Electrical Characteristics”) for exact EEADR) due to the Reset condition forcing the
limits. contents of the registers to zero.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
7.4 Writing to the Data EEPROM should be kept clear at all times, except when updating
Memory the EEPROM. The WREN bit is not cleared
by hardware
To write an EEPROM data location, the address must
After a write sequence has been initiated, EECON1,
first be written to the EEADRH:EEADR register pair
EEADRH, EEADR and EEDATA cannot be modified.
and the data written to the EEDATA register. Then the
The WR bit will be inhibited from being set unless the
sequence in Example 7-2 must be followed to initiate
WREN bit is set. Both WR and WREN cannot be set
the write cycle.
with the same instruction.
The write will not initiate if the above sequence is not
At the completion of the write cycle, the WR bit is
exactly followed (write 55h to EECON2, write AAh to
cleared in hardware and the EEPROM Write Complete
EECON2, then set WR bit) for each byte. It is strongly
Interrupt Flag bit (EEIF) is set. The user may either
recommended that interrupts be disabled during this
enable this interrupt, or poll this bit. EEIF must be
code segment.
cleared by software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
XXXXIF IPEN
XXXXIE GIEL/PEIE
XXXXIP
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
INT1IF
Additional Peripheral Interrupts INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
RD LATA RD LATA
Data
Bus Data
D Q Bus D Q
WR LATA VDD WR LATA
or or
PORTA PORTA
CK Q P CK Q I/O pin(1)
N
Data Latch Data Latch
D Q
N I/O pin(1) D Q VSS
WR TRISA Schmitt
WR TRISA VSS CK Q
CK Q Trigger
Analog TRIS Latch Input
TRIS Latch Input
Mode Buffer
RD TRISA
RD TRISA TTL
Input
Buffer
Q D Q D
ENEN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
To A/D Converter and LVD Modules
Data Bus
RD LATA
D Q
VDD
WR LATA or PORTA
CK Q P
Data Latch
N I/O pin(1)
D Q
WR TRISA VSS
CK Q
TRIS Latch
TTL
RD TRISA Input
Buffer
ECRA6 or RCRA6 Enable
Q D
EN
RD PORTA
EXAMPLE 10-2: INITIALIZING PORTB The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
CLRF PORTB ; Initialize PORTB by
loses the I/O function and become a programming test
; clearing output
; data latches
function.
CLRF LATB ; Alternate method Note: When LVP is enabled, the weak pull-up on
; to clear output
RB5 is disabled.
; data latches
MOVLW 0xCF ; Value used to
; initialize data FIGURE 10-5: BLOCK DIAGRAM OF
; direction RB7:RB4 PINS
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs VDD
; RB<7:6> as inputs RBPU(2) Weak
P Pull-up
Data Latch
Each of the PORTB pins has a weak internal pull-up. A Data Bus
D Q
single control bit can turn on all the pull-ups. This is WR LATB I/O pin(1)
or PORTB
performed by clearing bit RBPU (INTCON2<7>). The CK
weak pull-up is automatically turned off when the port TRIS Latch
pin is configured as an output. The pull-ups are D Q
disabled on a Power-on Reset.
WR TRISB TTL
CK Input
Note: On a Power-on Reset, these pins are Buffer ST
configured as digital inputs. Buffer
RD TRISB
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB RD LATB
bit must be set to ‘1’. Latch
Q D
The other four PORTB pins (RB7:RB4) have an inter-
RD PORTB
rupt-on-change feature. Only pins configured as inputs Q1
EN
can cause this interrupt to occur (i.e., any RB7:RB4 pin Set RBIF
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
Q D
are compared with the old value latched on the last RD PORTB
read of PORTB. The “mismatch” outputs of RB7:RB4 From other EN
are OR’ed together to generate the RB Port Change RB7:RB4 pins Q3
Interrupt with Flag bit, RBIF (INTCON<0>). RB7:RB5 in Serial Programming Mode
This interrupt can wake the device from Sleep. The Note 1: I/O pins have diode protection to VDD and VSS.
user, in the Interrupt Service Routine, can clear the 2: To enable weak pull-ups, set the appropriate TRIS bit(s)
interrupt in the following manner: and clear the RBPU bit (INTCON2<7>).
TRIS Latch
D Q
TTL
WR TRIS Input
CK Buffer
RD TRIS
Q D
RD Port
EN
INTx
RD TRISB
RD LATB
Q D
RD PORTB
EN
RD PORTB
CCP2 or INT3
Schmitt Trigger
Buffer
CCP2MX = 0
P
RD LATC 1
Data Bus
D Q
WR LATC or I/O pin(1)
CK Q
WR PORTC
Data Latch N TRIS OVERRIDE
D Q Pin Override Peripheral
TRIS VSS
WR TRISC Q
CK Override RC0 Yes Timer1 Osc for
Logic Timer1/Timer3
TRIS Latch
RC1 Yes Timer1 Osc for
RD TRISC Timer1/Timer3,
Schmitt CCP2 I/O
Peripheral Output Trigger RC2 Yes CCP1 I/O
Enable(2)
Q D RC3 Yes SPI/I2C
Master Clock
EN
RC4 Yes I2C Data Out
RD PORTC
RC5 Yes SPI Data Out
Peripheral Data In
RC6 Yes USART1 Async
Xmit, Sync Clock
Note 1: I/O pins have diode protection to VDD and VSS. RC7 Yes USART1 Sync
2: Peripheral Output Enable is only active if Peripheral Select is active. Data Out
PORTD/CCP1 Select
PSPMODE
RD LATD
D Q
I/O pin(1)
WR TRISD
CK Q 0 N
TRIS Latch
PSP Write
1 VSS
TTL Buffer
RD TRISD
1
Q D
0
RD PORTD ENEN Schmitt Trigger
0
Input Buffer
PSP Read
1
Q D
EN
EN
RD PORTD
RD LATD
Data Latch
D Q
WR TRISD TTL
CK Input
TRIS Latch Buffer
RD TRISD
Bus Enable
System Bus Data/TRIS Out
Control
Drive Bus
Instruction Register
Instruction Read
P
RD LATE 1 I/O pin(1)
Data Bus D Q
WR LATE
or WR PORTE CK Q
Data Latch N
D Q TRIS OVERRIDE
VSS
WR TRISE CK Q TRIS
Pin Override Peripheral
Override
TRIS Latch RE0 Yes External Bus
RE1 Yes External Bus
RD TRISE
Schmitt RE2 Yes External Bus
Peripheral Enable Trigger RE3 Yes External Bus
Q D RE4 Yes External Bus
RE5 Yes External Bus
EN
RE6 Yes External Bus
RD PORTE
RE7 Yes External Bus
Peripheral Data In
Q D
EN
EN
RD PORTE
RD LATE
Data Latch
D Q
WR TRISE TTL
CK Input
TRIS Latch Buffer
RD TRISE
Bus Enable
System Bus Data/TRIS Out
Control
Drive Bus
Instruction Register
Instruction Read
RE0/RD/AD8 bit 0 ST/TTL(1) Input/output port pin, read control for Parallel Slave Port or
address/data bit 8
For RD (PSP Control mode):
1 = Not a read operation
0 = Read operation, reads PORTD register (if chip selected)
RE1/WR/AD9 bit 1 ST/TTL(1) Input/output port pin, write control for Parallel Slave Port or
address/data bit 9
For WR (PSP Control mode):
1 = Not a write operation
0 = Write operation, writes PORTD register (if chip selected)
RE2/CS/AD10 bit 2 ST/TTL(1) Input/output port pin, chip select control for Parallel Slave Port or
address/data bit 10
For CS (PSP Control mode):
1 = Device is not selected
0 = Device is selected
RE3/AD11 bit 3 ST/TTL(1) Input/output port pin or address/data bit 11.
RE4/AD12 bit 4 ST/TTL(1) Input/output port pin or address/data bit 12.
(1)
RE5/AD13 bit 5 ST/TTL Input/output port pin or address/data bit 13.
RE6/AD14 bit 6 ST/TTL(1) Input/output port pin or address/data bit 14.
RE7/CCP2/AD15 bit 7 ST/TTL(1) Input/output port pin, Capture2 input/Compare2 output/PWM output
(PIC18F8X20 devices in Microcontroller mode only) or
address/data bit 15.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP
Control mode.
Port/Comparator Select
P
1
RD LATF
Data Bus
D Q
WR LATF I/O pin
or CK Q
WR PORTF
Data Latch N
D Q
WR TRISF VSS
CK Q
TRIS Latch Analog
Input
Mode
RD TRISF Schmitt
Trigger
Q D
EN
RD PORTF
To A/D Converter
RD LATF
RD LATF
Data
Data Bus
Bus D Q
D Q
WR LATF WR LATF or I/O pin
VDD WR PORTF
or CK
WR PORTF CK Q
P Data Latch
Data Latch
D Q
D Q N I/O pin Schmitt
WR TRISF Trigger
CK Input
WR TRISF Buffer
CK Q VSS TRIS Latch TTL
Analog
Input Input
TRIS Latch Buffer
Mode
RD TRISF
RD TRISF ST
Input Q D
Buffer
Q D
ENEN
EN RD PORTF
RD PORTF
SS Input
To A/D Converter or Comparator Input
Note 1: I/O pins have diode protection to VDD and VSS. Note: I/O pins have diode protection to VDD and VSS.
P
RD LATG 1
Data Bus
D Q
WR LATG or I/O pin(1)
CK Q
WR PORTG
Data Latch N
D Q
TRIS VSS
WR TRISG CK Q Override
Logic
TRIS Latch
RD TRISG
Schmitt
Peripheral Output Trigger TRIS OVERRIDE
Enable(2)
Q D Pin Override Peripheral
EN
RG0 Yes CCP3 I/O
Q D
EN
EN
RD PORTH
To A/D Converter
Q D
EN
EN
RD PORTH
RD LATD
I/O pin(1)
Data Bus Port
D Q 0
Data 1
WR LATH
CK
or
PORTH Data Latch
D Q
WR TRISH TTL
CK
Input
TRIS Latch Buffer
RD TRISH
External Enable
System Bus Address Out
Control
Drive System
To Instruction Register
Instruction Read
Q D
ENEN
RD PORTJ
RD LATJ
I/O pin(1)
Data Bus D Q
Port 0
Data
WR LATJ 1
CK
or
PORTJ Data Latch
D Q
WR TRISJ
CK
TRIS Latch
RD TRISJ
Control Out
System Bus External Enable
Control
Drive System
Q D
ENEN
RD PORTJ
RD LATJ
I/O pin(1)
Data Bus Port
D Q 0
Data 1
WR LATJ CK
or
PORTJ Data Latch
D Q
WR TRISJ
CK
TRIS Latch
RD TRISJ
UB/LB Out
System Bus WM = 01
Control Drive System
Write
TTL WR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Data Bus
FOSC/4 0
8
0
Sync with
1 Internal TMR0
RA4/T0CKI pin Clocks
Programmable 1
Prescaler
T0SE (2 TCY delay)
3 PSA
Set Interrupt
T0PS2, T0PS1, T0PS0 Flag bit TMR0IF
T0CS on Overflow
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FOSC/4 0
0
Sync with Set Interrupt
1 Internal TMR0L TMR0
Clocks High Byte Flag bit TMR0IF
RA4/T0CKI Programmable 1 on Overflow
Prescaler 8
pin (2 TCY delay)
T0SE
3
PSA Read TMR0L
T0PS2, T0PS1, T0PS0 Write TMR0L
T0CS 8
8
TMR0H
Data Bus<7:0>
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
TMR1H
8
8
Write TMR1L
CCP Special Event Trigger
Read TMR1L
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Sets Flag
TMR2
Output(1) bit TMR2IF
Prescaler Reset
FOSC/4 TMR2
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS1:T2CKPS0
PR2 4
T2OUTPS3:T2OUTPS0
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
T13CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
T1OSI Oscillator(1) Clock 2
TMR3CS Sleep Input
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
8 T3CCPx Synchronized
Set TMR3IF Flag bit TMR3 0
on Overflow Timer3 CLR Clock Input
High Byte TMR3L
1
To Timer1 Clock Input TMR3ON
On/Off T3SYNC
T1OSC
T1OSO/
T13CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
T1OSI Oscillator(1) Clock 2 Sleep Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Sets Flag
TMR4
Output(1) bit TMR4IF
Prescaler Reset
FOSC/4 TMR4
1:1, 1:4, 1:16
2 Postscaler
Comparator
EQ 1:1 to 1:16
T4CKPS1:T4CKPS0
PR4 4
T4OUTPS3:T4OUTPS0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used Timer3 is used for all Capture
and Compare operations for for Capture and Compare or for Capture and Compare or and Compare operations for
all CCP modules. Timer2 is PWM operations for CCP1 PWM operations for CCP1 all CCP modules. Timer4 is
used for PWM operations for only (depending on selected and CCP2 only (depending on used for PWM operations for
all CCP modules. Modules mode). the mode selected for each all CCP modules. Modules
may share either timer All other modules use either module). Both modules may may share either timer
resource as a common time Timer3 or Timer4. Modules use a timer as a common time resource as a common time
base. may share either timer base if they are both in base.
Timer3 and Timer4 are not resource as a common time Capture/Compare or PWM Timer1 and Timer2 are not
available. base, if they are in Capture/ modes. available.
Compare or PWM modes. The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in Capture/
Compare or PWM modes.
TMR1
and
T3CCP2 Enable
Edge Detect
TMR1H TMR1L
CCP1CON<3:0>
Q’s
Q S Output
Logic Comparator
RC2/CCP1 pin R Match
TRISC<2>
Output Enable CCP1CON<3:0> T3CCP2 0 1
Mode Select
CCPR1H (Slave)
16.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
Comparator R Q
CCPR1L register and to the CCP1CON<5:4> bits. Up
RC2/CCP1
to 10-bit resolution is available. The CCPR1L contains
TMR2 (Note 1) the eight MSbs and the CCP1CON<5:4> contains the
S
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
Comparator TRISC<2>
Clear Timer,
used to calculate the PWM duty cycle in time:
CCP1 pin and
latch D.C.
PR2 EQUATION 16-2:
Note 1: 8-bit timer is concatenated with 2-bit internal Q PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
clock or 2 bits of the prescaler to create 10-bit TOSC • (TMR2 Prescale Value)
time base.
A PWM output (Figure 16-5) has a time base (period) CCPR1L and CCP1CON<5:4> can be written to at any
and a time that the output stays high (duty cycle). time, but the duty cycle value is not latched into
The frequency of the PWM is the inverse of the period CCPR1H until after a match between PR2 and TMR2
(1/period). occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
FIGURE 16-5: PWM OUTPUT The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
Period doublebuffering is essential for glitchless PWM
operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
Duty Cycle
TMR2 prescaler, the CCP1 pin is cleared.
TMR2 = PR2
TMR2 = PR2
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE 4
RC3/SCK/
SCL 2 (
TMR2 Output
2
)
Edge
Select Prescaler TOSC
4, 16, 64
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SDO SDI
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
While in Sleep mode, the slave can transmit/receive 2: If the SPI is used in Slave mode with CKE
data. When a byte is received, the device will wake-up set, then the SS pin control must be
from Sleep. enabled.
When the SPI module resets, the bit counter is forced
17.3.7 SLAVE SELECT to ‘0’. This can be done by either forcing the SS pin to
SYNCHRONIZATION a high level or clearing the SSPEN bit.
The SS pin allows a Synchronous Slave mode. The To emulate two-wire communication, the SDO pin can
SPI must be in Slave mode with SS pin control enabled be connected to the SDI pin. When the SPI needs to
(SSPCON1<3:0> = 04h). The pin must not be driven operate as a receiver, the SDO pin can be configured
low for the SS pin to function as an input. The Data as an input. This disables transmissions from the SDO.
Latch must be high. When the SS pin is low, transmis- The SDI can always be left as an input (SDI function),
sion and reception are enabled and the SDO pin is since it cannot create a bus conflict.
driven. When the SS pin goes high, the SDO pin is no
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit 0
(SMP = 0) bit 7 bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2↓
SSPSR to
SSPBUF
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
DS39609B-page 172
Receiving Address R/W = 0 Receiving Data ACK Receiving Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus master
(PIR1<3>) terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
Data in SCL held low P
sampled while CPU
responds to SSPIF
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software Cleared in software
From SSPIF ISR From SSPIF ISR
SSPBUF is written in software SSPBUF is written in software
CKP
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
DS39609B-page 173
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 17-10:
DS39609B-page 174
Clock is held low until Clock is held low until
update of SSPADD has update of SSPADD has
taken place taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte Receive Data Byte
R/W = 0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Bus master
terminates
SSPIF transfer
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
Cleared in software
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
Bus master
terminates
Clock is held low until Clock is held low until transfer
update of SSPADD has update of SSPADD has Clock is held low until
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software
BF (SSPSTAT<0>)
DS39609B-page 175
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17.4.4 CLOCK STRETCHING 17.4.4.3 Clock Stretching for 7-bit Slave
Both 7- and 10-bit Slave modes implement automatic Transmit Mode
clock stretching during a transmit sequence. 7-bit Slave Transmit mode implements clock stretching
The SEN bit (SSPCON2<0>) allows clock stretching to by clearing the CKP bit after the falling edge of the
be enabled during receives. Setting SEN will cause ninth clock, if the BF bit is clear. This occurs,
the SCL pin to be held low at the end of each data regardless of the state of the SEN bit.
receive sequence. The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
17.4.4.1 Clock Stretching for 7-bit Slave low, the user has time to service the ISR and load the
Receive Mode (SEN = 1) contents of the SSPBUF before the master device can
In 7-bit Slave Receive mode, on the falling edge of the initiate another transmit sequence (see Figure 17-9).
ninth clock at the end of the ACK sequence, if the BF Note 1: If the user loads the contents of SSPBUF,
bit is set, the CKP bit in the SSPCON1 register is setting the BF bit before the falling edge of
automatically cleared, forcing the SCL output to be the ninth clock, the CKP bit will not be
held low. The CKP being cleared to ‘0’ will assert the cleared and clock stretching will not occur.
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding 2: The CKP bit can be set in software,
the SCL line low, the user has time to service the ISR regardless of the state of the BF bit.
and read the contents of the SSPBUF before the
17.4.4.4 Clock Stretching for 10-bit Slave
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see Transmit Mode
Figure 17-13). In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
Note 1: If the user reads the contents of the
state of the UA bit, just as it is in 10-bit Slave Receive
SSPBUF before the falling edge of the
mode. The first two addresses are followed by a third
ninth clock, thus clearing the BF bit, the
address sequence, which contains the high-order bits
CKP bit will not be cleared and clock
of the 10-bit address and the R/W bit set to ‘1’. After
stretching will not occur.
the third address sequence is performed, the UA bit is
2: The CKP bit can be set in software, not set, the module is now configured in Transmit
regardless of the state of the BF bit. The mode and clock stretching is controlled as in 7-bit
user should be careful to clear the BF bit Slave Transmit mode (see Figure 17-11).
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX-1
SCL
Master device
CKP asserts clock
Master device
deasserts clock
WR
SSPCON
DS39609B-page 178
Clock is not held low
because buffer full bit is
clear prior to falling edge Clock is held low until Clock is not held low
of 9th clock CKP is set to ‘1’ because ACK = 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPIF
Bus master
(PIR1<3>) terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
CKP
CKP
If BF is cleared written
prior to the falling to ‘1’ in
edge of the 9th clock, software
PIC18F6520/8520/6620/8620/6720/8720
SSPIF
Bus master
(PIR1<3>) terminates
Cleared in software Cleared in software Cleared in software transfer
Cleared in software
BF (SSPSTAT<0>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
UA (SSPSTAT<1>)
DS39609B-page 179
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PIC18F6520/8520/6620/8620/6720/8720
17.4.5 GENERAL CALL ADDRESS If the general call address matches, the SSPSR is
SUPPORT transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
The addressing procedure for the I2C bus is such that
SSPIF interrupt flag bit is set.
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the When the interrupt is serviced, the source for the inter-
master. The exception is the general call address, rupt can be checked by reading the contents of the
which can address all devices. When this address is SSPBUF. The value can be used to determine if the
used, all devices should, in theory, respond with an address was device specific or a general call address.
Acknowledge. In 10-bit mode, the SSPADD is required to be updated
The general call address is one of eight addresses for the second half of the address to match and the UA
reserved for specific purposes by the I2C protocol. It bit is set (SSPSTAT<1>). If the general call address is
consists of all ‘0’s with R/W = 0. sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
The general call address is recognized when the Gen-
half of the address is not necessary, the UA bit will not
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
be set and the slave will begin receiving data after the
set). Following a Start bit detect, 8 bits are shifted into
Acknowledge (Figure 17-15).
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>) ‘0’
Internal SSPM3:SSPM0
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Clock Arbitrate/WCOL Detect
SDA In Clock
SSPSR
(hold off clock source)
MSb LSb
Receive Enable
Acknowledge
Generate
SCL
SSPM3:SSPM0 SSPADD<6:0>
SDA DX DX-1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCL
TBRG
S
1st bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here
End of Xmit
TBRG
SCL TBRG
RSEN bit set Sr = Repeated Start
DS39609B-page 188
Write SSPCON2<0> SEN = 1, ACKSTAT in
Start condition begins SSPCON2 = 1
From slave, clear ACKSTAT bit SSPCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 of 10-bit Address ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPSTAT<0>)
PEN
R/W
PIC18F6520/8520/6620/8620/6720/8720
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Write to SSPCON2<0> (SEN = 1),
begin Start Condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPCON2<3> (RCEN = 1)
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of Acknow-
Set SSPIF interrupt ledge sequence
at end of receive
at end of Acknowledge
SSPIF sequence
Set P bit
Cleared in software Cleared in software Cleared in software Cleared in software (SSPSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPIF
responds to SSPIF
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
ACKEN
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
DS39609B-page 189
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17.4.12 ACKNOWLEDGE SEQUENCE 17.4.13 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit, PEN (SSPCON2<2>). At the end of a receive/
(SSPCON2<4>). When this bit is set, the SCL pin is transmit, the SCL line is held low after the falling edge
pulled low and the contents of the Acknowledge data bit of the ninth clock. When the PEN bit is set, the master
are presented on the SDA pin. If the user wishes to gen- will assert the SDA line low. When the SDA line is sam-
erate an Acknowledge, then the ACKDT bit should be pled low, the Baud Rate Generator is reloaded and
cleared. If not, the user should set the ACKDT bit before counts down to ‘0’. When the Baud Rate Generator
starting an Acknowledge sequence. The Baud Rate times out, the SCL pin will be brought high and one
Generator then counts for one rollover period (TBRG) TBRG (Baud Rate Generator rollover count) later, the
and the SCL pin is deasserted (pulled high). When the SDA pin will be deasserted. When the SDA pin is sam-
SCL pin is sampled high (clock arbitration), the Baud pled high while SCL is high, the P bit (SSPSTAT<4>) is
Rate Generator counts for TBRG. The SCL pin is then set. A TBRG later, the PEN bit is cleared and the SSPIF
pulled low. Following this, the ACKEN bit is automatically bit is set (Figure 17-24).
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23). 17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
17.4.12.1 WCOL Status Flag is in progress, then the WCOL bit is set and the
If the user writes the SSPBUF when an Acknowledge contents of the buffer are unchanged (the write doesn’t
sequence is in progress, then WCOL is set and the occur).
contents of the buffer are unchanged (the write doesn’t
occur).
SCL 8 9
SSPIF
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSP module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
BCLIF SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF
TBRG TBRG
SDA
FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLIF ‘0’
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF in software
SDA
SCL
RSEN
BCLIF
Cleared in software
S ‘0’
SSPIF ‘0’
TBRG TBRG
SDA
SCL
S ‘0’
SSPIF
PEN
BCLIF
P ‘0’
SSPIF ‘0’
SDA
SCL goes low before SDA goes high,
Assert SDA
set BCLIF
SCL
PEN
BCLIF
P ‘0’
SSPIF ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
SPBRG
TX9
Baud Rate Generator
TX9D
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)
Write to TXREG
Word 1 Word 2
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXIF bit
(Interrupt Reg. Flag) Word 1 Word 2
RX9
RX pin
Pin Buffer Data
and Control Recovery
RX9D RCREG Register
FIFO
SPEN
8
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
RC6/TX1/CK1
pin
Write to
TXREG Reg
Write Word 1 Write Word 2
TXIF bit
(Interrupt Flag)
TRMT
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
RC6/TX1/CK1 pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
RC6/TX1/CK1 pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Synchronous Slave mode differs from the Master mode 1. Enable the synchronous slave serial port by
in the fact that the shift clock is supplied externally at setting bits SYNC and SPEN and clearing bit
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead CSRC.
of being supplied internally in Master mode. TRISC<6> 2. Clear bits CREN and SREN.
must be set for this mode. This allows the device to 3. If interrupts are desired, set enable bit TXxIE.
transfer or receive data while in Sleep mode. Slave 4. If 9-bit transmission is desired, set bit TX9.
mode is entered by clearing bit CSRC (TXSTAx<7>). 5. Enable the transmission by setting enable bit
TXEN.
18.4.1 USART SYNCHRONOUS SLAVE
6. If 9-bit transmission is selected, the ninth bit
TRANSMIT
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave 7. Start transmission by loading data to the
modes are identical, except in the case of the Sleep TXREGx register.
mode.
8. If using interrupts, ensure that the GIE and PEIE
If two words are written to the TXREG and then the bits in the INTCON register (INTCON<7:6>) are
SLEEP instruction is executed, the following will occur: set.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXxIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
e) If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VCFG1
A/D VREF+ A/D VREF-
VCFG0
00 AVDD AVSS
01 External VREF+ AVSS
10 AVDD External VREF-
11 External VREF+ External VREF-
AN14
AN13
AN12
AN10
PCFG3 AN11
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG0
0000 A A A A A A A A A A A A A A A A
0001 D D A A A A A A A A A A A A A A
0010 D D D A A A A A A A A A A A A A
0011 D D D D A A A A A A A A A A A A
0100 D D D D D A A A A A A A A A A A
0101 D D D D D D A A A A A A A A A A
0110 D D D D D D D A A A A A A A A A
0111 D D D D D D D D A A A A A A A A
1000 D D D D D D D D D A A A A A A A
1001 D D D D D D D D D D A A A A A A
1010 D D D D D D D D D D D A A A A A
1011 D D D D D D D D D D D D A A A A
1100 D D D D D D D D D D D D D A A A
1101 D D D D D D D D D D D D D D A A
1110 D D D D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D D D D
A = Analog input D = Digital I/O
Note: Shaded cells indicate A/D channels available only on PIC18F8X20 devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
The analog reference voltage is software selectable to Each port pin associated with the A/D converter can be
either the device’s positive and negative supply voltage configured as an analog input (RA3 can also be a
(VDD and VSS), or the voltage level on the RA3/AN3/ voltage reference), or as a digital I/O. The ADRESH
VREF+ pin and RA2/AN2/VREF- pin. and ADRESL registers contain the result of the A/D
The A/D converter has a unique feature of being able conversion. When the A/D conversion is complete, the
to operate while the device is in Sleep mode. To oper- result is loaded into the ADRESH/ADRESL registers,
ate in Sleep, the A/D conversion clock must be derived the GO/DONE bit (ADCON0 register) is cleared and
from the A/D’s internal RC oscillator. A/D interrupt flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 19-1.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
(Input Voltage) 0011
10-bit AN3
Converter
A/D 0010
AN2
0001
VCFG1:VCFG0 AN1
0000
VDD AN0
VREF+
Reference
Voltage VREF-
VSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6X20 devices.
2: I/O pins have diode protection to VDD and VSS.
CPIN ILEAKAGE
VAIN CHOLD = 120 pF
5 pF VT = 0.6V
± 500 nA
VSS
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
A VIN- D VIN-
RF4/AN9 RF4/AN9
A VIN+ C2 Off (Read as ‘0’) D VIN+ C2 Off (Read as ‘0’)
RF3/AN8 RF3/AN8
A VIN-
RF4/AN9 A VIN-
RF4/AN9
A VIN+ C2 C2OUT C2OUT
RF3/AN8 A VIN+ C2
RF3/AN8
RF1/AN6/C2OUT
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 100 CM2:CM0 = 101
A VIN- A VIN-
RF6/AN11 RF6/AN11
VIN+ C1 C1OUT VIN+ C1 C1OUT
RF5/AN10 A RF5/AN10 A
RF2/AN7/C1OUT
A VIN-
RF4/AN9
C2 C2OUT A VIN-
RF3/AN8 D VIN+ RF4/AN9
D VIN+ C2 C2OUT
RF3/AN8
RF1/AN6/C2OUT
One Independent Comparator with Output Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 001 CM2:CM0 = 110
A VIN- A
RF6/AN11 RF6/AN11 CIS = 0 VIN-
A VIN+ C1 C1OUT RF5/AN10 A CIS = 1
RF5/AN10 VIN+ C1 C1OUT
RF2/AN7/C1OUT A
RF4/AN9 VIN-
CIS = 0
A CIS = 1
RF3/AN8 C2 C2OUT
D VIN- VIN+
RF4/AN9
D VIN+ C2 Off (Read as ‘0’)
RF3/AN8 CVREF
From VREF Module
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
Port pins
MULTIPLEX
+ -
CxINV
To RF1 or
RF2 pin
Bus Q D
Data
Read CMCON EN
Set
CMIF Q D
bit From
Other EN
Comparator
CL Read CMCON
Reset
VDD
VT = 0.6V RIC
RS < 10k
Comparator
AIN Input
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VDD VREF+
CVREN
8R R R R R
CVRR
8R
CVRSS = 0
CVRSS = 1
VREF-
CVR3
CVREF 16-1 Analog Mux (From CVRCON<3:0>)
CVR0
21.3 Operation During Sleep The voltage reference module operates independently
of the comparator module. The output of the reference
When the device wakes up from Sleep through an generator may be connected to the RF5 pin if the
interrupt or a Watchdog Timer time-out, the contents of TRISF<5> bit is set and the CVROE bit is set. Enabling
the CVRCON register are not affected. To minimize the voltage reference output onto the RF5 pin,
current consumption in Sleep mode, the voltage configured as a digital input, will increase current
reference should be disabled. consumption. Connecting RF5 as a digital output with
VRSS enabled will also increase current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to VREF.
Figure 21-2 shows an example buffering technique.
R(1) RF5
CVREF
Module +
CVREF Output
–
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits CVRCON<3:0> and CVRCON<5>.
VA
VB
Voltage
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TA TB
Time
The block diagram for the LVD module is shown in supply voltage is equal to the trip point, the voltage
Figure 22-2. A comparator uses an internally gener- tapped off of the resistor array is equal to the 1.2V
ated reference voltage as the set point. When the internal reference voltage generated by the voltage ref-
selected tap output of the device voltage crosses the erence module. The comparator then generates an
set point (is lower than), the LVDIF bit is set. interrupt signal, setting the LVDIF bit. This voltage is
Each node in the resistor divider represents a “trip software programmable to any one of 16 values (see
point” voltage. The “trip point” voltage is the minimum Figure 22-2). The trip point is selected by programming
supply voltage level at which the device can operate the LVDL3:LVDL0 bits (LVDCON<3:0>).
before the LVD module asserts an interrupt. When the
16 to 1 MUX
LVDIF
The LVD module has an additional feature that allows LVDIN (Figure 22-3). This gives users flexibility
the user to supply the trip voltage to the module from because it allows them to configure the Low-Voltage
an external source. This mode is enabled when bits Detect interrupt to occur at any voltage in the valid
LVDL3:LVDL0 are set to ‘1111’. In this state, the com- operating range.
parator input is multiplexed from the external input pin,
FIGURE 22-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD3:LVD0 LVDCON
Register
16 to 1 MUX
LVDIN LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
VDD
VLVD
LVDIF
Enable LVD
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
WDT
Time-out
INT pin
INTF flag
(INTCON<1>) Interrupt Latency(3)
GIEH bit
(INTCON<7>) Processor in
Sleep
INSTRUCTION FLOW
PC PC PC+2 PC+4 PC+4 PC + 4 0008h 000Ah
Instruction Inst(0008h)
Fetched Inst(PC) = Sleep Inst(PC + 2) Inst(PC + 4) Inst(000Ah)
Instruction Inst(PC + 2) Dummy Cycle Dummy Cycle Inst(0008h)
Executed Inst(PC - 1) Sleep
23.4 Program Verification and In the PIC18FXX20 family, the block size varies with
Code Protection the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
The overall structure of the code protection on the 8 Kbytes each. The first block is further divided into a
PIC18 Flash devices differs significantly from other boot block of 2 Kbytes and a second block (Block 0) of
PICmicro® devices. The user program memory is 6 Kbytes, for a total of five blocks. The organization of
divided on binary boundaries into individual blocks, the blocks and their associated code protection bits are
each of which has three separate code protection bits shown in Figure 23-3.
associated with it:
For PIC18FX620 and PIC18FX720 devices, program
• Code-Protect bit (CPn) memory is divided into blocks of 16 Kbytes. The first
• Write-Protect bit (WRTn) block is further divided into a boot block of 512 bytes
• External Block Table Read bit (EBTRn) and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
The code protection bits are located in Configuration devices and nine for 128-Kbyte devices. The organiza-
Registers 5L through 7H. Their locations within the tion of the blocks and their associated code protection
registers are summarized in Table 23-3. bits are shown in Figure 23-4.
Unimplemented
Read ‘0’s
1FFFFFh
WRT1, EBTR1 = 11
007FFFh
008000h
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
00BFFFh
00C000h
WRT3, EBTR3 = 11
00FFFFh
When the DEBUG bit in the CONFIG4L Configuration It should be noted that once the LVP bit is programmed
register is programmed to a ‘0’, the In-Circuit Debugger to ‘0’, only the High-Voltage Programming mode is
functionality is enabled. This function allows simple available and only High-Voltage Programming mode
debugging functions when used with MPLAB® IDE. can be used to program the device.
When the microcontroller has this feature enabled, When using Low-Voltage ICSP Programming, the part
some of the resources are not available for general must be supplied 4.5V to 5.5V if a bulk erase will be
use. Table 23-4 shows which features are consumed executed. This includes reprogramming of the code-
by the background debugger. protect bits from an on state to an off state. For all other
cases of Low-Voltage ICSP, the part may be
programmed at the normal operating voltage. This
means unique user IDs or user code can be
reprogrammed or added.
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 0x7F
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL n, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW — Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO n Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP — No Operation 1 0000 0000 0000 0000 None
NOP — No Operation 1 1111 xxxx xxxx xxxx None 4
POP — Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH — Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP — Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSRx 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP unless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
Cycles: 1 Words: 1
Cycles: 2 Words: 1
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
0≤b≤7 0≤b<7
a ∈ [0,1] a ∈ [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the Description: If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped. next instruction is skipped.
If bit ‘b’ is ‘0’, then the next If bit ‘b’ is ‘1’, then the next
instruction fetched during the current instruction fetched during the current
instruction execution is discarded instruction execution is discarded
and a NOP is executed instead, and a NOP is executed instead,
making this a two-cycle instruction. If making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected ‘a’ = 1, then the bank will be selected
as per the BSR value (default). as per the BSR value (default).
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register ‘f’ Data operation register ‘f’ Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
Cycles: 1 Words: 1
Description: Clears the contents of the specified Encoding: 0000 0000 0000 0100
register. If ‘a’ is ‘0’, the Access Description: CLRWDT instruction resets the
Bank will be selected, overriding Watchdog Timer. It also resets the
the BSR value. If ‘a’ = 1, then the postscaler of the WDT. Status bits
bank will be selected as per the TO and PD are set.
BSR value (default). Words: 1
Words: 1 Cycles: 1
Cycles: 1 Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode No Process No
Decode Read Process Write operation Data operation
register ‘f’ Data register ‘f’
Example: CLRWDT
Example: CLRF FLAG_REG,1
Before Instruction
Before Instruction WDT Counter = ?
FLAG_REG = 0x5A After Instruction
After Instruction WDT Counter = 0x00
FLAG_REG = 0x00 WDT Postscaler = 0
TO = 1
PD = 1
Description: The contents of register ‘f’ are com- Encoding: 0110 001a ffff ffff
plemented. If ‘d’ is ‘0’, the result is Description: Compares the contents of data
stored in W. If ‘d’ is ‘1’, the result is memory location ‘f’ to the contents
stored back in register ‘f’ (default). of W by performing an unsigned
If ‘a’ is ‘0’, the Access Bank will be subtraction.
selected, overriding the BSR value. If ‘f’ = W, then the fetched
If ‘a’ = 1, then the bank will be instruction is discarded and a NOP
selected as per the BSR value is executed instead, making this a
(default). two-cycle instruction. If ‘a’ is ‘0’, the
Words: 1 Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
Cycles: 1 then the bank will be selected as
Q Cycle Activity: per the BSR value (default).
Q1 Q2 Q3 Q4 Words: 1
Decode Read Process Write to Cycles: 1(2)
register ‘f’ Data destination
Note: 3 cycles if skip and followed
Example: COMF REG, 0, 0 by a 2-word instruction.
Before Instruction Q Cycle Activity:
REG = 0x13
Q1 Q2 Q3 Q4
After Instruction
Decode Read Process No
REG = 0x13
register ‘f’ Data operation
W = 0xEC
If skip:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation
CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W
Syntax: [ label ] CPFSGT f [,a] Syntax: [ label ] CPFSLT f [,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
a ∈ [0,1] a ∈ [0,1]
Operation: (f) − (W), Operation: (f) – (W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None Status Affected: None
Encoding: 0110 010a ffff ffff Encoding: 0110 000a ffff ffff
Description: Compares the contents of data Description: Compares the contents of data
memory location ‘f’ to the contents memory location ‘f’ to the contents
of W by performing an unsigned of W by performing an unsigned
subtraction. subtraction.
If the contents of ‘f’ are greater than If the contents of ‘f’ are less than
the contents of WREG, then the the contents of W, then the fetched
fetched instruction is discarded and instruction is discarded and a NOP
a NOP is executed instead, making is executed instead, making this a
this a two-cycle instruction. If ‘a’ is two-cycle instruction. If ‘a’ is ‘0’, the
‘0’, the Access Bank will be Access Bank will be selected. If ‘a’
selected, overriding the BSR value. is ‘1’, the BSR will not be
If ‘a’ = 1, then the bank will be overridden (default).
selected as per the BSR value Words: 1
(default).
Cycles: 1(2)
Words: 1 Note: 3 cycles if skip and followed
Cycles: 1(2) by a 2-word instruction.
Note: 3 cycles if skip and followed Q Cycle Activity:
by a 2-word instruction.
Q1 Q2 Q3 Q4
Q Cycle Activity: Decode Read Process No
Q1 Q2 Q3 Q4 register ‘f’ Data operation
Decode Read Process No If skip:
register ‘f’ Data operation Q1 Q2 Q3 Q4
If skip: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
No No No No If skip and followed by 2-word instruction:
operation operation operation operation Q1 Q2 Q3 Q4
If skip and followed by 2-word instruction: No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No
operation operation operation operation Example: HERE CPFSLT REG, 1
NLESS :
Example: HERE CPFSGT REG, 0 LESS :
NGREATER : Before Instruction
GREATER : PC = Address (HERE)
Before Instruction W = ?
PC = Address (HERE) After Instruction
W = ? If REG < W;
After Instruction PC = Address (LESS)
If REG ≥ W;
If REG > W; PC = Address (NLESS)
PC = Address (GREATER)
If REG ≤ W;
PC = Address (NGREATER)
Description: The eight-bit literal ‘k’ is loaded into Encoding: 0110 111a ffff ffff
W. Description: Move data from W to register ‘f’.
Words: 1 Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Cycles: 1 Access Bank will be selected,
Q Cycle Activity: overriding the BSR value. If ‘a’ = 1,
Q1 Q2 Q3 Q4 then the bank will be selected as
Decode Read Process Write to W
per the BSR value (default).
literal ‘k’ Data Words: 1
Cycles: 1
Example: MOVLW 0x5A
Q Cycle Activity:
After Instruction Q1 Q2 Q3 Q4
W = 0x5A Decode Read Process Write
register ‘f’ Data register ‘f’
Cycles: 1
Example:
Q Cycle Activity:
Q1 Q2 Q3 Q4
None.
Decode Read Process Write
register ‘f’ Data register ‘f’
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: [ label ] POP Syntax: [ label ] PUSH
Operands: None Operands: None
Operation: (TOS) → bit bucket Operation: (PC+2) → TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the Description: The PC+2 is pushed onto the top of
return stack and is discarded. The the return stack. The previous TOS
TOS value then becomes the value is pushed down on the stack.
previous value that was pushed This instruction allows
onto the return stack. implementing a software stack by
This instruction is provided to modifying TOS and then pushing it
enable the user to properly manage onto the return stack.
the return stack to incorporate a Words: 1
software stack.
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Q Cycle Activity: Decode PUSH PC+2 No No
Q1 Q2 Q3 Q4 onto return operation operation
Decode No POP TOS No stack
operation value operation
Example: PUSH
Example: POP Before Instruction
GOTO NEW
TOS = 00345Ah
Before Instruction PC = 000124h
TOS = 0031A2h
Stack (1 level down) = 014332h After Instruction
PC = 000126h
After Instruction TOS = 000126h
Stack (1 level down) = 00345Ah
TOS = 014332h
PC = NEW
RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry
Syntax: [ label ] RLNCF f [,d [,a] Syntax: [ label ] RRCF f [,d [,a]
Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255
d ∈ [0,1] d ∈ [0,1]
a ∈ [0,1] a ∈ [0,1]
Operation: (f<n>) → dest<n+1>, Operation: (f<n>) → dest<n-1>,
(f<7>) → dest<0> (f<0>) → C,
Status Affected: N, Z (C) → dest<7>
Description: The contents of register ‘f’ are Encoding: 0011 00da ffff ffff
rotated one bit to the left. If ‘d’ is ‘0’, Description: The contents of register ‘f’ are
the result is placed in W. If ‘d’ is ‘1’, rotated one bit to the right through
the result is stored back in register the Carry flag. If ‘d’ is ‘0’, the result
‘f’ (default). If ‘a’ is ‘0’, the Access is placed in W. If ‘d’ is ‘1’, the result
Bank will be selected, overriding is placed back in register ‘f’
the BSR value. If ‘a’ is ‘1’, then the (default). If ‘a’ is ‘0’, the Access
bank will be selected as per the Bank will be selected, overriding
BSR value (default). the BSR value. If ‘a’ is ‘1’, then the
register f
bank will be selected as per the
BSR value (default).
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4 Cycles: 1
Decode Read Process Write to Q Cycle Activity:
register ‘f’ Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register ‘f’ Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
6.0V
5.5V
5.0V PIC18FX520
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
6.0V
5.5V
5.0V
4.5V PIC18LFX520
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz FMAX
Frequency
Note: VDDAPPMIN is the minimum voltage of the Picmicro® device in the application.
6.0V
5.5V
5.0V PIC18FX620/X720
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
6.0V
5.5V
5.0V
PIC18LFX620/X720
4.5V
Voltage
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz FMAX
Frequency
In Microcontroller mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In modes other than Microcontroller mode:
FMAX = (5.45 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;
FMAX = 16 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the Picmicro® device in the application.
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
D001 VDD Supply Voltage
PIC18LFXX20 2.0 — 5.5 V HS, XT, RC and LP Oscillator mode
PIC18FXX20 4.2 — 5.5 V
D001A AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V
D002 VDR RAM Data Retention 1.5 — — V
Voltage(1)
D003 VPOR VDD Start Voltage — — 0.7 V See section on Power-on Reset for details
to ensure internal
Power-on Reset signal
D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset for details
to ensure internal
Power-on Reset signal
D005 VBOR Brown-out Reset Voltage
BORV1:BORV0 = 11 N/A — N/A V Reserved
BORV1:BORV0 = 10 2.64 — 2.92 V
BORV1:BORV0 = 01 4.11 — 4.55 V
BORV1:BORV0 = 00 4.41 — 4.87 V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Device Typ Max Units Conditions
No.
Param
Sym Characteristic Min Max Units Conditions
No.
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer VSS 0.15 VDD V VDD < 4.5V
D030A — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer VSS 0.2 VDD V
RC3 and RC4 VSS 0.3 VDD V
D032 MCLR VSS 0.2 VDD V
D032A OSC1 (in XT, HS and LP modes) VSS 0.2 VDD V
and T1OSI
D033 OSC1 (in RC and EC mode)(1) VSS 0.2 VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 0.25 VDD + 0.8V VDD V VDD < 4.5V
D040A 2.0 VDD V 4.5V ≤ VDD ≤ 5.5V
D041 with Schmitt Trigger buffer 0.8 VDD VDD V
RC3 and RC4 0.7 VDD VDD V
D042 MCLR, OSC1 (EC mode) 0.8 VDD VDD V
D042A OSC1 and T1OSI 1.6 VDD V LP, XT, HS, HSPLL
modes(1)
D043 OSC1 (RC mode)(1) 0.9 VDD VDD V
IIL Input Leakage Current(2,3)
D060 I/O ports — ±1 µA VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D061 MCLR — ±5 µA VSS ≤ VPIN ≤ VDD
D063 OSC1 — ±5 µA VSS ≤ VPIN ≤ VDD
IPU Weak Pull-up Current
D070 IPURB PORTB weak pull-up current 50 400 µA VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
Param
Sym Characteristic Min Max Units Conditions
No.
VOL Output Low Voltage
D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D083 OSC2/CLKO — 0.6 V IOL = 1.6 mA, VDD = 4.5V,
(RC mode) -40°C to +85°C
D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
VOH Output High Voltage(3)
D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D090A VDD – 0.7 — V IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
D092 OSC2/CLKO VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V,
(RC mode) -40°C to +85°C
D092A VDD – 0.7 — V IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin
Capacitive Loading Specs
on Output Pins
D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101 CIO All I/O pins and OSC2 — 50 pF To meet the AC Timing
(in RC mode) Specifications
D102 CB SCL, SDA — 400 pF In I2C mode
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PICmicro device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D300 VIOFF Input Offset Voltage — ± 5.0 ± 10 mV
D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio 55 — — dB
300 TRESP Response Time(1) — 150 400 ns PIC18FXX20
300A 600 ns PIC18LFXX20
301 TMC2OV Comparator Mode Change to — — 10 µs
Output Valid
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD.
Param
Sym Characteristics Min Typ Max Units Comments
No.
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/4 LSb Low Range (VRR = 1)
— — 1/2 LSb High Range (VRR = 0)
D312 VRUR Unit Resistor Value (R) — 2k — Ω
310 TSET Settling Time(1) — — 10 µs
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
VDD
(LVDIF can be
VLVD cleared in software)
(LVDIF set by hardware)
LVDIF
VDD/2
RL Pin CL
VSS
CL
Pin
RL = 464Ω
VSS CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKO
Q4 Q1 Q2 Q3
OSC1
10 11
CLKO
13 12
14 19 18
16
I/O pin
(Input)
17 15
20, 21
Q1 Q2 Q3 Q4 Q1 Q2
OSC1(1)
167
ALE 168
164
169
171
CE
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.
Q1 Q2 Q3 Q4 Q1 Q2
OSC1(1)
A<19:16> Address
Address
BA0
166
153
150
156
151
ALE
171
CE
171A
154
WRH or
WRL
157 157A
UB or
LB
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.
150 TADV2ALL Address Out Valid to ALE ↓ (address setup time) 0.25 TCY – 10 — — ns
151 TALL2ADL ALE ↓ to Address Out Invalid (address hold time) 5 — — ns
153 TWRH2ADL WRn ↑ to Data Out Invalid (data hold time) 5 — — ns
154 TWRL WRn Pulse Width 0.5 TCY – 5 0.5 TCY — ns
156 TADV2WRH Data Valid before WRn ↑ (data setup time) 0.5 TCY – 10 — — ns
157 TBSV2WRL Byte Select Valid before WRn ↓ (byte select setup 0.25 TCY — — ns
time)
157A TWRH2BSI WRn ↑ to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns
166 TALH2ALH ALE ↑ to ALE ↑ (cycle time) — TCY — ns
171 TALH2CSL Chip Enable Active to ALE ↓ — — 10 ns
171A TUBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34 34
I/O Pins
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference 36
Voltage Stable
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
Symbol Characteristic Min Typ Max Units Conditions
No.
T0CKI
40 41
42
T1OSO/T13CKI
45 46
47 48
TMR0 or
TMR1
CCPx
(Capture Mode)
50 51
52
CCPx
(Compare or PWM Mode)
53 54
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 26-6 for load conditions.
SS
70
SCK
(CKP = 0)
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76
74
73
SS
81
SCK
(CKP = 0)
71 72
79
73
SCK
(CKP = 1)
80
78
75, 76
74
Note: Refer to Figure 26-6 for load conditions.
SS
70
SCK
(CKP = 0) 83
71 72
78 79
SCK
(CKP = 1)
79 78
80
75, 76 77
74
73
70
SCK 83
(CKP = 0)
71 72
SCK
(CKP = 1)
80
75, 76 77
SDI
MSb In bit 6 - - - -1 LSb In
74
Note: Refer to Figure 26-6 for load conditions.
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
91 92
SDA
In
110
109 109
SDA
Out
SCL
91 93
90 92
SDA
Start Stop
Condition Condition
SDA
Out
RC6/TX1/CK1
pin
121 121
RC7/RX1/DT1
pin
120
122
Note: Refer to Figure 26-6 for load conditions.
RC6/TX1/CK1
pin 125
RC7/RX1/DT1
pin
126
BSF ADCON0, GO
(Note 2)
131
Q4
130
A/D CLK 132
ADIF TCY
GO DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
FIGURE 27-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
20
18
14 5.0V
12 4.5V
IDD (mA)
10 4.0V
3.5V
8
6 3.0V
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
FIGURE 27-2: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) INDUSTRIAL
20
5.5V
18
Typical: statistical mean @ 25°C
5.0V
16 Maximum: mean + 3σ (-40°C to +85°C)
Minimum: mean – 3σ (-40°C to +85°C)
4.5V
14
12 4.0V
IDD (mA)
10 3.5V
3.0V
6
4
2.5V
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
20
5.5V
18
Typical: statistical mean @ 25°C 5.0V
Maximum: mean + 3σ (-40°C to +125°C)
16
Minimum: mean – 3σ (-40°C to +125°C)
4.5V
14
4.0V
12
I DD (mA)
10 3.5V
3.0V
6
4
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
FIGURE 27-4: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
20
18
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
16
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
14
5.0V
12
4.5V
IDD (mA)
10 4.0V
8 3.5V
6
3.0V
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
20
18
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +85°C)
16
Minimum: mean – 3σ (-40°C to +85°C)
5.0V
14
4.5V
12
4.0V
IDD (mA)
10 3.5V
3.0V
6
4
2.5V
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
FIGURE 27-6: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED
20
5.5V
18
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C) 5.0V
16
Minimum: mean – 3σ (-40°C to +125°C)
4.5V
14
12 4.0V
IDD (mA)
10 3.5V
3.0V
6
4
2.5V
2.0V
0
4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0
FOSC (MHz)
3.0
2.0
5.5V
IDD (uA)
5.0V
1.5
4.5V
4.0V
1.0
3.5V
3.0V
2.5V
0.5
2.0V
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
FIGURE 27-8: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) INDUSTRIAL
3.0
5.5V
2.0
5.0V
IDD (uA)
4.5V
1.5
4.0V
3.5V
1.0
3.0V
2.5V
2.0V
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
100
90
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to +125°C)
80
Minimum: mean – 3σ (-40°C to +125°C)
5.5V
70
5.0V
60
4.5V
IDD (uA)
50 4.0V
3.5V
40
3.0V
30
2.5V
2.0V
20
10
0
0 10 20 30 40 50 60 70 80 90 100
FOSC (kHz)
FIGURE 27-10: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) INDUSTRIAL
120
5.0V
80
4.5V
IDD (uA)
4.0V
60
3.5V
3.0V
40
2.5V
2.0V
20
0
0 10 20 30 40 50 60 70 80 90 100
FOSC (kHz)
300
5.0V
200
4.5V
4.0V
IDD (uA)
150 3.5V
3.0V
2.5V
100
2.0V
50
0
0 10 20 30 40 50 60 70 80 90 100
FOSC (kHz)
FIGURE 27-12: TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
18
5.0V
12
4.5V
10
IDD (mA)
4.0V
8 3.5V
6
3.0V
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
18
5.5V
Typical: statistical mean @ 25°C
16 Maximum: mean + 3σ (-40°C to +125°C)
Minimum: mean – 3σ (-40°C to +125°C) 5.0V
14
4.5V
12
4.0V
10
IDD (mA)
3.5V
6 3.0V
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
100
Max
(-40°C:+125°C)
10
Max
(-40°C:+85°C)
IPD (uA)
0.1
Typ
(25°C)
0.01
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
1000
100
IPD (uA)
Max
Max
(-40°C:+125°C)
(-40°C:+85°C)
10
Typ
(25°C)
1
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 27-16: TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
1000
100
Max
(-40°C:+85°C)
IPD (uA)
10
Typ
(25°C)
0.1
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
0.55
0.40
5.5V
0.35
5.0V
0.30
IDD (mA)
4.5V
0.25
4.0V
0.20
3.5V
0.15
3.0V
0.10
2.5V
0.05 2.0V
0.00
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
FIGURE 27-18: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
0.55
0.40
4.5V
0.35
0.30
IDD (mA)
4.0V
0.25
3.5V
0.20
0.15
3.0V
2.5V
0.10
2.0V
0.05
0.00
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20
FOSC (MHz)
30
5.5V
20
5.0V
IDD (mA)
4.5V
15
4.2V
4.0V
10
3.5V
5 3.0V
2.5V
2.0V
0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
FIGURE 27-20: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) INDUSTRIAL
(PIC18F8520 DEVICES ONLY)
30
5.0V
20
4.5V
4.2V
IDD (mA)
15 4.0V
10 3.5V
3.0V
5
2.5V
2.0V
0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
20
5.5V
14
5.0V
12
IDD (mA)
4.5V
10 4.2V
4.0V
8
3.5V
6 3.0V
4
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
FIGURE 27-22: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
(PIC18F8520 DEVICES ONLY)
30
27
5.0V
18
IDD (mA)
4.5V
15
4.2V
4.0V
12
9 3.5V
6
3.0V
3
2.5V
2.0V
0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
30
27
5.5V
Typical: statistical mean @ 25°C
24 Maximum: mean + 3σ (-40°C to +85°C)
Minimum: mean – 3σ (-40°C to +85°C) 5.0V
21
4.5V
18
4.2V
IDD (mA)
4.0V
15
12
3.5V
9
6 3.0V
3 2.5V
2.0V
0
4 8 12 16 20 24 28 32 36 40
FOSC (MHz)
FIGURE 27-24: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED
(PIC18F8520 DEVICES ONLY)
20
18
5.0V
12
4.5V
IDD (mA)
10 4.2V
4.0V
8 3.5V
3.0V
6
4
2.5V
2
2.0V
0
4 6 8 10 12 14 16 18 20 22 24 26
FOSC (MHz)
3.5
-40°C
-40C
Differential or Integral Nonlinearity (LSB)
+25°C
25C
2.5
+85°C
85C
2
1.5
0.5
+125°C
125C
0
2 2.5 3 3.5 4 4.5 5 5.5
VDD and VREFH (V)
FIGURE 27-26: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C)
2.5
Differential or Integral Nonlinearilty (LSB)
1.5
Max
Max (-40°C
(-40C toto125C)
+125°C)
Typ
Typ (+25°C)
(25C)
0.5
0
2 2.5 3 3.5 4 4.5 5 5.5
VREFH (V)
XXXXXXXXXX PIC18F6620
XXXXXXXXXX -I/PT
XXXXXXXXXX 0410017
YYWWNNN
XXXXXXXXXXXX PIC18F8720
XXXXXXXXXXXX -E/PT
YYWWNNN 0410017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
D1 D
2
1
B
n
CH x 45 °
α
A
c
A2
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β A1
(F)
E
E1
#leads=n1
D1 D
2
B 1
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(F)
INDEX
A Analog Input Model .................................................. 217
Baud Rate Generator .............................................. 183
A/D ................................................................................... 213
Capture Mode Operation ......................................... 151
A/D Converter Interrupt, Configuring ....................... 217
Comparator Analog Input Model .............................. 227
Acquisition Requirements ........................................ 218
Comparator I/O Operating Modes (Diagram) .......... 224
Acquisition Time ....................................................... 218
Comparator Output .................................................. 226
ADCON0 Register .................................................... 213
Comparator Voltage Reference ............................... 230
ADCON1 Register .................................................... 213
Compare Mode Operation ....................................... 152
ADCON2 Register .................................................... 213
Low-Voltage Detect (LVD) ....................................... 234
ADRESH Register ............................................ 213, 215
Low-Voltage Detect (LVD) with External Input ........ 234
ADRESL Register ............................................ 213, 215
MSSP (I2C Master Mode) ........................................ 181
Analog Port Pins ...................................................... 128
MSSP (I2C Mode) .................................................... 166
Analog Port Pins, Configuring .................................. 219
MSSP (SPI Mode) ................................................... 157
Associated Register Summary ................................. 221
On-Chip Reset Circuit ................................................ 29
Calculating Minimum Required
PIC18F6X20 Architecture ............................................ 9
Acquisition Time (Example) ............................. 218
PIC18F8X20 Architecture .......................................... 10
CCP2 Trigger ........................................................... 220
PLL ............................................................................ 23
Configuring the Module ............................................ 217
PORT/LAT/TRIS Operation ..................................... 103
Conversion Clock (TAD) ........................................... 219
Conversion Requirements ....................................... 341 PORTA
RA3:RA0 and RA5 Pins ................................... 104
Conversion Status (GO/DONE Bit) .......................... 215
Conversion TAD Cycles ............................................ 220 RA4/T0CKI Pin ................................................ 104
Conversions ............................................................. 220 RA6 Pin (as I/O) .............................................. 104
PORTB
Converter Characteristics ........................................ 340
Equations ................................................................. 218 RB2:RB0 Pins .................................................. 107
Minimum Charging Time .......................................... 218 RB3 Pin ........................................................... 107
RB7:RB4 Pins .................................................. 106
Special Event Trigger (CCP) .................................... 152
Special Event Trigger (CCP2) .................................. 220 PORTC (Peripheral Output Override) ...................... 109
TAD vs. Device Operating Frequencies (Table) ....... 219 PORTD and PORTE
Parallel Slave Port ........................................... 128
Absolute Maximum Ratings ............................................. 307
AC (Timing) Characteristics ............................................. 320 PORTD in I/O Port Mode ......................................... 111
PORTD in System Bus Mode .................................. 112
Load Conditions for Device
Timing Specifications ....................................... 321 PORTE in I/O Mode ................................................. 115
Parameter Symbology ............................................. 320 PORTE in System Bus Mode .................................. 115
PORTF
Temperature and Voltage Specifications ................. 321
Timing Conditions .................................................... 321 RF1/AN6/C2OUT and
ACKSTAT Status Flag ..................................................... 187 RF2/AN5/C1OUT Pins ............................ 117
RF6/RF3 and RF0 Pins ................................... 118
ADCON0 Register ............................................................ 213
GO/DONE Bit ........................................................... 215 RF7 Pin ........................................................... 118
ADCON1 Register ............................................................ 213 PORTG (Peripheral Output Override) ..................... 120
PORTH
ADCON2 Register ............................................................ 213
ADDLW ............................................................................ 265 RH3:RH0 Pins in System Bus Mode ....... 123
Addressable Universal Synchronous Asynchronous RH3:RH0 Pins in I/O Mode .............................. 122
RH7:RH4 Pins in I/O Mode .............................. 122
Receiver Transmitter (USART) ................................ 197
ADDWF ............................................................................ 265 PORTJ
ADDWFC ......................................................................... 266 RJ4:RJ0 Pins in System Bus Mode ................. 126
RJ7:RJ6 Pins in System Bus Mode ................. 126
ADRESH Register .................................................... 213, 215
ADRESL Register .................................................... 213, 215 PORTJ in I/O Mode ................................................. 125
Analog-to-Digital Converter. See A/D. PWM Operation (Simplified) .................................... 154
Reads from Flash Program Memory ......................... 65
ANDLW ............................................................................ 266
ANDWF ............................................................................ 267 Single Comparator ................................................... 225
Assembler Table Read Operation ............................................... 61
Table Write Operation ............................................... 62
MPASM Assembler .................................................. 301
Table Writes to Flash Program Memory .................... 67
B Timer0 in 16-bit Mode .............................................. 132
Baud Rate Generator ....................................................... 183 Timer0 in 8-bit Mode ................................................ 132
BC .................................................................................... 267 Timer1 ..................................................................... 136
BCF .................................................................................. 268 Timer1 (16-bit R/W Mode) ....................................... 136
BF Status Flag ................................................................. 187 Timer2 ..................................................................... 142
Block Diagrams Timer3 ..................................................................... 144
16-bit Byte Select Mode ............................................. 75 Timer3 in 16-bit R/W Mode ...................................... 144
16-bit Byte Write Mode .............................................. 73 Timer4 ..................................................................... 148
16-bit Word Write Mode ............................................. 74 USART Receive ...................................................... 206
A/D ........................................................................... 216
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