Compact Car Parking System

-1-
COMPACT CAR PARKING SYSTEM

A.A.N.M. & V.V.R.S.R.POLYTECHNIC, GUDLAVALLERU

CHAPTER-1
INTRODUCTION
Today, due to the advent of the latest technology, there is a solution that is
being for every problem. Almost, any problem that plagues humanity has been given a
severe thrash in the form of a sound reciprocation.
Even in this new era, where the size of an electronic gadget has been reduced to a
pin size object, that retains all the features of its complex version, some problems still
plague humanity. At this point of time, the main problems that have been troubling
human life are Unemployment, Pollution, Poverty, Traffic congestion at crowded areas
etc.,
We have always been in the forefront to find at least a paltry solution to any one of
the problems that have existed for so long now. We decided to whet our inquisitive
brains in order to find a tentative solution to any one problem. During this course of
time, we have decided to find an exciting reply to the parking of cars at crowded areas.
With this spark, we could ignite a whole new concept that is bound to create tremors
among the unruly people who demand a huge amount just for parking. Thus, this small
spark of ours ignited into the idea "Micro controller based Compact Parking System.
Now a days, vehicle parking near shopping malls is one of the biggest problems in
the world. Two wheelers need a small space for parking whereas four wheelers occupy
a relatively wider parking in this system. In this system, we have placed vertical racks in
underground that are capable of moving up and down because of a driving mechanism.
This driving mechanism is taken care by the usage of stepper motors. A versatile Micro
controller AT89C51 is used to control all operations. This system also uses a serial
EEPROM to store a password. An LCD display and a keyboard have been provided for
the user to view and type the passwords respectively.
The principle here is the fact that when a car arrives for parking, IR gate sensor
makes the gate to open upon receiving a feedback from the Micro controller regarding a
vacant rack. The vacant rack's number will be automatically displayed on the display.
The user then can type a four-digit password and after it gets accessed, the rack
automatically goes underground.
Thus, we hope that system solves the parking problem at least to some extent.

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CHAPTER-2
BLOCK DIAGRAM

FIG 2.1 BLOCK DIAGRAM

The block diagram includes the Micro controller unit that controls all the control
operations and the interfaced units include the keyboard, serial EEPROM, LCD and the
MOSFET driver circuits which connect the stepper motors to the micro controller unit.
The keyboard helps in entering the password which is stored in the serial EEPROM and
the LCD helps in the display of the rack number for the user. The IR
transmitter/receiver senses the arrival of the car and sends the information to the micro
controller unit to perform the required task. The zero position feedback system helps in
indicating the position of the rack. Two stepper-motors are used; one for the movement
of the rack and the other is for the gate movement.

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CHAPTER 3
PRINCIPLE OF OPERATION

The principle of operation includes the sensing of the car by the IR sensor and the
driving mechanism by the stepper motor
When a car arrives for parking, IR sensor placed at the gate will give feed back to
micro controller. MC checks the vacant rack. Then MC moves the stepper motor till the
vacant rack is placed in front of the gate.
In this system we are providing vertical racks, placed in under ground. These racks
are connected to a driving mechanism, which will move the racks in upward or
downward direction. Stepper motors are used in driving mechanism because of their
precise movements.
When power is switched on, controller is reset by power on reset circuit. Then it
scans gate sensor continuously. As soon as a car is placed between the sensors, the IR
beam is intersected and the Rx o/p will go high. By sensing this, micro controller opens
the gate by driving stepper motor 6 revolutions to open 90 up. Then it searches for
vacant rack and drives other motor 10 revolutions per rack to place the rack in front of
the gate. While moving lift, it scans slot sensors to sense the position. When the plate
attached backside of the rack crosses the slot, then it intersects the light beam so that the
output goes low. After sensing this, micro controller stops the rack movement. After
parking the vehicle, the user has to enter his password, using keyboard to protect his
rack. Then the gate closes and rack moves to home position and store the rack position
as filled in memory.
Again when the user press open key, system asks for password and when it
matches, it opens the rack again and store the rack position as vacant in memory then it
moves into home position after time delay.
A full wave rectifier along with filter and regulator is used to generate +12V
unregulated and +5V regulated D.C. +12V is used for stepper motor driving and +5V is
used for control circuit operation.

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CHAPTER 4
WORKING OF SYSTEM

There are two processes, the user has to undergo
1. Entering.
2. Leaving.

ENTERING:

When a vehicle arrives for parking, the IR sensor present near the gate will sense the car
and sends the information to the MC. The MC checks for the vacant racks and places
the vacant rack in front of the gate and opens the gate. Then the user parks the vehicle
on the rack and then finally gives the password. After entering the password, the buzzer
gives a beep sound and displays the number of the rack in which the car is placed. This
completes the entry action.

LEAVING:

When the user wants to get his car back then he need to enter the number of the rack
and then the password. Then the microcontroller identifies the car based on the
password and opens the gate and places the car on the track opening the gate. This
completes the leaving action and the rack is available for further use.

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CHAPTER-5
CIRCUIT DIAGRAM

FIG-5.1.CIRCUIT DIAGRAM

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CHAPTER 6
CIRCUIT DESCRIPTION
6.1 HARDWARE DESCRIPTION:
The micro-controller continuously keeps on checking the status of the IR
transmitter/receiver that is connected to the 8 pin and when the input to that pin is low it
indicates the presence of vehicle and then it keeps on checking the status of the racks
inorder to find the vacant rack. After finding the vacant rack it energizes the stepper
motor connected to the rack by passing a low-level input to the driver circuits connected
to pins P
3.4
to P
3.7
. The slot sensor connected to the port P
3.2
helps in placing the rack at
the right position near the gate. After the rack reaches the ground level the stepper
motor of the gate is energized to open the gate. It takes 2 revolutions for the gate to
open. Then the vehicle is placed on the rack and the user gives the password through the
keypad. This is stored in the serial EEPROM through the control pins connected to P
3.0
and P
3.1
. Whet the user gives the number of the rack it senses that it is a leaving process
and asks for password. After retrieving the car it clears the password memory by
passing all zeros. After a particular amount of delay the gate automatically closes. All
the control is done through software programming.
The hardware circuitry comprises of the following:
1. Power supply
2. IR Transmitter/Receiver
3. Micro controller (AT89C51)
4. 16x2 character LCD
5. 4x3 matrix Key pad
6. Stepper motor
7. MOSFET driver circuitry
8. Slot sensor
9. Serial EEPROM (AT24C04)
10. LM358
11. Buzzer
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6.1.1 POWER SUPPLY:

FIG 6.1 POWER SUPPLY

Power supply unit provides 5V regulates power supply to the systems. It consists
of two parts namely,
1. Rectifier
2. Monolithic voltage regulator

RECTIFIER:
Here the step down transformer 230-0V/12-0-12 and gives the secondary current up
to 2A, to the Rectifier. The Transformer secondary is provided with a center tap.
Hence the voltage V
1
and V
2
are equal and are having a phase difference of 180
0
. So it
is anode of Diode D
1
is positive with respect to the center tap, the anode of the other
diode D
2
will be negative with respect to the center tap. During the positive half cycle
of the supply D
1
conducts and current flows through the center tap D
1
and load.
During this period D
2
will not conduct as its anode is at a negative potential. During the
negative half cycle of the supply voltage, the voltage on the diode D
2
will be positive
and hence D
2
conducts. The current flows through the transformer winding, Diode D
2

and load. It is to be noted that the current I
1
and I
2
are flowing in the same direction in
load.

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The average of the two currents I
1
and I
2
flow through the load producing a voltage
drop, which is the D.C. output voltage of the rectifier. Using capacitor filters the ripple
in the out waveform can be minimized. The voltage can be regulated by using
monolithic IC voltage regulators.

MONOLITHIC IC VOLTAGE REGULATOR:
A voltage regulator is a circuit that supplies a constant voltage regardless of
changes in load currents. Although voltage regulators can be designed using op-amps, it
is quicker and easier to use IC voltage regulators. Furthermore, IC voltage regulators are
versatile and relatively inexpensive and are available with features such as
programmable output, current/voltage boosting, internal short-circuit current limiting,
thermal shutdown and floating operation for high voltage applications.

Here we are using 7800 series voltage regulators. The 7800 series consists of 3-
terminal positive voltage regulators with seven voltage options. These ICs are designed
as fixed voltage regulators and with adequate heat sinking can deliver output currents in
excess of 1A. Although these devices do not require external components, such
components can be used to obtain adjustable voltages and currents. For proper operation
a common ground between input and output voltages is required. In addition, the
difference between input and output voltages (Vi Vo) called drop out voltage, must be
typically 1.5V even during the low point as the input ripple voltage. Further more, the
capacitor C
i
is required if the regulator is located an appreciable distance from a power
supply filter. Typical performance parameters for voltage regulators are line regulation,
load regulation, temperature stability and ripple rejection. Line regulation is defined as
the change in output voltage for a change in the input voltage and is usually expressed
in millivolts or as a percentage of Vo. Temperature stability or average temperature
coefficient of output voltage (Tcvo) is the change in output voltage per unit change in
temperature and is expressed in either millivolts/C or parts per million (PPM/C).
Ripple rejection is the measure of a regulators ability to reject ripple voltage. It is
usually expressed in decibels. The smaller the values of line regulation, load regulation
and temperature stability the better the regulation.

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6.1.2 IR TRANSMITTER AND RECEIVER:

FIG 6.2 IR TRANSMITTER/RECEIVER CIRCUIT

Infrared transmitter is one type of LED which emits infrared rays generally called IR
Transmitter. Similarly IR Receiver is used to receive the IR rays transmitted by the IR
transmitter. One important point is that both IR transmitter and receiver should be
placed in a straight line to each other.
IR transmitter continuously emits the IR light rays. When an obstacle occurs these
rays are reflected by the obstacle and are collected by IR receiver. The IR receiver is
connected to the comparator. The comparator is constructed using LM358. In the
comparator circuit the reference voltage is given to inverting input terminal. The non-
inverting terminal is connected to IR receiver. When no interrupt occurs the IR rays are
not reflected to the receiver so the IR receiver is not conducting. So the comparator
inverting input voltage is higher then non-inverting input. So it sends an active low pulse
to the MCU. When there is vehicle in between transmitter and receive, IR rays are collected
by receiver and the non-inverting input voltage is greater and thus sends a high pulse to
the micro-controller which indicates the presence of vehicle. Thus the vehicle is detected.
6.1.3 MICRO CONTROLLER(AT89C51)
The system requirements and control specifications clearly rule out the use of 16, 32 or
64 bit micro controllers or microprocessors. Systems using these may be earlier to
implement due to large number of internal features. They are also faster and more
reliable but, the above application is satisfactorily served by 8-bit micro controller.
Using an inexpensive 8-bit Microcontroller will doom the 32-bit product failure in any
competitive market place.

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The micro controller employed here is AT89C51.The reason for adopting this
micro controller is the 8-bit Microcontroller available in the market the main answer
would be because it has 4 Kb on chip flash memory which is just sufficient for our
application. The on-chip Flash ROM allows the program memory to be reprogrammed
in system or by conventional non-volatile memory Programmer. The Atmel AT89C51
is a powerful microcomputer which provides a highly-flexible and cost-effective
solution to many embedded control applications. Moreover ATMEL is the leader in
flash technology in todays market place and hence using
AT 89C51 is the optimal solution.

FIG 6.3 PIN DIAGRAM OF AT89C51

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FIG 6.4 BLOCK DIAGRAM OF AT89C51
FEATURES:
Compatible with MCS-51 Products
4K Bytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel

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SALIENT FEATURES:
The 89C51 can be configured to bypass the internal 4K ROM and run solely with
external program memory. For this its external access (EA) pin has to be grounded,
which makes it equivalent to 8031. The program store enable (PSEN) signal acts as read
pulse for program memory. The data memory is external only and a separate RD* signal
is available for reading its contents. Use of external memory requires that three of its 8-bit
ports (out of four) are configured to provide data/address multiplexed bus. Hi address bus and
control signals related to external memory use. The RXD and TXD ports of UART also appear
on pins 10 and 11 of 8051 and 8031, respectively. One 8-bit port, which is bit addressable is
extremely useful for control applications.
The UART utilizes one of the internal timers for generation of baud rate. The crystal used for
generation of CPU clock has therefore to be chosen carefully. The 11.0596 MHz crystals;
available abundantly, can provide a baud rate of 9600.

HARDWARE DETAILS:
The on chip oscillator of 89C51 can be used to generate system clock. Depending upon
version of the device, crystals from 3.5 to 12 MHz may be used for this purpose. The
system clock is internally divided by 6 and the resultant time period becomes one
processor cycle. The instructions take mostly one or two processor cycles to execute,
and very occasionally three processor cycles. The ALE (address latch enable) pulse rate
is 16th of the system clock, except during access of internal program memory, and thus
can be used for timing purposes.
The two internal timers are wired to the system clock and prescaling factor is decided
by the software, apart from the count stored in the two bytes of the timer control
registers. One of the counters, as mentioned earlier, is used for generation of baud rate
clock for the UART. It would be of interest to know that the 8052 have a third timer,
which is usually used for generation of baud rate.
The reset input is normally low and taking it high resets the micro controller, In the
present hardware, a separate CMOS circuit has been used for generation of reset signal
so that it could be used to drive external devices as well.

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WRITING THE SOFTWARE:
The 89C51 has been specifically developed for control applications. As mentioned
earlier, out of the 128 bytes of internal RAM, 16 bytes have been organized in such a
way that all the 128 bits associated with this group may be accessed bit wise to facilitate
their use for bit set/reset/test applications. These are therefore extremely useful for
programs involving individual logical operations. One can easily give example of lift
for one such application where each one of the floors, door condition, etc may be
depicted by a single hit.
The 89C51 has instructions for bit manipulation and testing. Apart from these, it has 8-bit
multiply and divide instructions,which may be used with advantage. The 89C51 has short
branch instructions for 'within page' and conditional jumps, short jumps and calls within 2k
memory space which are very convenient, and as such the controller seems to favor programs
which are less than 2k byte long. Some versions of 8751 EPROM devices have a security bit
which can be programmed to lock the device and then the contents of internal program EPROM
cannot be read. The device has to be erased in full for further alteration, and thus it can only be
reused but not copied. EEPROM and FLASH memory versions of the device are also available
now.
MEMORY UNIT:
Memory is part of the micro controller whose function is to store data. The easiest way
to explain it is to describe it as one big closet with lots of drawers. If we suppose that we
marked the drawers in such a way that they cannot be confused, any of their contents
will then be easily accessible. It is enough to know the designation of the drawer and so
its contents will be known to us for sure.
Memory components are exactly like that. For a certain input we get the contents of a
certain addressed memory location and thats all. Two new concepts are brought to us:
addressing and memory location. Memory consists of all memory locations, and
addressing is nothing but selecting one of them. This means that we need to select the
desired memory location on one hand, and on the other hand we need to wait for the
contents of that location. Besides reading from a memory location, memory must also
provide for writing onto it. This is done by supplying an additional line, called control
line. We will designate this line as R/W. Control line is used in the following way: if
r/w=1, reading is done, and if opposite is true then writing is done on the memory
location. Memory is the first element, and we need a few operation of our micro
controller.
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CENTRAL PROCESSING UNIT :
Let us add 3 more memory locations to a specific block that builds in capability to
multiply, divide, subtract, and move its contents from one memory location onto
another. The part we just added in is called central processing unit (CPU). Its memory
locations are called registers.
Registers are therefore memory locations whose role is to help with performing various
mathematical operations or any other operations with data wherever data can be found.
Look at the current situation. We have two independent entities (memory and CPU),
which are interconnected, and thus any exchange of data is hindered, as well as its
functionality. If, for example, we wish to add the contents of two memory locations and
return the result again back to memory, we would need a connection between memory
and CPU. Simply stated, we must have some way through data goes from one block
to another.
BUS:
It represents a group of 8, 16, or more wires. There are two types of buses: address and data
bus. The first one consists of as many lines as the amount of memory we wish to address, and
the other one is as wide as data, in our case 8 bits or the connection line. First one serves to
transmit address from CPU memory, and the second to connect all blocks inside the micro
controller.
INPUT-OUTPUT UNIT;
Those locations weve just added are called ports. There are several types of ports: input,
output or bi-directional ports. When working with ports, first of all it is necessary to choose
which port we need to work with, and then to send data to, or take it from the port. When
working with it the port acts like a memory location. Something is simply being written into or
read from it, and it could be noticed on the pins of the micro-controller.
6.1.4 LIQUID CRYSTAL DISPLAY:
The alphanumeric 16character X 2line LCD requires 8data lines and also 3 control
signals and they are interfaced to 3664.By using 2 ports, port 0&3 data pins are
connected to LCD as data bus. Port0 can be basically used as I/O port i.e. it can be
programmed as an input or as an output port. That means if it is programmed as output
port, suppose if it is required to read data from LCD immediately it is not possible.
Before reading the data it is required to make the port as an input port. Data reading
from LCD gives an erroneous reading & should not be implemented.
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Because of this port5 is made as input / output port depending on the situation. The
control signals are connected to port 3 pins. They are EN bar & RS bar, RW bar. At
different instance such as data write / command write / data read etc. Various signals are
to be provided as indicated by the by the LCD manufacturers.

FIG 6.5 LCD PIN CONFIGURATION

To interface the LCD, to the Micro controller it require an 8 bit and also three control
signals differentiate the data from the control words send to the LCD. The Micro
controller has to send the necessary control words followed by the data to be displayed.
Depending on the operation to be performed the control words are selected and passes
to the LCD. The data to be displayed on the LCD is to be sent in the ASCII format.
Thus all the character to be displayed are converted into ASCII form and then sent to
the LCD along with different control words. The control word differentiates the various
operations to be executed. It is also possible to read the LCD data if required.
The control signals to the LCD are also provided by the Micro controller. This is also
done through pins 2.5, 2.6, 2.7.Through program necessary control signals are passed to
the LCD by using the bits of the port. The remaining can be used for some other
purpose if there is a need. The software controls the necessary ports and performs the
task it is designed .

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PIN DESCRIPTION:

-17-

6.1.5 4 by3 MATRIX KEYPAD:
This simple 4x3 keypad permits data entry to a microcontroller I/O port .The 4 rows are
connected via 100k pull-down resistors to ground, so reading a row with all switches
open returns a "0". Rows 1, 2, 3 and 4 are connected to port pins 1, 2, 3 and 4
respectively and Columns 1, 2 and 3 are routed to port pins 5, 6 and 7 respectively.

FIG 6.6 KEYPAD
6.1.6 STEPPER MOTORS
These motors are also called stepping motors or step motors. This name is used because
this motor rotates trough a fixed angular step in response to each input current pulse
received by its controller. In the recent years, there has been wide demand of stepping
motors because of the explosive growth of the computer industry. This popularity is due
to the fact that they can be directly controlled by computers, microprocessors and
programmable controllers.
As we know industrial motors are used to convert electrical energy into
mechanical energy but they cannot be used for precision positioning of an object. These
stepper motors are ideally suited for situations where precise positioning is required.
When a command pulse is received each time the output shaft rotates in a series of
discrete angular intervals. When number of pulses supplied are definite then shaft of the
stepper motor turns through definite known angle. This makes stepper motor suited for
open loop position control because no feedback need to be taken from the shaft.

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Such motors develop some torques ranging from 1Mn-m. In a tiny wristwatch motor of
3mm diameter, up to 40N-M in a motor of 15cm diameter suitable for machine tool
applications. Power output ranges from 1Wto a max of 2500W. The only moving party
in a stepper motor is its rotor, which has no windings, commutator or brushes. This
feature makes it quite robust and reliable.

STEP ANGLE: The angle through which motor shaft rotates for each command is
called the step angle. Smaller the stepper angle, greater the no. of steps for revolution
and higher the resolution or accuracy of positioning obtained. The step angle can be as
small as 0.72 degrees as large as 90 degrees. But most common step sizes are 1.8, 2.5,
7.5 and 15.

Resolution is given by the number of steps needed to complete one revolution of
the rotor shaft. Higher the resolution greater the extraordinary ability to operate at very
high stepping rates up to (20,000 steps 1 second) Operation at high speeds is called
slewing.

Stepping motors come in two varieties, permanent magnet and variable reluctance
(there are also hybrid motors, which are indistinguishable from permanent magnet
motors from the controller's point of view). Lacking a label on the motor, you can
generally tell the two apart by feel when no power is applied. Permanent magnet motors
tend to "cog" as you twist the rotor with your fingers, while variable reluctance motors
almost spin freely (although they may cog slightly because of residual magnetization in
the rotor). You can also distinguish between the two varieties with an ohmmeter.
Variable reluctance motors usually have three (sometimes four) windings, with a
common return, while permanent magnet motors usually have two independent
windings, with or without center taps. Center-tapped windings are used in unipolar
permanent magnet motors.

-19-


Stepping motors come in a wide range of angular resolution. The coarsest motors
typically turn 90 degrees per step, while high- resolution permanent magnet motors are
commonly able to handle 1.8 or even 0.72 degrees per step. With an appropriate
controller, most permanent magnet and hybrid motors can be run in half steps, and some
controllers can handle smaller fractional steps or micro steps. For both permanent
magnet and variable reluctance stepping motors, if just one winding of the motor is
energized, the rotor (under no load) will snap to a fixed angle and then hold that angle
until the torque exceeds the holding torque of the motor, at which point, the rotor will
turn, trying to hold at each successive equilibrium point.

UNIPOLAR MOTORS

FIG 6.7 UNIPOLAR STEPPER MOTOR

Unipolar stepping motors, both Permanent magnet and hybrid stepping motors with 5 or
6 wires are usually wired as shown in the schematic in FIG 6.7, with a center tap on
each of two windings. In use, the center taps of the windings are typically wired to the
positive supply, and the two ends of each winding are alternately grounded to reverse
the direction of the field provided by that winding.

The motor cross section shown in FIG 6.7 is of a 30 degree per step permanent magnet
or hybrid motor -- the difference between these two motor types is not relevant at this
level of abstraction. Motor winding number 1 is distributed between the top and bottom
stator pole, while motor winding number 2 is distributed between the left and right
motor poles. The rotor is a permanent magnet with 6 poles, 3 souths and 3 norths,
arranged around its circumference.
-20-


For higher angular resolutions, the rotor must have proportionally more poles. The
30- degree per step motor in the figure is one of the most common permanent magnet
motor designs, although 15 and 7.5 degree per step motors are widely available.
Permanent magnet motors with resolutions as good as 1.8 degrees per step are made,
and hybrid motors are routinely built with 3.6 and 1.8 degrees per step, with resolutions
as fine as 0.72 degrees per step available.
As shown in the figure, the current flowing from the center tap of winding 1 to terminal
a causes the top stator pole to be a north pole while the bottom stator pole is a south
pole. This attracts the rotor into the position shown. If the power to winding 1 is
removed and winding 2 is energized, the rotor will turn 30 degrees, or one step.

CONCEPTUAL MODEL OF UNIPOLAR STEPPER MOTOR

FIG 6.8 CONCEPTUAL MODEL OF UNIPOLAR STEPPER MOTOR

With center taps of the windings wired to the positive supply, the terminals of each
winding are grounded, in sequence, to attract the rotor, which is indicated by the arrow
in the picture. (Remember that a current through a coil produces a magnetic field.)
This conceptual diagram depicts a 90-degree step per phase.
-21-


In a basic "Wave Drive" clockwise sequence, winding 1a is de-activated and winding 2a
activated to advance to the next phase. The rotor is guided in this manner from one
winding to the next, producing a continuous cycle. Note that if two adjacent
windings are activated, the rotor is attracted mid-way between the two windings.

The following table describes 3 useful stepping sequences and their relative merits. The
sequence pattern is represented with 4 bits, a '1' indicates an energized winding. After
the last step in each sequence the sequence repeats. Stepping backwards through the
sequence reverses the direction of the motor.

Table of Stepping Sequences
Sequence Name Description
0001
0010
0100
1000
Wave
Drive,
One-
Phase
Consumes the least power. Only one phase is
energized at a time. Assures positional accuracy
regardless of any winding imbalance in the
motor.
0011
0110
1100
1001
Hi-
Torque,
Two-
Phase
Hi Torque - This sequence energizes two
adjacent phases, which offers an improved
torque-speed product and greater holding torque.
-22-

0001
0011
0010
0110
0100
1100
1000
1001
Half-Step Half Step - Effectively doubles the
stepping resolution of the motor, but the
torque is not uniform for each step.
(Since we are effectively switching
between Wave Drive and Hi-Torque with
each step, torque alternates each step.)
This sequence reduces motor resonance,
which can sometimes cause a motor to
stall at a particular resonant frequency.
Note that this sequence is 8 steps.

IDENTIFYING STEPPER MOTORS

FIG 6.9 STEPPER MOTOR IDENTIFICATION DIAGRAM

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Stepper motors have numerous wires, 4, 5, 6, or 8. When you turn the shaft you will
usually feel a "notched" movement. Motors with 4 wires are probably bipolar motors
and will not work with a Unipolar control circuit. The most common configurations are
pictured above. Measuring from one coil to the other will show an open circuit, since
the 2 coils are not connected.

SHORTCUT FOR FINDING THE PROPER WIRING SEQUENCE
Connect the center tap(s) to the power source (or current-Limiting resistor.) Connect the
remaining 4 wires in any pattern. If it doesn't work, you only need try these 2 swaps...
1 2 4 8 - (arbitrary first wiring order)
1 2 8 4 - switch end pair
1 8 2 4 - switch middle pair
You're finished when the motor turns smoothly in either direction. If the motor turns in
the opposite direction from desired, reverse the wires so that ABCD would become
DCBA.

HEAT CONSIDERATIONS

Over-heating can be an early indicator of a problem or need for additional heat sinking.
This is true of both the controller and motors. Components can be warm to the touch,
but not so hot that you can't leave your finger on them for a few seconds.
Motors are designed to be mounted in such a way that, heat is drawn away from the
motors. This is usually accomplished with a metal mounting bracket. Motors that are
not yet mounted may require some type of temporary heat sinking. Motors heat more
running at the LOW speeds or in Hold Mode.

-24-


6.1.7 MOSFET DRIVER CIRCUITRY:

FIG 6.10 MOSFET DRIVER CIRCUIT

When the output of the controller is high, the base current I flows in to base of the
transistor, thus providing voltage drop more then 0.7V across the Ve junction, thus the
transistor goes in to saturation mode. So the Ic is maximum and the voltage drop across
the Vce junction is zero. I.e. the input to MOSFET is zero. So the MOSFET will not
conduct and stepper motor coil will not energize.
If the output of the controller is low, the base current I is zero, thus providing
voltage drop less then 0.1V across the V
BE
junction, thus the transistor goes in to cut-off
mode. So the Ic is minimum and the voltage drop across the V
CE
junction is maximum.
I.e. the input to MOSFET is almost Vcc. So the MOSFET will conduct and stepper
motor coil get energized. For driving of motor coils, we used IRF540 MOSFET, which
are having low on-state resistance so that the dissipation is less, fast switching and low
thermal resistance. This MOSFET is driven by BC548 transistor. For each motor four
MOSFET sections are required.
6.1.8 SLOT SENSOR:
This device has a compact construction where the emitting-light sources and the
detectors are located face-to-face on the same optical axis. The operating wavelength is
950 nm. The detector consists of a phototransistor.

-25-


APPLICATIONS:
Contactless optoelectronic switch, control and counter

FEATURES:
Compact construction
No setting efforts
case variations
Polycarbonate case protected against ambient light
Current Transfer Ratio (CTR) of typical 2.5%

6.1.9 SERIAL EEPROM (AT24C04):
There are several forms of memory that don't require the standard address bus and data
bus wiring. These memories are called serial memories, and they are just the ticket to
allow you to store large amounts of information without giving up those precious I/O
lines. There are several different styles of serial EEPROM. The big advantage to using a
Serial EEPROM is that the wiring only requires 4 signal lines from the CPU to operate
it.
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial
electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation are
essential. The entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.

FIG 6.11 PIN DIAGRAM OF AT24C04 PIN DESCRIPTION

-26-


SERIAL CLOCK (SCL) : The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight
1K/2K devices may be addressed on a single bus system (device addressing is discussed
in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs
for hard wire addressing and a total of four 4K.The A0 pin is a no connect and can be
connected to ground.
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no connects
and can be connected to ground.
WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal Read/Write
operations when connected to ground (GND). When the Write Protect pin is connected
to VCC, the write protection feature is enabled.
6.1.10 LM358:
These devices consist of two independent, high-gain, frequency-compensated
operational amplifiers designed to operate from a single supply over a wide range of
voltages. Operation from split supplies also is possible if the difference between the two
supplies is 3 V to 30 V (3 V to 26 V for the LM2904 and LM2904Q), and VCC is at
least 1.5 V more positive than the input common-mode voltage. The low supply-current
drain is independent of the magnitude of the supply voltage. Applications include
transducer amplifiers, dc amplification blocks, and all the conventional operational
amplifier circuits that now can be implemented more easily in single-supply-voltage
systems. For example, these devices can be operated directly from the standard 5-V
supply used in digital systems and easily provide the required interface electronics
without additional 5-V supplies.

-27-


FIG 6.12 PIN DIAGRAM OF LM358
FEATURES:
Wide Range of Supply Voltages
Single Supply . . . 3 V to 30 V
Dual Supplies
Low Supply-Current Drain Independent of
Supply Voltage . . . 0.7 mA Typ
Common-Mode Input Voltage Range
Low Input Bias and Offset Parameters:
Input Offset Voltage . . . 3 mV Type
Input Offset Current . . . 2 nA Type
Input Bias Current . . . 20 nA Type
Differential Input Voltage Range Equal to
Maximum-Rated Supply Voltage . . . 32 V
(LM2904 and LM2904Q . . . 26 V)
Open-Loop Differential Voltage
Amplification . . . 100 V/mV Type
Internal Frequency Compensation
6.1.11 BUZZER:

FIG 6.13 BUZZER CIRCUIT

-28-


When the output of the controller is high, the base current I
B
flows in to base of the
transistor, thus providing voltage drop more then 0.7V across the V
BE
junction, thus the
transistor goes in to saturation mode. So the I
C
is maximum and the LED will glow and
simultaneously, buzzer gives a beep sound.

6.2 SOFTWARE DESCRIPTION

ALGORITHM:

STEP 1: INTIALISE THE MICRO-CONTROLLER AND OTHER FUNCTIONS
INTIALISE I/O PORTS, STACK POINTER
INTIALISE LCD AND DISPLAY TITLES
MOVE THE RACK TO HOME POSITION
READ EEPROM

STEP 2: SCAN THE SENSOR
IF SENSOR NOT ACTIVE, DISPLAY PUT CAR ON TRACK
IF ACTIVE, CHECK THE STATUS OF EACH RACK
IF RACK1 VACANT OPEN RACK1
ELSE IF RACK2 VACANT OPEN RACK2
IF NO RACK IS VACANT DISPLAY RACKS FILLED

STEP 3: OPEN THE GATE AND SCAN FOR PASSWORD
IF WAITING FOR PASSWORD, STORE NUMBERS AS
PASSWORDS,
SET THE STATUS OF THAT PARTICULAR RACK. (FOR ENTRY
PROCESS)
ELSE IF KEY1 PRESSED, SCAN FOR PASSWORD 1.

STEP 4: IF CODE ENTERED AND # IS PRESSED
STORE THE PASSWORD AND RETURN TO STEP2 ( FOR
ENTERING
PROCESS)
IF PASSWORD MATCHED, OPEN THE CORRESPONDING RACK
AND
RESET THE FLAG STATUS OF THAT RACK.(FOR LEAVING
PROCESS)
IF NOT MATCHED COUNT FALSE COUNTS AND IF GREATER
THAN 3
RING BUZZER

-29-

PROGRAMMING:

;> TITLE : COMPACT PARKING SYSTEM
;> TARGET : AT89C51
;>
;---------------------------------------------------------------------------------------------------------
;>
;> INCLUDES :
$MOD51
;>
;---------------------------------------------------------------------------------------------------------
;>
;> HARD WARE DETAILS :
;>
;> DISPLAY ENABLE - P2.5
DEN BIT P2.5
;> DISPLAY READ/WRITE - P2.6
DRW BIT P2.6
;> DISPLAY REG SELECT - P2.7
DRS BIT P2.7
;> BUZZER CONTROL - P2.4
BUZ BIT P2.4
;> SERIAL DATA I/O - P3.1
SDA BIT P3.1
;> SERIAL CLOCK - P3.0
SCL BIT P3.0
;> CAR ARRIVAL FB - P1.7
CAF BIT P1.7
;> SENSOR FEED BACK EN - P3.3
LIFTFB BIT P3.3
;> GATE OPEN LIMIT - P3.2
GATEFB BIT P3.2
;>
;---------------------------------------------------------------------------------------------------------
;>
;> FLAGS:
BUSY_CHEK BIT 00H
KEY_RLS BIT 01H
INT_FLG BIT 02H
ENTR_FLG BIT 03H
OPEN_CLS BIT 04H
CLEAR_SEND BIT 05H
OPERATION BIT 06H
CLOSE BIT 07H
RACK_V1 BIT 08H
RACK_V2 BIT 09H
RACK_V3 BIT 0AH

-30-


RACK_V4 BIT 0BH
KEY_LOCK BIT 10H
MSG_LOCK BIT 11H
;>
;---------------------------------------------------------------------------------------------------------
;>
;> VARIABLES:
VACANT DATA 21H
MOT_CNT1 DATA 25H
MOT_CNT2 DATA 26H
PRV_KEY DATA 30H
KEY_PRS DATA 31H
KEY_VAL1 DATA 32H
KEY_VAL2 DATA 33H
DSP_BUF DATA 34H
ADDR_LO DATA 36H
ASC_VAL DATA 37H
KEY_VAL DATA 38H
DSP_PTR DATA 39H
MOT_COM DATA 3AH
STEP_CNT DATA 3BH
FAULT_CNT DATA 3CH
RACK_NO DATA 3DH
MEM_PTR DATA 3EH
MENU DATA 3FH
PSS_WD_A1 DATA 40H
PSS_WD_A2 DATA 41H
PSS_WD_A3 DATA 42H
PSS_WD_B1 DATA 43H
PSS_WD_B2 DATA 44H
PSS_WD_B3 DATA 45H
PSS_WD_C1 DATA 46H
PSS_WD_C2 DATA 47H
PSS_WD_C3 DATA 48H
PSS_WD_D1 DATA 49H
PSS_WD_D2 DATA 4AH
PSS_WD_D3 DATA 4BH
RACK_STS DATA 4CH

FLT_CNT DATA 4DH
TMP_WD_D1 DATA 50H
TMP_WD_D2 DATA 51H
TMP_WD_D3 DATA 52H
;>
;---------------------------------------------------------------------------------------------------------
;>

-31-


;> DEFINITIONS :
COM EQU 0fch ; command ;display headers
DAT EQU 0fdh ; data
EOL EQU 0feh ; end of line
FADDR EQU 0A0h ; read status register
PADDR EQU 00h ; programmable address (0..7)
;>
;---------------------------------------------------------------------------------------------------------
---
;>
;> VECTOR ADDRESESS:
ORG 0000H
ljmp RESET

; ORG 0003H
; reti
; ORG 000BH
; reti
; ORG 0013H
; reti
; ORG 001BH
; reti
;>
;---------------------------------------------------------------------------------------------------------
;>
RESET:
mov P3, #0FFH ; move all ports HIGH
mov P2, #0FFH
mov P1, #0FFH
mov P0, #0FFH
mov sp, #065H ; init stack pointer
mov DSP_PTR, #8BH
mov FLT_CNT, #00H
mov MEM_PTR, #PSS_WD_A1
mov R1, MEM_PTR
setb BUZ
; lcall DLY1
mov dptr, #INITIALISE
lcall MESSAGE
lcall DLY1
mov dptr, #WELCOME
lcall MESSAGE
lcall DLY
mov dptr, #COLLEGE
lcall MESSAGE

-32-


lcall DLY
mov dptr, #NAME
lcall MESSAGE
lcall DLY
mov dptr, #PRES
lcall MESSAGE
lcall DLY
mov dptr, #NAME1
lcall MESSAGE
lcall DLY
mov dptr, #NAME2
lcall MESSAGE
lcall DLY
mov dptr, #HOD
lcall MESSAGE
lcall DLY
mov dptr, #CLRSCR
lcall MESSAGE
lcall DLY1
mov dptr, #MOV_HOME
lcall MESSAGE

clr INT_FLG
clr ENTR_FLG
mov MENU, #00H
lcall BRING_HOME_LIFT
lcall READ_CARD
; mov RACK_STS, #00H
mov VACANT, RACK_STS
clr OPEN_CLS
clr MSG_LOCK
;>
;---------------------------------------------------------------------------------------------------------
;>
MAIN:
orl P2, #0FH
orl P3, #0F0H
jb ENTR_FLG, DONT_DISP_1
jb MSG_LOCK, DONT_DISP_1
setb MSG_LOCK
lcall MESSAGE
mov dptr, #TRACK
lcall MESSAGE
mov dptr, #BLANK2
lcall MESSAGE

-33-


DONT_DISP_1:

lcall MENUS
lcall OPTIONS
lcall DLY1
jb CAF, MAIN
lcall DLY1
jb CAF, MAIN
lcall DLY1
jb CAF, MAIN
clr MSG_LOCK
jb OPEN_CLS, DONT_OPRN_RACKS
setb OPEN_CLS
clr OPERATION
clr CLOSE
lcall RACK_OPEN_CLOSE
DONT_OPRN_RACKS:
ljmp MAIN
;>
;---------------------------------------------------------------------------------------------------------
;>
DISP_LET:
lcall READY ; Check weather display is ready
setb DRS
setb BUSY_CHEK
mov P0, R7 ; place the data at port 1
clr DRW
nop
setb DEN ; send enable strobe
clr DEN ;
ret ; return to message
;>
;---------------------------------------------------------------------------------------------------------
;>
DISP_COM:
clr DRS
clr BUSY_CHEK
mov P0, R7 ; place the data at port 1
clr DRW
nop
clr DEN ;
;>
;---------------------------------------------------------------------------------------------------------
;>

-34-


MESSAGE: ; sub for sending charactors to display
push acc
MESSAGE1:
clr a ; Clr accumulator
movc a, @a+dptr ; Load accumulator with the contents of dptr
inc dptr ;
cjne a, #EOL, COMD ; If the data is not end of line goto comd
pop acc
ret ; if the data is end of line stop sending

COMD: ;
cjne a, #COM, DDATA ; if the data is not command goto data
clr DRS ; COMMAND MODE
clr BUSY_CHEK
sjmp MESSAGE1 ; goto message again

DDATA: ;

cjne a, #DAT, SENDIT ; if the data is not data to be send goto
comd
setb DRS ; set DRS to high ( DATA MODE )
setb BUSY_CHEK

SENDIT: ;
mov p0, a ; place the data at port 1
clr DRW ; set WRITE MODE
nop
clr DEN ;
;>
;---------------------------------------------------------------------------------------------------------
;>
READY: ; sub to check display busy

clr DEN ; disable display buffer
mov p0, #0ffh ; set port1 in read mode
clr DRS ; COMMAND MODE
setb DRW ; READ MODE
WAIT: ;
clr DEN ; send enable strobe
setb DEN ;
jb p0.7, WAIT ; if display is not send ready signal be in loop
clr DEN ; disable display buffer
jnb BUSY_CHEK, NO_DRS_SET

-35-


setb DRS
NO_DRS_SET
;>
;---------------------------------------------------------------------------------------------------------
;>
LIFT_UP:
mov DPTR, #STEP_LIFT
mov MOT_CNT1, #20D
MOT_LOOP1:
mov MOT_CNT2, #210D
MOT_LOOP2:
inc STEP_CNT
mov A, STEP_CNT
cjne A, #04h, NOTCH5
mov STEP_CNT, #00h
NOTCH5:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P3
anl A, #0FH
orl A, R2
mov P3, A
lcall DLY2
djnz MOT_CNT2, MOT_LOOP2
orl P3, #0F0H
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
LIFT_DOWN:
mov MOT_CNT1, #20D
MOT_LOOP3:
mov MOT_CNT2, #150D
MOT_LOOP4:
dec STEP_CNT
mov A, STEP_CNT
cjne A, #0FFh, NOTCH6
mov STEP_CNT, #03h
NOTCH6:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P3
anl A, #0FH

-36-


orl A, R2
mov P3, A
lcall DLY2
orl P3, #0F0H
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
GATE_DOWN:
mov DPTR, #STEP_GATE
mov MOT_CNT1, #02D
MOT_LOOP5:
mov MOT_CNT2, #100D
MOT_LOOP6:
inc STEP_CNT
mov A, STEP_CNT
mov STEP_CNT, #00h
NOTCH4:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P2
anl A, #0F0H
orl A, R2
mov P2, A
lcall DLY2
lcall DLY2
orl P2, #0FH
ret
;>
;---------------------------------------------------------------------------------------------------------
;>

GATE_UP:
mov DPTR, #STEP_GATE
mov MOT_CNT1, #02D
MOT_LOOP7:
mov MOT_CNT2, #200D
MOT_LOOP8:
dec STEP_CNT
mov A, STEP_CNT

-37-


mov STEP_CNT, #03h
NOTCH3:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P2
anl A, #0F0H
orl A, R2
mov P2, A
lcall DLY2
lcall DLY2
jnb GATEFB, SKIP_STOP_GM
ret
SKIP_STOP_GM:
orl P2, #0FH
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
RACK_OPEN_CLOSE:
jnb OPERATION, SKIP_SENCE_SEQ1 ; RACK OPENING SEQUENCE
ljmp SKIP_SENCE_SEQ
SKIP_SENCE_SEQ1:
mov A, RACK_STS ; CHECK WEATHER RACKS ARE EMPTY
anl A, #0FH
cjne A, #0FH, RACK_NOT_EMPTY
mov DPTR, #NOT_EMPT
lcall MESSAGE
lcall DLY
ljmp SKIP_SENCE_SEQ
RACK_NOT_EMPTY:
jb RACK_V1, DONT_MOVE_LIFT1A
setb RACK_V1
orl RACK_STS, #01H ; load_rack 1 as fill
mov RACK_NO, #01H
mov DPTR, #RACK_1
lcall MESSAGE
lcall DLY
; mov MOT_COM, #01H
; lcall MOT_CNTRL
ljmp DONT_MOVE_LIFT1D
DONT_MOVE_LIFT1A:
jb RACK_V2, DONT_MOVE_LIFT1B
setb RACK_V2

-38-


mov RACK_NO, #02H
mov DPTR, #RACK_2
lcall MESSAGE
mov MOT_COM, #01H
lcall MOT_CNTRL
DONT_MOVE_LIFT1B:
jb RACK_V3, DONT_MOVE_LIFT1C
setb RACK_V3
mov RACK_NO, #03H
mov DPTR, #RACK_3
lcall MESSAGE
mov MOT_COM, #01H
lcall MOT_CNTRL
mov MOT_COM, #01H
lcall MOT_CNTRL
DONT_MOVE_LIFT1C:
jb RACK_V4, DONT_MOVE_LIFT1D
setb RACK_V4
mov RACK_NO, #04H
mov DPTR, #RACK_4
lcall MESSAGE
mov MOT_COM, #01H
lcall MOT_CNTRL
mov MOT_COM, #01H
lcall MOT_CNTRL
mov MOT_COM, #01H
lcall MOT_CNTRL
DONT_MOVE_LIFT1D:
lcall DLY1
mov dptr, #GATE_OPEN
lcall MESSAGE
mov MOT_COM, #03H ; OPENING GATE WHEN CAR
ARRIVAL
lcall MOT_CNTRL
lcall DLY1

setb OPERATION ; STOP OPENING RACKS
setb KEY_LOCK
mov MENU, #00H
lcall MESSAGE
mov DPTR, #CLRSCR

-39-


lcall MESSAGE
mov DPTR, #ASK_COD ; ASK FOR PASS WORD
lcall MESSAGE
setb ENTR_FLG ; ENABLE KEY BOARD FOR ENTERING
VALUES

mov A, RACK_NO
cjne A, #01H, LOAD_MPT1
mov MEM_PTR, #PSS_WD_A1
LOAD_MPT1:
mov MEM_PTR, #PSS_WD_B1
LOAD_MPT2:
mov MEM_PTR, #PSS_WD_C1
LOAD_MPT3:
mov MEM_PTR, #PSS_WD_D1
LOAD_MPT4:
mov R1, MEM_PTR
mov DSP_PTR, #8BH
SKIP_SENCE_SEQ:
;----------------------------------------------------------------------------
jnb CLOSE, SKIP_CLOSE_RACK ; CLOSING SEQUENCE

clr CLOSE
lcall DLY1
clr KEY_LOCK
mov dptr, #GATE_CLO
lcall MESSAGE
mov MOT_COM, #04H ; GATE CLOSING WHEN CAR PARKED
lcall MOT_CNTRL

mov A, RACK_NO
cjne A, #01H, MOVE_BACK_RACK1
mov DPTR, #RACK_C1
lcall MESSAGE
; mov MOT_COM, #02H
MOVE_BACK_RACK1:
mov A, RACK_NO
mov DPTR, #RACK_C2
lcall MESSAGE
MOVE_BACK_RACK2:
mov A, RACK_NO

-40-


mov DPTR, #RACK_C3
lcall MESSAGE
MOVE_BACK_RACK3:
mov A, RACK_NO
mov DPTR, #RACK_C4
lcall MESSAGE
MOVE_BACK_RACK4:

SKIP_CLOSE_RACK:
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
MOT_CNTRL:
mov A, MOT_COM
cjne A, #01H, MOVE_LIFT_UP
lcall LIFT_UP
MOVE_LIFT_UP:
mov A, MOT_COM
cjne A, #02H, MOVE_LIFT_DOWN
lcall LIFT_DOWN
MOVE_LIFT_DOWN:
mov A, MOT_COM
cjne A, #03H, MOVE_GATE_UP
lcall GATE_UP
MOVE_GATE_UP:
mov A, MOT_COM
cjne A, #04H, MOVE_GATE_DOWN
lcall GATE_DOWN
MOVE_GATE_DOWN:
mov MOT_COM, #00h
;>
;---------------------------------------------------------------------------------------------------------
;>
BRING_HOME_LIFT:
mov MOT_CNT1, #02D
MOT_LOOP9:
mov MOT_CNT2, #200D
MOT_LOOP10:
inc STEP_CNT
mov A, STEP_CNT

-41-


mov STEP_CNT, #00h
NOTCH2:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P3
anl A, #0FH
orl A, R2
mov P3, A
lcall DLY2

MOVE_MOT_DOWN:
dec STEP_CNT
mov A, STEP_CNT
mov STEP_CNT, #03h
NOTCH1:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P3
anl A, #0FH
orl A, R2
mov P3, A
lcall DLY2
jnb LIFTFB, MOVE_MOT_DOWN

mov MOT_CNT1, #02D
MOT_LOOP11:
mov MOT_CNT2, #75D
MOT_LOOP12:
dec STEP_CNT
mov A, STEP_CNT
mov STEP_CNT, #03h
NOTCH0:
mov A, STEP_CNT
movc A, @A+dptr
mov R2, A
mov A, P3
anl A, #0FH
orl A, R2

-42-


mov P3, A
lcall DLY2
orl P3, #0F0H
;>
;---------------------------------------------------------------------------------------------------------
;>
SELECT_RACKS:
mov A, MENU
cjne A, #01H, DONT_SELECT_RACK1
clr RACK_V1
anl RACK_STS, #0FEH ; load_rack 1 as fill
mov RACK_NO, #01H
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
mov DPTR, #RACK_1
lcall MESSAGE
lcall DLY
lcall MESSAGE
mov MOT_COM, #03H ; OPENING GATE WHEN CAR
ARRIVAL
lcall MOT_CNTRL
lcall DLY
lcall DLY
lcall DLY
lcall DLY
mov dptr, #GATE_CLOS
lcall MESSAGE
mov MOT_COM, #04H ; GATE CLOSING WHEN CAR
PARKED
lcall MOT_CNTRL
mov DPTR, #RACK_C1
lcall MESSAGE
mov DPTR, #REMOVE
lcall MESSAGE
lcall DLY
lcall DLY
lcall DLY

-43-


DONT_SELECT_RACK1:
mov A, MENU
clr RACK_V2
anl RACK_STS, #0FDH ; load_rack 1 as fill
mov RACK_NO, #02H
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
mov DPTR, #RACK_2
lcall MESSAGE
mov MOT_COM, #01H ; OPENING RACK
lcall MOT_CNTRL
lcall MESSAGE
mov MOT_COM, #03H ; OPENING GATE
lcall MOT_CNTRL
lcall DLY
lcall DLY
lcall DLY
lcall DLY
lcall MESSAGE
PARKED
lcall MOT_CNTRL
mov DPTR, #RACK_C2
lcall MESSAGE
mov DPTR, #REMOVE
lcall MESSAGE
lcall DLY
lcall DLY
lcall DLY
DONT_SELECT_RACK2:
mov A, MENU
clr RACK_V3
anl RACK_STS, #0FBH ; load_rack 1 as fill
mov RACK_NO, #03H
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
mov DPTR, #RACK_3

-44-


lcall MESSAGE
lcall MOT_CNTRL
lcall MOT_CNTRL
lcall MESSAGE
lcall MOT_CNTRL
lcall DLY
lcall DLY
lcall DLY
lcall DLY
lcall MESSAGE
PARKED
lcall MOT_CNTRL
mov DPTR, #RACK_C3
lcall MESSAGE
mov DPTR, #REMOVE
lcall MESSAGE
lcall DLY
lcall DLY
lcall DLY
DONT_SELECT_RACK3:
mov A, MENU
clr RACK_V4
anl RACK_STS, #0F7H ; load_rack 1 as fill
mov RACK_NO, #04H
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
mov DPTR, #RACK_4
lcall MESSAGE
lcall MOT_CNTRL
lcall MOT_CNTRL
lcall MOT_CNTRL

-45-


lcall MESSAGE
lcall MOT_CNTRL
lcall DLY
lcall DLY
lcall DLY
lcall DLY
lcall MESSAGE
mov MOT_COM, #04H ; GATE CLOSING WHEN CAR PARKED
lcall MOT_CNTRL
mov DPTR, #RACK_C4
lcall MESSAGE
mov DPTR, #REMOVE
lcall MESSAGE
lcall DLY
lcall DLY
lcall DLY
DONT_SELECT_RACK4:
;>
;---------------------------------------------------------------------------------------------------------
;>
DLY:
mov r4, #0Fh
GONE: mov r5, #00h
OUT: mov r6, #00h
IN: djnz r6, IN
djnz r5, OUT
djnz r4, GONE
ret
DLY1:
mov r4, #07h
GONE1: mov r5, #04h
OUT1: mov r6, #00h
IN1: djnz r6, IN1
djnz r5, OUT1
djnz r4, GONE1
ret
DLY2:
mov r4, #03h
GONE2: mov r5, #04h
OUT2: mov r6, #075h
IN2: djnz r6, IN2
djnz r5, OUT2
djnz r4, GONE2
ret

-46-


;>
;---------------------------------------------------------------------------------------------------------
---
;>
KBREAD: ; key board sub
mov P1, #0EFH
nop
mov A, P1
anl A, #0FH
mov KEY_VAL1, A

mov P1, #0DFH
nop
mov A, P1
anl A, #0FH
swap A
orl KEY_VAL1, A

mov P1, #0BFH
nop
mov A, P1
anl A, #0FH
mov KEY_VAL2, A

mov PRV_KEY, KEY_PRS
mov A, KEY_VAL1

cjne A, #0FEH, NOT_KEY1
mov KEY_PRS, #01H
ajmp CHEK_BOUNSE
NOT_KEY1:
cjne A, #0FDH, NOT_KEY2
mov KEY_PRS, #04H
ajmp CHEK_BOUNSE
NOT_KEY2:
cjne A, #0FBH, NOT_KEY3
mov KEY_PRS, #07H
ajmp CHEK_BOUNSE
NOT_KEY3:
cjne A, #0F7H, NOT_KEY4
mov KEY_PRS, #0AH
ajmp CHEK_BOUNSE
NOT_KEY4:
cjne A, #0EFH, NOT_KEY5
mov KEY_PRS, #02H
ajmp CHEK_BOUNSE

-47-


NOT_KEY5:
cjne A, #0DFH, NOT_KEY6
mov KEY_PRS, #05H
ajmp CHEK_BOUNSE
NOT_KEY6:
cjne A, #0BFH, NOT_KEY7
mov KEY_PRS, #08H
ajmp CHEK_BOUNSE
NOT_KEY7:
cjne A, #7FH, NOT_KEY8
mov KEY_PRS, #00H
ajmp CHEK_BOUNSE
NOT_KEY8:
mov A, KEY_VAL2
cjne A, #0EH, NOT_KEY9
mov KEY_PRS, #03H
ajmp CHEK_BOUNSE
NOT_KEY9:
cjne A, #0DH, NOT_KEY0
mov KEY_PRS, #06H
ajmp CHEK_BOUNSE
NOT_KEY0:
cjne A, #0BH, NOT_KEYS
mov KEY_PRS, #09H
ajmp CHEK_BOUNSE
NOT_KEYS:
cjne A, #07H, NOT_KEYH
mov KEY_PRS, #0BH
ajmp CHEK_BOUNSE
NOT_KEYH:
mov KEY_PRS, #0FFH
CHEK_BOUNSE:
mov A, KEY_PRS
cjne A, PRV_KEY, SET_BOUNCE
SET_BOUNCE:
jc SET_BOUNCE1
clr KEY_RLS
ret
SET_BOUNCE1:
setb KEY_RLS
ret
;>
;---------------------------------------------------------------------------------------------------------
---
;>

-48-


MENUS: ; key board sub

lcall KBREAD ; READ KEY
jb KEY_RLS, GOTO_DESELECT ; IF NOT KEYHIT JUMP
ret
GOTO_DESELECT:
mov KEY_VAL, KEY_PRS ; SAVE PRESENT KEY
mov A, KEY_VAL ;
cjne A, #0AH, GOTO_LAST ; COMPARE BOTH KEY VALS
GOTO_LAST:
jc READ_NUM_KEYS
ret
READ_NUM_KEYS:
jb ENTR_FLG, DISPLAY_CODE
ret
DISPLAY_CODE:
mov A, KEY_VAL
cjne A, #01H, GOTO_KEY2 ; IF KEY != 1 THEN JUMP NEXT
mov ASC_VAL, #31H ; KEY = '1'
GOTO_KEY2:
GOTO_KEY3:
GOTO_KEY4:
GOTO_KEY5:
GOTO_KEY6:
GOTO_KEY7:
GOTO_KEY8:
GOTO_KEY9:
GOTO_KEY0:

-49-


GOTO_KEY1:
; cjne A, #0AH, GOTO_KEYA ; IF KEY != 1 THEN JUMP NEXT
; mov ASC_VAL, #'A' ; KEY = '0'
; GOTO_KEYA:
; cjne A, #0BH, GOTO_KEYB ; IF KEY != 1 THEN JUMP NEXT
; mov ASC_VAL, #'B' ; KEY = '0'
; GOTO_KEYB:
; cjne A, #0CH, GOTO_KEYC ; IF KEY != 1 THEN JUMP NEXT
; mov ASC_VAL, #30H ; KEY = '0'
; GOTO_KEYC:
; cjne A, #0DH, GOTO_KEYD ; IF KEY != 1 THEN JUMP NEXT
; GOTO_KEYD:
; cjne A, #0EH, GOTO_KEYE ; IF KEY != 1 THEN JUMP NEXT
; GOTO_KEYE:
; cjne A, #0FH, GOTO_KEYF ; IF KEY != 1 THEN JUMP NEXT
; GOTO_KEYF:
mov A, KEY_VAL
mov @R1, A
mov r7, DSP_PTR
lcall DISP_COM
mov R7, ASC_VAL
lcall DISP_LET
inc R1
inc DSP_PTR
mov A, DSP_PTR
cjne A, #8EH, SKIP_RE_ADR
mov DSP_PTR, #8BH
mov R1, MEM_PTR
SKIP_RE_ADR:
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
OPTIONS:
jnb KEY_RLS, TRY_SEL_2 ; IF NOT KEYHIT JUMP
mov A, KEY_VAL ;
cjne A, #0AH, TRY_SEL_1
ajmp GOTO_STRTM
TRY_SEL_1:
mov A, KEY_VAL ;
cjne A, #0BH, TRY_SEL_2
ajmp GOTO_SENDM

-50-

TRY_SEL_2:

jb KEY_LOCK, GET_RACK_4

mov A, KEY_VAL ;
cjne A, #01H, GET_RACK_1
ljmp GOTO_OPEN_RACK1
GET_RACK_1:
mov A, KEY_VAL ;
GET_RACK_2:
mov A, KEY_VAL ;
GET_RACK_3:
mov A, KEY_VAL ;
GET_RACK_4:
ret

GOTO_STRTM:
clr RACK_V1
clr RACK_V2
clr RACK_V3
clr RACK_V4
mov RACK_STS, #00H
mov FLT_CNT, #00H
mov MENU, #00H
mov PSS_WD_A1, #00H
mov PSS_WD_A2, #00H
mov PSS_WD_A3, #00H
mov PSS_WD_B1, #00H
mov PSS_WD_B2, #00H
mov PSS_WD_B3, #00H
mov PSS_WD_C1, #00H
mov PSS_WD_C2, #00H
mov PSS_WD_C3, #00H
mov PSS_WD_D1, #00H
mov PSS_WD_D2, #00H
mov PSS_WD_D3, #00H
lcall BYTE_FILL
ret
;------------------------------------------

-51-


GOTO_SENDM:
mov A, MENU
xrl A, #00H
jnz COMPARE_CODES
lcall BYTE_FILL
clr OPEN_CLS
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
clr ENTR_FLG
setb OPERATION
setb CLOSE
lcall RACK_OPEN_CLOSE
ret
;. . . . . . . . . . . . . . . . . . . . . . .
COMPARE_CODES:
mov A, MENU
cjne A, #01H, COMPARE_CODE1
mov A, PSS_WD_A3
cjne A, TMP_WD_D3, NOT_MATCHED_A1
mov A, PSS_WD_A2
mov A, PSS_WD_A1
lcall SELECT_RACKS
setb BUZ
mov FLT_CNT, #00H
ljmp COMPARE_CODE1
NOT_MATCHED_A1:
mov DPTR, #INVALID_COD
lcall MESSAGE
lcall DLY
inc FLT_CNT
mov a, FLT_CNT
cjne A, #03H, COMPARE_CODE1A
COMPARE_CODE1A:
jc COMPARE_CODE1
clr BUZ
lcall DLY
setb BUZ

-52-


COMPARE_CODE1:
;. . . . . . . . . . . . . . . . . . . . . . .
mov A, MENU
mov A, PSS_WD_B3
cjne A, TMP_WD_D3, NOT_MATCHED_B1
mov A, PSS_WD_B2
mov A, PSS_WD_B1
lcall SELECT_RACKS
setb BUZ
mov FLT_CNT, #00H
ljmp COMPARE_CODE2
NOT_MATCHED_B1:
lcall MESSAGE
lcall DLY
inc FLT_CNT
mov a, FLT_CNT
COMPARE_CODE2A:
jc COMPARE_CODE2
clr BUZ
lcall DLY
setb BUZ
COMPARE_CODE2:
;. . . . . . . . . . . . . . . . . . . . . . .
mov A, MENU
mov A, PSS_WD_C3
cjne A, TMP_WD_D3, NOT_MATCHED_C1
mov A, PSS_WD_C2
mov A, PSS_WD_C1
lcall SELECT_RACKS
setb BUZ
mov FLT_CNT, #00H
ljmp COMPARE_CODE3
NOT_MATCHED_C1:
lcall MESSAGE
lcall DLY
inc FLT_CNT
mov a, FLT_CNT

-53-


COMPARE_CODE3A:
jc COMPARE_CODE3
clr BUZ
lcall DLY
setb BUZ
COMPARE_CODE3:
;. . . . . . . . . . . . . . . . . . . . . . .
mov A, MENU
mov A, PSS_WD_D3
cjne A, TMP_WD_D3, NOT_MATCHED_D1
mov A, PSS_WD_D2
mov A, PSS_WD_D1
lcall SELECT_RACKS
setb BUZ
mov FLT_CNT, #00H
ljmp COMPARE_CODE4
NOT_MATCHED_D1:
lcall MESSAGE
lcall DLY
inc FLT_CNT
mov a, FLT_CNT
COMPARE_CODE4A:
jc COMPARE_CODE4
clr BUZ
lcall DLY
setb BUZ
COMPARE_CODE4:
clr ENTR_FLG
mov MENU, #00H
RET
;. . . . . . . . . . . . . . . . . . . . . . .

;------------------------------------------
GOTO_OPEN_RACK1:
clr MSG_LOCK
mov A, MENU
cjne A, #00H, SKIP_ENTR_MENU1
mov MENU, #01H
setb ENTR_FLG

-54-


lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
lcall MESSAGE
mov MEM_PTR, #TMP_WD_D1
mov R1, MEM_PTR
SKIP_ENTR_MENU1:
ret
;------------------------------------------
GOTO_OPEN_RACK2:
clr MSG_LOCK
mov A, MENU
mov MENU, #02H
setb ENTR_FLG
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
lcall MESSAGE
mov R1, MEM_PTR
SKIP_ENTR_MENU2:
ret
;------------------------------------------
GOTO_OPEN_RACK3:
clr MSG_LOCK
mov A, MENU
mov MENU, #03H
setb ENTR_FLG
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
lcall MESSAGE
mov R1, MEM_PTR
SKIP_ENTR_MENU3:
ret
;------------------------------------------

-55-


GOTO_OPEN_RACK4:
clr MSG_LOCK
mov A, MENU
mov MENU, #04H
setb ENTR_FLG
lcall MESSAGE
mov DPTR, #CLRSCR
lcall MESSAGE
lcall MESSAGE
mov R1, MEM_PTR
SKIP_ENTR_MENU4:
ret
;>
;---------------------------------------------------------------------------------------------------------
---
;>
READ_CARD:
lcall VERIFY_BYTE_FILL
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
BYTE_FILL:

; Fill every byte in an AT24Cxx with the same value.
; Writes one address at a time (page mode is not used).
; Returns CY set to indicate write timeout.
; Destroys A, B, DPTR, XDATA, ADDR_HI:ADDR_LO.

push dpl
push dph
push acc
push b
mov R1, #PSS_WD_A1
mov dptr, #0000h ; initialize address pointer
BF51:
mov ADDR_LO, dpl ; set up address
mov b, #40h ; retry counter
BF52:
mov a, #PADDR ; programmable address
lcall WRITE_BYTE ; try to write
jnc BF53 ; jump if write OK
djnz b, BF52 ; try again

-56-


setb c ; set timeout error flag
ajmp BF54 ; exit
BF53:
inc R1
inc dptr ; advance address pointer
cjne R1, #PSS_WD_A1 + 14d, BF51 ; jump if not last
clr c ; clear error flag
BF54:
pop b
pop acc
pop dph
pop dpl
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
VERIFY_BYTE_FILL:

; Verify that all bytes in an AT24Cxx match a fill value.
; Reads and verifies one byte at a time (page mode is not used).
; Performs a Random Read function to initialize the internal
; address counter and checks the contents of the first address.
; Then performs multiple Current Address Read functions to step
; through the remaining addressess.
; Returns CY set to indicate read timeout or compare fail.
; Destroys A, B, DPTR.
push dpl
push dph
push acc
push b

mov r0, #PSS_WD_A1
mov dptr, #0000h ; initialize address pointer/counter
mov ADDR_LO, dpl ; set up address
mov b, #20h ; retry counter
VB81:
mov a, #PADDR ; programmable address
lcall READ_RANDOM ; try to read
mov @r0, a ; jump if compare error
inc r0
jnc VB82 ; jump if read OK
djnz b, VB81 ; try again
ljmp VB86 ; set error flag and exit
VB82:
mov a, #PADDR

-57-


lcall READ_CURRENT
mov @r0, a ; jump if compare error
inc r0
inc dptr ; advance address pointer

cjne R0, #PSS_WD_A1 + 14d, VB82 ; jump if not last
ajmp VB87 ; exit
VB86:
setb c ; set error flag
VB87:
pop b
pop acc
pop dph
pop dpl

ret
;>
;---------------------------------------------------------------------------------------------------------
;>
WRITE_BYTE:

; AT24Cxx Byte Write function.
; Called with programmable address in A, byte address in
; register pair ADDR_HI:ADDR_LO, data in register XDATA.
; Does not wait for write cycle to complete.
; Returns CY set to indicate that the bus is not available
; or that the addressed device failed to acknowledge.
; Destroys A.

lcall START
jc WB49 ; abort if bus not available

rl a ; programmable address to bits 3:1
orl a, #FADDR ; add fixed address
clr acc.0 ; specify write operation
lcall SHOUT ; send device address
jc WB48 ; abort if no acknowledge

mov a, ADDR_LO ; send low byte of address
lcall SHOUT ;


mov a, @R1 ; get data
lcall SHOUT ; send data

-58-


WB48:
lcall STOP
WB49:
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
READ_CURRENT:

; AT24Cxx Current Address Read function.
; Called with programmable address in A. Returns data in A.

lcall START
jc RC45 ; abort if bus not available

setb acc.0 ; specify read operation
jc RC44 ; abort if no acknowledge

lcall SHIN ; receive data byte
lcall NAK ; do not acknowledge byte
RC44:
lcall STOP
RC45:
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
READ_RANDOM:

; AT24Cxx Random Read function.
; Called with programmable address in A, byte address in
; register pair ADDR_HI:ADDR_LO. Returns data in A.

push b
mov b, a ; save copy of programmable address

; Send dummy write command to set internal address.

-59-


lcall START
jc RR47 ; abort if bus not available

clr acc.0 ; specify write operation
jc RR46 ; abort if no acknowledge

mov a, ADDR_LO ; send low byte of address
lcall SHOUT ;
jc RR46 ; abort if no acknowledge

; Call Current Address Read function.

mov a, b ; get programmable address
lcall READ_CURRENT
ajmp RR47 ; exit
RR46:
lcall STOP
RR47:
pop b

ret
;>
;---------------------------------------------------------------------------------------------------------
;>
START:

; Send START, defined as high-to-low SDA with SCL high.
; Return with SCL, SDA low.
; Returns CY set if bus is not available.

setb SDA
setb SCL

; Verify bus available.

jnb SDA, S40 ; jump if not high
jnb SCL, S40 ; jump if not high

nop ; enforce setup delay and cycle delay
nop
clr SDA
nop ; enforce hold delay

-60-


nop ;
nop ;
nop ;
nop ;
nop ;
clr SCL

ajmp S41
S40:
setb c ; set error flag
S41:
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
STOP:

; Send STOP, defined as low-to-high SDA with SCL high.
; SCL expected low on entry. Return with SCL, SDA high.

clr SDA
nop ; enforce SCL low and data setup
nop
nop
setb SCL
nop ; enforce setup delay
nop ;
nop ;
nop ;
nop ;
nop ;
setb SDA
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
SHIN:

; Shift in a byte from the AT24Cxx, most significant bit first.
; SCL expected low on entry. Return with SCL low.
; Returns received data byte in A.
setb SDA ; make SDA an input
push b
mov b, #08H ; bit count

-61-


SH43:
nop ;
nop ;
nop ;
nop ;

setb SCL ; raise clock
nop ; enforce SCL high
nop ;
nop ;
nop ;
mov c, SDA ; input bit
rlc a ; move bit into byte
clr SCL ; drop clock
djnz b, SH43 ; next bit

pop b

ret
;>
;---------------------------------------------------------------------------------------------------------
;>
SHOUT:

; Shift out a byte to the AT24Cxx, most significant bit first.
; SCL, SDA expected low on entry. Return with SCL low.
; Called with data to send in A.
; Returns CY set to indicate failure by slave to acknowledge.
; Destroys A.

push b
mov b, #08H ; bit counter
SO42:
rlc a ; move bit into CY
mov SDA, c ; output bit
nop ;
nop ;
nop ;
nop ;
nop ;

-62-


djnz b, SO42 ; next bit

setb SDA ; release SDA for ACK
nop ; enforce SCL low and tAA
nop ;
setb SCL ; raise ACK clock
nop ;
nop ;
nop ;
mov c, SDA ; get ACK bit
clr SCL ; drop ACK clock

pop b
ret
;>
;---------------------------------------------------------------------------------------------------------
;>
NAK:

; Clock out a negative acknowledge bit (high).
; SCL expected low on entry. Return with SCL low, SDA high.

setb SDA ; NAK bit
nop ;
nop ;
nop ;
nop ;
nop ;
nop ;
nop ;
nop ;

ret
;>
;---------------------------------------------------------------------------------------------------------
;>
;> ROM TABLE AREA
;>

-63-


INITIALISE:
db COM, 30h, 30h, 30h, 30h, 3ch, 06h, 0ch, 01h, EOL
NAME:
db COM, 80h, DAT, 'COMPACT PARKING', COM, 0C0H, DAT,'
SYSTEM ', EOL
WELCOME:
db COM, 80h, DAT, '**** WELCOME ***', EOL
COLLEGE:
db COM, 80h, DAT, ' S.S.C.E.T. ', COM, 0C0H, DAT,'
LANKAPALLI ', EOL
PRES:
db COM, 80h, DAT, 'SUBMITTED BY.. ', COM, 0C0H, DAT,'
', EOL
NAME1:
db COM, 80h, DAT, 'V.SAI ANUSHA ', COM, 0C0H,
DAT,'G.L.KUMARI ', EOL
NAME2:
db COM, 80h, DAT, 'Y.NIHARIKA ', COM, 0C0H,
DAT,'Y.SRILEKHA ', EOL
HOD:
db COM, 80h, DAT, 'OUR GUIDE&HOD.. ', COM, 0C0H,
DAT,'YRK.PARAMA HAMSA', EOL
ASK_COD:
db COM, 80h, DAT, 'ENTER CODE: ', EOL
INVALID_COD:
db COM, 80h, DAT, 'INVALID CODE.. ', EOL
NOT_LOD:
db COM, 080h, DAT, 'INVALID CODE.. ', EOL
RACK_1:
db COM, 080h, DAT, 'OPENING RACK 1..', EOL
RACK_2:
RACK_3:
RACK_4:
RACK_C1:
db COM, 080h, DAT, 'CLOSING RACK 1..', EOL
RACK_C2:
RACK_C3:
RACK_C4:
TRACK:
db COM, 080h, DAT, 'PUT CAR ON TRACK', EOL

-64-


GATE_OPEN:
db COM, 080h, DAT, 'GATE OPENING ', EOL
GATE_CLOS:
db COM, 080h, DAT, 'GATE CLOSING... ', EOL
MOV_HOME:
db COM, 080h, DAT, 'MOVING TO HOME..', EOL
NOT_EMPT:
db COM, 080h, DAT, 'RACKS FILLED ', EOL
REMOVE:
db COM, 080h, DAT, 'VACANT THE TRACK', EOL
BLANK2:
db COM, 0C0h, DAT, ' ', EOL
CLRSCR:
db COM, 01h, EOL
;>
;---------------------------------------------------------------------------------------------------------
;>
ORG 0D00H

STEP_LIFT:
db 09CH
db 05CH
db 06CH
db 0ACH

STEP_GATE:
db 19H
db 15H
db 16H
db 1AH

END

-65-


CHAPTER 7
FABRICATION MODEL

A) HARDWARE CIRCUITRY

B) RACK MECHANISM C) OVERALL VIEW
FIG.7.FABRICATION MODEL

-66-


CHAPTER 8
REAL TIME APPLICATION

This system is extensively in use in Japan and Singapore and it can be referred to as
Puzzle Parking and requires minimum space.. This system involves the arrangement
of the racks both horizontally and vertically. A car will be placed on a slot and is
controlled by a computer that keeps the track of all vacant slots. In real time application
Hydraulic lifts are used to lift the cars and the computer guides the lifts to place them in
the vacant slot.

The Municipal Corporation of Delhi (MCD) has decided to construct multi-level
parking lots in Paharganj and Karol Bagh that will have minimum human involvement.
It has got Rs 4.8 crore for the Paharganj parking that can hold 500 cars and Rs 5 crore
for the one at Karol Bagh that can accommodate 300 cars.

In real time application the specifications can be considered as follows:

Mode of drive Motor drive
Size of car
(LWH)
5000mm1850mm1550mm
Weight of car 2000Kg
Lifting motor
power
15KW
Lifting speed 70m/min
Sliding speed 8m/min
Electricity AC380V,50Hz,3phases 5 wires system
Electricity power 20kw
Safeguard devices Ejection-type anti-fall device
Warning devices Yes
Frame
composition
Columns and beams are made of H type steel, Channel steel, angle steel
and square pipes

-67-


CHAPTER 9
ADVANTAGES OF THE SYSTEM
Uses the most modern and latest technology, ensuring long life. The life span and
functioning of all the mechanical parts can be guaranteed for over 20 years, if
maintained properly by the user.
Reduced ground space requirement as compared to conventional parking systems.
Low parking and retrieval times 90 seconds to 150 seconds per car depending on
the configuration.
Reduced noise levels in such systems, when compared to conventional parking lots
as car engines are not running while being parked in and out.
Minimal maintenance required.
Safe operation; safety devices conforming to the EU standards used.
Environment friendly, as car engines are not running while being parked in and out.
Reduced chances of fire hazard and no risk to human lives.
No danger of assaults, car break-ins and damages to personal belongings as there is
no human presence inside the parking tower.
The whole structure can be customized as per customers requirements and
limitations. Each level inside the parking system can be varied as per the dimensions of
various cars, as SUVs would need a much larger clear height than a normal sedan.
These systems can be built for maximizing space and volume utilization.

-68-


CHAPTER 10
CONCLUSION AND FUTURE SCOPE

In the conventional parking, each car is parked in separate space, which occupies large
space. In this system, in one cars space, we can park more no of cars depends on lift
capacity.
In this project we introduced security with just password, which can be tampered by a
technical person. But this is cheaper method. By introducing biometric security systems
like, finger print sensor, skull sensor, eye sensor etc, no one can tamper the system,
which gives full security to our car parked. But the cost of the system will be high.
By adding more no of vertical racks side-by-side, which are attached to walls, we can
save cellar space and can be used for other purposes and also parking and taking a car is
very easy. By implementing these systems, bigger complexes need not to leave their
costly lands for parking. Though the cost of our system is high, compared to land costs
at prime centers, our system cost will be cheaper.

-69-


ANNEXURE-A
AT89C51 DATASHEET
ABSOLUTE MAXIMUM RATINGS:

DC CHARACTERISTICS:
The values shown in this table are valid for TA = -40C to 85C and VCC = 4.0V to
5.5V, unless otherwise noted.

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not
guaranteed to sink current greater than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

-70-


AC CHARACTERISTICS
Under operating conditions, load capacitance for Port 0, ALE/PROG, and
PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS:

-71-


ANNEXURE-B
IRF540 DATASHEET
Absolute Maximum Ratings TC = 25
o
C, Unless Otherwise Specified

NOTE: 1. TJ = 25
o
C to TJ = 150
o
C.
ELECTRICAL SPECIFICATIONS: TC = 25
o
C, Unless Otherwise Specified

-72-


ANNEXURE-C
BC547 DATASHEET
ABSOLUTE MAXIMUM RATINGS: Ta=25C unless otherwise noted.

ELECTRICAL CHARACTERISTICS: Ta=25C unless otherwise noted.

-73-


ANNEXURE-D
LM358 DATASHEET
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE
RANGE:

Notes: 1. All voltage values, except differential voltages and VCC specified for measurement of IOS, are
with respect to the network ground terminal.
2. Differential voltages are at IN+ with respect to IN.
3. Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
4. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power
dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/JA. Operating at the absolute
maximum TJ of 150C can affect reliability.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
6. Maximum power dissipation is a function of TJ(max), JC, and TC. The maximum allowable power
dissipation at any allowable case temperature is PD = (TJ(max) TC)/JC. Operating at the absolute
maximum TJ of 150C can affect reliability.
7. The package thermal impedance is calculated in accordance with MIL-STD-883.

-74-


ELECTRICAL CHARACTERISTICS AT SPECIFIED FREE-AIR TEMPERATURE,
VCC = 5 V:

-75-


ANNEXURE-E
TCST1000 DATASHEET
ABSOLUTE MAXIMUM RATINGS:
INPUT (EMITTER):

OUTPUT (DETECTOR):

COUPLER:

ELECTRICAL CHARACTERISTICS (T
amb
=25
o
C):
INPUT (EMITTER):

OUTPUT (DETECTOR):

COUPLER:

-76-


ANNEXURE-F
THERMAL AND ELECTRICAL CHARACTERISTICS OF IN4007

-77-


ANNEXURE-G
ELECTRICAL CHARACTERISTICS OF LM358

-78-


ANNEXURE-H
ELECTRICAL CHARACTERISTICS OF 7805

-79-


ANNEXURE-I
DATA SHEET OF SERIAL EEPROM AT24C04

-80-


BIBILOGRAPHY

1) www.atmel.com
2) www.wikipedia.com
3) www.datasheetcatalog.com

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COMPACT CAR PARKING SYSTEM

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