A HIGH GAIN AMPLIFIER USING A CASCADING ARCHITECTURE

A. E. Hashim, R. L.Geiger

Iowa State University
348 Durham Center
Ames, Iowa 50011, USA

ABSTRACT

High gain amplifiers with fast settling times are needed
for high-speed data converter applications. Cascading
amplifiers is generally a good way to achieve the desired
open loop gain however; stability and settling speed
become a concern. A cascading architecture that is
inherently stable and maintains good settling performance
was previously discussed. In this paper, a transistor level
three stage implementation is presented that achieves over
100dB of gain while maintaining good settling
performance.

1. INTRODUCTION

Data converter circuits require fast settling and high gain
amplifiers. The high gain is needed for the output of the
amplifier to settle accurately to the desired final value.
Cascode amplifiers are widely used because they satisfy
both requirements. The problem with using the cascode
amplifiers is the limitation that occurs due to the need of a
high supply voltage to provide an acceptable output signal
swing. This becomes a problem especially with the
technology pushing towards smaller device sizes and
lower supply voltages. An alternative that does not require
large supplies is to cascade amplifiers to achieve the
desired gain. Various cascade feed forward schemes
already exist [1][3][4][5]. However, they introduce pole-
zero pairs that exhibit imperfect cancellation. This causes
the appearance of slow settling components in the
transient response. Unless the magnitude of the effects
are sufficiently small, long settling time constants can not
be tolerated in many applications.

A method for cascading amplifier stages to achieve the
desired gain and at the same time maintain comparable
settling time to that of a basic amplifier was previously
presented. In this paper a transistor level implementation
of the cascaded architecture is discussed. It is shown that
a stable high gain amplifier (100+ dB) can be obtained
from cascading simple amplifier stages and the
compensation is inherent in the system.

2. ARCHITECTURE BACKGROUND


+
-
OUT
+
-
OUT
A1(S)
A2(S)
+
-
An(S)
Out
+
-
OUT
(n-3)stages

Figure 1, Cascaded amplifier architecture

A previous paper [6] introduced a new cascading structure
that is inherently stable. The architecture is composed of
(n-1) identical amplifiers cascaded together and the output
is again cascaded into an amplifier that has a gain-
bandwidth product modestly higher than the rest of the
amplifiers to keep the overall structure stable in the
presence of negative feedback. The amplifiers are
cascaded in the manner shown in figure 1.

A2(S)
A1(S)
+
-
OUT Vo
R1
A3(S)
+
-
OUT
+
-
OUT
R2
A(S)
Vi

Figure 2, Three stage cascaded amplifier in inverting
configuration

Considering a three stage cascade in closed loop as shown
in figure 2 and writing the closed loop transfer function,
we get the following equation:

( )( )
3
3 2 1
1
2 2
2 1 1
2
2 1 1 1 2
1 1
1
s
R
R
s s
s s R R
V
V
in
o

+ + + +
+ +
=
... (1)
where,
i
i
GB
1
= ..... (2)
When in closed loop, the two zeros will cancel two of the
poles leaving only one dominant pole in the system and
no extra compensation is required. However the condition
for stability for the closed loop transfer function is
3
7 . 2 > where
2 1
= = (since the first two
stages are identical.) Figure 3 below shows the root locus
of the structures transfer function.


Figure 3, Closed loop pole/zero plot

The open and closed loop zeroes are located at half the
gain-bandwidth of the first and second stage amplifiers.
The dominant pole location is a variable that can be
changed by increasing or decreasing the third stage pole
location. As will be shown, the location of the dominant
pole relative to the zeroes is a very critical design
parameter for the structure.

High DC gains can be achieved by this structure but there
is a cap on the maximum closed loop gain. Since the
zeros stay constant whether in open loop or closed loop, if
the thirst stage pole happens to be at a much lower
frequency than the frequency of the zeroes, the possible
stable closed loop gain will drop to a very low value if not
less than 0dB making the amplifier useless in closed loop.
So it is important to carefully design the pole frequency of
the third stage.

It is also worthwhile to mention that this amplifier is not
open loop stable but this is not a concert because it is
closed loop stable and phase margins of 90 deg are
achievable.

3. CASCADE AMPLIFIER DESIGN

The architecture used makes it easy to design the
transistor level implementation since no special features
are required in the individual amplifiers. The only
architectural requirement is that the last stage must have a
higher gain-bandwidth product that the previous identical
stages. How much higher, depends on how much closed
loop gain is required from the overall amplifier and how
fast is the amplifier required to settle.
If the gain-bandwidth of the third stage (GB
3
) is much
higher than the gain-bandwidth of the first two stages
(GB
1,2
), we will maximize the possible closed loop gain
but at the same time we will be jeopardizing the settling
performance of the amplifier. This is because the closed
loop dominant pole will no longer be close to the zeroes
and any mismatch in the pole-zero cancellation shown in
figure 3 will add a considerable slow settling component
to the step function. See figure 4 below.


Figure 4, Open loop gain plot (a) & pole-zero plot (b)
for GB
3
>> GB
1,2


On the other hand, if the gain-bandwidth of the third stage
(GB
3
) is close to the gain-bandwidth of the first two
stages (GB
1,2
), the step response will have a large
overshoot and to get the amplifier to settle fast, we will
need to design all three stages to have high gain-
bandwidths and this will require a considerable amount of
power. See figure 5 below.

The solution in to find the medium point where we can
balance the settling time, DC gain, overall bandwidth of
the amplifier, possible closed loop gain and power
dissipation. To do so, a spreadsheet was generated to look
at how these variables are affected with varying all the
input parameters. The design presented in this paper was
optimized for all the above mentioned parameters, in
particular to achieve 135dB of gain and 100MHz unity
gain frequency. We could have just as well optimized the
design for only one, two or three of the parameters. For
example if a faster settling response is desired, it could be
done but it will cost more power.
dB
Log f
3
rd
stage pole
zeroes
40 dB/dec
20 dB/dec
(a)
(b)
real
J
2
1
2
3
+j
2
3

2 poles
1
st
& 2
nd

stage poles

Figure5, Open loop gain plot (a) & pole-zero plot (b)
for GB
3
> GB
1,2


The circuit was designed in a 0.5 process. A simple five
transistor Transconductance Amplifier was used for each
stage of the amplifier. Figure 6 shows the over all
schematic and figure 7, shows the schematic for each of
the first and second stages.

A small load capacitor was added to each of the first two
stages to control their pole location. The transistors of the
first two stages are not as big as those of the third stage
because the first two stages have a lower gain-bandwidth
and they drive much smaller capacitors than the third
stage (which was designed to drive 20pF.) This
combination of lower bandwidth and lower load
capacitance allows for a minute amount of power to be
dissipated in these stages relative to the third stage.


Figure 6, Implemented circuit
A simple five transistor implementation was used for the
third stage so as not to add an extra pole in the system
which would need to be compensated.

The first two stages were designed to have a tail current of
20A verses 8mA needed for the third stage. In other
words the power dissipated in the first two stages
combined is 200W while the power dissipated in the
third stage is 40mW (V
DD
= 5V.)


Figure 7, 1
st
and 2
nd
stage OTA schematic

In the next section we will discuss the results obtained
from simulating the amplifier design.

4. SIMULATION RESULTS

All simulations were run using HSpice level 49 models.
The amplifier was simulated in the inverting unity gain
configuration.


Figure 8, Open loop characteristic

A DC gain of 131 dB was achieved with a unity gain
frequency of 102 MHz. Figure 8 above shows the open
V+ V-
out
V+
V-
out
dB
Log f
1
st
& 2
nd

stage poles
3
rd
stage
pole
40 dB/dec
20 dB/dec
(a)
(b)
real
J
zeroes
60 dB/dec
Stage 1
Stage 2
loop bode plot of the amplifier while figure 9 below
shows the step response (1V step.)


Figure 9, Inverting unity gain step response

Table 1 below summarizes the results obtained from
simulating the amplifier while table 2 shows the settling
performance of the amplifier.

Table 1, Table of amplifier characteristics
Process 0.5
VDD (V) 5
Cload (pF) 20
DC Gain (dB) 131
Unity gain freq. (MHz) 102
Power Dissipation (mW) 40.2
Output Signal Swing (V) 0.22 - 4.76
Slew rate (V/s) 400

Table 2, Amplifier settling performance
% settled Time to settle (ns)
10 6
1 87
0.1 141

It is important to point out that the amplifier settling
performance could be improved if the power budget is
increased.

5. CONCLUSIONS

In this paper a cascaded amplifier circuit that achieves
over 120dB of gain and a unity gain bandwidth in excess
of 100MHz was presented. The design was optimized for
one set of conditions but it can easily be modified to
enhance any desired characteristic. The circuit was
comprised of basic amplifiers that are not necessarily high
gain but an overall high gain is achieved by cascading
these amplifiers. No complicated compensation schemes
were required for stabilizing the circuit.
6. REFERENCES

[1] Apfel, R. and Gray, P., A fast-settling
monolithic operational amplifier using doublet
compression techniques, IEEE J. Solid-State
Circuits, vol. Sc-9, No. 6, pp332-340, Dec. 1974

[2] Geiger, R., "Zero Sensitivity Active Filters
Employing Finite Gain Voltage Amplifiers,"
ISCAS, pp. 1064-1068, New York, NY, May
1978

[3] You, F., Embabi, S. and Snchez-Sinencio E.,
Multistage Amplifier Topologies with Nested
Gm-C Compensation, IEEE J. Solid-State
Circuits, Vol. 32, pp. 2000-2011, Dec 1997

[4] Ng, J., Ziazadeh, R. and Allstot D., A
Multistage Amplifier Technique with Embedded
Frequency Compensation, IEEE J. Solid-State
Circuits, Vol. 34, pp. 339-347, Mar 1999

[5] Schlarmann, M. and Geiger, R., A New
Multipath Amplifier Design Technique for
Enhancing Gain without Sacrificing Bandwidth,
ISCAS, Vol. 2, pp. 610-615, Orlando, Fl, May
1999

[6] Hashim A. and Geiger R., An Amplifier
Structure for High-Gain and Fast Settling
Applications, ISCAS, Vol. 2, pp. 823-826,
Phoenix, Az, May 2002