Step by Step Design Tutorial of a

fixed-frequency adapter < 75 W

with very low power consumption
Presented by: Petr Papica
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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2
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
The flyback, a popular structure
The flyback converter is widely used in consumer products
Ease of design, low-cost, well-known struture
Poor EMI signature, bulky transformer, practical up to 150 W
flyback 10 35 W
DVD player
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3
flyback 40 180 W
notebook
flyback 3 5 W
charger
EPA 2.0 (External Power Supplies)
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4
(was > 0.84 in previous version 1.1)
(< 0.5 W in 1.1)
(< 0.75 W in 1.1)
EPS 5.0 (ENERGY STAR

Program Requirements
for Computers)
Defines E
TEC
for different types of products as a Typical Energy Consumption
For the desktop and notebook product categories TEC will be determined by the following formula:
E
TEC
= (8760/1000) * (P
off
* T
off
+ P
sleep
* T
sleep
+ P
idle
* T
idle
)
where all Px are power values in watts, all Tx are Time values in % of year, and the TEC E
TEC
is in units
of kWh and represents annual energy consumption based on mode weightings
The light load efficiency and no load consumption is more important
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5
Desktops and Integrated Computers (kWh) Notebook Computers (kWh)
TEC (kWh)
Category A: 148.0
Category B: 175.0
Category C: 209.0
Category D: 234.0
Category A: 40.0
Category B: 53.0
Category C: 88.5
E
TEC
requirement desktops and notebooks
Effective from July 1, 2009 (except: game consoles from July 1, 2010)
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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6
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
1
2
4
drv
7
5
drv
8
9 12
11
drv
Vout
Vout
Vout
gnd
gnd
a
b
c
Vin
D
C
SW1
L
1 N
Vin
D
C
SW1
L
Vin
SW1
D
C
An isolated buck-boost
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7
buck-boost
ground referenced
buck-boost
input referenced
flyback
isolated ground referenced
The flyback converter is an isolated version of the buck-boost cell
By rotating the switch, we obtain a ground-referenced isolated converter
Keep this in mind for the small-signal analysis!
Vin
Vout
L
C
R
IL
IL
SW
VL
V(SW / D) = Vin
IL
Vin
Vout
L
C
R
IL
IL
VL
V(SW / D) = Vout
IL
Vout
D
On-time and freewheel
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in
peak valley on
V
I I t
L
= +
out
valley peak off
V
I I t
L
=
SWis closed, D is blocked
SWis open, D is closed
IL
IL
Circulates in the
same direction
When the switch closes, current ramps-up in L
At the switch opening, the stored energy is dumped into C
Vin
D1
1:N
Cout Rload
Vout
.
.
drv
The flyback circuit
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9
Similar buck-boost equations hold when scaled by the turn ratio N
The switch is now ground referenced for an easier drive
We have galvanic isolation between the primary and the secondary
drv
Vin
C
R
-Vin.N
.
.
Vout
ILp
VLp
Lp
(Np)
Ls
(Ns)
0
IC
IR
Vout
ILs = 0
VLs
D
in
on
p
V
S
L
=
in
peak valley on
p
V
I I t
L
= +
CCM
in
peak on
V
I t
L
=
DCM
The turn-on event
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SW
ILp
N = Ns / Np
S
The controller instructs the power switch to turn on
The current increases in the inductor in relationship to V
in
and L
p
The output capacitor supplies the load on its own
p
L
in out
PIV V N V = +
Reverse voltage on the diode
Simplified, no leakage
Vin
C
R
.
.
VLp=Vout/N
Lp
(Np)
Ls
(Ns)
Vin+VLp
IC IR
Vout
ILs = ILp / N
VLs
D
V
Lp
(t)
V
in
V
out
/N
Applying volt-second balance, CCM
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11
Vin+VLp
N = Ns / Np
ILp=0
S
,
out
DS off in in r
V
V V V V
N
= + = +
Simplified, no leakage
Reflected
voltage
( ) ( )
1 1
out on sw
in off sw
V Nt NDT ND
V t D T D
= = =

t
on
= DT
sw
t
off
= (1-D)T
sw
dc transfer function in CCM
V
Lp
(t)
V
out
/N
V
in
DT
Vin
C
R
.
.
VLp=0
Lp
(Np)
Ls
(Ns)
Vin
IC
IR
Vout
ILs = 0
VLs
Applying volt-second balance, DCM
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12
t
on
= DT
sw
t
off
= (1-D)T
sw
2
out load
in p sw
V R
D
V L F
=
dc transfer function in DCM
N no longer plays a role
R
load
, L
p
and F
sw
do
Vin
N = Ns / Np
, DS off in
V V =
2 4
X1
PSW1
RON = 10m
3
Cout
470u
IC = 10
Rload
2
5
Vin
100
Vout
6 1
X2
XFMR
RATIO = -0.1
Ls
Vds
IIn
.
.
Lp
2.2m
D1
D
Flyback, typical waveforms
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RON = 10m
ROFF = 1Meg
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
V2
S
A simple flyback circuit without parasitic elements
It runs open-loop for the sake of simplicity
Vout = 8 V
0
400m
800m
1.20
1.60
i
i
n

i
n

a
m
p
e
r
e
s
p
l
o
t
1
1
750m
850m
950m
1.05
1.15
i
(
l
p
)

i
n

a
m
p
e
r
e
s
p
l
o
t
2
2
130
190
250

i
n

v
o
l
t
s
p
l
o
t
3
3
I
in
(t)
I
Lp
(t) L
I
I
peak
V
in
out
V N
out in
V N V +
Diode blocks
0
400m
800m
1.20
1.60
i
i
n

i
n

a
m
p
e
r
e
s
p
l
o
t
1
1
750m
850m
950m
1.05
1.15
i
(
l
p
)

i
n

a
m
p
e
r
e
s
p
l
o
t
2
2
130
190
250

i
n

v
o
l
t
s
p
l
o
t
3
3
I
in
(t)
I
Lp
(t) L
I
I
peak
V
in
out
V N
out in
V N V +
Diode blocks
Input current
I
valley
E
valley
E
peak
Flyback, typical waveforms, CCM
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14
10.0
70.0
130
v
d
s

i
n

v
o
l
t
s
p
l
o
t
3
8.81
8.83
8.85
8.87
8.89
v
o
u
t

i
n

v
o
l
t
s
p
l
o
t
4
4
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
0
4.00
8.00
12.0
16.0
i
d
(
d
1
)

i
n

a
m
p
e
r
e
s
p
l
o
t
5
5
V
DS
(t)
V
out
(t)
V
in
Output cap.
refueling
Output capacitor
supplies the load
I
d
(t)
I
peak
/ N
10.0
70.0
130
v
d
s

i
n

v
o
l
t
s
p
l
o
t
3
8.81
8.83
8.85
8.87
8.89
v
o
u
t

i
n

v
o
l
t
s
p
l
o
t
4
4
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
0
4.00
8.00
12.0
16.0
i
d
(
d
1
)

i
n

a
m
p
e
r
e
s
p
l
o
t
5
5
V
DS
(t)
V
out
(t)
V
in
Output cap.
refueling
Output capacitor
supplies the load
I
d
(t)
I
peak
/ N
0
100m
200m
300m
400m
i
i
n

i
n

a
m
p
e
r
e
s
P
l
o
t
1
1
0
100m
200m
300m
400m
i
(
l
p
)

i
n

a
m
p
e
r
e
s
P
l
o
t
2
2
200
300
400

i
n

v
o
l
t
s
P
l
o
t
3
I
in
(t)
I
Lp
(t)
V
DS
(t)
L
I
I
peak
V
out
V N out in
V N V +
DCM (core reset)
Diode blocks
0
100m
200m
300m
400m
i
i
n

i
n

a
m
p
e
r
e
s
P
l
o
t
1
1
0
100m
200m
300m
400m
i
(
l
p
)

i
n

a
m
p
e
r
e
s
P
l
o
t
2
2
200
300
400

i
n

v
o
l
t
s
P
l
o
t
3
I
in
(t)
I
Lp
(t)
V
DS
(t)
L
I
I
peak
V
out
V N out in
V N V +
DCM (core reset)
Diode blocks
Input current
E
valley
= 0
E
peak
Flyback, typical waveforms, DCM
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15
0
100
200
v
d
s

i
n

v
o
l
t
s
P
l
o
t
3
3
12.632
12.636
12.640
12.644
12.648
v
o
u
t

i
n

v
o
l
t
s
P
l
o
t
4
4
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
-1.00
0
1.00
2.00
3.00
i
d
(
d
1
)

i
n

a
m
p
e
r
e
s
P
l
o
t
5
5
V
out
(t)
V
in
out
Output cap.
refueling
Output capacitor
supplies the load
I
d
(t)
I
peak
/ N
0
100
200
v
d
s

i
n

v
o
l
t
s
P
l
o
t
3
3
12.632
12.636
12.640
12.644
12.648
v
o
u
t

i
n

v
o
l
t
s
P
l
o
t
4
4
3.002m 3.006m 3.010m 3.014m 3.018m
time in seconds
-1.00
0
1.00
2.00
3.00
i
d
(
d
1
)

i
n

a
m
p
e
r
e
s
P
l
o
t
5
5
V
out
(t)
V
in
out
Output cap.
refueling
Output capacitor
supplies the load
I
d
(t)
I
peak
/ N
V
DS
is back
to V
in
when
all SW are
blocked.
2
,
1
2
p
L valley p valley
E L I =
2
,
1
2
p
L peak p peak
E L I =
Initially stored energy
Stored energy at t
on
( )
2 2 2 2
,
1 1 1
2 2 2
p
L accu p peak p valley p peak valley
E L I L I L I I = =
Accumulated energy at T
sw
Energy transfer in CCM and DCM
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16
Power (watts) is energy (joules) averaged over time (a switching cycle, seconds)
( )
2 2
1
2
out peak valley p sw
P I I L F =
2
1
2
out peak p sw
P I L F =
CCM
DCM, I
valley
= 0
Eta, the efficiency
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
www.onsemi.com
17
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
The leakage inductance
The coupling in a transformer is not perfect
Some induction lines couple in the air: leakage flux
Closed path
in the air
Leakage flux
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in the air
Closed path
in the air
Leakage flux
Leakage flux
An equivalent transformer model
For a two-winding transformer, the model is simple:
Two leakage inductors
One magnetizing inductor
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19
L
leak1
L
leak2
L
p
1:N
primary secondary
Vin
SW
.
ILp
VLp
Lp
(Np)
0
Lleak
ILp
ILp
D
Vin
(Vout+Vf) / N
Lleak
Ipeak
Lleak
Lp
Ipeak
VLp
D
The leakage role
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20
SW
ILp
Clump
ILp
S
Clump
VDS
S
The switch closes:
Current flows in L
leak
and L
p
The switch opens:
The current charges the lump capacitor
1
3
Lprim
3m
Icoil
5
Cout1
2.2mF
9
Resr1
60m
8
Lleak
15u
7
10
X4
XFMR-AUX
RATIO_POW = -0.05
RATIO_AUX = -0.06
Vdrain
12
Rprim
0.5
11
Id
D5
1N5822
dem
IReso
R6
4.7k
C6
600p
X3
Rload
9
Vin
350 V
Vout
16 V
0
200
400
600
800
v
d
r
a
in
,

v
(
9
)

in

v
o
lt
sV
DS
(t)
V
in
V
DS,max
750 V
Valley switching
1
3
Lprim
3m
Icoil
5
Cout1
2.2mF
9
Resr1
60m
8
Lleak
15u
7
10
X4
XFMR-AUX
RATIO_POW = -0.05
RATIO_AUX = -0.06
Vdrain
12
Rprim
0.5
11
Id
D5
1N5822
dem
IReso
R6
4.7k
C6
600p
X3
Rload
9
Vin
350 V
Vout
16 V
0
200
400
600
800
v
d
r
a
in
,

v
(
9
)

in

v
o
lt
sV
DS
(t)
V
in
V
DS,max
750 V
Valley switching
Drain-source excursion
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21
4
Rsense
0.5
Creso
1.5n
IReso
6
X3
MTP4N85m
7.940m 7.944m 7.949m 7.953m 7.957m
time in seconds
-800m
-400m
0
400m
800m
I
Lp
(t)
I
Lleak
(t)
I
peak
= 695 mA
drv
4
Rsense
0.5
Creso
1.5n
IReso
6
X3
MTP4N85m
7.940m 7.944m 7.949m 7.953m 7.957m
time in seconds
-800m
-400m
0
400m
800m
I
Lp
(t)
I
Lleak
(t)
I
peak
= 695 mA
drv
Reflected V
out
( )
out f
leak
DS,max in peak
lump
V V
L
V V I
N C
+
= + +
Characteristic
impedance
Need to limit the excursion!
8 4
3
7
Cout
470u
IC = 10
Rload
1k
9
Vin
100
V2
Vout
2
6
1
X2
XFMR
RATIO = -0.1
Ls
Vds
5
IIn
.
.
Lp
{Lp}
Lleak
{Leak}
parameters
Lp=2.2m
k=0.02
C2
100p
D1
1n5819
Resr
150m
Rs
250m
Dbody
VLp
VLeak
ILp
ILeak
ID1
10
D3
MUR160
Vclamp
150
V
clamp
D
clp
C
clp
R
clp
L
p
The need of a clamp
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22
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
V2
k=0.02
Leak=Lp*k
100p
The clamp is made by a low impedance voltage source
When the drain reaches V
in
+ V
clamp
, the clamp diode conducts
-60.0m
20.0m
100m
180m
260m
i
l
p

i
n

a
m
p
e
r
e
s
p
l
o
t
1
2
-60.0m
20.0m
100m
180m
260m
i
l
l
e
a
k

i
n

a
m
p
e
r
e
s
P
l
o
t
3
3
I
Lp
(t)
I
leak
(t)
I
peak
= 236 mA I
peak
= 210 mA
0
t
rr
t = 480 ns
-60.0m
20.0m
100m
180m
260m
i
l
p

i
n

a
m
p
e
r
e
s
p
l
o
t
1
2
-60.0m
20.0m
100m
180m
260m
i
l
l
e
a
k

i
n

a
m
p
e
r
e
s
P
l
o
t
3
3
I
Lp
(t)
I
leak
(t)
I
peak
= 236 mA I
peak
= 210 mA
0
t
rr
t = 480 ns
Leakage inductor
reset sequence
A reduced secondary-side current
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23
100m
700m
1.30
1.90
2.50
i
d
1

i
n

a
m
p
e
r
e
s
p
l
o
t
2
4
3.011m 3.015m 3.019m 3.023m 3.027m
time in seconds
-40.0
40.0
120
200
280
v
d
s

i
n

v
o
l
t
s
P
l
o
t
4
1
I
d
(t)
V
DS
(t)
I
d,peak
=2.1 A
t
rr
100m
700m
1.30
1.90
2.50
i
d
1

i
n

a
m
p
e
r
e
s
p
l
o
t
2
4
3.011m 3.015m 3.019m 3.023m 3.027m
time in seconds
-40.0
40.0
120
200
280
v
d
s

i
n

v
o
l
t
s
P
l
o
t
4
1
I
d
(t)
V
DS
(t)
I
d,peak
=2.1 A
t
rr
250
410
570
v
d
r
a
i
n

i
n

v
o
l
t
s
p
l
o
t
1
V
in
2
R
L
e

V
r
V
r
V
r
+ V
in
V
in
+ V
clamp
250
410
570
v
d
r
a
i
n

i
n

v
o
l
t
s
p
l
o
t
1
V
in
2
R
L
e

V
r
V
r
V
r
+ V
in
V
in
+ V
clamp
250
410
570
v
d
r
a
i
n

i
n

v
o
l
t
s
p
l
o
t
1
V
in
2
R
L
e

V
r
V
r
V
r
+ V
in
V
in
+ V
clamp
Ringing and turn-on in the valleys?
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24
1.002m 1.008m 1.015m 1.021m 1.028m
time in seconds
-70.0
90.0
v
d
r
a
i
n
1
valleys
t
v
V
DS
(t)
1.002m 1.008m 1.015m 1.021m 1.028m
time in seconds
-70.0
90.0
v
d
r
a
i
n
1
valleys
t
v
1.002m 1.008m 1.015m 1.021m 1.028m
time in seconds
-70.0
90.0
v
d
r
a
i
n
1
valleys
t
v
V
DS
(t)
( )
0
1
2
v p leak lump
t L L C
f
= = +
Wait until the drain voltage is minimum and reduce turn-on losses: valley switching!
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
www.onsemi.com
25
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Power stage: Schematic of flyback converter
www.onsemi.com
26
prim
N
N
N
sec
=
Power stage design: Bulk capacitor
out out out
I V P =

out
in
P
P =
P
Output power P
out
Estimation of input power P
in
Estimate the based
on the EPA standard
www.onsemi.com
27
min ,
,
bulk
in
avg in
V
P
I =
Average input current I
in,avg
Design the bulk capacitor for the maximum output power and
the minimum input line voltage.
Power stage design: Bulk capacitor
1
st
current approach

V
b
u
l
k
V
b
u
l
k
,
m
i
n
(
(

|
|

\
|

=

peak
bulk
bulk
avg in
line
bulk
V
V
V
I
f
C 1 cos
1
1
2
1
1 ,

Simple current approach:

avg in
bulk
V
t I
C

=
2 ,
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28
2
nd
power approach
bulk
bulk
V
C

=
line
f
T
1
=
2
min
2
2
2
V V
t P
C
peak
in
bulk

=
Use t
2
=7.5 to 8.5ms for f
line
= 50Hz
Low volume bulk: large ripple, better PF, lower input RMS current
High volume bulk: low ripple, bad PF, high input RMS current
Consideration:
Power stage design: Drain voltage
t
leak
V
r
V
l
e
a
k
V
c
l
a
m
p
V
ds
(t)
V
ds_max
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29
t
rec
t
off
t
on
V
r
V
d
s
_
p
k
V
b
u
l
k
T
sw
t
Power stage design: Transformer ratio
( )
max , max ,
,
20 85 . 0
bulk DS
diode f out C
V V V
V V k
N

+
=
+
Transformer ratio consideration of the V
DSS
of used Q1
Reflected voltage V
r
at primary from secondary
r
clamp
C
V
V
k =
The 20V means margin for clamping diode turning-on overshoot.
N
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30
N
V V
V
diode f out
r
,
+
=
min ,
max
bulk r
r
V V
V
DC
+
=
Maximum duty cycle DC
max
In CCM operation:
In DCM operation doesnt depend on N:
min , min ,
max
2
load
sw prim
bulk
out
R
F L
V
V
DC

=
prim
N
N
N
sec
=
Power stage design: Current ripple
The average shared
transformer current reflected
to primary winding I
L,avg
max
,
,
DC
I
I
avg in
avg L
=
I
v
a
l
l
e
y

I
I
p
e
a
k
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31
Choose the relative ripple I
r
: it affects the operation in the CCM or DCM
avg L
r
I
I
I
,

=
avg L r
I I I
,
=
valley peak
I I I =
|

\
|
+ =
2
1
,
r
avg L peak
I
I I

|

\
|
=
2
1
,
r
avg L valley
I
I I

For universal AC input design use the Ir in range 0.5 to 1.0
For European AC input use the Ir in range 0.8 to 1.6
Power stage design: Primary inductance
I F
DC V
L
sw
bulk
prim

=
max min ,
|
|

\
|

+ =
3
2
2
max
I
I I I DC I
peak peak primRMS
Transformer primary winding inductance L
prim
Maximum RMS value of the current flowing through primary winding I
prim,RMS
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32
|

\
3
max peak peak primRMS
N
I
I
peak
peak
=
sec,
N
I
I

=
sec
( )
|
|

\
|

+ =
3
1
2
sec
sec sec,
2
sec, max sec
I
I I I DC I
peak peak RMS
Maximum RMS value of the current flowing through secondary winding I
sec,RMS
Power stage design: Q1 selection
Then the right device is chosen by parameters V
DSmax
, I
peak
, t
on
, t
off
Conduction loss at Q1 should be approx. 1% of the Pout
2
,
100
RMS prim
out
DSon
I
P
R

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33
Current sensing resistor R
sense
selection
peak
ILIM
sense
I
V
R

=
1 . 1
sense primRMS sense
R I P =
2
The 1.1 factor means 10% margin for L
prim
and other
parameters spread, to be able to deliver maximum power.
Power stage design: Secondary rectification
out bulk
V N V PIV + =
max ,
The next important parameters for
D1 selection are I , I and
D1 selection:
Cout selection:
Reverse voltage across D1
Minimum C
out
value
sw ripple out
out
out
F V
DC I
C

,
max
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34
D1 selection are I
sec,peak
, I
out
and
the fast and soft recovery
peak
ripple out
I
V
ESR
sec,
,

2 2
sec, , out rms rms Cout
I I I =
The maximum allowed ESR of C
out
It is recommended to use more parallel
C
out
for lowering the output voltage ripple.
Dominant part
Power stage design: Clamping network
TVS losses in the suppressor:
RCD clamp 1
st
iteration:
r clamp
clamp
sw peak leak sw clamp clamp
V V
V
F I L F E P

= =
2
2
1
better EMI response
better at no load conditions
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35
sw peak leak
clamp leak
clamp
F I L
V V
R


=
2
2
clamp
clamp
clamp
R
V
P
2
=
sw clamp ripple
clamp
clamp
F R V
V
C

>
These values need to be optimized for the
no load consumption and losses in slow
clamping diode D2
TVS vs RCD clamp comparison
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36
Drain voltage ringing with TVS as clamp Drain voltage ringing with RCD as clamp
Ch1 Drain, Ch3 Clamp node
Different R
damp
used in clamp
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
www.onsemi.com
37
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Application schematic
www.onsemi.com
38
The losses distribution
1.52
2.44
2.53
2.78
1.50
2.00
2.50
3.00
Power loss [W]
Losses distribution measured without EMI filters and surge protecting NTC
www.onsemi.com
39
Input line Input power Output power Total loss power Efficiency
110 V / 60 Hz 72.5 W 63.62 W 8.88W 87.75%
0.00
0.50
1.00
I
n
p
u
t

r
e
c
t
i
f
i
e
r
T
r
a
n
s
f
o
r
m
e
r
P
r
i
m
a
r
y

s
w
i
t
c
h
S
e
c
o
n
d
a
r
y

r
e
c
t
i
f
i
e
r
Optimization of efficiency
There was not found excessive contributor of losses in the
power stage of the flyback converter
Losses in all components should be decreased
Optimization approach:
1) decreasing the losses in power stage by selection of
primary switch Q1 and secondary rectifier D1
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40
primary switch Q1 and secondary rectifier D1
2) decreasing the losses in power stage by decreasing
losses in transformer
3) try to improve the bridge rectifier (not much space)
4) decreasing the conductive losses in EMI filters
5) Do we need surge protecting NTC in case of low value
bulk capacitor ?
Influence of EMI filters
Input EMI filter contributes to the conductive losses mainly at full load
and low line condition
The high inductance 22mH or more is needed to reject the low
frequency emissions ( below 1 MHz )
There is needed to use two chamber CM choke or 2 CM mode chokes
to reject the high frequency emissions above 10MHz
Output EMI filter (CM choke) reject the high frequency emissions from
the DC cord, only low inductance is needed low Rdc low
www.onsemi.com
41
the DC cord, only low inductance is needed low Rdc low
conduction losses
The most important are losses in the high inductance input common
choke from the efficiency optimization point of view
Note from experiments:
There was found an influence of HF ripple at input current to the precision of measurement of input power
using wattmeter YOKOGAWA WT210. There were measured lower input power with the connected 100uH
common choke in comparison without any EMC filter. (at the same conditions) It is better always to use some
EMI filter, with small Rdc to reject the error given by the noisy HF currents.
Transformer optimization result
Transformer ratio Ns/Np optimization
88.00%
88.50%
89.00%
89.50%
E
f
f
i
c
i
e
n
c
y

[
%
]
Q1 breakdown
area
Optimum ratio
The optimum ratio is
given by the Q1
maximum break down
voltage with 15%
derating factor
Decreasing the Ns/Np
decreases the
secondary winding
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42
85.50%
86.00%
86.50%
87.00%
87.50%
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Transformer ratio Ns/Np [-]
E
f
f
i
c
i
e
n
c
y

[
%
]
secondary winding
losses and primary
RMS current
Decreasing the Ns/Np
increases the Q1
switching losses and
secondary RMS
current
Improving Efficiency
Sources of loss:
Switching losses:
Losses caused by leakage inductance:
SW off turn DRAIN DRAIN switching loss
F V C P =

2
) ( ) (
2
1
F I L P =
2
1
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43
Ways to improve efficiency:
Lower the switching frequency F
SW
frequency foldback at light loads
Lower the Drain voltage at turn-off valley switching
SW peak leak loss(leak)
F I L P =
2
2
1
Synchronous rectification
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44
New SR controller NCP4303
coming in 2010
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
www.onsemi.com
45
Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Application schematic
www.onsemi.com
46
+
-1.50
497m
2.50
4.50
6.50
v
e
r
r
,

r
a
m
p

i
n

v
o
l
t
s
p
l
o
t
1
1
2
5.00
7.00

i
n

v
o
l
t
s
p
l
o
t
2
100 %
PWM
modulator
V
error
D
+
-1.50
497m
2.50
4.50
6.50
v
e
r
r
,

r
a
m
p

i
n

v
o
l
t
s
p
l
o
t
1
1
2
5.00
7.00

i
n

v
o
l
t
s
p
l
o
t
2
100 %
PWM
modulator
V
error
D
The voltage-mode PWM generation
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47
-
10.0u 30.0u 50.0u 70.0u 90.0u
time in seconds
-1.00
1.00
3.00
o
u
t

i
n

v
o
l
t
s
p
l
o
t
2
3
0 %
D
-
10.0u 30.0u 50.0u 70.0u 90.0u
time in seconds
-1.00
1.00
3.00
o
u
t

i
n

v
o
l
t
s
p
l
o
t
2
3
0 %
D
In voltage-mode, one compares the error voltage to a fix ramp
This is Pulse Width Modulation also called PWM
+
-
+
-
Vin
Vout
Rupper
Error
Amplifier
PWM
comparator
This level
sets the duty-cycle
The voltage-mode PWM generation
www.onsemi.com
48
-
Vref
Rlower
Rsense
I > Imax ?
--> reset
The inductor current is sensed for safety only
1.31m 1.65m 1.99m 2.33m 2.67m
time in seconds
-500m
500m
1.50
2.50
3.50
v
f
b

i
n

v
o
l
t
s
-1.00
0
1.00
2.00
3.00
i
d
r
a
i
n

i
n

a
m
p
e
r
e
s
p
l
o
t
1
12
3.00 3.50
S
Q
Q
E
rr
o
r
v
o
lta
g
e
MOSFET
1.31m 1.65m 1.99m 2.33m 2.67m
time in seconds
-500m
500m
1.50
2.50
3.50
v
f
b

i
n

v
o
l
t
s
-1.00
0
1.00
2.00
3.00
i
d
r
a
i
n

i
n

a
m
p
e
r
e
s
p
l
o
t
1
12
3.00 3.50
S
Q
Q
E
rr
o
r
v
o
lta
g
e
MOSFET
The current-mode PWM generation
www.onsemi.com
49
2.50m 2.57m 2.65m 2.72m 2.80m
time in seconds
-1.00
0
1.00
2.00
i
d
r
a
i
n

i
n

a
m
p
e
r
e
s
-500m
500m
1.50
2.50
v
f
b

i
n

v
o
l
t
s
P
l
o
t
2
34
R
Inductor peak current
2.50m 2.57m 2.65m 2.72m 2.80m
time in seconds
-1.00
0
1.00
2.00
i
d
r
a
i
n

i
n

a
m
p
e
r
e
s
-500m
500m
1.50
2.50
v
f
b

i
n

v
o
l
t
s
P
l
o
t
2
34
R
Inductor peak current
In current-mode, the error voltage fixes the peak current
+
-
Vin
Vout
Rupper
Error
Amplifier
Current sense
This level
sets the peak current
S
Q
Q
clock
The current-mode PWM generation
www.onsemi.com
50
+
-
Vref
Rlower
Current sense
comparator
Rsense
R
The sense resistor provides a pulse-by-pulse current limit
Same modulation between VM and CM
Both modulators use trailing edge modulation
on
off
Trailing Trailing edge
modulation
Clock
feedback
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51
off
on
Leading Leading edge
modulation
Clock
Clock
off
feedback
NCP1237/38/87/88 flyback controller
The NCP1237/38/87/88 series represents the next generation of fixed frequency PWM controllers. It targets
applications where cost-effectiveness, reliability, design flexibility and low standby power are compulsory.
High-voltage current source
with built-in Brown-out and
mains OVP
Freq. reduction in light load
conditions and skip mode
Adjustable Over Power
Protection
Fewer components and
rugged design
Extremely low no-load
standby power
Simple option to alter the
max. peak current set
point at high line
Unique Features Benefits
Value Proposition
Application Data
DSS
Dual
OCP
Latch
Auto
Recovery
NCP1237A Yes Yes Yes
NCP1237B Yes Yes Yes
www.onsemi.com
52
AC-DC adapters for notebooks, LCD monitor, game
console, printers
CE applications (DVD, STB)
NCP1237/38xDR2G - NCP1287/88xDR2G
SOIC-7 2500p per reel
Others Features
Ordering & Package Information
Market & Applications
Latch-off input for severe fault conditions, allowing
direct connection of NTC
Timer-based protection: auto-recovery or latched
Dual OCP option available
Built-in ramp compensation
Frequency jittering for a softened EMI signature
Vcc operation up to 30 V
Pb
O, DW
Various options available depending
upon end applications needs
NCP1237B Yes Yes Yes
NCP1238A Yes No Yes
NCP1238B Yes No Yes
NCP1287A HV only Yes Yes
NCP1287B HV only Yes Yes
NCP1288A HV only No Yes
NCP1288B HV only No Yes
NCP1237/38/87/88 Built-in Startup FET
High startup current to
A flyback auxiliary winding supplies
biasing voltage in normal condition to
save power
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53
No startup resistor!
Low initial startup current to prevent
damage if Vcc pin is shorted to ground.
High startup current to
reduce charging time
Saves PCB area
& saves power
How it works...
NCP1237/38/87/88 Dynamic Self Supply (optional)
2
C
+
-
4
3
ON/OFF
pin8
pin6
11.3V avg
Vcc
on
Vcc
off
Vcc
(Vcc)
(HV)
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54
C
10.5V/12V
10.00M 30.00M 50.00M 70.00M 90.00M
ON
OFF
Current
source
Power ON Current Source turns ON V
cc
is rising; no output pulses
V
cc
reaches Vcc
(on)
Current Source turns OFF V
cc
is falling; output is pulsing
V
cc
falls to Vcc
(off)
Current Source turns ON V
cc
is rising; output is pulsing
No need of auxiliary winding! Dynamic Self-Supply
NCP1237/38/87/88 Dual startup current level
Startup current is
low initially to
Startup current is
www.onsemi.com
55
low initially to
prevent damage
when V
CC
pin is
grounded.
Startup current is activated when V
CC
drops to V
CC(off)
. Hence, the voltage
never drops below V
CC(off)
after startup.
off when V
CC
reaches V
CC(on)
NCP1237/38/87/88 Brown-out and Mains OVP
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56
Can be connected to the
half-wave rectified ac line
Detection independent of
Ripple on HV pin
NCP1237/38/87/88 Brown-out and Mains OVP
time
VHV
One Shot
V
HV(start)
Starts
only at
V
CC(on)
V
HV(stop)
HV
timer
starts
HV
timer
restarts
www.onsemi.com
57
Passes full line cycle drop-out Timer-based detection
time
One Shot
time
DRV
40ms min.
Brown-out
t
I
peak
I
Lp
S
Lp
Detection
occurs here
Turn off is
delayed
I
peak,max
controller
I
peak,max
real
t
I
peak
I
Lp
S
Lp
Detection
occurs here
Turn off is
delayed
I
peak,max
controller
I
peak,max
real
Current overshoot: do not underestimate it
www.onsemi.com
58
t
prop
t
t
prop
t
Watch-out for clamp voltage variations, at start-up or in short-circuit
The main problem comes from the propagation delay!
sense,max in,max
peak ,max prop
sense p
V V
I t
R L
= +
NCP1237/38/87/88 Over Power Protection
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59
The compensation current
creates an offset on the
Current Sense signal
Over Power Protection Maximum output power clamped
Need to compensate for the
effect of the propagation delay
NCP1237/38/87/88 Dual OCP threshold
V
OUT
Fault timer
starts
V
OUT
Fault timer
starts
Over
load
Over
load
Transient
peak
power
Output still in regulation
www.onsemi.com
60
Accommodates large output
power transients
Suitable for printers
Skip Output
load
Max
output
power
Skip Output
load
Max
peak
power
Max
DC
power
0.7V at
CS pin
0.7V at
CS pin
0.5V at
CS pin
These protections use the Up/Down counters, like classical analog integration.
NCP1237/38/87/88 4 ms Soft Start
with soft-start
time
voltage / current
without soft-start
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61
time
V
CC
Max. current setpoint envelope
4 ms digital soft-start operation
Stressless start-up phase 4 ms Soft Start
NCP1237/38/87/88 Frequency Foldback
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62
Increased efficiency
Switching frequency
lowered at light load
No audible noise
Switching frequency
clamped at 25 kHz
NCP1237/38/87/88 Recover from Standby
Soft-Skip
mode is left as
soon as the
voltage on the
feedback pin

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63
Improved Load Transient
response time
Transient Load Detect
Function (TLD)
feedback pin
reaches the
TLD threshold
NCP1237/38/87/88 Latch-off Protection
V
LATCH
OK
Latch!
Latch!
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64
time
Latch!
Less external components needed
An NTC thermistor can be directly connected to the IC
CCM operation, current instabilities
clock
I
peak
I
L
Perturbation has gone
I
L
(0)
I
L
(0)
t
clock
I
peak
I
L
Perturbation has gone
I
L
(0)
I
L
(0)
t
III
Duty-cycle < 50%
Asymptotically stable
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65
I
L
(0)
clock
I
peak
Duty clamp
I
L
I
L
(0)
t
I
L
(0)
clock
I
peak
Duty clamp
I
L
I
L
(0)
t
clock
I
peak
Duty clamp
I
L
I
L
(0)
t
Duty-cycle > 50%
Asymptotically unstable
CCM operation, curing current instabilities
I
L
I
L
(0)
I (T )
S
1
S
2

I
L
(0)
S
a
c
b
I
L
(T
sw
)
err
i
V
R
I
L
I
L
(0)
I (T )
S
1
S
2

I
L
(0)
S
a
c
b
I
L
(T
sw
)
err
i
V
R
( )
2
2
1
( ) (0) (0)
'
n
a
n
L sw L L
a
S
S
I nT I I a
S d
d S
(

(
( = =
(
+
(

Must stay
below 1
1
a
S
S

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66
t
dT
sw
dT
sw
T
sw
I
L
(T
sw
)
t
t
dT
sw
dT
sw
T
sw
I
L
(T
sw
)
t
2
2
1
1
0
a
S
S
S

<
+
2
50%
a
S S >
Inject ramp compensation
Up to
d = 100%
There is a built in slope compensation with no external setting
The internal slope compensation is activated if the duty cycle is higher
than 40%
The amount of slope compensation is 5mV/% observed at CS pin
NCP1237/38/87/88 Slope compensation
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Block schematic
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Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Reducing No-load Input Power
Static losses in the start-up circuit:
Start-up resistor permanently drawing current from the bulk capacitor
Ways to lower the start-up circuit losses
With external start-up resistor Extremely low start-up current
Integrated start-up current source Extremely low leakage when off
Connect the start-up circuit to the half-wave rectified ac input
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Connect the start-up circuit to the half-wave rectified ac input
Vcc
1
2
3
4 5
8
6
7
HV rail
NCP1351
Start-up resistors
50.0
150
250
350
V
peak
RstartupHW
I1
50.0
150
250
350
V
peak
RstartupHW
I1
startup
startupHW
R
R

=
Selected from
bulk connection
Reducing No-load Input Power
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10.0M 30.0M 50.0M 70.0M 90.0M
time in secs
-50.0
Cbulk
Vcc
RstartupHW
CVcc
auxiliary
winding
Mains
input
10.0M 30.0M 50.0M 70.0M 90.0M
time in secs
-50.0
Cbulk
Vcc
RstartupHW
CVcc
auxiliary
winding
Mains
input
4
startup
startupHW
R
R
P
P

=
Brings a 21% reduction in power
No load input power reducing approach
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Decrease the transformer leakage inductance
Use the controller IC with the frequency foldback and skip mode features
Do not allow the DSS operation (Vcc cap increase)
In case of low Vcc and high aux winding leakage increase the aux number of turns
to disable the DSS
Decrease the value of the Vcc damping resistor (may affect the EMI)
No load input power reducing approach
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Lower the M1 switching losses
Optimize the clamping circuitry
Reduce the losses in the secondary rectifier and its snubber
Decrease the TL431 biasing
Decrease the cross current through the feedback resistor divider
Set a stable operation for all loading currents
Do not use the output voltage indication LED
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Area product A
P
There is defined the area product A
P
[m
4
]
Product of effective window area W
a
[m
2
] and iron cross
section area A
c
[m
2
]
c a P
A W A =
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Allows fast, effective and optimal magnetic design
Should be published in core datasheet
Window utilization factor Ku
Ku is a measure of the amount of copper that appears in
the window area of transformer. This window utilization
factor is affected by:
1) Wire insulation
2) Wire lay (fill factor)
3) Bobbin area
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3) Bobbin area
4) Insulation required for multilayer windings or between windings
Typical values lay in range 0.35 to 0.48
The load coefficient K
load
Flux density in magnetic should be designed at I
peak
with
some margin (5%) to avoid saturation
Do you really need 100% Iout for 100% time??
If not, decrease core size!!
,RMS out
I
K =
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max , ,
,
RMS out
RMS out
load
I
I
K =
Example:
Maximum DC output current is 3.5A, but its only needed for
transients
The long term RMS value is only 1.75A (at least 10 min.)
Loading coefficient is only 0.5 (not 1) core size is smaller
losses in core and in copper are smaller
Flyback transformer core sizing
The core size can be calculated by the A
P
factor in case of these inputs:
1. Converter parameters: L
prim
, I
peak
, K
load
, I
r
, DC
max
2. Core maximum flux density B
max
considered with the hysteresis and
eddy current losses at switching frequency F
sw
3. Winding parameters (utilization factors for primary and secondary
windings Ku
prim
, Ku
sec
), (current densities in primary and secondary
windings J
prim
, J
sec
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windings J
prim
, J
sec
Now the appropriate core can be selected from the vendor products list by
the A
P
factor .
( )
2
2
sec sec
max max
max
2
2 3
12
1
+
+

|
|

\
|

=
r
r
prim prim
load
peak prim
P
I
I
Ku J
DC
Ku J
DC
K
B
I L
A

Windings design
Number of turns of primary winding
c
peak prim
prim
A B
I L
NT

=
max
NT N NT =
Number of turns of secondary winding
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prim
NT N NT =
sec
sec
,
,
NT
V V
V V
NT
diode f out
Vcc f CC
aux

+
+
=
Number of turns of auxiliary winding
Air gap length l
g
r
peak
g
MPL
B
I N
l

=
max
0
MPL core magnetic path length

0
- permeability of vacuum
MPL l
g
<< in case of
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l
g
A
c
MPL

0
- permeability of vacuum

r
- permeability of core
In case an EE, RM or pot core is used, divide
the calculated l
g
by factor 2, because your
core has 2 air gaps in magnetic path
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
How to improve EMI of my design?
AC line filter
Diode snubber
DC output filter
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DRV damping
Power switch loop
Clamping loop
All switching loops with RF currents should have small area
Divide input AC filter at two chokes to decrease the parasitic capacitance
coupling
CY closes the current loop for the RF currents injected via transformer
Diode snubber design
Snubber resistance value should be close to the characteristic
impedance of ringing circuitry
d
SEC leak
snubber
C
L
R
,
=
L
leak,SEC
the transformer leakage
inductance observed from
secondary side
C
d
reverse direction diode
capacitance
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RC time constant of the snubber should be small compared to the
switching period but long compared to the voltage rise time
d snubber
C C 4 3
capacitance
PCB Layout tips
Clamping loop DRV loop
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Output loop
Capacitor pads arrangement for
better filtering RF currents
Power switch loop
Diode snubber
Agenda
Application and requirements
Flyback converter basics
Flyback converter parasitic
Design step 1: Power stage
Design step 2: Efficiency optimization
Design step 3: Control mode and protections
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Design step 3: Control mode and protections
Design step 4: No Load Input Power
Design step 5: Magnetics
Design step 6: EMI
Demoboard example
Preliminary demonstration board
A typical 65 W notebook adapter (19 V output)
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(optimized for EPS 2.0)
Schematic of preliminary demonstration board
A typical 65 W notebook adapter (19 V output)
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(optimized for EPS 2.0)
Demonstration board Efficiency (measured with DC cord)
V
IN
% of P
OUTnom
115 Vac/60Hz 230 Vac/60Hz
100 %
(65 W)
87.10 % 87.37 %
75 %
87.52 % 87.63 %
The DC cord length is 1.05m and copper cross sec. is 0.75mm
2
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75 %
(49 W)
87.52 % 87.63 %
50 %
(32 W)
87.54 % 87.88 %
25 %
(16 W)
87.79 % 85.96 %
Average at 115Vac is 87.32% and at 230 Vac is 87.21 %
Demonstration board Standby Power
Light load and no load input power with the NCP1237
V
IN
P
OUT
115 Vac/60Hz 230 Vac/50Hz
10 %
(6.5 W)
86.55 % 83.74 %
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89
5 %
(3.3 W)
85.40 % 78.72 %
1 %
(0.65 W)
77.49 % 73.77 %
No load
51.1 mW 73.5 mW
80
82
84
86
88
90
E
f
f
i
c
i
e
n
c
y

[
%
]
Demonstration board Efficiency
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70
72
74
76
78
0 10 20 30 40 50 60 70
Pout [W]
E
f
f
i
c
i
e
n
c
y

[
%
]
115 Vac - NCP1237
230 Vac - NCP1237
Demonstration board conducted EMI
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80% of full load (2.72A) at 230V/50Hz NCP1237B65kHz
NCP1237B100kHz frequency jittering
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Ref1 DRV frequency
NCP1237B100kHz frequency foldback
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Ch1 DRV, Ch2 FB, Ref1 DRV frequency
Load transient response from 20% to 100%
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Ch1 Drain, Ch2 FB, Ch3 Vout (AC coupling), Ch4 - Iout
Load transient response from 100% to 20%
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Ch1 Drain, Ch2 FB, Ch3 Vout (AC coupling), Ch4 - Iout
Conclusion
Meeting the most recent requirements from ENERGY STAR

or IEC is possible with the classical Flyback converter

The new controller NCP1237/37/87/88 with frequency
foldback and skip-mode at light load makes it possible
Average efficiencies above 87% are possible
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No-load input power below 300 mWis possible
No-load input power below 100 mWis achievable, although
the controller alone cannot ensure this. The whole power
supply must be designed to reduce power waste.
References
Tutorial and Application notes:
http://www.onsemi.com/pub_link/Collateral/TND376-D.PDF
http://www.onsemi.com/pub_link/Collateral/AND8461-D.PDF
http://www.onsemi.com/pub_link/Collateral/DN06074.PDF
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http://www.onsemi.com/pub_link/Collateral/DN06074.PDF
Feedback loop design spreadsheet:
http://www.onsemi.com/pub/Collateral/FLYBACK DWS.XLS.ZIP
Thank You! Any Questions?
Backup
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Over power compensation
sense
OPP
OPP off
sense
OPP
OPP
P
PROP
bulk
sense
CS
PEAK
R
R
g V
R
R
g
L
t
V
R
V
I +
|
|

\
|
+ =
int
R t
The overpower compensation affects the primary peak current, by the following
formula:
Then the overpower compensation resistor can be calculated:
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OPP P
sense PROP
OPP
g L
R t
R

=
The over power compensating resistor affects only the I
peak
value, but in CCM the
output power is given by the following formula, where I
valley
plays a role:
( )
2 2
2
1
valley peak sw prim out
I I F L P =
2
nd
level over current protection
( )
sense
OPP
OPP off bulk
sense
CStran
TRAN
R
R
g V V
R
V
I =
The overpower compensation affects the 2
nd
level over current
protection by the addition of bulk voltage feed forward.
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The 2
nd
level over current protection can be used for
reducing the transformer size to and keeping the peak
power capability.
Spread sheet design of OPC
Inputs:
Output voltage Vout [V] 19
Primary turns N1 [-] 100
Secondary turns N2 [-] 25
Ramp Comp at CS RaCo [mV/%] 5
Maximum int set point Vilimit [V] 0.7
Sensing resistor Rsense [Ohm] 0.235
OPC design spread sheet was created and the user can choose the right
R
OPP
and its effect to I
peak
, I
tran
, P
out
and P
tran
:
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Sensing resistor Rsense [Ohm] 0.235
Propagation delay tprop [ns] 100
Primary inductance Lp [uH] 560
Vin to Iopp ratio gopp [uS] 0.5
Over power comp resistor Ropp [Ohm] 680
Switching frequency Fsw [kHz] 65
2nd level overcurrent prot Vcstran [V] 0.5
Spread sheet design of OPC
Pmax & Ptran vs line input voltage
40.0
60.0
80.0
100.0
120.0
140.0
P
m
a
x

[
W
]
,

P
t
r
a
n

[
W
]
Ipeak & Itran vs line input voltage
1.0
1.5
2.0
2.5
3.0
3.5
I
p
e
a
k

[
A
]
,

I
t
r
a
n

[
A
]
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0.0
20.0
0 50 100 150 200 250 300 350 400
Vbulk [V]
Ptran Pmax
0.0
0.5
0 50 100 150 200 250 300 350 400
Vin [V]
Ipeak Itran
Keeping constant I
peak
in CCM mode tends to I
valley
decreasing with
increasing the Vin. Thats why the maximum output deliverable power
P
out
increases with increasing Vin. Choose the right compensation.