35

CHAPTER 4
BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Section 4-1 Boolean Operations and Expressions

1. X = A + B + C + D
This is an OR configuration.

2. Y = ABCDE

3. X = C B A

4. (a) 0 + 0 + 1 = 1 (b) 1 + 1 + 1 = 1
(c) 1 0 0 = 1 (d) 1 1 1 = 1
(e) 1 0 1 = 0 (f) 1 1 + 0 1 1 = 1 + 0 = 1

5. (a) AB = 1 when A = 1, B = 1
(b) C B A = 1 when A = 1, B = 0, C = 1
(c) A + B = 0 when A = 0, B = 0
(d) C B A = 0 when A = 1, B = 0, C = 1
(e) C B A = 0 when A = 1, B = 1, C = 0
(f) B A = 0 when A = 1, B = 0
(g) C B A = 1 when A = 1, B = 0, C = 0

6. (a) X = (A + B)C + B

A B C A + B (A + B)C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1

(b) X = C B A ) (

A B C B A X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Chapter 4

36
(c) X = C B A + AB

A B C C B A AB X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1

(d) X = (A + B)( A + B)

A B A + B B A X
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1

(e) X = (A + BC) ) ( C B

A B C A + BC C B X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
1
1
1
0


Section 4-2 Laws and Rules of Boolean Algebra

7. (a) Commutative law of addition
(b) Commutative law of multiplication
(c) Distributive law

8. Refer to Table 4-1 in the textbook.

(a) Rule 9: A A
(b) Rule 8: 0 A A (applied to 1st and 3rd terms)
(c) Rule 5: A + A = A
(d) Rule 6: A A = 1
(e) Rule 10: A + AB = A
(f) Rule 11: B A B A A (applied to 1st and 3rd terms)
Chapter 4
37
Section 4-3 DeMorgans Theorems

9. (a) B A B A B A
(b) B A B A B A
(c) C B A = C B A
(d) C B A ABC
(e) C B A ) ( ) ( C B A C B A
(f) D C B A CD AB
(g) ) )( ( ) ( ) ( D C B A CD AB CD AB
(h) D C B A D C B A D C B A ) )( (

10. (a) D C B A ) ( ) ( D C B A D C B A
(b) ) ( ) ( ) ( ) ( EF CD B A EF CD AB EF CD AB
= ) )( ( F E D C B A
(c) D C B A D C B A D ABC D C B A ) (
(d) ) )( ( ) ( ) ( D C B A D C B A D C B A D C B A
= D C B A D C B A D C B A D C B A
(e) ) ( ) ( ) )( ( CD AB F E CD AB CD AB F E CD AB
= ) )( ( ) )( ( CD AB F E CD AB
= ABCD F E D C AB ) )( (

11. (a) KLM HIJ EFG ABC KLM HIJ EFG ABC ) )( ( ) ( ) (
= ) )( )( )( ( KLM HIJ EFG ABC KLM HIJ EFG ABC
= ) )( )( )( ( M L K J I H G F E C B A
(b) BC CD C B A BC CD C B A BC CD C B A ) )( ( ) )( ( ) (
= BC D C B A BC D C B A C B A BC D C C B A ) 1 ( ) (
= BC C B A
(c) ) )( )( )( ( H G F E D C B A
= H G F E D C B A ) )( )( ( ) ( H G F E D C B A

Chapter 4

38
Section 4-4 Boolean Analysis of Logic Circuits

12. (a) AB = X
(b) A= X
(c) A + B = X
(d) A + B + C = X

13. See Figure 4-1.





















14. See Figure 4-2.



X
X
Chapter 4
39
15. See Figure 4-3.


















16. (a) See Figure 4-4(a).
(b) See figure 4-4(b).










17. See Tables 4-1 and 4-2.

Table 4-1
INPUTS OUTPUT
VCR CAMI RDY RECORD
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Table 4-2
INPUTS OUTPUT
RTS ENABLE BUSY SEND
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1




FIGURE 4-3
FIGURE 4-3
Chapter 4

40
18. (a) X = A + B

A B X
0
0
1
1
0
1
0
1
0
1
1
1

(c) X = AB + BC

A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
1
1


(b) X = AB

A B X
0
0
1
1
0
1
0
1
0
0
0
1

(d) X = (A + B)C

A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
(e) X = ) )( ( C B B A

A B C A + B C B X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
1
1
1
0
1


Section 4-5 Simplification Using Boolean Algebra

19. (a) A(A+ B) = AA + BB = A + AB = A(1 + B) = A

(b) AB AAB A A AB A A 0 ) ( AB

(c) ) ( B B C C B BC = C(1) = C

(d) B A A AA B A A A ) ( = A + (0)B = A + 0 = A

(e) ) 1 ( ) ( C A C B A B B C A C B A C B A BC A C B A
= C B C A ) ( ) ( B A C B A A C C A C B A

Chapter 4
41
20. (a) C B B A AC A C B B A AC AA C A B A ) )( (
= C B A C B A C B B C A ) 1 ( ) 1 (
(b) ) 1 ( ) 1 ( B A E D C CD C B A E D C B A BCD A C B A B A
= B A
(c) A C B C A AB A C B A AB A C AB AB ) (
) 1 ( ) 1 ( B C A C B C A C B C A A C B C A B A
= A + C
(d) C AB A AB A C AAB AAB C AB AB A A ) )( (
= AB ) 1 ( 0 0 C AB C AB AB
(e) C B A AB AB C B C A AB AB C B A AB ) ( ) (
= C AB C AB AB

21. (a) F D D D BE BD BD F D D E D B BD ) ( ) (
= F D BE BD F D BE BD 0
(b) D C B A C B A D C B A C B A C B A D C B A C B A C B A ) (
= D B A C B A ) ( ) ( D C B A D C C B A
(c) ) )( )( 1 ( ) )( )( ( D B C B C B D B C B B BC B
= ) )( ( ) )( ( ) )( ( D B BC B D B BC BB D B C B B
= B(1 + C)(B + D) = B(B + D) = BB + BD = B + BD = B(1 + D) = B
(d) CD B A D C AB ABCD CD AB CD AB ABCD ) ( ) ( ) ( ) (
= CD B CD A D AB C AB ABCD
= D AB C AB B A B CD D AB C AB B A AB CD ) ( ) (
= AB CD ) ( ) 1 ( CD AB CD D AB C AB CD D AB C AB A CD
(e) ) ( )] ( [ AC BC C ABC ABABC AC BC C AB ABC
= ABC + 0(BC + AC) = ABC

Chapter 4

42
22. First develop the Boolean expression for the output of each gate network and simplify.

(a) See Figure 4-5.













X = D AC C A A B B A D AC C B A B D C A C B A ) ( ) (
= D AC C B B A ACD C A B ) (

(b) See Figure 4-6.












X = D AC B A D AC C B A C B A D AC B A ) 1 (

(c) See Figure 4-7.











X = D C B B A No further simplification is possible.


FIGURE 4-5
FIGURE 4-6
FIGURE 4-7
Chapter 4
43
(d) See Figure 4-8.











X = D AC B A No further simplification is possible.


Section 4-6 Standard Forms of Boolean Expressions

23. (a) B A BC AC B A B B BC AC B C B A ) )( (
(b) C B AC CC B AC C C B A ) (
(c) (A + C)(AB + AC) = AAB + AAC + ABC + ACC = AB + AC + ABC + ACC
= (AB + AC)(1 + C) = AB + AC

24. (a) CD CD B A AB CDCD CD B A AB CD B A CD AB ) (
= CD AB CD B A AB ) 1 (
(b) ABD ABBD C B AB BD C B AB 0 ) ( = ABD
(c) BD C B ABC A D C B AC B A ) ( ] ) ( [
= ) 1 ( ) 1 ( C BD A D C B BD BC A D C B BD ABC A
= A + BD

25. (a) The domain is A, B, C
The standard SOP is: BC A ABC C B A C B A

(b) The domain is A, B, C
The standard SOP is: C B A C B A ABC

(c) The domain is A, B, C
The standard SOP is: C B A C AB ABC

26. (a) AB + CD = CD B A BCD A CD B A D C AB D C AB D ABC ABCD
(b) ABD = D C AB ABCD
(c) A + BD = D C AB D C AB CD B A D C B A D C B A D C B A
+ BCD A D C B A ABCD D ABC

FIGURE 4-8
Chapter 4

44
27. (a) : BC A ABC C B A C B A 101 + 100 + 111 + 011
(b) : C B A C B A ABC 111 + 101 + 001
(c) : C B A C AB ABC 111 + 110 + 101

28. (a) : CD B A BCD A CD B A D C AB D C AB D ABC ABCD
1111 + 1110 + 1101 + 1100 + 0011 + 0111 + 1011
(b) : D C AB ABCD 1111 + 1101
(c) D C AB D C AB CD B A D C B A D C B A D C B A
+ : BCD A D C B A ABCD D ABC
1000 + 1001 + 1010 + 1011 + 1100 + 1101 + 1110 + 1111 + 0101 + 0111

29. (a) ) )( )( )( ( C B A C B A C B A C B A
(b) ) )( )( )( )( ( C B A C B A C B A C B A C B A
(c) ) )( )( )( )( ( C B A C B A C B A C B A C B A

30. (a) ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A
) )( )( )( ( D C B A D C B A D C B A D C B A
(b) ) )( )( )( ( D C B A D C B A D C B A D C B A
( )( )( )( )( ) A B C D A B C D A B C D A B C D A B C D
) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A
(c) ) )( )( )( ( D C B A D C B A D C B A D C B A
) )( ( D C B A D C B A

Section 4-7 Boolean Expressions and Truth Tables

31. (a) Table 4-3
A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1


(b) Table 4-4
X Y Z Q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
1
0
Chapter 4
45
32. (a) Table 4-5
A B C D X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0

(b) Table 4-6
W X Y Z Q
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
33. (a) C B A C B A C AB C B A BC A C B A C A C AB B A

(b) X YZ WZ XYZ W XYZ W XYZ W XYZ W XYZ
+ Z Y X W Z Y X W Z XY W Z Y X W
+ WXYZ Z WXY Z Y WX YZ X W Z Y X W

Table 4-7
A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0

Table 4-8
W X Y Z Q
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1

Chapter 4

46
34. (a) Table 4-9
A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0

(b) Table 4-10
A B C D X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1

35. (a) Table 4-11
A B C X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1

(b) Table 4-12
A B C D X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
0
0
0
1
0
0
1
1
1
1
1


36. (a) X = ABC C B A C B A C B A
X = ) )( )( )( ( C B A C B A C B A C B A
(b) X = ABC C B A C AB
X = ) )( )( )( )( ( C B A C B A C B A C B A C B A
(c) X = D C AB D C B A D BC A D C B A CD B A D C B A D C B A
X = ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A
) )( )( )( ( D C B A D C B A D C B A D C B A


Chapter 4
47
(d) X = ABCD D C AB CD B A BCD A D C B A D C B A D C B A
X = ) )( )( )( )( ( D C B A D C B A D C B A D C B A D C B A
) )( )( )( ( D C B A D C B A D C B A D C B A

Section 4-8 The Karnaugh Map

37. See Figure 4-9.

38. See Figure 4-10.

39. See Figure 4-11.












Section 4-9 Karnaugh Map SOP Minimization

40. See Figure 4-12.





















FIGURE 4-9
FIGURE 4-10 FIGURE 4-11
FIGURE 4-12
Chapter 4

48
41. See Figure 4-13.



























42. (a) ABC C B A C C AB ABC C B A AB ) (
= ABC C B A C AB ABC
= C AB C B A ABC

(b) BC A A C C B A AB BC A A C C B B A BC A ) ( ) )( ( ) ( ) )( (
= ABC BC A C B A C B A C AB ABC
= BC A C B A C B A C AB ABC

(c) D BC A D C B D AC D C B A
= D BC A D C B A A CD B B A D C B A ) ( ) ( =
= D BC A D C B A D C AB D C B A D ABC D C B A

(d) ABCD D C B CD D C B A B A
= ABCD D C B A A CD B B A A D C B A D D C C B A ) ( ) )( ( ) )( (
= BCD A CD B A ABCD D C B A ABCD D ABC D C B A D C B A
ABCD D C B A D C AB CD B A
= D C B A D C AB CD B A BCD A CD B A ABCD D ABC D C B A D C B A
= D ABC ABCD D C AB CD B A D C B A D C B A BCD A D C B A CD B A
F E F D X
FIGURE 4-13
Chapter 4
49
43. See Figure 4-14.




























44. See Figure 4-15.




FIGURE 4-14
FIGURE 4-15
Chapter 4

50
45. Plot the 1s from Table 4-11 in the text on the map as shown in Figure 4-16 and simplify.

















46. Plot the 1s from Table 4-12 in the text on the map as shown in Figure 4-17 and simplify.
















47. See Figure 4-18.



FIGURE 4-16
FIGURE 4-17
FIGURE 4-18
Chapter 4
51
Section 4-10 Five-Variable Karnaugh Maps

48. . X ABCDE A BCDE
See Figure 4-19.


















49. See Figure 4-20.




















FIGURE 4-20
FIGURE 4-19
Chapter 4

52
50. See Figure 4-21.




















Section 4-11 Describing Logic with an HDL

51. entity AND_OR is
port (A, B, C, D, E, F, G, H, I: in bit; X: out bit);
end entity AND_OR;
architecture Logic of AND_OR is
begin
X <= (A and B and C) or (D and E and F) or (G and H and I);
end architecture Logic;

52. The VHDL program:

entity SOP is
port (A, B, C: in bit; X: out bit);
end entity SOP;
architecture Logic of SOP is
begin
Y <= (A and not B and C) or (not A and not B and C) or
(A and not B and not C) or (not A and B and C);
end architecture Logic;

System Application Activity

53. An LED display is more suitable for low-light conditions because LEDs emit light and LCDs
do not.

54. The purpose of the invalid code detector is to detect the codes 1010, 1011, 1100, 1101, 1110,
and 1111 to activate the display for letters.

FIGURE 4-21
Chapter 4
53
55. The standard SOP expression for segment c is:
c =
3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H
This expression is minimized in Figure 4-22.




















56. The standard SOP expression for segment d is:
d =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H
This expression is minimized in Figure 4-23.
























FIGURE 4-23
FIGURE 4-22
The standard expression requires three 4-input AND gates, one 3-input OR gate, and 3 inverters.
The minimum expression requires two 2-input AND gates, one 2 input OR gate, and 2 inverters.
The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.
The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2-input
OR gate, and 2 inverters.
Chapter 4

54
The standard SOP expression for segment e is:
e =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H H H H H
This expression is minimized in Figure 4-24.





















The standard SOP expression for segment f is:
f =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H
This expression is minimized in Figure 4-25.





















FIGURE 4-25
FIGURE 4-24
The standard expression requires five 4-input AND gates, one 5-input OR gate, and 3 inverters.
The minimum expression requires one 3-input AND gate.
The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.
The minimum expression requires one 2-input AND gate.
Chapter 4
55
The standard SOP expression for segment g is:
g =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H
This expression is minimized in Figure 4-26.






















Special Design Problems

57. Connect the OR gate output for each segment to an inverter and then use the inverter output to
drive the segment with a HIGH.

58. See Figure 4-27. F = 1111
The expression for segment a to include the letter F is:
a =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H
The expression is minimized in Figure 4-27.















FIGURE 4-26
FIGURE 4-27
The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.
The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2 input
OR gate, and 2 inverters.
Chapter 4

56
59. See Figure 4-28. Segment b is used for letters A and d.
b =
3 2 1 0 3 2 1 0
H H H H H H H H

















See Figure 4-29. Segment c is used for letters A, b, and d.
c =
3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H
















FIGURE 4-28
FIGURE 4-29
Chapter 4
57
See Figure 4-30. Segment d is used for b, C, d, and E.
d =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H


















See Figure 4-31. Segment e is used for A, b, C, d, E, and F.
e =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H H H H H H H H H


















FIGURE 4-30
FIGURE 4-31
Since segment e is active-LOW for all letters, e = 0.
Chapter 4

58
See Figure 4-32. Segment f is used for A, b, C, E, and F.
f =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H H H H H



















See Figure 4-33. Segment g is used in A, b, d, E, and F.
g =
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
H H H H H H H H H H H H H H H H H H H H



















FIGURE 4-32
FIGURE 4-33
Chapter 4
59
60. The invalid code detector must disable the display when any numerical input (0-9) occurs. A
HIGH enables the display and a LOW disables it. A circuit that detects the numeric codes and
produces a LOW is shown in Figure 4-34.



















Multisim Troubleshooting Practice

61. Input A inverter output open.

62. Input A of segment e OR gate open.

63. Segment b OR gate output open.


FIGURE 4-34