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Q5
The parameters of a hierarchical memory system are specified as follows: Main
memory size = 8K blocks
Cache memory size = 512 blocks
Block size = 16 words
Determine the size of the tag field under the following conditions:
a. Fully associative mapping
b. Direct mapping
c. Set associative mapping with 16 blocks/set
TAG SET/BLOCK WORD
a) 13 0 4
b) 4 9 4
c) 8 5 4
Q6What is the average access time of a system having three levels of memory hierarchy: a cache
memory, a semiconductor main memory, and magnetic disk secondary memory. The access times
of these memories are 20 ns, 200 ns, and 2 ms, respectively. The cache hit ratio is 80 per cent and
the main memory hit ratio is 99 per cent.
Answer:
First, compute the CPI for each processor:
Processor X: 1 * 0.35 + 2 * 0.30 + 4 * 0.35
= 0.35 + 0.60 + 1.40
= 2.35 cycles/instruction
Y- Option 1: 1 * 0.35 + 3 * 0.30 + 4 * 0.35
= 0.35 + 0.90 + 1.40
= 2.65 cycles/instruction
Y- Option 1: 1 * 0.35 + 2 * 0.30 + 3 * 0.35
= 0.35 + 0.60 + 1.05
= 2.00 cycles/instruction
Next, compute how long it would take to execute an “average”
instruction. This is done by dividing CPI (cycles/instruction) by clock
rate (cycles/second) to give (seconds/instruction):
Processor X: 2.35 / 1.0 = 2.35 ns/instruction
Y- Option 1: 2.65 / 1.2 = 2.21 ns/instruction
Y- Option 2: 2.00 / 0.9 = 2.22 ns/instruction
Then, compute the speedups:
Y- Option 1: 2.35/2.21= 1.063
Y- Option 2: 2.35/2.22= 1.059
So the speedups can either be phrased as “Option 1 is 6.3% faster than
X, and Option 2 is 5.9% faster than X” or “Option 1 is 1.063 times
faster than X, and Option 2 is 1.059 times faster than X”.
QFor this problem, assume that you have a processor with a cache connected to main memory
via a bus. A successful cache access by the processor (a hit) takes 1 cycle. After an
unsuccessful cache access (a miss), an entire cache block must be fetched from main memory
over the bus. The fetch is not initiated until the cycle following the miss. A bus transaction
consists of one cycle to send the address to memory, four cycles of idle time for main-memory
access, and then one cycle to transfer each word in the block from main memory to the cache.
Assume that the processor continues execution only after the last word of the block has
arrived. In other words, if the block size is B words (at 32 bits/word), a cache miss will cost 1
+ 1 + 4 + B cycles. The following table gives the average cache miss rates of a 1 Mbyte cache
for various block sizes:
Write an expression for the average memory access time for a 1-Mbyte cache and a B-word block size (in
terms of the miss ratio m and B).
Average access time = (1-m)(1 cycle) + (m)(6 + B cycles) = 1 + (m)(5+B) cycles
What block size yields the best average memory access time?
If bus contention adds three cycles to the main-memory access time, which block size yields the best average
memory access time?
If bus width is quadrupled to 128 bits, reducing the time spent in the transfer portion of a bus transaction to
25% of its previous value, what is the optimal block size? Assume that a minimum one transfer cycle is
needed and don't include the contention cycles introduced in part (C).