What Every Designer Should Know About

MOSFETs (Up to 200V)

Power Seminar 2004
2
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
3
Synchronous Buck Converters
HIGH SIDE (control) switch is ON for a short time
Switching losses per cycle will be high as the full current and
the full input voltage need to be switched
Due to the low duty cycle, the conduction losses will be much
less than for an equivalent Low Side switch
LOW SIDE (synchronous) switch is ON for most of the time
Conduction losses will dominate
Switching losses per cycle are lower as the full input current is
switched at the low side Schottky diode forward voltage
4
Synchronous Buck Converter
Duty Cycle = Vout / Vin
Each MOSFET sees a maximum voltage of Vin Vds(on) of
other MOSFET.
However
5
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
6
Switch Node Spikes Higher than Input Voltage!
(Notebook FDS6294 upper FET / FDS7088N3 x1 Lower FET)
V
GS
FDS7088N3
V
DS
FDS7088N3
Anti-parallel diode, switch timing, package inductance, board layout
Conditions:
Vin = 19V
Iout = 15A
Still air
7
As Switching Frequencies Increase
As MOSFETs switch faster, ringing will tend to increase.
In spite of careful MOSFET structure design and choice of doping
densities etc., the trend is towards an increasingly snappy diode.
The Ratio tb / ta is called Softness
Factor and is key in reducing EMI
8
Making MOSFETs with a Faster Diode
SyncFet Adding an anti-parallel Schottky on same silicon.
SyncFet is an order of magnitude trr and Qrr improvement over
the best co-packaged hybrid of a MOSFET and Schottky. We can
design MOSFETs with alternating MOSFET and Schottky strips to
minimize trr and Qrr.
OR
Improving existing diode by creating recombination centers in
body-epitaxy interface.
Platinum doping is most popular method for softness.
So far, not introduced in low voltage MOSFETs because trr and
Qrr are much lower than in high voltage MOSFETs.
9
Low Side FET Switching Waveforms no RC
Snubber
(Notebook FDS6294 upper FET / FDS6288 x2 Lower FET)
Vgs FDS6288
Vds FDS6288
10
Low Side FET Switching Waveforms with 1.5nF,
3.3 RC Snubber
(Notebook FDS6294 upper FET / FDS6288 x2 Lower FET)
Vgs FDS6288
Vds FDS6288
11
Low Side SyncFET Switching Waveforms
(Notebook FDS6294 upper FET / FDS6688S x2 Lower FET)
Vgs
FDS6688S
Vds
FDS6688S
12
Converter Efficiency Comparison
13
Thermal Camera Images
(FDS6288 vs. FDS6688S, 19Vin, 1.3Vout@20A)
FDS6294 HS, FDS6288 LS FDS6294 HS, FDS6688S LS
FDS6294
(83C)
FDS6288
(80C)
FDS6688S
(73C)
FDS6294
(71C)
14
Eas Single Pulse Avalanche Energy
Single pulsed avalanche energy ( ) guaranteed by test.
Energy level to endure without fail
E
AS
15
Notebook FDS6294 upper FET / FDS7288N3 x2
Lower FET
(Lower FET switching waveforms) Zoom in of slide 20.
Conditions:
Vin = 19V
Iout = 15A
Still air
dVDS/dt = 9.6V/ns
16
Avalanche Energy Rating :
The Avalanche Current is the Key Parameter
17
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
18
Shoot Through
Adaptive gate delay circuits prevent shoot-through in most
cases.
However, a phenomenon known as dv/dt or false turn-
on can cause shoot-through to occur.
This problem shows up as poor efficiency and higher
MOSFET temperatures in both MOSFETs and higher EMI.
19
PWMIC - Switch Timing
(AN-6005 Loss Calculations with Excel Spreadsheet)
20
dV/dt Turn On
False turn on
Possible to control externally
C
GD
= Crss
C
GS
= Ciss Crss
C
DS
= Coss Crss
R
Driver
21
dV/dt Resulting in False Turn On
dV/dt turn-on happens as you turn on
the high side MOSFET. The high dv/dt
couples with charge through Cgd of the
low side MOSFET and drives the gate of
the low side MOSFET higher. This spike
is sufficient to turn on the lower
MOSFET and cause shoot-through.
22
Notebook FDS6294 upper FET / Competition x1
Lower FET
(Lower FET switching waveforms) Second slope dV/dt induced
shoot through loss.
Conditions:
Vin = 19V
Iout = 15A
Still air
Double
slope
in Vds
Slope
changes
in this
area
where
Vgs > Vth
23
Reducing Turn On dv/dt
dv/dt turn-on can also be
reduced by increasing the rise
time. This is achieved by
adding a resistor in the boot
circuit to slow turn on of the
high side MOSFET
If you must use a gate
resistor, add a low drop
Schottky in parallel
24
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
25
Parasitics in a Synchronous Buck Converter
26
Notebook FDS6294 High Side FET / Competition
x1 Low Side FET
Gate
noise
during
dVds/dt
Gate rings
below -1V.
During
dVds/dt,
gate has
actually
rung back to
positive.
Gate L-C ringing can destroy gate drivers and cause false turn on.
27
Go to www.fairchildsemi.com/models, click on FetBench
28
Choose the Sync Buck Application
29
30
Package Impedance Comparisons

Comparison of Electrical Characteristics of Various Power Packages
i)
Ldd
nH
Lgg
nH
Rd
m
Rs
m
Rg
m
Package
Description
2 x 2.5 mm BGA 0.056 0.011 0.032 0.05 0.16 0.79
4 x 3.5 mm BGA 0.064 0.006 0.034 0.02 0.06 0.95
5 x 5.5 mm BGA 0.048 0.006 0.041 0.01 0.04 0.78
0.744
SO-8 0.457 0.901 1.849 0.12 2.04 20.15
SO-8 Wireless 0.601 0.709 0.932 0.16 0.23 1.77
IPAK (TO-251) 2.920 3.490 4.630 0.25 0.74 8.18
DPAK (TO-252) 0.026 3.730 4.870 0.00 0.77 8.21
D2PAK (TO-263) 0.000 7.760 9.840 0.00 0.96 12.59
FLMP ( Large 3s)
FLMP ( Large 7s) 0.194
0.943
0.921
0.002
0.002
0.245
0.137
2.046
2.038
0.000
0.000
Lss
nH
31
BGA vs. SO-8 Same Die, Same Application
BGA MOSFETs SOIC MOSFETs

ch4 = SW node, Ch 3 = LDRV
T
R

4nS
ch1 = HDRV, Ch 2 = LDRV
T
R

20nS
32
Package Impedances - Conclusions

IPAK is an inexpensive package taking up very little real estate but
inductances are very high. Not suitable for high frequencies.
As switching frequencies increase, DPAK and SO-8 will be
replaced by BGAs and FLMPs.
You should not blindly use same package for high and low side
especially if you can use a smaller package with lower parasitics
for high side switches. Under 10m , 30V in 3x3 MLP.
33
As Switching Frequencies Increase...
MORE FOCUS ON REDUCING PARASITICS :
(DUAL MOSFET+ PWMIC) COMBINATIONS :
Hybrid Packaging
Monolithic Solutions
Make your own combination with better packages with BGAs.
Pay attention to layout especially around switch nodes and
gate circuits.
34
Hybrid Synchronous Bucks
3-Paddle 5x6mm
0.65mm pitch MLP
(Bottom View)
VIN
VSEN
PGND
AGND
LDRV
HDRV
SW
COMP
VCC
SS
Q1
Q2
BOOT
PGOOD
SW
VSEN
P3
PGND
14
P1
C
OUT
VOUT
L
OUT
R2
R
1
P2
VIN
BOOT
8
SS
CSS
COMP
VCC
13
15
12
16
10
R
3
C1
11
PGOOD
6.5 TO 24V
VOUT
FPWM#
9
+5
PWM
MOD-
ULATOR
EN
VOUT
BOOT
PVIN
PVIN
PVIN
PVIN
SW
SW
SW
+5 VCC
FPWM#
VSEN
SS
COMP
PGOOD
EN
VOUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
P
1
G
N
D
P
2
V
I
N
P
3
S
W
35
Hybrid Sync-Buck PCB Layout
(Target Area < 0.3 sq in. for 5A, 12Vin)
I
n
d
u
c
t
o
r
:
C
o
i
l
t
r
o
n
i
c
s
U
P
1
B

S
E
R
I
E
S
I
n
d
u
c
t
o
r
:
C
o
i
l
t
r
o
n
i
c
s
U
P
1
B

S
E
R
I
E
S
GND
VIN
P1
P2
P3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
0
6
0
3
C
a
p
1
2
0
6
C
a
p
1206
Cap
1
2
0
6
C
a
p
1
2
1
0

C
A
P
0603
R
0603
R 0
6
0
3
R
0
.
5

"
0.5875 "
36
FAN20XX
Monolithic Synchronous Buck Family Overview
Over 90% Efficiency
3.0V to 5.5V VIN
IN
Programmable phase
clock synchronization
Internal power MOSFETs
Current and thermal limit
Programmable auto-restart
on fault
Current mode control
FAN 2011 and FAN2012 are examples
7
8
SS
12
I(LIM)
13
R(T)
CSS
VCC
15
CLOCK
10
EN
SW
FB
Q1
Q2
PWM
MODULATOR
GND
14
PVIN
P1
C
OUT
VOUT
L
OUT
R2
R
1
9
PGOOD
VOUT
11
R(LIM)
RT
37
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
38
Industrial Low Voltage MOSFETS
Low Voltage MOSFETs in industrial applications are really very
different from those in surface mount DC-DC converters.
MOSFETs in industrial applications are closer to High Voltage
MOSFETs in some design and critical parameters.
Planar MOSFETs have some advantages at high currents over
Trench.
Industrial Applications UPS systems, Inverters, Battery Powered
Motor Drives (people movers), Automotive Audio etc.
39
Paralleling Power MOSFETs in Industrial
Applications
MOSFET paralleling is generally easier than any other power
semiconductor device thanks to positive temperature coefficient
Applications such as UPS, Drives etc. have numerous paralleled
MOSFETs. TO-220 and TO-263 (D2PAK) are the most popular
package
As low voltage power MOSFET technologies evolve, what is best
for high frequency dc-dc switching converters may not be best for
these industrial applications
40
Parallel Operation of MOSFETs
Static and Dynamic Current Sharing
Circuit Parasitics
V
Ls Ls
Ld Ld
Rd Rd
R
load
L
load
L
layout
Kelvin source
Rg Rg
S1
G1
Rg1
S2
G2
Rg2
S3
G3
Rg3
Rg4
S4
G4
41
Circuit Layout Considerations: Dynamic
Conduction
Severe turn-on and turn-off current differences may
result from mismatched devices
ISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)
1
i_high_vgsth
2
i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5U
time ( 7.5 s / div.)
12.0
36.0
60.0
84.0
108
i
_
h
i
g
h
_
v
g
s
t
h
,

i
_
l
o
w
_
v
g
s
t
h

i
n

a
m
p
s
P
l
o
t
1
1
2
5
14V
5 50
8u 0.01
10V
42
Dynamic Current Balancing
20nH Added to Source
Switching current balance improved with intentional addition of
limited source inductance
ISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)
Note that the negative tempco of VGS(th) tends to increase
current Imbalance.
1 i_high_vgsth 2 i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5U
time in secs
12.0
36.0
60.0
84.0
108
i
_
h
i
g
h
_
v
g
s
t
h
,

i
_
l
o
w
_
v
g
s
t
h

i
n

a
m
p
s
P
l
o
t
1
21
5
14V
5 50
8u 0.01
10V
20nH
20nH
43
Circuit Layout Considerations: Dynamic
Conduction
Switching waveform balance obtained with 1 turn common mode
inductor in series with device sources
Forces synchronized turn-on and turn-off
ISL9N302AS3ST, reference Lot Y149 (devices #4 and #7)
1 i_high_vgsth 2 i_low_vgsth
7.50U 22.5U 37.5U 52.5U 67.5U
time in secs
12.0
36.0
60.0
84.0
108
i
_
h
i
g
h
_
v
g
s
t
h
,

i
_
l
o
w
_
v
g
s
t
h

i
n

a
m
p
s
P
l
o
t
1
12
5
14V
5 50
8u 0.01
10V
1T
Magnetics Inc
YF40705-TC
Lmag = 2.5uH
Ll k = 20nH
K=0.992, r = 0.0001
44
Summary: Circuit Layout Considerations
Use symmetrical layout to minimize & equalize parasitic
impedances
Use shared heat sink to match TJmax even if uneven current
results
TJmax has most profound effect on reliability
Vgs(th) has a negative temperature coefficient
Use a fast gate drive signal: Less time spent in active region
Dynamic current sharing improves with faster switching
select the gate resistor as small as possible
during switch on no ringing shall be allowed
Inductance inserted in FET source lead is very effective for
dynamic current sharing
Reduced switching speed and increased switching loss
45
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
46
Planar vs. Trench MOSFETS
Planar
Trench
R
DS(on)
= R
Channel
+ R
Epitaxial
+ R
Package
R
DS(on)
= R
Channel
+ R
JFET
+ R
Epitaxial
+ R
Package
R
Package
Drain
Gate
Source
Source
R
Epitaxial
R
JFET
R
Channel
Drain
Gate
Gate
Source
R
Channel
R
Package
R
Epitaxial
47
HUF75545P3 FDB045AN08A0
(Older Planar) (Newer Trench)
R
DS(on)
10mW 4.5mW
Qg 235nC 138nC
Pd 270W 310W
t
rr
(@ 25 C) 100ns 53ns
Q
rr
(@ 25 C) 300nC 54nC
75V MOSFET Technology Trends. Comparing MOSFETs of equal die size.
Comparison of MOSFET Key Parameters
48
trr: Anti-parallel Diode Recovery
Test
Conditions:
V
DD
= 60V
I
D
= 20A
di/dt =
520 A/ s
49
Thermal Analysis
Worst Case for the inverter MOSFETs = Output short circuit
For this case a low RQjc is most important:
HUF75545P3 FDB045AN08A0
RQjc 0.55 K/W 0.48 K/W
50
Maximum Current at Short Circuit
Transconductance vs. Current Crowding
HUF75545P3
Older Planar
FDB045AN08A0
Newer Trench
51
Outline
Computer/Consumer SMD Switch Applications
Synchronous Buck Regulators
Node Voltage Overshoots
MOSFET Body Diode & Avalanche Ruggedness
Switch Timing and dV/dt Shoot Through
Package and Layout Parasitics
Industrial Applications
Paralleling Multiple MOSFETs
Trench vs. Planar
RC DrainSource Snubbers
52
Adding Gate Resistors
Many applications need
MOSFETs in parallel for
extremely low on-resistance.
Since costs are optimized
around TO-220 die size, banks
are common
Use of built-in resistor shows a
decrease of circuit oscillation
and EMI
53
FDB3632 (NO RC Circuit Across FET)
(Test Conditions: VDS = 50Vdc, ID = 40A, VGS = 10V, L=10uH, TJ = 25C)
Rge = 51
Eon = 164uJ
Rge = External Gate Resistor
54
FDB3632 (With RC Circuit Across FET, D-S)
(Test Conditions: VDS = 50Vdc, ID = 40A, VGS = 10V, L=10mH, TJ = 25C)
Rge = 51
Eon = 208uJ
R-C Snubber
C=2000pF
R=1
Rge = External Gate Resistor