Inveters

After completion of this lesson the reader will be able to:
(i) Identify the essential components of a voltage source inverter.

(ii) Explain the principle behind dc to ac conversion.
(iii) Identify the basic topology of single-phase and three-phase inverters and explain
its principle of operation.
(iv) Explain the gate drive circuit requirements of inverter switches.

The word inverter in the context of power-electronics denotes a class of power conversion (or
power conditioning) circuits that operates from a dc voltage source or a dc current source and
converts it into ac voltage or current. The inverter does reverse of what ac-to-dc converter
does (refer to ac to dc converters). Even though input to an inverter circuit is a dc source, it is
not uncommon to have this dc derived from an ac source such as utility ac supply. Thus, for
example, the primary source of input power may be utility ac voltage supply that is converted
to dc by an ac to dc converter and then inverted back to ac using an inverter. Here, the final ac
output may be of a different frequency and magnitude than the input ac of the utility supply.

[The nomenclature inverter is sometimes also used for ac to dc converter circuits if the
power flow direction is from dc to ac side. However in this lesson, irrespective of power
flow direction, inverter is referred as a circuit that operates from a stiff dc source and
generates ac output. If the input dc is a voltage source, the inverter is called a voltage
source inverter (VSI). One can similarly think of a current source inverter (CSI), where the
input to the circuit is a current source. The VSI circuit has direct control over output (ac)
voltage whereas the CSI directly controls output (ac) current. Shape of voltage
waveforms output by an ideal VSI should be independent of load connected at the output.]

The simplest dc voltage source for a VSI may be a battery bank, which may consist of several
cells in series-parallel combination. Solar photovoltaic cells can be another dc voltage source.
An ac voltage supply, after rectification into dc will also qualify as a dc voltage source. A
voltage source is called stiff, if the source voltage magnitude does not depend on load connected
to it. All voltage source inverters assume stiff voltage supply at the input.

Some examples where voltage source inverters are used are: uninterruptible power supply (UPS)
units, adjustable speed drives (ASD) for ac motors, electronic frequency changer circuits etc.
Most of us are also familiar with commercially available inverter units used in homes and offices
to power some essential ac loads in case the utility ac supply gets interrupted. In such inverter
units, battery supply is used as the input dc voltage source and the inverter circuit converts the dc
into ac voltage of desired frequency. The achievable magnitude of ac voltage is limited by the
magnitude of input (dc bus) voltage. In ordinary household inverters the battery voltage may be
just 12 volts and the inverter circuit may be capable of supplying ac voltage of around 10 volts
(rms) only. In such cases the inverter output voltage is stepped up using a transformer to meet the
load requirement of, say, 230 volts.

33.1 How to Get AC Output From DC Input Supply?

Figs. 33.1(a) and 33.1(b) show two schematic circuits, using transistor-switches, for generation
of ac voltage from dc input supply. In both the circuits, the transistors work in common emitter
configuration and are interconnected in push-pull manner. In order to have a single control signal
Version 2 EE IIT, Kharagpur 3
Introduction to VSI
for the transistor switches, one transistor is of n-p-n type and the other of p-n-p type and their
emitters and bases are shorted as shown in the figures. Both circuits require a symmetrical
bipolar dc supply. Collector of n-p-n transistor is connected to positive dc supply (+E) and that
of p-n-p transistor is connected to negative dc supply of same magnitude (-E). Load, which has
been assumed resistive, is connected between the emitter shorting point and the power supply
ground.

In Fig. 33.1(a), the transistors work in active (amplifier) mode and a sinusoidal control voltage of
desired frequency is applied between the base and emitter points. When applied base signal is
positive, the p-n-p transistor is reverse biased and the n-p-n transistor conducts the load current.
Similarly for negative base voltage the p-n-p transistor conducts while n-p-n transistor remains
reverse biased. A suitable resistor in series with the base signal will limit the base current and
keep it sinusoidal provided the applied (sinusoidal) base signal magnitude is much higher than
the base to emitter conduction-voltage drop. Under the assumption of constant gain (h
fe
) of the
transistor over its working range, the load current can be seen to follow the applied base signal.
Fig. 33.2(a) shows a typical load voltage (in blue color) and base signal (green color) waveforms.
This particular figure also shows the switch power loss for n-p-n transistor (in brown color). The
other transistor will also be dissipating identical power during its conduction. The quantities in
Fig. 33.2(a) are in per unit magnitudes where the base values are input supply voltage (E) and the
load resistance (R). Accordingly the base magnitudes of current and power are E/R and E
2
/R
respectively. As can be seen, the power loss in switches is a considerable portion of circuits
input power and hence such circuits are unacceptable for large output power applications.

As against the amplifier circuit of Fig. 33.1(a), the circuit of Fig. 33.1(b) works in switched
mode. The conducting switch remains fully on having negligible on-state voltage drop and the
non-conducting switch remains fully off allowing no leakage current through it. The load voltage
waveform output by switched-mode circuit of Fig. 33.1(b) is rectangular with magnitude +E
when the n-p-n transistor is on and E when p-n-p transistor is on. Fig. 33.2(b) shows one such
waveform (in pink color). The on and off durations of the two transistors are controlled so that (i)
the resulting rectangular waveform has no dc component (ii) has a fundamental (sinusoidal)
component of desired frequency and magnitude and (iii) the frequencies of unwanted harmonic
voltages are much higher than that of the fundamental component. The fundamental sine wave in
Fig. 33.2(b), shown in blue color, is identical to the sinusoidal output voltage of Fig. 33.2(a).

Both amplifier mode and switched mode circuits of Figs. 33.1(a) and 33.1(b) are capable of
producing ac voltages of controllable magnitude and frequency, however, the amplifier circuit is
not acceptable in power-electronic applications due to high switch power loss. On the other
hand, the switched mode circuit generates significant amount of unwanted harmonic voltages
along with the desired fundamental frequency voltage. As will be shown in some later lessons,
the frequency spectrum of these unwanted harmonics can be shifted towards high frequency by
adopting proper switching pattern. These high frequency voltage harmonics can easily be
blocked using small size filter and the resulting quality of load voltage can be made acceptable.


- E
+E
LOAD (R)
S
Fig. 33.1 (a): A push-pull
active amplifier circuit
- E
+E
LOAD (R)
S
Fig. 33.1 (b): A push-pull
switched mode circuit
*
*


The magnitude, phase and frequency of the fundamental voltage waveform in Fig. 33.2(b) is
solely determined by the magnitude of supply voltage and the switching pattern of the push-pull
circuit shown in Fig. 33.1(b). Thus, as long as the transistors work in the switch-mode (fully on
or fully off), the output voltage is essentially load-independent.

33.2 What If The Load Is Not Resistive?

Circuit of Fig. 33.1(b) will not be able to output proper voltage waveform for a non-resistive load
for the reasons mentioned below.

Transistors used in the circuit of Fig. 33.1(b) are meant to carry only unidirectional current (from
collector to emitter) and thus if the upper (n-p-n) transistor is on, the current must enter the star
(*) marked terminal of the load and this same terminal will get connected to the positive dc
supply (+E), other load terminal being at ground potential. When n-p-n transistor turns off and p-
n-p type turns on, the load voltage and current polarities reverse simultaneously (p-n-p transistor
can only carry current coming out of star marked end of load). Such one to one matching
between the instantaneous polarities of load voltage and load current can be achieved only in
purely resistive loads. For a general load the instantaneous current polarity may be different from
instantaneous load-voltage polarity. As pointed out in section 33.1, the inverter switching-pattern
fixes the output waveform irrespective of the load. Thus the magnitude, phase and frequency of
the fundamental voltage output by a VSI is independent of the nature of load. Thus it turns out
that for a non-resistive load the switches in the circuit of Fig. 33.1(b) should be able to carry bi-
directional current and at the same time be controllable. [A mechanical switch realized using
an electromagnetic contactor is one example of the bi-directional current carrying
controllable switch. However electromagnetic contactors are not capable of operating at
high frequency, in the range of kilohertz, and may not be suitable for present application.]
If an anti-parallel diode is connected across each transistor switch, as shown in Fig. 33.3(a), the
combination can conduct a bi-directional current. Now the transistor in anti-parallel with the
diode may be considered as a single switch. [A major difference exists between this bi-
directional electronic switch and a bi-directional current carrying mechanical switch. The
mechanical switch can be subjected to bi-directional voltage. When off, the mechanical
switch can block both positive and negative voltage across its terminals. The electronic
switch of Fig. 33.3(a) can block only one polarity of voltage, the one that keeps the diode
reverse biased. Under this polarity of voltage the switch can remain off as long as the base
(or the gate) terminal is not given the turn-on signal. When applied voltage polarity is
reversed the diode starts conducting and so the switch is not able to block the flow of
reverse current.] In spite of unidirectional voltage blocking capability, the new electronic
switch (similar to the one shown in Fig. 33.3(a)) suffices for the inverter application as pointed
out in the following paragraphs.

The push-pull circuit operation is now revisited using bi-directional current carrying switches.
The modified circuit is shown in Fig. 33.3(b). It may be noted that both IGBT and BJ T type
transistors, when bypassed by anti-parallel diode, qualify as bi-directional current carrying
switches. However, IGBT switch is controlled by gate voltage whereas the BJ T


+E
Gate
(control)
Input /
Output
Input /
Output
Control
Analogous to
Fig. 33.3(a): Bi-directional controlled
switch
- E
LOAD
S
Fig. 33.3 (b): Modified push-pull circuit
*
+
_
D
1
D
2
Q
2
Q
1
SW
1
SW
2
switch is controlled using base current. [IGBT switches are easier to use, are much faster and
are available in higher voltage and current ratings. As a result BJT switches are becoming
obsolete.] In the circuit of Fig. 33.3(b), n-p-n transistor (Q
1
) together with diode (D
1
) constitutes
the upper switch (SW
1
). Similarly lower switch (SW
2
) consists of p-n-p transistor (Q
2
) in anti-
parallel with diode (D
2
). By applying positive base-to-emitter voltage of suitable magnitude to
transistor Q
1
, the upper switch is turned on. Once the upper switch (diode D
1
or transistor
Q
1
) is conducting star end of load is at +E potential and diode D
2
of lower switch gets
reverse biased. Transistor Q
2
is also reverse biased due to application of positive base voltage
to the transistors. Thus while switch SW
1
is conducting current, switch SW
2
is off and is
blocking voltage of magnitude 2E. Similarly when applied base voltage to the transistors is
made negative, Q
1
is reverse biased and Q
2
is forward biased. This results in SW
1
turning
off and SW
2
turning on. Now SW
1
blocks a voltage of magnitude 2E.

It may be interesting to see how diodes follow the switching command given to the transistor
part of the switches. To illustrate this point some details of circuit operation with an inductive
load, consisting of a resistor and an inductor in series, is considered. As is well known, current
through such loads cannot change abruptly. The electrical inertial time constant of the load,
given by its L (inductance) / R (resistance) ratio, may in general be large compared to the chosen
switching time period of the transistor switches. Thus the transistors Q
1
and Q
2
may turn-on
and turn-off several times before the load current direction changes. Let us consider the time
instant when instantaneous load current is entering the star end of the load in Fig. 33.3(b). Now
with the assumed load current direction when Q
1
is given turn-on signal current flows from
positive dc supply, through transistor Q
1
, to load. Next, when Q
1
is turned-off and Q
2
is
turned on (but load current direction remaining unchanged) the load current finds its path
through diode of lower switch (D
2
). Whether D
2
or Q
2
conducts, voltage drop across SW
2
is
virtually zero and it can be considered as a closed or a fully-on switch. In the following
switching cycle when Q
1
is turned on again (load current direction still unchanged) the load
current path reverts back from D
2
to Q
1
. It may not be difficult to see how this happens.
While current flowed through D
2
the load circuit got connected to negative emf (-E) of the
supply. When Q
1
conducts the positive (+E) emf supports the load current. The natural choice
for load current is to move from D
2
to Q
1
. In fact turning on of Q
1
will make D
2
reverse
biased. The reader may repeat a similar exercise when the instantaneous load current comes out
of the star end of load. Thus it will be evident that diodes do not need a separate command to
turn on and off. Irrespective of the load current direction, turning on of Q
1
makes SW
1
on and
similarly turning off of Q
1
(with simultaneous turn-on of Q
2
) makes SW
2
on. Q
1
and Q
2

are turned on in a complementary manner. It may not be difficult to see that the circuit of Fig.
33.3(b) will work satisfactorily for a purely resistive load and a series connected resistor-
capacitor load too.

The push-pull circuit of Fig. 33.3(b) has some technical demerits that have been discussed
below.

First, it needs a bipolar dc supply with identical magnitudes of positive and negative supply
voltages. For practical reasons it would have been simpler if only one (uni-polar) dc source was
required. In fact some circuit topologies realize a bi-polar dc supply by splitting the single dc
voltage-source through capacitive potential divider arrangement. [A resistive potential divider
will be terribly inefficient.] Two identical capacitors of large magnitude are put across the dc
supply and the junction point of the capacitors is used as the neutral (ground) point of the bi-
polar dc supply. Fig. 33.3(c) shows one such circuit where a single dc supply has been split in
two halves. In such circuits the voltages across the two capacitors may not remain exactly
balanced due to mismatch in the loading patterns or mismatch in leakage currents of the
individual capacitors. Also, unless the capacitors are of very large magnitude, there may be
significant ripple in the capacitor voltages, especially at low switching frequencies. The
requirement of splitting a single dc source is eliminated if a full bridge circuit, as mentioned in
the next section, is used.

The second demerit of the push-pull circuit shown in Fig. 33.3(b) is the requirement of two
different kinds of transistors, one n-p-n type and the other p-n-p type. The switching speeds of n-
p-n and p-n-p transistors are widely different unless they are produced carefully as matched
pairs. In power electronic applications, n-p-n transistors are preferred as they can operate at
higher switching frequencies. Similarly n-channel MOSFETs and IGBTs are preferred over their
p-channel counterparts. The difficulty in using two n-p-n transistors in the above discussed push-
pull circuit is that they can no longer have a common base and a common emitter point and thus
it wont be possible to have a single base drive signal for controlling both of them. The base
signals for the individual transistors will then need to be separate and isolated from each other.
The difficulty in providing isolated base signals for the two transistors is, often, more than
compensated by the improved capability of the circuit that uses both n-p-n transistors or n-
channel IGBTs. The circuit in Fig. 33.3(c) shows identical transistors (n-channel IGBTs) for both
upper and lower switches. The gate drive signals of the two transistors (IGBTs) now need to be
different and isolated as the two emitter points are at different potentials. The circuit in Fig.
33.3(c) is better known as a half bridge inverter.


Fig. 33.3(c): Topology of a 1-phase half bridge VSI
E
dc
Q
1
Q
2
D
1
D
2
A
0.5E
dc
0.5E
dc
+
_
+
_
+
_
LOAD O
P
N

33.3 General Structure of Voltage Source Inverters

Figs. 33.4 (a) and 33.4(b) show the typical power-circuit topologies of a single-phase and a
three-phase voltage source inverter respectively. These topologies require only a single dc
source and for medium output power applications the preferred devices are n-channel IGBTs.
E
dc
is the input dc supply and a large dc link capacitor (C
dc
) is put across the supply terminals.
Capacitors and switches are connected to dc bus using short leads to minimize the stray
inductance between the capacitor and the inverter switches. Needless to say that physical layout
of positive and negative bus lines is also important to limit stray inductances. Q
1
, Q
2
, Q
3
etc. are
fast and controllable switches. D
1
, D
2
, D
3
etc. are fast recovery diodes connected in anti-parallel
with the switches. A, B and C are output terminals of the inverter that get connected to the
ac load. A three-phase inverter has three load-phase terminals whereas a single-phase inverter
has only one pair of load terminals.

The current supplied by the dc bus to the inverter switches is referred as dc link current and has
been shown as i
dc
in Figs 33.4(a) and 33.4(b). The magnitude of dc link current often changes
in step (and some times its direction also changes) as the inverter switches are turned on and off.
The step change in instantaneous dc link current occurs even if the ac load at the inverter output
is drawing steady power. However, average magnitude of the dc link current remains positive if
net power-flow is from dc bus to ac load. The net power-flow direction reverses if the ac load
connected to the inverter is regenerating. Under regeneration, the mean magnitude of dc link
current is negative. [The dc link current may conceptually be decomposed into its dc and ac
components. The individual roles of the dc voltage source and the dc link capacitor may
be clearly seen with respect to the dc and ac components of the dc link current. For the dc
component of current the capacitor acts like open circuit. As expected, under steady state,
the capacitor does not supply any dc current. The dc part of bus current is supplied solely
by the dc source. A practical dc voltage source may have some resistance as well as some
inductance in series with its internal emf. For dc component of bus current, the source
voltage appears in series with its internal resistance (effect of source inductance is not felt).
But for ac component of current, the internal dc emf of source appears as short and its
series impedance (resistance in series with inductance) appears in parallel with the dc-link
capacitor. Thus the ac component of current gets divided into these two parallel paths.
However, the high frequency component of ac current mainly flows through the capacitor,
as the capacitive impedance is lower at high frequencies. The step change in dc link current
is associated with significant amount of high frequency components of current that
essentially finds its path through the capacitor.]

For an ideal input (dc) supply, with no series impedance, the dc link capacitor does not have any
role. However a practical voltage supply may have considerable amount of output impedance.
The supply line impedance, if not bypassed by a sufficiently large dc link capacitor, may cause
considerable voltage spike at the dc bus during inverter operation. This may result in
deterioration of output voltage quality, it may also cause malfunction of the inverter switches as
the bus voltage appears across the non-conducting switches of the inverter. Also, in the absence
of dc link capacitor, the series inductance of the supply line will prevent quick build up or fall of
current through it and the circuit behaves differently from the ideal VSI where the dc voltage
supply is supposed to allow rise and fall in current as per the demand of the inverter circuit.

[It may not be possible to reduce supply line inductance below certain limit. Most dc
supplies will inherently have rather significant series inductance, for example a
conventional dc generator will have considerable armature inductance in series with the
armature emf. Similarly, if the dc supply is derived after rectifying ac voltage, the ac
supply line inductance will prevent quick change in rectifier output current. The effect of
ac line inductance is reflected on the dc side as well, unless this inductance is effectively
bypassed by the dc side capacitor. Even the connecting leads from the dc source to the
inverter dc bus may contribute significantly to the supply line inductance in case the lead
lengths are large and circuit lay out is poor. It may be mentioned here that an inductance,
in series with the dc supply, may at times be welcome. The reason being that for some types
of dc sources, like batteries, it is detrimental to carry high frequency ripple current. For
such cases it is advantageous if the dc source has some series inductance. Due to series
inductance of the source, the high frequency ripple will prefer to flow through the dc link
capacitor and thus relieve the dc source.]

The dc link capacitor should be put very close to the switches so that it provides a low
impedance path to the high frequency component of the switch currents. The capacitor itself
must be of good quality with very low equivalent series resistor (ESR) and equivalent series
inductor (ESL). The length of leads that interconnect switches and diodes to the dc bus must also
be minimum to avoid insertion of significant amount of stray inductances in the circuit. The
overall layout of the power circuit has a significant effect over the performance of the inverter
circuit.


LOAD
E
dc
C
dc
_
+
Q
1
D
1
Q
2
D
2
Q
3
Q
4
D
3
D
4
Fig. 33.4(a): Topology of a 1-phase VSI
E
dc
C
dc
_
+
Q
1
D
1
Q
2
D
2
Q
3
Q
4
D
3
D
4
Fig. 33.4(b): Topology of a 3-phase VSI
Q
5
Q
6
D
5
D
6
C B A
A B
i
dc
i
dc

[One of the thumb rules for good circuit layout is to put the conductor pairs carrying same
magnitude but opposite direction of currents close by, the minimum distance between them
being decided only by their voltage isolation requirement. Thus the positive and negative
terminals of the dc bus should run close by. A twisted wire pair may be an example of two
closely running wires.]
The details of the inverter circuits shown in Figs. 33.4(a) and 33.4(b) are discussed in later
lessons. However it may be mentioned here that these circuits are essentially extension of the
half bridge circuit shown in Fig. 33.3(c). For example, the single-phase bridge circuit of Fig.
33.4(a) may be thought of as two half-bridge circuits sharing the same dc bus. Thus the single
phase full-bridge (often, simply called as bridge) circuit has two legs of switches, each leg
consisting of an upper switch and a lower switch. J unction point of the upper and lower switches
is the output point of that particular leg. Voltage between output point of legs and the mid-
potential of the dc bus is called as pole voltage referred to the mid potential of the dc bus. One
may think of pole voltage referred to negative bus or referred to positive bus too but unless
otherwise mentioned pole voltages are assumed to be referred to the mid-potential of the dc bus.
The two pole voltages of the single-phase bridge inverter generally have same magnitude and
frequency but their phases are 180
0
apart. Thus the load connected between these two pole
outputs (between points A and B) will have a voltage equal to twice the magnitude of the
individual pole voltage. The pole voltages of the 3-phase inverter bridge, shown in Fig. 33.4(b),
are phase apart by 120
0
each.

33.4 Need For Isolated Gate-Control Signals For The Switches

As already mentioned the switches in bridge configurations of inverters, as in Figs. 33.3(c),
33.4(a) and 33.4(b), need to be provided with isolated gate (or base) drive signals. The individual
control signal for the switches needs to be provided across the gate (base) and source (or emitter)
terminals of the particular switch. The gate control signals are low voltage signals referred to the
source (emitter) terminal of the switch. For n-channel IGBT and MOSFET switches, when gate
to source voltage is more than threshold voltage for turn-on, the switch turns on and when it is
less than threshold voltage the switch turns off. The threshold voltage is generally of the order of
+5 volts but for quicker switching the turn-on gate voltage magnitude is kept around +15 volts
where as turn-off gate voltage is zero or little negative (around 5 volts). It is to be remembered
that the two switches of an inverter-leg are controlled in a complementary manner. When the
upper switch of any leg is on, the corresponding lower switch remains off and vice-versa.
When a switch is on its emitter and collector terminals are virtually shorted. Thus with upper
switch on, the emitter of the upper switch is at positive dc bus potential. Similarly with lower
switch on, the emitter of upper switch of that leg is virtually at the negative dc bus potential.
Emitters of all the lower switches are solidly connected to the negative line of the dc bus. Since
gate control signals are applied with respect to the emitter terminals of the switches, the gate
voltages of all the upper switches must be floating with respect to the dc bus line potentials. This
calls for isolation between the gate control signals of upper switches and between upper and
lower switches. Only the emitters of lower switches of all the legs are at the same potential (since
all of them are solidly connected to the negative dc bus) and hence the gate control signals of
lower switches need not be isolated among themselves. As should be clear from the above
discussion, the isolation provided between upper and lower switches must withstand a peak
voltage stress equal to dc bus voltage. Gate-signal isolation for inverter switches is generally
achieved by means of optical-isolator (opto-isolator) circuits. Fig.33.5 shows a typical opto-
isolator circuit. The circuit makes use of a commercially available opto-coupler IC, shown within
dotted lines in the figure. Input stage of the IC is a light emitting diode (LED) that emits light
when forward biased. The light output of the LED falls on reverse biased junction of an optical
diode. The LED and the photo-diode are suitably positioned inside the opto-coupler chip to
ensure that the light emitted by the LED falls on the photo-diode junction. The gate control
pulses for the switch are applied to the input LED through a current limiting resistor of
appropriate magnitude. These gate pulses, generated by the gate logic circuit, are essentially in
the digital form. A high level of the gate signal may be taken as on command and a low level
(at ground level) may be taken as off command. Under this assumption, the cathode of the LED
is connected to the ground point of the gate-logic card and anode is fed with the logic card
output. The circuit on the output (photo-diode) side is connected to a floating dc power supply,
as shown in Fig. 33.5. The control (logic card) supply ground is isolated from the floating-supply
ground of the output. In the figure the two grounds have been shown by two different symbols.
The schematic connection shown in the figure indicates that the photo-diode is reverse biased. A
resistor in series with the diode indicates the magnitude of the reverse leakage current of the
diode. When input signal to LED is high, LED conducts and the emitted light falls on the reverse
biased p-n junction. Irradiation of light causes generation of significant number of electron-hole
pairs in the depletion region of the reverse biased diode. As a result magnitude of reverse leakage
current of the diode increases appreciably. The resistor connected in series with the photo-diode
now has higher voltage drop due to the increased leakage current. A signal comparator circuit
senses this condition and outputs a high level signal, which is amplified before being output.
Thus an isolated and amplified gate signal is obtained and may directly be connected to the gate
terminal of the switch (often a small series resistor, as suggested by the switch manufacturer, is
put between the output signal and the gate terminal of the switch).


Signal
comparator and
power amplifier
circuit
+V
CC
(floating)
Output
Floating
Ground
Control
Ground
Fig.33.5: A schematic opto-isolator circuit
Photo-diode
L
E
D

33.5 Classification of Voltage Source Inverters

Voltage source inverters can be classified according to different criterions. They can be classified
according to number of phases they output. Accordingly there are single-phase or three-phase
inverters depending on whether they output single or three-phase voltages. It is also possible to
have inverters with two or five or any other number of output phases. Inverters can also be
classified according to their ability in controlling the magnitude of output parameters like,
frequency, voltage, harmonic content etc. Some inverters can output only fixed magnitude
(though variable frequency) voltages whereas some others are capable of both variable voltage,
variable frequency (VVVF) output. Output of some voltage source inverters is corrupted by
significant amount of many low order harmonics like 3
rd
,

5
th
, 7
th
, 11
th
, 13
th
order of the desired
(fundamental) frequency voltage. Some other inverters may be free from low order harmonics
but may still be corrupted by some high order harmonics. Inverters used for ac motor drive
applications are expected to have less of low order harmonics in the output voltage waveform,
even if it is at the cost of increased high order harmonics. Higher order harmonic voltage
distortions are, in most ac motor loads, filtered away by the inductive nature of the load itself.

Inverters may also be classified according to their topologies. Some inverter topologies are
suitable for low and medium voltage ratings whereas some others are more suitable for higher
voltage applications. The inverters shown in Figs. 33.3(c), 33.4(a) and 33.4(b) are two level
inverters as the pole voltages may acquire either positive dc bus or negative dc bus potential. For
higher voltage applications it may not be uncommon to have three level or five level inverters.

Quiz Problems

1. A large capacitor, put across dc bus of a voltage source inverter, is intended to:
(a) allow a low impedance path to the high frequency component of dc link current.
(b) to minimize high frequency current ripple through the ideal dc source.
(c) to maintain a constant dc link current.
(d) to protect against switch failure.
2. A diode in anti-parallel with the controlled switch, like IGBT, is used in VSI to:
(a) prevent reversal of dc link current.
(b) allow a non-unity power factor load at the output.
(c) protect the circuit against accidental reversal of dc bus polarity.
(d) none of the above.
3. The inverter switches work in fully-on or fully-off mode to achieve:
(a) easier gate control circuit for the switching devices.
(b) minimum distortion in the output voltage waveform.
(c) reduced losses in the switches.
(d) satisfactory operation for non-resistive load at the output.
4. Gate (base) signals to the VSI switches, using n-channel IGBTs, need to be isolated to
allow:
(a) protection of switches against short at the inverter output terminals.
(b) switches to be connected in bridge fashion.
(c) lower losses in the gate drive circuit.
(d) a dc link voltage higher than the switch voltage rating.

(Answers to the quiz problems: 1-a, 2-b, 3-c, 4-b)
(i) Explain the operating principle of a single-phase square wave inverter.
(ii) Compare the performance of single-phase half-bridge and full-bridge inverters.
(iii) Do harmonic analysis of load voltage and load current output by a single-phase
inverter.
(iv) Decide on voltage and current ratings of inverter switches.

Voltage source inverters (VSI) have been introduced in Lesson-33. A single-phase square wave
type voltage source inverter produces square shaped output voltage for a single-phase load. Such
inverters have very simple control logic and the power switches need to operate at much lower
frequencies compared to switches in some other types of inverters, discussed in later lessons. The
first generation inverters, using thyristor switches, were almost invariably square wave inverters
because thyristor switches could be switched on and off only a few hundred times in a second. In
contrast, the present day switches like IGBTs are much faster and used at switching frequencies
of several kilohertz. As pointed out in Lesson-26, single-phase inverters mostly use half bridge
or full bridge topologies. Power circuits of these topologies are redrawn in Figs. 34.1(a) and
34.1(b) for further discussions.

In this lesson, both the above topologies are analyzed under the assumption of ideal circuit
conditions. Accordingly, it is assumed that the input dc voltage (E
dc
) is constant and the switches
are lossless. In half bridge topology the input dc voltage is split in two equal parts through an
ideal and loss-less capacitive potential divider. The half bridge topology consists of one leg (one
pole) of switches whereas the full bridge topology has two such legs. Each leg of the inverter
consists of two series connected electronic switches shown within dotted lines in the figures.
Each of these switches consists of an IGBT type controlled switch across which an uncontrolled
diode is put in anti-parallel manner. These switches are capable of conducting bi-directional
current but they need to block only one polarity of voltage. The junction point of the switches in
each leg of the inverter serves as one output point for the load.

In half bridge topology the single-phase load is connected between the mid-point of the input dc
supply and the junction point of the two switches (in Fig. 34.1(a) these points are marked as O
and A respectively). For ease of understanding, the switches Sw1 and Sw2 may be assumed to
Fig. 34.1(a): A 1-phase half bridge VSI
E
dc
A
0.5E
dc
0.5E
dc
+
_
+
_
+
_
LOAD O
P
N
LOAD
E
dc
C
dc
_
+
Fig. 34.1(b): A 1-phase full-bridge VSI
A B
i
dc
P
N
C

C

Sw1
Sw1
Sw2
Sw3
Sw4
Sw2
Analysis of 1-Phase,Square - Wave Voltage Source
Inverter
be controlled mechanical switches that open and close in response to the switch control signal. In
fact in lesson-33 (section 33.2) it has been shown that the actual electronic switches mimic the
function of the mechanical switches. Now, if the switches Sw1 and Sw2 are turned on alternately
with duty ratio of each switch kept equal to 0.5, the load voltage (V
AO
) will be square wave with
a peak-to-peak magnitude equal to input dc voltage (E
dc
)
.
Fig. 34.2(a) shows a typical load
voltage waveform output by the half bridge inverter. V
AO
acquires a magnitude of +0.5 E
dc
when
Sw1 is on and the magnitude reverses to -0.5 E
dc
when Sw2 is turned on. Fig. 24.2 also shows
the fundamental frequency component of the square wave voltage, its peak-to-peak magnitude
being equal to
4
dc
E
. The two switches of the inverter leg are turned on in a complementary

manner. For a general load, the switches should neither be simultaneously on nor be
simultaneously off. Simultaneous turn-on of both the switches will amount to short circuit across
the dc bus and will cause the switch currents to rise rapidly. For an inductive load, containing an
inductance in series, one of the switches must always conduct to maintain continuity of load
current. In Lesson-33 (section 33.2) a case of inductive load has been considered and it has been
shown that the load current may not change abruptly even though the switching frequency is
very high. Such a situation, as explained in lesson-33, demands that the switches must have bi-
directional current carrying capability.

34.1 Harmonic Analysis of The Load Voltage And Load Current
Waveforms

The load voltage waveform shown in Fig. 34.2(a) can be mathematically described in terms of its
Fouriers components as:

1,3,5,7,...,
2
sin( )
dc
AO
n
E
V
n
=
=

nwt (34.1)
,where n is the harmonic order and
2
w
is the frequency (f) of the square wave. f also

happens to be the switching frequency of the inverter switches. As can be seen from the
expression of Eqn. 34.1, the square wave load voltage consists of all the odd harmonics and their
magnitudes are inversely proportional to their harmonic order. Accordingly, the fundamental
frequency component has a peak magnitude of
2
dc
E
and the nth harmonic voltage (n being odd

integer) has a peak magnitude of
2
dc
E
n
. The magnitudes of very high order harmonic voltages
become negligibly small. In most applications, only the fundamental component in load voltage
is of practical use and the other higher order harmonics are undesirable distortions. Many of the
practical loads are inductive with inherent low pass filter type characteristics. The current
waveforms in such loads have less higher order harmonic distortion than the corresponding
distortion in the square-wave voltage waveform. A simple time domain analysis of the load
current for a series connected R-L load has been presented below to corroborate this fact. Later,
for comparison, frequency domain analysis of the same load current has also been done.

34.1.1 Time Domain Analysis

The time domain analysis of the steady state current waveform for a R-L load has been presented
here. Under steady state the load current waveform in a particular output cycle will repeat in
successive cycles and hence only one square wave period has been considered. Let t=0 be the
instant when the positive half cycle of the square wave starts and let I
0
be the load current at this
instant. The negative half cycle of square wave starts at t=0.5T and extends up to T. The circuit
equation valid during the positive half cycle of voltage can be written as below:
0.5
dc
di
Ri L E
dt
+ = , for 0 <t <0.5T ...(34.2)

Similarly the equation for the negative half cycle can be written as
0.5
dc
di
Ri L E
dt
+ = , for 0.5T <t <T .(34.3)
, where T (=1/f) is the time period of the square wave.

The instantaneous current i during the first half of square wave may be obtained by solving
Eqn.(34.2) and putting the initial value of current as I
0
.
Accordingly,
0
0.5
( ) (1 )
dc
t t
E
i t e I e
R

= + for 0 <t <0.5T ..(34.4)
, where =L/R is the time constant of the R-L load.

The current at the end of the positive half cycle becomes the starting current for the negative half
cycle.
Thus the next half cycle starts with an initial current =
0
0.5
2 2
(1 )
dc
T T
E
e I e
R

+ . The
circuit equation for the next half cycle may now be written as

0
( ) ( )
2 2
0.5 0.5
2 2
( ) (1 ) (1 )
dc dc
T T
t t
T T
E E
i t e e I e e
R R

= + +

for 0.5T <t<T

Simplifying the above equation one gets:
0
( )
2
0.5
( ) (1 )
dc dc
T
t
t t
E E
i t e I e e
R R

= + + +

, for 0.5T <t <T .(34.5)

Under steady state, the instantaneous magnitude of inductive load current at the end of a periodic
cycle must equal the current at the start of the cycle. Thus putting t=T in Eqn. (34.5), one gets the
expression for I
0
as,
0 0
0.5
2
(1 )
dc dc
T T
E E
I e I e
R R
T
e

= + + +
or,
0
0.5
2
1 (1 )
dc dc
T T
E E
I e e e
R R

= +

1
T

or,
0
2
0.5 0.5 1 1
2 2
1 1
dc dc dc
T
E E E e
I
T
R R R
e e
T

= =

+ +

.(34.6)
Substituting the above expression for I
0
in Eqn. (34.4) one gets,

2
0.5 1 2
( )
2
1
dc
t T
E e e
i t
T
R
e

+
=

+

, for 0 <t <0.5T ....(34.7)

It may be noted from Eqn. (34.7) that the load current at the end of the positive half cycle of
square wave (at t=0.5T) simply turns out to be I
0
. This is expected from the symmetry of the
load voltage waveform. Load current expression for the negative half cycle of square wave can
similarly be calculated by substituting for I
0
in Eqn. (34.5). Accordingly,

( )
2
0.5
( )
2
1
dc dc
T
t
E E e
i t
T R R
e
= +

, for 0.5T <t <T

or,
( )
2
2
0.5 1 2
( )
2
1
dc
T
t
T
E e e
i t
T
R
e

, for 0.5T <t <T ............... (34.8)

The current expressions given by Eqns. (34.7) and (34.8) have been plotted in Figs. 34.2(b) to
34.2(e) for different time constants of the R-L load. The current waveforms have been
normalized against a base current of 0.5
dc
E
R
. The square wave voltage waveform, normalized
against a base voltage of has also been plotted together with the current waveforms. It can
be seen that the load current waveform repeats at fundamental frequency and the higher order
harmonic distortions reduce as the load becomes more inductive. For L/R ratio of 2, the 3
0.5
dc
E
rd
order
harmonic distortion in the load current together with its fundamental component has been shown
in Fig. 34.2(e). In this case, it can be seen that the relative harmonic distortion in load current
waveform is much lower than that of the voltage waveform shown in Fig. 34.2(a). The basis for
calculating the magnitude of different harmonic components of load current waveform has been
shown in the next subsection that deals with frequency domain analysis.

34.1.2 Frequency Domain Analysis

The square shape load voltage may be taken as superposition of different harmonic voltages
described by Eqn. 34.1. The load current may similarly be taken as superposition of harmonic
currents produced by the different harmonic voltages. The load current may be expressed in
terms of these harmonic currents. To illustrate this the series connected R-L load has once again
been considered here. First the expressions for different harmonic components of load current are
calculated in terms of load parameters: R and L/R (or ) and inverter parameters: dc link voltage
(E
dc
) and time period of square wave (T).

For the fundamental harmonic frequency the load impedance (Z
1
) and load power factor angle
(
1
) can be calculated to be

Z
1
=
2 2
2
2
4
(
L
R
T
+ ) and
1
=
1
2
tan
L
TR
..(34.9)

The load impedance and load power factor angle for the n
th
harmonic component (Z
n
and
n
respectively) will similarly be given by,

Z
n
=
2 2 2
2
2
4
( )
n L
R
T
+ and
n
=
1
2
tan
nL
TR
..(34.10)

The fundamental and n
th
harmonic component of load current, (I
load
)
1
and (I
load
)
n
respectively, can
be found to be

(I
load
)
1
=
1
1
2
sin( )
dc
E
wt
Z
and (I
load
)
n
=
2
sin( )
dc
n
n
E
nwt
n Z
(34.11)

The algebraic summation of the individual harmonic components of current will result in the
following expression for load current.

1,3,5,7,...,
2
sin( )
dc
Load n
n n
E
I
n Z
=
=

nwt .(34.12)

From Eqns. 34.10 and 34.12 it may be seen that the contribution to load current from very higher
order harmonics become negligible and hence the infinite series based expression for load
current may be terminated beyond certain values of harmonic order n. For L/R ratio =2T, the
individual harmonic components of load current normalized against a base current of
0.5
dc
E
R
have been calculated below:
(I
load
)
1,normalized
=
1
2
4
sin( tan 4 )
1 16
wt

+
=0.1sin( 1.491) wt
(I
load
)
3,normalized
=
1
2
4
sin(3 tan 12 )
3 1 144
wt

+
=0.011sin(3 1.544) wt
(I
load
)
5,normalized
=
1
2
4
sin(5 tan 20 )
5 1 400
wt

+
=0.004sin(5 1.555) wt
(I
load
)
7,normalized
=
1
2
4
sin(7 tan 28 )
7 1 784
wt

+
=0.002sin(7 1.559) wt
(I
load
)
11,normalized
=
1
2
4
sin(11 tan 44 )
11 1 1936
wt

+
= 0.0008sin(11 1.564) wt

It may be concluded that for L/R =2T, the contribution to load current from 13
th
and higher
order harmonics are less than 1% of the fundamental component and hence they may be
neglected without any significant loss of accuracy.

Fig. 34.2(f) shows the load voltage and algebraic summation of the first five dominant harmonics
(fundamental, 3
rd
, 5
th
, 7
th
and 11
th
) in the load current, the expressions for which have been given
above. In Fig. 34.2(g) the load current waveforms of Fig. 34.2(e) and 34.2(f) have been
superimposed for comparison. It may be seen that the load current waveform of Fig. 34.2(f)
calculated using truncated series of the frequency domain analysis very nearly matches with the
exact waveform of Fig. 34.2(e), calculated using time domain analysis.

34.2 Analysis Of The Single-Phase Full Bridge Inverter

Single-phase half bridge inverter has already been described above. The single-phase full bridge
circuit (Fig. 34.1(b)) can be thought of as two half bridge circuits sharing the same dc bus. The
full bridge circuit will have two pole-voltages (V
AO
and V
BO
), which are similar to the pole
voltage V
AO
of the half bridge circuit. Both V
AO
and V
BO
of the full bridge circuit are square
waves but they will, in general, have some phase difference. Fig. 34.3 shows these pole voltages
staggered in time by t seconds. It may be more convenient to talk in terms of the phase
displacement angle defined as below:
=(2 )
t
T
Radians..(34.13)
, where t is the time by which the two pole voltages are staggered and T is the time period of
the square wave pole voltages.

The pole voltage V
AO
of the full bridge inverter may again be written as in Eqn. 34.1, used
earlier for the half bridge inverter. Taking the phase shift angle into account, the pole-B
voltage may be written as
1,3,5,7,...,
2
sin ( )
dc
BO
n
E
V
n
=
=

n wt (34.14)
Difference of V
AO
and V
BO
gives the line voltage V
AB
. In full bridge inverter the single phase
load is connected between points A and B and the voltage of interest is the load voltage V
AB
.
Taking difference of the voltage expressions given by Eqns. 34.1 and 34.14, one gets
[
1,3,5,7,...,
2
sin sin ( )
dc
AB
n
E
V nwt
n
=
=
]
n wt (34.15)


The fundamental component of V
AB
may be written as
[ ]
,1
2 4
sin sin( ) cos( )sin
2 2
dc dc
AB
E E
V wt wt wt

= = ...(34.16)
The n
th
harmonic component in V
AB
may similarly be written as
[ ]
,
2 4
sin sin ( ) cos ( )sin
2 2
dc dc
AB n
E E n
V nwt n wt n wt
n n

= = .(34.17)

From Eqn. 34.16, the rms magnitude of the fundamental component of load voltage may be
written as
,1
( ) 0.9 sin
2
AB rms dc
V E

= ....(34.18)
The rms magnitude of load voltage can be changed from zero to a peak magnitude of .
The peak load voltage magnitude corresponds to =180 degrees and the load voltage will be
zero for =0
0.9
dc
E
0
. For =180 degrees, the load voltage waveform is once again square wave of
time period T and instantaneous magnitude E.

As the phase shift angle changes from zero to 180
0
the width of voltage pulse in the load voltage
waveform increases. Thus the fundamental voltage magnitude is controlled by pulse-width
modulation.
Also, from Eqns. 34.17 and 34.1 it may be seen that the line voltage distortion due to higher
order harmonics for pulse width modulated waveform (except for =180
0
)

is less than the
corresponding distortion in the square wave pole voltage. In fact, for some values of phase shift
angle () many of the harmonic voltage magnitudes will drastically reduce or may even get
eliminated from the load voltage. For example, for =60
0
the load voltage will be free from 3
rd

and multiples of third harmonic.

34.3 Voltage And Current Ratings Of Inverter Switches

Switches in each leg of the inverter operate in a complementary manner. When upper switch of a
leg is on the lower switch will need to block the entire dc bus voltage and vice versa. Thus the
switches must be rated to block the worst-case instantaneous magnitude of dc bus voltage. In
practical inverters the switch voltage ratings are taken to be somewhat higher than the worst-case
dc voltage to account for stray voltages produced across stray inductances, the turn-on transient
voltage of a power diode etc. For a well laid out circuit a 50% margin over the dc-bus voltage
may be the optimum switch voltage rating. Each switch of the inverter carries load current during
half of the current cycle. Hence the switches must be rated to withstand the peak magnitude of
instantaneous load current. The semiconductor switches have very small thermal time constant
and they cannot withstand overheating for more than a few milli seconds. Thus even though the
load current passes through the switches only in alternate half cycles, the thermal limit may be
reached during half cycle of current itself. It may be pointed out that each inverter switch
consists of a controlled switch in anti-parallel with a diode. The distribution of current between
the diode and the controlled switch will depend on the load power factor at the operating
frequency. In general both diode as well as the controlled switch should be rated to carry the
peak load current.

34.4 Applications Of Square Wave Inverter

The square wave voltage-source inverter discussed in this lesson finds application in many low
cost ac motor drives, uninterruptible power supply units and in circuits utilizing electrical
resonance between an inductor and a capacitor. Some examples of circuits utilizing resonance
phenomenon are induction heating units and electronic ballasts for fluorescent lamps.

Quiz Problems

1. A single-phase full bridge inverter with square wave pole voltages is connected to a dc
input voltage of 600 volts. What maximum rms load voltage can be output by the
inverter? How much will be the corresponding rms magnitude of 3
rd
harmonic voltage
(a) Approximately 270 volts of fundamental and 30 volts of 3
rd
harmonic voltage
(b) Approx. 480 volts fundamental and 160 volts of 3
rd
harmonic voltage
(c) Approx. 540 volts fundamental and 180 volts of 3
rd
harmonic voltage
(d) Approx. 270 volts fundamental and 90 volts of 3
rd
harmonic voltage
2. How does the output power handling capacity of a single-phase half bridge inverter
compare with that of a single-phase full bridge inverter when they are connected to same
dc bus voltage and the peak current capability of the inverter switches is also same. Also
compare their costs.
(a) The half bridge inverter can output double power but cost also doubles.
(b) The half bridge inverter can output only half the power but cost is less.
(c) The half bridge inverter can output only half the power but cost is nearly same
(d) The output power capability is same but half bridge inverter costs less.
3. A single-phase full bridge inverter is connected to a purely resistive load. Each inverter
switch consists of an IGBT in anti-parallel with a diode. For this load how does the diode
conduction loss compare with the IGBT conduction loss?
(a) Diode and IGBT will have nearly same conduction loss
(b) Diode conduction loss will be nearly half of the IGBT loss
(c) Diode will have no conduction loss
(d) IGBT will have no conduction loss
4. Using frequency domain analysis estimate the ratio of 5
th
and 7
th
harmonic currents in a
purely inductive load that is connected to the output of a single phase half bridge inverter
with square wave pole voltages.
(a) 5
th
harmonic current will be nearly double of the 7
th
harmonic current
(b) 5
th
harmonic current will be 40% more than the 7
th
harmonic current
(c) 5
th
harmonic current will be zero while 7
th
harmonic current will be present
(d) Both 5
th
and 7
th
harmonic currents will be zero

(Answers to the quiz problems: 1-d, 2-b, 3-c, 4-a)

(i) Explain the operating principle of a three-phase square wave inverter.
(ii) Understand the limitations and advantages of square-wave inverters.
(iii) Do harmonic analysis of load voltage and load current output by the three-phase
sq. wave inverter.

The basic configuration of a Voltage Source Inverter (VSI) has been described in Lesson 33.
Single-phase half-bridge and full-bridge configurations of VSI with square wave pole voltages
have been analyzed in Lesson 34. In this lesson a 3-phase bridge type VSI with square wave pole
voltages has been considered. The output from this inverter is to be fed to a 3-phase balanced
load. Fig. 35.1 shows the power circuit of the three-phase inverter. This circuit may be identified
as three single-phase half-bridge inverter circuits put across the same dc bus. The individual pole
voltages of the 3-phase bridge circuit are identical to the square pole voltages output by single-
phase half bridge or full bridge circuits. The three pole voltages of the 3-phase square wave
inverter are shifted in time by one third of the output time period. These pole voltages along with
some other relevant waveforms have been plotted in Fig. 35.2. The horizontal axis of the
waveforms in Fig. 35.2 has been represented in terms of t, where is the angular frequency
(in radians per second) of the fundamental component of square pole voltage and t stands for
time in second. In Fig. 35.2 the phase sequence of the pole voltages is taken as V
AO
, V
BO
and
V
CO
. The numbering of the switches in Fig. 35.1 has some special significance vis--vis the
output phase sequence.

Fig. 35.1: A 3-phase Voltage Source Inverter (VSI) feeding a balanced load
E
dc
C
dc
_
+
A
i
dc
P
n
B
Sw1
Sw2
Sw3
Sw4
C
Sw5
Sw6
A
B
C
3-phase
balanced load
N

3-Phase Voltage Source Inverter With Square Wave Output

t

To appreciate the particular manner in which the switches have been numbered, the conduction-
pattern of the switches marked in Fig. 35.2 may be noted. It may be seen that with the chosen
numbering the switches turn on in the sequence:- Sw1, Sw2, Sw3, Sw4, Sw5, Sw6, Sw1, Sw2,
.and so on. Identifying the switching cycle time as 360 degrees (2 radians), it can be seen that
each switch conducts for 180
0
and the turning on of the adjacent switch is staggered by 60
degrees. The upper and lower switches of each pole (leg) of the inverter conduct in a
0 /3 2/3 4/3 5/3 2 7/3 8/3 3 10/3
11/3 3
V
AB
V
AN
V
BN
t
t
E
dc
-E
dc
1/3E
dc
2/3E
dc
2/3E
dc
-2/3E
dc
-2/3E
dc
1/3E
dc
-1/3E
dc
-1/3E
dc
0
0
0
aveforms output by a 3-phase square wave VSI Fig. 35.2: Some relevant voltage w
V
AO
V
BO
t
0.5E
dc
- 0.5E
dc
t

- 0.5E
dc
0.5E
dc
0
0
Sw1 Sw1
Sw4 Sw4
Sw3 Sw3
0.5E
dc
t
0
- 0.5E
dc
Sw5
Sw2 Sw2
Sw5
Sw6
Sw6
V
CO
Sw5
Sw6
complementary manner. To reverse the output phase sequence, the switching sequence may
simply be reversed.

Considering the symmetry in the switch conduction pattern, it may be found that at any time
three switches conduct. It could be two from the upper group of switches, which are connected to
positive dc bus, and one from lower group or vice-versa (i.e., one from upper group and two
from lower group). According to the conduction pattern indicated in Fig. 35.2 there are six
combinations of conducting switches during an output cycle:- (Sw5, Sw6, Sw1), (Sw6, Sw1,
Sw2), (Sw1, Sw2, Sw3), (Sw2, Sw3, Sw4), (Sw3, Sw4, Sw5), (Sw4, Sw5, Sw6). Each of these
combinations of switches conducts for 60
0
in the sequence mentioned above to produce output
phase sequence of A, B, C. As will be shown later the fundamental component of the three
output line-voltages will be balanced. The load side phase voltage waveforms turn out to be
somewhat different from the pole voltage waveforms and have been dealt with in the next
section.

35.1 Determination Of Load Phase-Voltages

Fig. 35.1 shows a star connected balanced 3-phase load. The three load terminals are connected
to the three output points (A, B, C) of the inverter. The neutral point N of the load is
deliberately left open for some good reasons mentioned later. The load side phase voltages V
AN
,

V
BN
and V
CN
can be determined from the conduction pattern of the inverter switches. With
reference to Fig. 35.2, it may be seen that for 0t/3, switches Sw5, Sw6 and Sw1 conduct.
Under the assumption of ideal switches Fig. 35.3(a) will represent the equivalent inverter and
load circuit during the time interval 0t/3. In the equivalent circuit representation the non-
conducting switches have been omitted and a cross (X) sign is used to represent a conducting
switch. For a balanced 3-phase load the instantaneous phase voltage waveforms have been
derived below for the following two cases (i) when the 3-phase load is purely resistive and (ii)
when the load, in each phase, consists of a resistor in series with an inductor and a back e.m.f. In
both the cases the equivalent circuit of Fig. 35.3(a) has been referred to derive the expression for
load-phase voltage.

X
Sw6
X
Sw5
E
dc
+
_
N
B
A
C
X
Sw1

V
AN
= 1/3 E
dc
V
BN
= -2/3 E
dc
V
CN
= 1/3 E
dc

Fig. 35.3(a): Schematic load circuit during conduction of Sw5, Sw6 and Sw1

For case (i), when the load is a balance resistive load, it is very easy to see that the instantaneous
phase voltages, for 0t/3, will be given by V
AN
=1/3 E
dc
, V
BN
=-2/3 E
dc
, V
CN
=1/3 E
dc
.

For case (ii), the following circuit relations hold good.

A
AN A A
di
V Ri L E
dt
= + + ,
B
N B
di
i L E
dt
= + +
B B
V R ,
C
CN C C
di
i L E
dt
= + + V R ...(35.1)
AN BN dc
V V E = , ....(35.2)
AN CN
V V =
where, , , are the instantaneous load-phase currents entering phases A, B and C
respectively. , and are the instantaneous magnitudes of load phase-emfs. R and L are
the per-phase load resistance and inductance that are connected in series with the corresponding
phase-emf. Since the load is balanced (with its neutral point floating) the algebraic sum of the
instantaneous phase currents and the phase emfs will be zero. Accordingly,

A
i
B
i
C
i
A
E
B
E
C
E
A
i + + =0 and + + =0(35.3)
B
i
C
i
A
E
B
E
C
E
From Eqns. 35.1 and 35.3, the following may be deduced:
( )
( ) ( ) ( )
A C B
AN CN A C A C B B B
d i i di
V V R i i L E E Ri L E V
dt dt
+
+ = + + + + = + + =
N
.... (35.4)

Now from Eqns. 35.2 and 35.4 it can be easily found that V
AN
=1/3 E
dc
, V
BN
=-2/3 E
dc
, V
CN
=
1/3 E
dc
.

Thus the instantaneous magnitudes of load phase voltages, in case of a more general (but
balanced) R-L-E load are same as in case of a simple balanced resistive load.

Fig. 35.3(b) shows the equivalent circuit during /3t2/3, when the switches Sw6, Sw1 and
Sw2 conduct. The instantaneous load phase voltages may be found to be V
AN
=2/3 E
dc
, V
BN
=
V
CN
=-1/3 E
dc
.

X
E
dc
+
_
X
C
A
B
X
Sw1
Sw2
Sw6
N
V
AN
= 2/3 E
dc
V
BN
= -1/3 E
dc
V
CN
= -1/3 E
dc
Fig. 35.3(b): Schematic load circuit during conduction of Sw6, Sw1 and Sw2

The load phase voltage waveforms for other switching combinations may be found in a similar
manner. Two of the phase voltages,V and V , along with line voltage V have been plotted
over two output cycles in Fig. 35.2. It may be seen that voltage V is similar to V but lags it
by one third of the output cycle period. Further, it can be verified that the load phase voltage V
also has a waveform identical to the two other phase voltages but time displaced by one third of
the output time period. V waveform leads V by 120 degrees in the time (t) frame. It
should be obvious that the fundamental component of the phase voltage waveforms will
constitute a balanced 3-phase voltage having a phase sequence A, B, C. It may also be recalled
that by suitably changing the switching sequence the output phase sequence can be changed. The
phase voltage waveforms of Fig. 35.2 show six steps per output cycle and are also referred as the
AN BN AB
BN AN
CN
CN AN
six-stepped waveform. A more detailed analysis of the load voltage waveforms is done in the
following section.

35.2 Harmonic Analysis Of Load Voltage Waveforms

The individual pole voltage waveforms output by the 3-phase square wave inverter are identical
to the output waveform of a single-phase half bridge inverter. As a consequence, the harmonic
analysis of the voltage waveform presented in section 34.1 of Lesson 34 is valid here too. The
expression for line voltage V
AB
is identical to the one given in Lesson 34 (Eqn.34.15), with
of Eqn. 34.15 replaced by 2/3 radians. For convenience the expressions for pole-A voltage
and line voltage are reproduced below in Eqns.35.5 and 35.6. The relevant
waveforms are shown in Fig.35.2.
AO
V
AB
V

1,3,5,7,...,
2
sin( )
dc
AO
n
E
V
n
=
=

nwt .....(35.5)

1,3,5,7,...,
2 2
sin sin ( )
3
dc
AB
n
E
V nwt n
n
wt

....(35.6)
Using equations 35.5 and 35.6, the expressions for remaining pole and line voltages can be
written simply by shifting the time (t) origin by the phase shift angle shown in Fig.35.2.
Accordingly the expressions for pole voltage and line voltage are written below in Eqns.
35.7 and 35.8 respectively.
BO
V
BC
V
1,3,5,7,...,
2 2
sin ( )
3
dc
BO
n
E
V
n
n wt

=
=

...(35.7)
1,3,5,7,...,
2 2
sin ( ) sin ( )
3 3
dc
BC
n
E
V n wt n
n
4
wt

=

=

....(35.8)
It may be verified that difference of and leads to the expression for . The
expression for a particular harmonic component in the voltage waveforms is determined simply
by substituting n in above equations by the harmonic order. Accordingly the fundamental
magnitude of line voltages , and can be written as:
AO
V
BO
V
AB
V
AB
V
BC
V
CA
V
,1
2 2 3 2
sin sin( ) sin( )
3 6
dc dc
AB
E E
V wt wt wt

= =

+
,1
2 3
sin( )
2
dc
BC
E
V wt

= ,
,1
2 3 7
sin( )
6
dc
CA
E
t V w

=
The three fundamental line voltages are balanced (have identical magnitudes and are phase apart
by 120
0
). For most practical loads only the fundamental component of the inverter output voltage
is of interest. However the inverter output also contains significant amount of higher order
harmonic voltages that cause undesirable distortion of the output waveform. It may, though, be
noted that there are no even harmonics and the line voltages are free from 3
rd
and multiples of 3
rd

order harmonics. Also, as the harmonic order (n) increases their magnitudes decrease inversely
with the harmonic order. When expressed as a fraction of fundamental voltage magnitude, the
line voltage distortions are mainly due to 20% of 5
th
harmonic, nearly 14% of 7
th
, nearly 9% of
11
th
and nearly 8% of 13
th
harmonic. Since most loads are inductive in nature with a low pass
filter type characteristics the effect of very high order harmonics may be neglected.
It may be noted that though the pole voltages have 3
rd
and multiples of 3
rd
order harmonic
distortions, the line voltages are free from these distortions. Hence the load neutral point, rather
than being connected to the mid-potential point of the input dc supply (as in a single-phase half
bridge inverter), is deliberately left floating. The floating neutral point does not allow a closed
path for the 3
rd
and multiples of 3
rd
harmonic currents to flow (3
rd
or multiples of 3
rd
harmonic
current, if present in the load phases, have identical instantaneous magnitudes in all the three
phases and their algebraic sum needs to flow in or out of the load neutral point). By keeping the
load neutral point floating, not only the need for bringing out the mid-potential point of dc
supply is done away with, the triplen harmonic distortions of the load current is totally
eliminated. Since there are no triplen harmonic currents in the load, the load-phase voltages are
also free from triplen harmonic distortions. In fact the six-stepped load-phase voltages shown in
Fig. 35.2 are found to be free from triplen harmonics. It turns out that by removing all triplen
harmonics from the square-shaped pole voltage waveform one can arrive at the corresponding
load-phase (six-stepped) voltage waveform. Accordingly the load-phase voltages may be
expressed in terms of its harmonic contents as shown below.
1,5,7,11,13...,
2
sin( )
dc
AN
n
E
V
n
=
=

nwt .....(35.9)
1,5,7,11,13...,
2 2
sin ( )
3
dc
BN
n
E
V
n
n wt

=
=

...(35.10)

1,5,7,11,13...,
2 2
sin ( )
3
dc
CN
n
E
V
n
n wt

=
=

+ ...(35.11)

For a balanced three-phase load, the instantaneous magnitude of any phase current can be
determined by superposition of different harmonic currents of the phase. For a simple three-
phase R-L load, the phase-A current ( ) expression in terms of resistance (R) and inductance
(L) of the load may be written as:
A
i

1
2 2 2 2
1,5,7,11,13...,
2
sin[ tan ( )]
dc
A
n
E n L
i n
R
n R n L

=
=
+
wt .....(35.12)

Phase-B and phase-C current expressions can be obtained simply by replacing t in Eqn. 35.12
by
2
( )
3
t

and
2
(
3
t )
+ respectively. A close look at Eqn. 35.12 will reveal that for a

purely inductive 3-phase load the 5
th
, 7
th
, 11
th
and 13
th
harmonic distortion in the load current (as
a percentage of fundamental component of current) will respectively be 4%, 2.04%, 0.83% and
0.59%. These distortions are much less than the corresponding distortions in the load voltage
waveforms. As a result the load current for highly inductive R-L load will have close to
sinusoidal shape.

35.3 Voltage And Current Ratings Of Inverter Switches

As in a single-phase square-wave inverter, switches in each leg of the three-phase inverter
operate in a complementary manner. When upper switch of a leg is on the lower switch will need
to block the entire dc bus voltage and vice versa. Thus the switches must be rated to block the
worst-case instantaneous magnitude of dc bus voltage. An extra safety margin over the worst-
case dc voltage, as discussed in Lesson-34, section 34.3, is recommended. Each inverter-switch
carries load-phase current during half of the current cycle. Hence the switches must be rated to
withstand the peak expected magnitude of instantaneous load-phase current. For a non-unity
power factor load, the diode connected in anti-parallel with the switch will conduct part of the
switch current. The distribution of current between the diode and the controlled switch will
depend on the load power factor at the operating frequency. In general both diode as well as the
controlled switch should be rated to carry the peak load current. These diodes also need to block
a peak reverse voltage equal to worst case voltage across the switches.

35.4 Use And Limitations Of 3-Phase Square Wave Inverter

The three-phase square wave inverter as described above can be used to generate balanced three-
phase ac voltages of desired (fundamental) frequency. However harmonic voltages of 5th, 7th
and other non-triplen odd multiples of fundamental frequency distort the output voltage. In many
cases such distortions in output voltages may not be tolerable and it may also not be practical to
use filter circuits to filter out the harmonic voltages in a satisfactory manner. In such situations
the inverter discussed in this lesson will not be a suitable choice. Fortunately there are some
other kinds of inverters, namely pulse width modulated (PWM) inverters, discussed in the next
lesson, which can provide higher quality of output voltage.

The square wave inverter discussed in this lesson may still be used for many loads, notably ac
motor type loads. The motor loads are inductive in nature with the inherent quality to suppress
the harmonic currents in the motor. The example of a purely inductive load discussed in the
previous section illustrates the effectiveness of inductive loads in blocking higher order harmonic
currents. In spite of the inherent low-pass filtering property of the motor load, the load current
may still contain some harmonics. These harmonic currents cause extra iron and copper losses in
the motor. They also produce unwanted torque pulsations. Fortunately the torque pulsations due
to harmonic currents are of high frequencies and their effect gets subdued due to the large
mechanical inertia of the drive system. The motor speed hardly changes in response to these
torque pulsations. However in some cases torque pulsations of particular frequencies may cause
unwanted resonance in the mechanical system of the drive. A special notch filter may then be
required to remove these frequencies from the inverter output voltage.

The input dc voltage to the inverter is often derived from an ac source after rectification and
filtering. A simple diode bridge rectifier followed by a filter capacitor is often the most cost-
effective method to get dc voltage from ac supply. In some applications, like in un-interrupted
power supplies, the dc input may be coming from a bank of batteries. In both these examples, the
input dc magnitude is fairly constant. With fixed input dc voltage the square-wave inverter can
output only fixed magnitude of load voltage. This does not suit the requirement in many cases
where the load requires a variable voltage variable frequency (VVVF) supply. In order that ac
output voltage magnitude is controllable, the inverter input voltage will need to be varied using
an additional dc-to-dc converter. However a better solution will be to use a PWM inverter (to be
discussed in the next lesson), which can provide a VVVF output with enhanced output voltage
quality.

In spite of the limitations, discussed above, the square wave inverter may be a preferred choice
on account of its simplicity and low cost. The switch control circuit is very simple and the
switching frequency is significantly lower than in PWM inverters. This results in low switching
losses. The switch cost may also be lower as one may do away with slower switching devices
and slightly lower rated switches. Another advantage over PWM inverter is its ability to output
higher magnitude of fundamental voltage than the maximum that can be output from a PWM
inverter (under the given dc supply condition). Listed below are two applications where a 3-
phase square wave inverter could be used.
(i) A low cost solid-state frequency changer circuit: This circuit converts the 3-phase ac
(input) voltages of one frequency to 3-phase ac (output) voltages of the desired
frequency. The input ac is first converted into dc and then converted back to ac of new
frequency. The square wave inverter discussed in this lesson may be used for dc to ac
conversion. Such a circuit may, for example, convert 3-phase ac voltages of 50 Hz to 3-
phase ac voltages of 60 Hz. The input to this circuit could as well have come from a
single-phase supply, in which case the single-phase ac is first converted into dc and
then converted back to 3-phase ac of the desired frequency.
(ii) An uninterrupted power supply circuit: Uninterrupted power supply circuits are used to
provide uninterrupted power to some critical load. Here a critical load requiring 3-
phase ac supply of fixed magnitude and frequency has been considered. In case ac
mains supply fails, the 3-phase load may be electronically switched, within few
milliseconds, to the output of the 3-phase square wave inverter. Input dc supply of the
inverter often comes from a battery bank.

Problems

(1) A 3-phase square wave inverter feeds a balanced 3-phase resistive-inductive load. The
load phase current will contain, apart from the fundamental frequency current, the
following harmonic currents:
(a) All odd multiples of fundamental
(b) All odd and even multiples of fundamental
(c) All even multiples of fundamental except 6
th
and multiples of 6
th

(d) All odd multiples of fundamental except 3
rd
and multiples of 3
rd

(2) The six-stepped load phase voltage of a 3-phase square wave inverter, with a dc link
voltage of 100 volts, will have the following rms magnitudes of 1
st
, 3
rd
and 5
th
harmonic
voltages:
(a) 10V, 30V and 50V respectively
(b) 100V, 33.3V and 20V respectively
(c) 90V, 30V and 0 respectively
(d) 45V, 0 and 9V respectively

(3) A 3-phase square wave inverter, fed from a fixed dc input, is capable of producing the
following type of ac (fundamental component) voltages:
(a) Variable voltage variable frequency type
(b) Fixed voltage variable frequency type
(c) Variable voltage fixed frequency type
(d) None of the above

(4) A 3-phase square wave inverter feeds a balanced 3-phase inductance type load. The
worst-case load phase current (peak magnitude) is expected to be 100 amps and the
worst-case dc input voltage is expected to be 600 volts. The diodes of the inverter will be
subjected to the following peak voltage and current stresses:
(a) 600V, 100A
(b) 600V, 70.7A
(c) 424V, 70.7A
(d) 424V, 100A

(Answers: 1-d, 2-d, 3-b, 4-a)

(i) Explain the philosophy behind PWM inverters.
(ii) Understand the advantages and disadvantages of PWM inverters.
(iii) Compare the quality of output voltage produced by different PWM inverters

Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in
practical applications. These inverters are capable of producing ac voltages of variable
magnitude as well as variable frequency. The quality of output voltage can also be greatly
enhanced, when compared with those of square wave inverters discussed in Lesson-35. The
PWM inverters are very commonly used in adjustable speed ac motor drive loads where one
needs to feed the motor with variable voltage, variable frequency supply. For wide variation in
drive speed, the frequency of the applied ac voltage needs to be varied over a wide range. The
applied voltage also needs to vary almost linearly with the frequency. PWM inverters can be of
single phase as well as three phase types. Their principle of operation remains similar and hence
in this lesson the emphasis has been put on the more general, 3-phase type PWM inverter.

There are several different PWM techniques, differing in their methods of implementation.
However in all these techniques the aim is to generate an output voltage, which after some
filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental
frequency and magnitude. As will be discussed later in this chapter, for the inverter topology
considered here, it may not be possible to reduce the overall voltage distortion due to harmonics
but by proper switching control the magnitudes of lower order harmonic voltages can be
reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a
situation is acceptable in most cases as the harmonic voltages of higher frequencies can be
satisfactorily filtered using lower sizes of filter chokes and capacitors. Many of the loads, like
motor loads have an inherent quality to suppress high frequency harmonic currents and hence an
external filter may not be necessary.

To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the
voltage waveform needs to be done. In the following discussions some of the results of harmonic
analysis done in the previous lessons have been borrowed. In Lesson-35, while discussing the 3-
phase square wave inverter it was shown that the magnitudes of fundamental components of the
inverter pole voltage (voltage between the output of an inverter leg and the mid potential point of
the input dc supply) and the load phase voltage are identical provided the load is a balanced 3-
phase load. In fact, after removing 3
rd
and multiples of 3
rd
harmonics from the pole voltage
waveform one obtains the corresponding load phase voltage waveform. The pole voltage
waveforms of 3-phase inverter are simpler to visualize and analyze and hence in this lesson the
harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of
the pole voltages. It is implicit that the load phase and line voltages will not be affected by the 3
rd

and multiples of 3
rd
harmonic components that may be present in the pole voltage waveforms.

3-Phase Pulse Width Modulated (PWM) Inverter
36.1 Nature Of Pole Voltage Waveforms Output By PWM
Inverters

Unlike in square wave inverters the switches of PWM inverters are turned on and off at
significantly higher frequencies than the fundamental frequency of the output voltage waveform.
The typical pole voltage waveform of a PWM inverter is shown in Fig. 36.1 over one cycle of
output voltage. In a three-phase inverter the other two pole voltages have identical shapes but
they are displaced in time by one third of an output cycle. Compared to the square pole voltage
waveform seen in Lesson-35, the pole voltage waveform of the PWM inverter changes polarity
several times during each half cycle. The time instances at which the voltage polarities reverse
have been referred here as notch angles. It may be noted that the instantaneous magnitude of pole
voltage waveform remains fixed at half the input dc voltage (E
dc
). When upper switch (S
U
),
connected to the positive dc bus is on, the pole voltage is +0.5 E
dc
and when the lower switch
(S
L
), connected to the negative dc bus, is on the instantaneous pole voltage is - 0.5 E
dc
. The
switching transition time has been neglected in accordance with the assumption of ideal
switches. It is to be remembered that in voltage source inverters, meant to feed an inductive type
load, the upper and lower switches of the inverter pole conduct in a complementary manner. That
is, when upper switch is on the lower is off and vice-versa. Both upper and lower switches

2
0
1
2
3
4
-0.5E
dc
0.5E
dc
Fig.36.1: A typical pole-voltage waveform of a PWM inverter
Pole
Voltage
t
/2
-4
-3
-2
-1

+1
+2
+3
+4
3/2
2-4
2-3
2-2
2-1
0
S
U
S
L
S
U
S
U
S
U
S
U S
U
S
U
S
U S
U
S
L S
L
S
L
S
L
S
L
S
L
S
L
S
L
should not remain on simultaneously as this will cause short circuit across the dc bus. On the
other hand one of these two switches in each pole (leg) must always conduct to provide
continuity of current through inductive loads. A sudden disruption in inductive load current will
cause a large voltage spike that may damage the inverter circuit and the load.

36.2 Harmonic Analysis Of Pole Voltage Waveform

The pole voltage waveform shown in Fig. 36.1 has half wave odd symmetry and quarter-wave
mirror symmetry. The half wave odd symmetry of any repetitive waveform f(t), repeating after
every 2/ duration, is defined by f(t) =- f(+t). Such a symmetry in the waveform amounts
to absence of dc and even harmonic components from the waveform. All inverter output voltages
maintain half wave odd symmetry to eliminate the unwanted dc voltage and the even harmonics.
The half wave odd symmetry followed by quarter wave mirror symmetry, defined by f(t) =f(-
t), results in presence of only sine components in the Fourier series representation of the
waveform. It may be verified that quarter wave symmetry may not hold good once the time
origin is shifted arbitrarily. However the half-wave odd symmetry is maintained in spite of
shifting of time origin. This is quite expected, as by just shifting the time origin new (even)
harmonic frequencies will not creep up in the voltage waveform, whereas by shifting time origin
the sine wave may become cosine or may have some other phase-shift. The quarter wave
symmetry talked above is not necessary for improvement of the output waveform quality; it
merely simplifies the Fourier analysis of the pole voltage waveform. It may also be noted that the
quarter wave symmetry is not achieved at the cost of compromising the inverters output
capability (in terms of magnitude and quality of achievable output voltage).

With the assumed quarter wave mirror symmetry and half wave odd symmetry the waveform
shown in Fig. 36.1 may be decomposed in terms of its Fourier components as below:-

1,3,5,....
sin
AO n
n
V b n t
=
=

..(36.1)
where is the instantaneous magnitude of the pole voltage shown in Fig. 36.1 and
is the peak magnitude of its n
AO
V
n
b
th
harmonic component. Because of the half wave and quarter
wave symmetry of the waveform, mentioned before, the pole voltage has only odd harmonics
and has only sinusoidal components in the Fourier expansion. Thus the pole voltage will have
fundamental, third, fifth, seventh, ninth, eleventh and other odd harmonics. The peak magnitude
of n
th
harmonic voltage is given as:
1 2 3
2
(1 2cos 2cos 2cos 2cos )
n
E
b n n n
n
4
n
= + + ..(36.2)
, where
1
,
2

3
and
4
are the four notch angles in the quarter cycle (0 2 t ) of
the waveform.

Now, as described in the beginning of this lesson, the third and multiples of third
harmonics do not show up in the load phase and line voltage waveforms of a balanced 3-phase
load. Most of the three phase loads of interest are of balanced type and for such loads one need
not worry about triplen (3
rd
and multiples of 3
rd
) harmonic distortion of the pole voltages. The
peak magnitudes of fundamental ( ) and three other lowest order harmonic voltages that matter
most to the load can be written as:
1
b

1 1 2 3
2
(1 2cos 2cos 2cos 2cos )
E
b
4

= + + ...(36.3)

5 1 2 3
2
(1 2cos5 2cos5 2cos5 2cos5 )
5
E
b
4

= + + ...(36.4)
7 1 2 3
2
(1 2cos7 2cos7 2cos7 2cos7 )
5
E
b
4

= + + ..(36.5)

11 1 2 3 4
2
(1 2cos11 2cos11 2cos11 2cos11 )
11
E
b
= + + ...(36.6)
It can be seen that the 3
rd
and 9
th
harmonics have been not considered, as they will not appear in
the load side phase and line voltages. Most of the industrial loads are inductive in nature with an
inherent quality to attenuate currents due to higher order harmonic voltages. Thus after
fundamental voltage, the other significant voltages for the load are 5
th
, 7
th
and 11
th
etc.

Generally, only the fundamental frequency component in the output voltage is of interest and all
other harmonic voltages are undesirable. As such one would like to eliminate as many low order
harmonics as possible. Accordingly the fundamental voltage magnitude ( ) may be set at the
desired value and the magnitudes of fifth ( ), seventh ( ) and eleventh ( ) harmonics may
be set to zero. These voltage magnitudes when substituted in the expressions given by Eqns. 36.3
to 36.6 will lead to the solutions of the notch angles. One may like to eliminate many more
unwanted harmonic frequencies from the load voltage waveform but this will require
introduction of more notch angles per quarter cycle of the pole voltage. In fact if there are k
notch angles per quarter cycle, k number of equations may be written each of which determines
the magnitude of a particular harmonic voltage. Now, each time a notch angle is encountered in
the pole voltage waveform, the top and bottom switches of that particular pole undergo a
switching transition (on to off or vice versa). The switching frequency (f
1
b
5
b
7
b
11
b
sw
) of the inverter
switches can be equated to

f
sw
=2 k f
1
...........(36.7)

, where one turn-on and one turn-off has been taken as one switching cycle, k is the number of
notches per quarter cycle and f
1
is the frequency of fundamental component in the output
voltage. Thus it can be seen that a better quality output waveform (in terms of elimination of
more numbers of unwanted harmonic voltages) comes at the cost of increasing the switching
frequency of the inverter. The switching frequency is directly proportional to the switching
losses in the inverter switches. Also, the switch must be capable of being switched on and off at
the required frequency. The IGBT switches used in medium power inverters are generally
switched at a frequency of 20 kHz or more. With a switching frequency of 20 kHz and the output
(fundamental) frequency of 50 Hz there will be up to 200 notches per quarter cycle of the output
waveform. The load voltage can thus be made virtually free of low order harmonics and the load
current (for an inductive load) can be expected to have a good quality sinusoidal waveform. The
switching frequency of 20 kHz is important in another sense too. The range of audible noise for
human beings extends from few Hertz to 20 kHz. Thus if the switching frequency is 20 kHz or
beyond, the switching frequency related audible noise will not be present when the inverter
operates. The inverter operation can then be very quite. If the inverter operates at low frequency,
the connecting wires to the switches etc. also carry low frequency current producing low
frequency vibrations (due to interaction of current with the stray magnetic field produced by
other conductors etc.) and result in audible noise. Similarly low frequency current through
inductors and transformers also produce audible noise. The humming or whistling type noise due
to low switching frequency may at times be too annoying and unacceptable.

36.3 Trade Off Between Low Order And High Order Harmonics

The 3-phase inverter with six switches connected in the bridge fashion is also known as a two-
level inverter because the inverter pole-voltage alternates between the two voltage levels of +0.5
E
dc
and - 0.5 E
dc
(the switching transition time has been neglected). The root mean square (rms)
of the pole voltage equals 0.5 E
dc
. Now a periodic function ( ) f t when expressed in terms of
its Fourier components satisfies the following mathematical identity.

..(36.8)
[ ]
2
2
1, ,
2,3,4,....,
( ) ( ) ( )
rms rms n rms
n
f t f t f t
=
= +

In Eqn. (36.8), ( )
rms
f t is the rms magnitude of the given periodic waveform where as
1,
( )
rms
f t and
,
( )
n rms
f t are the rms magnitudes of the fundamental component and n
th

harmonic component of the waveform respectively.

Also, if the waveform ( ) f t has half wave odd symmetry and quarter wave mirror symmetry,
its fundamental voltage can be expressed as

1,
0
2
( ) { ( )sin }
rms
t
f t f t
t d t
=
=

....(36.9)
Now let ( ) f t in the above equations (36.8 and 36.9) be replaced by the two-level pole voltage
waveform of the PWM inverter. The term on the left hand side of Eqn. (36.8) equals (0.5E
dc
)
2
.
The first term on the right hand side of Eqn. (36.8) is the square-of-rms (i.e., mean of square)
magnitude of the fundamental component of pole voltage whereas the second term on the right
hand side denotes the mean-of-square magnitude of the unwanted ripple in the pole voltage. As
can be seen, the rms magnitude of the fundamental pole voltage is always going to be less than
0.5E
dc
. Further, as given by Eqn. (36.9), the fundamental magnitude (rms) of PWM inverters
output pole-voltage will be less than 0.45E
dc
, which is the rms magnitude of fundamental pole
voltage of a 3-phase square wave inverter. [In case of square wave output, both ( ) f t and
sin t are positive during 0 t but the sign of ( ) f t in PWM waveform alternates
between positive and negative values.]

In case of PWM inverter the magnitude of fundamental output voltage is fixed by suitable pulse
width modulation (by selection of suitable notch angles for the waveform in Fig. 36.1). However,
as can be seen from Eqn. (36.8), the reduction in fundamental magnitude leads to increase in the
rms magnitude of the unwanted ripple voltage. Also, after fixing the fundamental voltage
magnitude if it is desired to eliminate some of the low order harmonics, it will be at the cost of
increasing the magnitudes of higher order harmonics. Thus, as far as the quality of inverter pole
voltage alone is concerned the PWM technique is not helping. However considering the fact that
most of the loads are inductive in nature with low pass filter type characteristics the load current
quality effectively improves by eliminating lower order harmonics from the pole voltage
waveform (even if the higher order harmonic magnitudes increase). In case the load, on its own,
is not able to filter out the harmonic voltages satisfactorily the inverter output may be passed
through some external filter before being applied to load. The required size of the external filter
will be small if the inverter output is free from low frequency harmonics.

36.4 Brief Description Of Some Popular PWM Techniques

The schematic PWM waveform shown in Fig. 36.1, is only representative in nature. The logic
described to select notch angles is also specific to one particular PWM technique that is known
as selective harmonic elimination technique. There are several other PWM techniques, the
important ones are:- SINE-PWM technique, Space Vector based PWM technique, Hysteresis
current controller based PWM technique etc. A few of these techniques have been dealt with, in
detail in the next few lessons.

Some of the PWM techniques can be realized using analog circuits alone; some others are more
easily realized with the help of digital processors like microprocessor, Digital signal processor
(DSP) or Personal Computer (PC), whereas some other PWM controllers could be a hybrid
between analog and digital circuits. For example, the selective harmonic elimination technique
described above requires numerical solutions of the transcendental equations for arriving at the
required notch angles. These transcendental equations are solved off-line and the information
regarding notch angles (switching instances) is stored in digital memory, like EPROM. It may be
realized that the notch instances may not occur at regular time intervals. Similarly fundamental
output voltage requirement may not remain fixed for all output frequencies and hence the
transcendental equations (similar to Eqns. 36.3 to 36.6) will be different for different output
frequencies. Also, as per Eqn. 36.7, if the switching frequency is kept constant, there will be
more notch angles (per quarter cycle) at low output frequencies and less number of notches at
higher frequencies. Thus the set of notch angles for one frequency may be different from the
notch angles at some other frequency. For satisfactory implementation of this technique,
generally the desired output frequency range is divided in few discrete frequencies. For example,
it may be desired to output a 3-phase balanced voltage in the frequency range of 5 Hz to 50 Hz
with the constraint that the ratio between output voltage magnitude and output frequency should
remain fixed to some predetermined value. Under this situation the output voltage range may be
discretized in steps of, say, 1Hz. Thus the available output may vary from 5 Hz to 50 Hz through
the following discrete values of intermediate frequencies: 6 Hz, 7 Hz, 8 Hz, , 49 Hz. The
desired magnitudes of output voltage for all these discrete frequencies is found out and
accordingly the notch angles are calculated to eliminate as many unwanted harmonics as possible
(keeping in mind the constraint on switching frequency). Now switching information for
successive output frequencies may be stored in successive memory blocks. For each of these
output frequencies, it may be convenient to discretize one complete output cycle time interval in
small steps (say, in steps of 10 microseconds) and the inverter switching word (as described
below) at these successive time intervals are then stored in the successive memory locations. The
switching word combines the switching information for all three legs (all six switches) of the
inverter and may be obtained in the form of a six bit binary word, each bit corresponding to one
particular switch. When a particular bit value is 1 that particular switch may require being
turned-on. Similarly 0 bit value may correspond to turn-off command of the switch. Now if the
memory block, containing switching information is addressed sequentially after every 10
microsecond (this being the time step, chosen above, to discretize the output cycle time period)
the desired switching pattern for the inverter switches may be obtained. The notch angles can
thus be realized with a maximum time error of 10 microseconds (which for 50 Hz output
corresponds to an error of 0.18
0
only). After completion of one output cycle the next cycle is
simply repeated like the previous one. One may move from one memory block to another
memory block (by suitably multiplexing the memory address-word) to obtain the inverter-
switching pattern for some other output frequency. The selective harmonic elimination technique
described above is also known as stored-PWM technique. The overall memory requirement may
be large but since the memory cost has been reducing over the years the stored-PWM technique
remains one of the most attractive techniques.

In contrast to the selective harmonic elimination technique discussed above, some other PWM
techniques, notably SINE-PWM and Space Vector-PWM techniques, try to match the mean
value of load voltage under the rectangular PWM waveform with the mean voltage of the desired
output waveform over every small time interval of the output cycle. If, for example, the desired
output voltage is a sinusoidal waveform of a given magnitude and of frequency f
1
, then for
every small time interval t of the output cycle period (such that t << 1/ f
1
) the mean (dc)
magnitude under desired sine wave and the mean dc voltage under the PWM pulses are made
equal. Now barring the mismatch in the instantaneous magnitudes of the sine wave and the PWM
wave within the small time period t, the two waveforms are matching. Thus the PWM
waveform may be considered to be the superposition of the desired output waveform and ripple
voltages of time period t. The ripple voltage waveform in each t time interval may not be
identical and hence ripple voltage may consist of a band of harmonics of high frequency. In the
frequency axis the high frequency harmonic voltages are far away from the desired voltage of
fundamental frequency f
1
and hence suitable low pass filter circuits may be used to block the
unwanted harmonic currents without affecting the magnitude of the fundamental frequency
current. Further details of these techniques may be found in later lessons.

Fig. 36.2: 1-phase half bridge VSI for CCPWM control
E
dc
S
U
S
L
A
0.5E
dc
0.5E
dc
+
_
+
_
+
_
LOAD O
P
N
I
L

Another popular PWM technique is current controlled PWM (CCPWM) technique. Here the
instantaneous magnitude of load current is directly controlled, within some tolerable error band,
to match the desired current shape. This technique is described below for a single-phase half
bridge inverter shown in Fig.36.2. The positive sense for the load current (I
L
) is taken along the
direction of arrow in Fig. 36.2. The actual load current is sensed with the help of a current sensor
and compared with its reference magnitude. The error in load current can be controlled, as
described below, by proper switching of the inverter switches. The load could be a R-L load or a
R-L-E load. In case of R-L-E load, it is assumed that the back emf (E) of the load has a peak
magnitude lower than the magnitude of instantaneous pole voltage (0.5E
dc
). To increase the
actual current along the direction of arrow (or to reduce the current flowing in a direction
opposite to the arrow) upper switch S
U
needs to be turned on, whereas turning on of lower
switch S
L
will produce the reverse effect. This can be verified simply by writing and analyzing
the loop voltage equation.

36.5 Two-Level Versus Three-Level PWM Inverters

As described in section 36.3, the three-phase bridge inverter consisting of six switches (shown in
Lesson-35) can output pole voltages of only two levels +0.5E
dc
and -0.5E
dc
. In contrast to a two-
level inverter, a three-level inverter is capable of producing three different pole-voltage levels,
namely, +0.5E
dc
, zero and -0.5E
dc
. The circuit details of three-level inverter will not be discussed
in this course but it can easily be shown that the three-level inverter will have better harmonic
spectrum in comparison to the two-level inverter. As described by Eqn. (36.8) in section 36.3,
any reduction in the fundamental output voltage magnitude of a two level inverter results in
increased rms magnitude of unwanted ripple in the output waveform. Now, let Eqn. (36.8) be
considered in relation to a three-level inverter. Since the pole voltage can now have zero level
too, the rms magnitude of the pole voltage can be brought below 0.5E
dc
. For lower magnitude of
fundamental pole-voltage, as given by Eqn. (36.9), suitable intervals of zero voltage level may be
introduced such that with lowering of fundamental voltage the rms of the overall pole voltage
also reduces. Thus the rms of the ripple voltage, in case of three-level inverter, can be made
lower than that of the two-level inverter.
The three-level versus two-level comparison can be applicable to a single-phase PWM inverter
too. Consider the single-phase full bridge circuit shown in Fig.36.3. For this circuit if all the time
one of the two diagonal pair of switches, (Sw1 and Sw4) or (Sw2 and Sw3), conduct the load
voltage will have two levels; +E or E. By suitably switching between one diagonal pair to
another diagonal pair one can obtain a PWM waveform similar to the pole voltage waveform of a
three-phase PWM inverter (only change is in the voltage magnitude). Now if the allowed
switching combination includes conduction of Sw1 along with Sw3 (or Sw2 along with Sw4) the
load voltage may have three-levels, i.e., +E, zero and E. As with a three-phase inverter, the
single phase PWM inverter too will have lower voltage distortion in case of three-level load
voltage (than the corresponding distortion in two level output).

36.6 Considerations On Switch Voltage And Current Ratings

As in square wave inverter the switches of PWM inverter must also be rated for the maximum dc
link voltage. There will, however, be a significant difference in the switch current ratings of the
square wave and PWM inverter for comparable magnitudes of inverters output current. This is
due to the increased switching losses in the PWM inverter. Since the switches in PWM inverter
operate at much higher frequencies than in square wave inverter, the switching losses in the
former are comparable to the conduction losses. This calls for suitable de-rating of the switch
current rating. For medium power rated inverters mostly IGBT switches (with fast acting anti-
parallel diodes) are used. Generally molded blocks of six switches and six diodes, connected in
LOAD
E
dc
C
dc
_
+
A B
Fig. 36.3: A 1-phase full-bridge VSI
i
dc
P
N
Sw1 Sw3
Sw2 Sw4
bridge fashion with their power and control terminals brought out, are commercially available.
These molded blocks come with isolated metallic case that need to be mounted on suitably sized
heat sinks for dissipation of thermal losses in the switch. The switch manufacturers provide the
turn-on and turn-off loss data for the switches for different magnitudes of dc link voltage, switch
current and gate-to-emitter voltages. Similarly conduction loss data for the switches and the
diodes are also provided. The thermal resistance data (thermal resistance between case and
semiconductor-junction) for the switches and diodes are also provided. The heat-sink
manufacturers provide data / guide lines for calculating the thermal resistance between heat sink
and ambient. The inverter designer needs to do a detailed analysis of the worst-case thermal
losses and temperature rise and need to limit the switch current accordingly. In PWM inverters,
because of large number of switching per output cycle, the load current frequently jumps from
controlled switch (say, IGBT) to diode and hence the diodes of the switches must also be rated to
carry the peak magnitude of load current. It is to be kept in mind that in PWM inverters the load
current polarity changes only according to the output frequency and not according to the
switching frequency. For load power factor close to one, as the PWM inverters output voltage
decreases the diode conduction duration increases. The worst-case diode losses also need to be
determined for deciding on the de-rating factor for diode currents.

Quiz Problems

(1) A PWM inverter is operated from a dc link voltage of 600 volts. The maximum rms line
voltage (fundamental component) will be less than or equal to:
(a) 600 volts
(b) 300 volts
(c) 467 volts
(d) 582 volts
(2) In the harmonic analysis of the pole-voltage waveform (produced by a three-phase PWM
inverter feeding a balanced three-phase load) the 3
rd
and multiples of 3
rd
harmonics are
ignored because:
(a) They will not appear in pole voltage
(b) They will not appear in load phase voltage
(c) They will not appear in load phase and line voltage
(d) They will appear in line voltage but not in phase voltage
(3) An IGBT based PWM inverter, with very large number of (nearly) evenly distributed
notches per output cycle, is used to feed a three-phase balanced R-L load with a load
power factor of 0.9. The peak magnitude of diode current and the IGBT current will have
the following relation:
(a) They will be equal
(b) Peak diode current will be less than half of the peak IGBT current
(c) Diode current will nearly be zero
(d) Peak diode current will be less than one third of the peak IGBT current
(4) A PWM inverter is capable of producing the following type of output voltage:
(a) Variable in magnitude and frequency
(b) Variable voltage, fixed frequency
(c) Fixed voltage, variable frequency
(d) Fixed voltage, fixed frequency
Answers to Quiz problems: 1-c, 2-c, 3-a, 4-a
After completion of this lesson, the reader shall be able to:
1. Explain the concept of sine-modulated PWM inverter
2. Design a simple controller for the sine-PWM inverter
3. Calculate output voltage magnitude from the inverter operating parameters
4. Compare sine-modulated PWM inverter with square wave inverter

The PWM inverter has been introduced in Lesson 36 and Fig. 36.1 shows a typical pole voltage
waveform, over one output cycle of the PWM inverter. It can be seen that the pole voltage
consists of large number of rectangular pulses whose widths are modulated suitably to provide
control over the output voltage (fundamental component) magnitude and, additionally, control
over the harmonic spectrum of the output waveform.

In Sine-PWM inverter the widths of the pole-voltage pulses, over the output cycle, vary in a
sinusoidal manner. The scheme, in its simplified form, involves comparison of a high frequency
triangular carrier voltage with a sinusoidal modulating signal that represents the desired
fundamental component of the pole voltage waveform. The peak magnitude of the modulating
signal should remain limited to the peak magnitude of the carrier signal. The comparator output
is then used to control the high side and low side switches of the particular pole. Fig. 37.1 shows
an op-amp based comparator output along with representative sinusoidal and triangular signals as
inputs. In the comparator shown in Fig. 37.1, the triangular and sinusoidal signals are fed to the
inverting and the non-inverting input terminals respectively and the comparator output
magnitudes for high and low levels are assumed to be +V
CC
and -V
CC
.

Time (mili sec.)
+
-
Q
Modulating
signal
Carrier
signal
Q
+V
CC
-V
CC
Fig. 37.1: A schematic circuit for comparison of Modulating and Carrier signals

The comparator output signal Q is used to turn-on the high side and low side switches of
the inverter pole. When Q is high, upper (high side) switch of the particular pole is turned on
and when Q is low the lower switch is turned on.
The pole voltage, thus obtained is a replica of the comparator output voltage. When Q=+V
CC
,
the pole voltage (measured with respect to the mid potential point of the dc supply) is +0.5E
dc
and
Sine PWM and its Realization
when Q=(-)V
CC
, the pole voltage becomes (-0.5)E
dc
. The input dc voltage to the inverter (E
dc
)
has been assumed to be of constant magnitude. Thus, on a normalized scale, the harmonic
contents in the comparator output voltage and the pole voltage waveforms are identical.
37.1 Analysis Of The Pole Voltage Waveform With A Dc
Modulating Signal
Before analyzing the sine-modulated pole voltage waveform, it would be revealing to consider a
pure dc signal (of constant magnitude) as the modulating wave. The magnitude of the dc
modulating signal is constrained to remain between the minimum and maximum magnitudes of
the triangular carrier signal. Fig. 37.2 illustrates one such case where the triangular carrier signal
varies between -1.0 and +1.0 units of voltage and the magnitude of the modulating wave is kept
at 0.4 unit of voltage. Now, the high frequency triangular carrier waveform is compared with the
dc modulating signal and the comparator output is used to control the high and low level
switches (S
U
and S
L
respectively) of the inverter pole shown in Fig. 37.2.

Fig. 37.2: Inverter pole voltage for a pure dc modulating waveform
V
AO
Q
0.5E
dc
- 0.5E
dc
+V
CC
-V
CC
Time in m.sec.
S
U
S
L
E
dc
0.5E
dc
0.5E
dc
+
_
+
_
+
_
Pole
Voltage
O
A
The figure also shows the comparator output (Q) and the pole voltage (V
AO
) waveforms for this
case. As can be seen, with pure dc modulating signal the pole voltage consists of pulses of
identical shapes repeating at carrier frequency. The Fourier series decomposition of pole voltage
waveform results into a mean (dc) voltage and harmonic voltages whose frequencies are integral
multiples of carrier frequency. By using simple mathematics the high-duration of the pulses (t ),
during which the pole voltage magnitude is 0.5E
h
dc
, can be found to be
(1 )
2
c
h
c
T V
t
V
= +
m
.... (37.1),
where is the time period of the triangular carrier waveform, is the magnitude of the
modulating signal and
c
T
m
V
c
V is the peak (positive) magnitude of the carrier signal.
In a similar manner the low-duration ( ) of pulses during which the pole voltage magnitude is -
0.5E
l
t
dc
, can be found as:
(1 )
2
c
l
c
T V
t
V
=
m
... (37.2)
The dc component of the pole voltage ( ) can be found to be
0
V
0
0.5
m
dc
c
V
V E
V
= ... (37.3)
c
V

c
V The dc modulating signal could acquire any magnitude between + and - and accordingly the
mean magnitude of pole voltage can vary within +0.5E
dc
and -0.5E
dc
. When the modulating
signal magnitude (V ) is zero, the high and low durations of the pole output pulses will be
identical and the mean pole voltage magnitude will be zero.
m
As mentioned before, apart from the dc component, the pole voltage consists of harmonics of
integral multiples of carrier frequency. The lowest order harmonic-frequency being same as the
carrier frequency.
37.2 Pole Voltage Waveform With Sinusoidal Modulating Signal
In the previous section a pure dc modulating signal was considered. Let now a slowly varying
sinusoidal voltage, with the following constraints, be considered as the modulating signal:
1. The peak magnitude of the sinusoidal signal is less than or equal to the peak magnitude of
the carrier signal. This ensures that the instantaneous magnitude of the modulating signal
never exceeds the peak magnitude of the carrier signal.
2. The frequency of the modulating signal is several orders lower than the frequency of the
carrier signal. A typical figure will be 50 Hz for the modulating signal and 20 Kilohertz
for the carrier signal. Under such high frequency ratios, the magnitude of modulating
signal will be virtually constant over any particular carrier-signal time period.

Because of the above assumptions some results of the previous section, where a pure dc
modulating signal was considered, may be used. Since the slowly varying modulating signal is
virtually constant over a high frequency carrier time period, the mean magnitude of the inverter
pole voltage averaged over a carrier time period will be proportional to the mean magnitude of
the modulating signal. Thus the discretely averaged magnitude of pole voltage (averaged over
successive high frequency carrier time period) is similar to the modulating signal. The pole
voltage waveform thus has a low frequency component whose instantaneous magnitude is
proportional to the modulating signal (also implying that they will have same frequency and will
be in-phase). Apart from this low frequency component the pole voltage will also have high
frequency harmonic voltages. However, unlike in the case of pure dc modulating signal the
harmonic frequencies are now not simply integral multiples of carrier frequency. This is so
because here the widths of the high frequency pole-voltage pulses do not remain constant
through out. The pulse widths get modulated as per equations (37.1) and (37.2) due to slowly
varying modulating signal. As a result the harmonics in the pole voltage waveform are of
frequencies that are shifted from the carrier (and multiples of carrier frequency) by the integral
multiples of modulating wave frequency. In fact one gets a band of harmonic frequencies
centered around the carrier and integral multiples of carrier frequency. The individual
frequencies that form the band are displaced from these central frequencies by integral multiples
of modulating wave frequency. However, the modulating wave frequency being negligible
compared to the carrier frequency, the dominant harmonics are still in the vicinity of carrier
frequency and multiples of carrier frequency. A more detailed harmonic analysis of the sine-
modulated pole voltage waveforms is beyond the scope of this course. The low frequency
(modulating frequency) component of the pole output voltage is often referred as fundamental
frequency component.

Now, in some cases the ratio of carrier and modulating frequencies may not be very high but the
pole voltage still has a fundamental frequency component proportional to and in-phase with the
modulating signal. The essential advantage of having very high carrier frequency, in comparison
to the modulating wave frequency, is that the useful fundamental frequency component of pole
voltage and the unwanted harmonics (having frequencies close to the carrier and multiples of
carrier frequency) are far apart on the frequency spectrum and one can virtually filter away the
harmonic voltages without attenuating the magnitude of the fundamental frequency component
by putting a suitable low pass filter. The filter size requirement remains small if the harmonics
are of high frequencies. In some applications, like ac motor drive application, the inherent low
pass filtering characteristics of the motor-load itself is enough to satisfactorily block the flow of
harmonic currents to the load. In such cases the need for external filter may not arise.

It may be obvious that high carrier frequency calls for high switching frequency of the inverter
switches. In fact the switches turn-on and turn-off once during each carrier cycle. Generally the
switches used in high power applications (say, more than few hundred kW) can be switched only
at sub kilohertz frequency and hence the carrier frequency cannot be arbitrarily high. The
switching frequency related losses are also to be considered before deciding the carrier frequency
of the sine-PWM inverter.
What Is Modulation Index?

Modulation index is the ratio of peak magnitudes of the modulating waveform and the carrier
waveform. It relates the inverters dc-link voltage and the magnitude of pole voltage
(fundamental component) output by the inverter. Now let
sin( )
m
V t be the modulating signal
and let the magnitude of triangular carrier signal vary between the peak magnitudes of +
c
V and -
c
V

m
V

c
V . The ratio of the peak magnitudes of modulating wave ( ) and the carrier wave ( ) is
defined as modulation-index ( ). In other words: m
m
c
V
m
V
= ... ...(37.4)
Normally the magnitude of modulation index is limited below one (i.e., 0< <1). From the
discussion in the previous section it can be concluded that for 0< <1, the instantaneous
magnitude of fundamental pole voltage (V
m
m
t
) will be given by:
AO,1
sin m V
AO,1
=0.5E
dc
( ) ... ....(37.5),
where is the angular frequency of the modulating waveform. For =1 the pole output
voltage (fundamental component) will have a rms magnitude of 0.35E
m
dc
(=
1
m
m m
2 2
E
dc
). This
magnitude, as can be found out from Sec. 34.1 of Lesson 34, is only 78.5% of the fundamental
pole voltage magnitude output by a square wave inverter operating from the same dc link
voltage.
What Is Over-Modulation?
When the peak magnitude of modulating signal exceeds the peak magnitude of carrier signal
(resulting in >1), the PWM inverter operates under over-modulation. During over-modulation
the fundamental component of the pole voltage increases slightly with increase in modulation
index but the linear relation between them, as shown by Eqn. (37.5), no longer continues. Also,
lower frequency harmonics crop up in the pole-output waveform. It may easily be seen that for
very high (say =infinity), the pole voltage shape will be identical to the square wave
shape discussed in Lesson-34. Over modulation is generally not preferred because of the
introduction of lower frequency harmonics in the output waveform and subsequent distortion of
the load current.
37.3 A 1-Phase Sine-PWM Inverter Of H-Bridge Topology
Lesson-34 shows the half bridge and full bridge topologies of a single phase square-wave
inverter. The single-phase full bridge is also called as H-bridge because of its resemblance with
the letter H. [The two legs (poles) of the inverter resemble the two vertical lines of H and the
horizontal line denotes the load, which is connected to the pole output points.] The switches and
the load in a single-phase full bridge PWM inverter are connected exactly as in a square-wave
inverter circuit. The difference lies in the conduction pattern of the inverter switches. In the
square-wave inverter the switches conduct continuously for 180
0
in each output cycle whereas in
PWM inverter large number of switching take place in each output cycle.
The half bridge sine-PWM inverter employing only one leg has already been described in the
previous section. The full bridge inverter employs one additional leg but the control signals of
the half bridge circuit may still be employed for switches of the other leg. As in the square-wave
inverter (Lesson-34) the diagonal switches of the two legs may be turned on together to produce
a load voltage that has double the magnitude of individual pole voltage. The PWM signals for
the high and low level switches of one leg (obtained by sine-triangle comparison) may again be
used for low and high level switches, respectively, of the other leg.


V
AO
V
BO
V
AB
0.5E
dc

0

-0.5E
dc
0.5E
dc

0

-0.5E
dc
E
dc

- E
dc
Carrier
signal
Modulating
Signal for
Pole-A
Modulating
Signal for
Pole-B
Angular freq. for fundamental
component in rad./sec
Fig. 37.3: Sine-PWM waveforms for single-phase H-Bridge inverter

Alternately (also, preferably), the modulating waveform for the other leg may be inverted
(keeping the carrier waveform same). The two inverted modulating waveforms are then
compared with the same carrier waveform using two different comparators. The comparator
outputs, one for each leg, are then used to switch the high and low level switches as in the half
bridge circuit.
Fig.37.3 shows the relevant waveforms that use two inverted sine waves as modulating signals
for the two legs of the inverter. For better visibility the ratio between the carrier and modulating
wave frequencies has been assumed equal to eight (normally carrier frequency is much higher)
and circuit waveforms for only part of the modulating wave cycle has been shown. In Fig.37.3,
the blue colored modulating wave is used for pole-A of the inverter and the green colored for
pole-B. The corresponding pole voltages (V , V
AO BO
) and the load voltage (V
AB
) are also shown
in the figure.

The scheme, using two inverted modulating waves, has the following advantages over the one
that uses single modulating wave and employs simultaneous switching of the diagonal switches
of the two legs:- (i) Overall harmonic distortion of the load voltage waveform is reduced and (ii)
the frequency of the ripple voltage in the load waveform doubles. Both these points may be
verified by mere inspection of the load voltage waveform shown in Fig.37.3. In case of single
modulating wave, the instantaneous load voltage has double the amplitude of pole-A voltage and
thus the harmonic distortion of the load voltage and pole voltage remains same. It may be noted
that the instantaneous magnitude of load voltage, in this case, has two levels (+0.5E
dc
and -
0.5E
dc
). In the alternate scheme, using two inverted modulating waves, the load voltage has
double the number of pulses per carrier time period, thus doubling the ripple frequency. Now,
higher the frequency of unwanted ripple-voltage, easier it is to filter out the ripple current. Also,
the load voltage now has three levels (+0.5E
dc
, zero, and -0.5E
dc
). Presence of zero duration
reduces the rms magnitude of the overall load voltage (fundamental component along with
harmonics), while keeping the magnitude of fundamental component of load voltage same as in
the previous case (the rms of the overall load voltage for the two-level waveform equals E
dc
).
Thus the overall distortion of the load voltage waveform is less.

37.4 Generation Of 3-Phase Sine-PWM Waveform
A three-phase inverter, as discussed in Lessons 36, can be used to output a three-phase sine
modulated pole-voltage pulses. Switches in each of the three poles of the inverter are
individually controlled as per the technique discussed in the previous section. For a balanced
three-phase output voltage from the inverter poles, the three sinusoidal modulating signals (one
for each pole) must also be balanced three-phase signals. The carrier waveform for all the three
poles may remain identical. The fundamental components of individual pole output voltages (for
0< <1) will thus be proportional to the corresponding modulating signals. For =1, the rms
magnitude of line-to-line voltage (fundamental component) output by the inverter will be equal
to
m m
3
2 2
E (=0.612E
dc dc
). A typical line voltage waveform (difference of two pole voltage
waveforms) will appear similar to the line voltage waveform (V ) shown in Fig.37.3.
AB
37.4 A Typical Circuit For Generation Of PWM Waveforms

As mentioned in the preceding section, a three-phase sine-PWM inverter would require a
balanced set of three sinusoidal modulating signals along with a triangular carrier signal of high
frequency. For a variable-voltage-variable-frequency (VVVF) type inverter, a typical
requirement for adjustable speed drives of ac motors, the magnitude as well as frequency of the
fundamental component of inverters output voltage needs to be controlled. This calls for
generation of three-phase balanced modulating signals of variable magnitude and frequency
which it may be emphasized, need to have identical magnitudes and phase difference of 120
degrees between them at all operating frequencies.

Generating a balanced three phase SINE waveforms of controllable magnitude and frequency is
a pretty difficult task for an analog circuit and hence a mixed analog and digital circuit is often
preferred. Fig. 37.4 shows a scheme, in block diagram, where the 3-phase analog SINE waves
are generated with the help of EPROMs, D/A converters etc.

V
M
Voltage to
Freq. (V/f)
Converter
V
C
+V
Divide by
2
10

counter
EPROM#2
loaded with
120
0
shifted
SINE Data
10 bit
address
D/A
Converter
#1
8 bit
Data
Frequency
Control
SINE
Wave
120
0
shifted
SINE Wave
Ref. Volt.
D/A
Converter
#2
EPROM#1
(1K) loaded
with SINE
Wave Data
+V
Fig.37.4: Schematic circuit for generation of balanced sinusoidal signals

In the circuit of Fig.37.4, two EPROMs are loaded with discrete values of SINE wave. The first
EPROM contains Sin() values and the second EPROM contains Sin(-120
0
) , for 0
0
< <
360
0
. Let us assume that the EPROMs have 1K (=1024) memory locations. In EPROM#1 Sin()
values are stored serially at discrete but regular intervals of values. Accordingly the first
location of EPROM#1 contains Sin(0
0
) in digital form, i.e., all the bits are zeroes. The second
memory location contains Sin(360
0
/1024) in the digital form and so on. Similarly the first
memory location of EPROM#2 contains Sin(120
0
) and second memory location has Sin(120
0
+
360
0
/1024) in digital form. The contents of a particular memory location can be accessed
asynchronously by feeding the corresponding address word. A 1K EPROM will have 10 address
lines. All address bits, when zero, point to first memory location. As the address word
increments the subsequent memory locations are addressed. The EPROMs generally have a 8
bit word length. Now, Sin() value, over the full range of , may either be positive or negative.
So while digitizing them care must be taken to identify one bit of the word as the sign bit. For
example, in the 8 bit (byte length) word the MSB may be used as sign bit with the understanding
that if this sign bit is zero the number is positive and if this bit is 1 the number is negative
(alternately, one may store 1+Sin() in the memory and the need to store negative numbers
will not arise). Leaving one bit (say MSB) as sign bit the 0.0 to 1.0 scale of Sin() magnitude is
divided in 2
7
=128 equal parts and accordingly the SINE value is digitized. Thus when Sin() =
1/128 the word to be stored should be 0000 0001. For lesser but positive value of Sin() the
word is 0000 0000. If, for example, Sin() =-1/64, the word to be stored should be 1000 0010.
Here 1 at the MSB location indicates that the number is negative. As seen in the block diagram
of Fig.37.4, each EPROM output is fed to a D/A (Digital to Analog) converter to finally come up
with analog value of Sin(). Now in the D/A converter, the sign bit is not to be fed. The MSB
input of D/A could be grounded. A separate simple logic circuit could take the MSB output of
EPROM for sign changing of the D/A output. One such simple arrangement (Fig.37.5) uses an
analog switch, an op-amp and a few resistors to assign correct sign to the analog output of the
D/A converter.

Fig.37.5: A simple sign corrector Circuit
GND
Op-
Amp
Sign
Corrected
D/A output
O/P
of
D/A
R
R
Analog
Switch
1 =ON
0 =Off
+
-
{
MSB of
EPROM

As mentioned earlier, an alternative arrangement for storing data in the EPROM could be to store
[1+Sin()] value in the memory locations so that negative numbers are not encountered. While
decoding the digital value into analog form (using Digital to Analog converter) the analog
equivalent of this extra 1 may be subtracted using a simple Op-amp based subtractor circuit.

In the circuit of Fig.37.4, a control voltage V
C
is applied to a voltage to frequency (V/f)
converter. The V/f converter should preferably have a linear relation between the applied voltage
and output frequency. The V/f converter output is fed as clock to a divide by 2
10
ripple counter
circuit. Ten address lines for the 1K EPROM are connected to the ten output lines of the ripple
counter. For a 2K EPROM eleven address lines are required and the appropriate counter would
then be a divide by 2
11
counter. The consecutive clock pulses to the ripple counter increment the
EPROMs address word sequentially, pointing to the next EPROM memory location after each
clock. The EPROM outputs data of the addressed memory location asynchronously. Since the
SINE wave data is loaded in the EPROM sequentially, the digital value of SINE wave is output
by the EPROM in the correct sequence. The D/A converter then converts the EPROM output
into an analog signal. The SINE wave output by D/A converter is however only a stepped
approximation of the continuous SINE wave but the number of steps per sine-wave cycle being
large (=612), the resolution is sufficient for the present purpose. The Address lines for the two
EPROMs are tied together. Thus when, say, first memory location of EPROM#1 is addressed the
first location of EPROM#2 is also simultaneously addressed. The SINE waves stored in the two
EPROMs are phase shifted by 120
0
and hence the corresponding D/A converters output 120
0

shifted SINE waves. The ten-bit address word generated by ripple counter repeats after 1024
counts and accordingly SINE wave data from the EPROMs are also repeated after 1024 counts
(this count represents one output cycle time period of the sinusoidal modulating wave). The rate
at which the address bus data changes decides the frequency of the output waveform, which
eventually is controlled by the control voltage V . D/A converters have reference voltage (+V
C Ref

and - V
Ref
) pins provided for setting the maximum and minimum excursion of the output voltage
waveform. In the circuit of Fig.37.4, it is assumed that -V pins are grounded and +V
Ref Ref
pins
are connected to the reference voltage V
M
. Thus V
M
decides the magnitude of analog
sinusoidal signal output by the D/A converter. The magnitude control signal V
M
may be tied to
frequency control signal V
C
and one may achieve proportional change in inverters output
voltage and frequency. The circuit in Fig.37.4 produces two SINE waveforms having identical
magnitude and frequency but phase shifted by 120
0
. The third modulating SINE wave could be
generated simply by adding these two waveforms followed by a sign inversion. [Sin() +Sin(-
120
0
) =- Sin(-240
0
)]. Thus a simple circuit using a couple of op-amps will get the third SINE
wave.

High frequency triangular carrier waveform generator and comparator etc. are pretty simple
circuits to realize. The comparator output gives the required PWM pattern. The output frequency
(as well as magnitude) can be varied in an open-loop or closed-loop by varying the control
voltages V and V
C M
.

Quiz Problems

(1) The over-modulation of sine-PWM inverter is generally avoided because it introduces:
(a) lower frequency harmonics in the inverter output waveform
(b) non-linearity between the magnitudes of modulating signal and fundamental voltage
output by the inverter
(c) both the above
(d) none of the above

(2) A three-phase sine-PWM inverter operates from a dc link voltage of 600 volts. For
modulation index =1.0 the rms magnitude of line voltage of fundamental frequency will
be equal to:
(a) 600 volts
(b) nearly 367 volts
(c) nearly 481 volts
(d) nearly 581 volts

(3) The carrier waveform of a sine-modulated PWM inverter is of 10 kHz frequency. When
the fundamental output frequency of the inverter is 50 Hz, the inverter switches need to
be turned-on and turned-off at a rate of
(a) 1000 times per second
(b) 10,000 times per second
(c) 50,000 times per second
(d) 50 times per second

(4) A three-phase sine-modulated PWM inverter is used to get a balanced 3-phase
fundamental output voltage. The modulating waveforms must have
(a) Three DC signals of identical magnitude
(b) Three balanced ac signals of fundamental frequency
(c) Three identical and in-phase ac signals of fundamental frequency
(d) Three balanced ac signals of carrier frequency

Answers to Question Problwm: 1-c, 2-b, 3-b, 4-b.
After completion of this lesson, the reader shall be able to:
1. Explain the concept of sine+3
rd
harmonic modulated PWM inverter
2. Explain Space-Vector based PWM (SVPWM) technique
3. Estimate output voltage of the inverter using above PWM techniques
4. Compare at least five different PWM techniques for a 3-phase inverter

Lessons-36 and 37 have dealt with PWM inverters. As pointed out in these lessons, the two main
advantages of PWM inverters in comparison to square-wave inverters are (i) control over output
voltage magnitude (ii) reduction in magnitudes of unwanted harmonic voltages. It was also
shown that PWM results in lower magnitude of output voltage of fundamental frequency. In the
context of SPWM (Lesson-37) it was seen that good quality output voltage requires the
modulation index (m) to be less than or equal to 1.0. For m>1 (over-modulation), the
fundamental voltage magnitude increases but at the cost of decreased quality of output
waveform. The maximum fundamental voltage that the SPWM inverter can output (without
resorting to over-modulation) is only 78.5% of the fundamental voltage output by square-wave
inverter. In this lesson some more PWM techniques have been introduced. The merits and
demerits of different PWM techniques may be compared under comparable circuit conditions on
the basis of factors like (i) quality of output voltage (ii) obtainable magnitude of output voltage
(iii) ease of control etc. The peak obtainable output voltage from the given input dc voltage is
one important figure of merit for the inverter and has been discussed in some more detail below.

38.1 How To Get More Output Voltage From The Same DC Bus
Voltage?

The inverter switches need to be rated to withstand the peak magnitude of input dc link voltage,
the maximum expected load current and should be able to safely dissipate the heat generated in
the switch due to conduction and switching losses. Because of high frequency switching, the
switches in PWM inverters have significantly more switching loss than in square wave inverters.
Often the switch chosen in PWM inverters is oversized, in terms of its current rating, so that the
sum total of switching loss and conduction loss remains well within the heat dissipation
capability of the switch and the associated heat sink. One may talk of the VA rating of the
switch, being the product of the switch voltage and current ratings. The switch cost may be
roughly taken as proportional to its VA rating. The VA rating of the inverter equals the
maximum VA of load power (considering only the fundamental component of output voltage
and current) that the inverter may output. On account of higher fundamental output voltage and
less switching loss, a square-wave inverter will produce a higher VA (for the given switch VA
ratings) than a PWM inverter. The square wave inverter can use slower switches, requires
simpler control circuit and thus the inverter cost comes further down. However due to better
quality of output voltage (and hence current), PWM inverters may be unavoidable in many
applications.

For identical magnitudes of switching frequency and switch voltage stress some particular PWM
techniques may allow more output voltage than other PWM techniques (in spite of comparable
quality of output voltages). Sometimes the lower achievable output voltage may mean that the
inverter is not suitable for given application. For example, consider a typical case where a 3-
phase 400 volts rated induction motor is to be fed from a PWM inverter for a wide range of
speed control. The dc bus voltage to the inverter is, in most cases, achieved after rectifying the 3-
Other Popular PWM Techniques
phase utility ac supply. Often a three-phase diode bridge rectifier followed by a large filter
capacitor is used to get dc bus voltage. The magnitude of dc bus voltage, so achieved, may be
considered close to the peak magnitude of supply line voltage. For 400 volts, 50 Hz, 3-phase
supply system the dc bus voltage will be around 566 volts (i.e. 4002 volts). Now using a
SPWM inverter with a dc link voltage of 566 volts, one can output maximum rms line voltage of
347 volts only (=0.612 E
dc
, as shown in Sec. 37.4 of Lesson-37). The SPWM inverter will, thus,
not be able to meet the rated voltage demand of 400 volts for the motor. Instead of SPWM
inverter, had one used a square wave inverter, the maximum magnitude of line voltage
(fundamental component) output by the inverter would have been 441 volts (=0.78 E
dc
, as per
Sec. 35.2, Lesson-35). Thus, on account of lower output voltage a SPWM inverter may be
unsuitable in certain application. Fortunately, there are some other PWM techniques that can
output good quality line voltage waveforms (similar to SPWM inverter) and can output higher
voltage. In this lesson two such popular PWM techniques namely, sine+3
rd
harmonic modulation
and space vector modulation techniques have been described. Later two more PWM techniques
that were briefly touched upon in Lesson-36 have been elaborated further.

38.2 Sine + 3
rd
Harmonic PWM Technique

The idea of Sine+3
rd
harmonic modulation technique is based on the fact that the 3-phase
inverter-bridge feeding a 3-phase ac load does not provide a path for zero-sequence component
of load current. As shown in Lessons-35 & 36, only three output points are brought out from a
three-phase inverter-bridge. These output points are connected to the three supply terminals of
the load. Such an arrangement does not cause any confusion for the delta connected load but for
a star connected load the neutral point remains floating. However for a balanced, three-phase,
star-connected load this should not be a drawback as the fundamental component in the load
phase voltage is identical to the fundamental component of inverters pole voltage. In fact, the
floating neutral point has the advantage that no zero sequence current (which includes dc, third
and integer multiples of third harmonics) will be able to flow through the load and hence even if
the pole voltage is distorted by, say, 3
rd
and integral multiples of third harmonics the load side
phase and line voltages will not be affected by these distortions. The Sine+3
rd
harmonic PWM
technique is a modification over the SPWM technique discussed in Lesson-37 wherein
deliberately some amount of third harmonic voltage is introduced in the pole voltage waveform.
Accordingly a suitable amount of third harmonic signal is added to the sinusoidal modulating
signal of fundamental frequency. Now, the resultant waveform (modified modulating signal) is
compared with the high frequency triangular carrier waveform. The comparator output is used
for controlling the inverter switches exactly as in SPWM inverter. Thus, as brought out in
Sec.37.2 of Lesson-37, the low frequency component of the pole voltage will be a replica of the
modified modulating signal provided (i) The instantaneous magnitude of the modified
modulating signal is always less than or equal to the peak magnitude of the carrier signal and (ii)
the carrier frequency is significantly higher than the frequency of modulating signal.
Accordingly, the pole voltage of Sine+3
rd
harmonic PWM inverter has same composition of
fundamental and third harmonic as in the modified modulating signal. However, as per the
earlier discussion, the third harmonic component of pole-voltage will not appear in the load
phase and line voltages. The advantage of adding small amount of third harmonic in the
modulating waveform is that it brings down the peak magnitude of the resultant modulating
waveform. The modified modulating waveform appears more flat topped than its fundamental
component. Thus if the fundamental sinusoidal modulating wave had a peak magnitude equal to
the peak magnitude of the triangular carrier wave (corresponding to modulation index m =1.0),
the addition of small percentage of 3
rd
harmonic to the fundamental wave causes the peak
magnitude of the combined signal to become lower than triangle waves peak magnitude.

Fig. 38.1: The modulating signal for Sine+3
rd
harmonic modulation
1.1547 Sin(t)
0.193 Sin(3t)
t in radians

In other words, a fundamental frequency signal having peak magnitude slightly higher than the
peak magnitude of the carrier signal, if mixed with suitable amount of 3
rd
harmonic may result in
a modified signal of peak magnitude not exceeding that of the carrier signal. Thus the peak of the
modulating signal remains lower than the peak of triangular carrier signal and still the
fundamental component of output voltage has a magnitude higher than what a SPWM can output
with m =1.0. As described earlier the load sees only the fundamental component of pole voltage
(and not the third harmonic) and thus the achievable load (output) voltage magnitude is higher
than that of SPWM inverter. It is to be noted that higher output voltage is achieved without
compromising on the quality of the output waveform. Fig. 38.1 illustrates this logic, wherein
[1.1547 Sin(t) +0.193 Sin(3t)] is the modulating waveform with a resultant peak magnitude
of just 1.0. A higher amount of third harmonic will cause the magnitude limit to be exceeded.
Thus the fundamental voltage output by the inverter employing Sine+3
rd
harmonic modulation
technique can be higher by nearly 15.47% than a simple SPWM inverter. Now let the practical
example of 400 volt rated induction motor drive considered in Sec. 38.1 be reconsidered but with
an inverter employing sine +3
rd
harmonic modulation. The maximum output voltage can now go
to 347*1.1547 volts =400 volts and the peak voltage requirement of the drive will be met.

38.3 Space Vector PWM (SV-PWM) Technique

The space vector modulation technique is somewhat similar to the Sine+3
rd
harmonic PWM
technique but the method of implementation is different. Before going into details of this
technique, it would be useful to explore the concept of voltage space-vector, in analogy with the
concept of flux space-vector as used in three-phase ac machine. The stator windings of a three-
phase ac machine (with cylindrical rotor), when fed with a three-phase balanced current produce
a resultant flux space-vector that rotates at synchronous speed in the space. The flux vector due
to an individual phase winding is oriented along the axis of that particular winding and its
magnitude alternates as the current through it is alternating. The magnitude of the resultant flux
due to all three windings is, however, fixed at 1.5 times the peak magnitude due to individual
phase windings. The resultant flux is commonly known as the synchronously rotating flux
vector.

Now, in analogy with the fluxes, if a three phase balanced voltage is applied to the windings of a
three-phase machine, a rotating voltage space vector may be talked of. The resultant voltage
space-vector will be rotating uniformly at the synchronous speed and will have a magnitude
equal to 1.5 times the peak magnitude of the phase voltage. Fig. 38.2 (a) shows a set of three-
phase balanced sinusoidal voltages. Let these voltages be applied to the windings of a three-
phase ac machine as shown in Fig. 38.2(b). Now, during each time period of the phase voltages
six discrete time instants can be identified, as done in Fig. 38.2(a), when one of the phase
voltages have maximum positive or negative instantaneous magnitude. The resultants of the
three space-voltages at these instants have been named V
1
to V
6.
The spatial positions of these
resultant voltage space-vectors have been shownin Fig. 38.2(b)
.
At these six discrete instants,
these vectors are aligned along the phase axes having maximum instantaneous voltage. As shown
in Fig. 38.2(a) the magnitude of these voltage vectors is 1.5 times the peak magnitude of
individual phase voltage.
The instantaneous voltage output from a 3-phase inverter, discussed in earlier lessons, cannot be
made to match the three sinusoidal phase voltages of Fig. 38.2(a) at all time instants. This is so
because the inverter outputs are obtained from rectangular pole voltages and contain, apart from
the fundamental, harmonic voltages too. However, the instantaneous magnitudes of the inverter
outputs and the sinusoidal voltages can be made to match at the six discrete instants (talked
above) of the output cycle. At these six discrete instants one of the phase voltages is at its
positive or negative peak magnitude and the other two have half of the peak magnitude. The
polarity of the peak phase-voltage is opposite to that of the other two phase-voltages. A similar
pattern is seen in the instantaneous phase voltages output by a 3-phase inverter and is explained
below.
Fig. 38.3 shows a three-phase voltage source inverter whose output terminals are fed to the three
terminal of a three-phase ac machine (in fact to any three-phase balanced load). From the
knowledge of 3-phase voltage source inverters, it may be obvious that the two switches of each
inverter pole conduct in a complementary manner. Thus the six switches of the three poles will
have a total of eight different switching combinations. Out of these eight combinations, two
combination wherein all the upper switches or all the lower switches of each pole are
simultaneously ON result in zero output voltage from the inverter. These two combinations are
referred as null states of the inverter. The remaining six switching combinations, wherein either
two of the high side (upper) switches and one of the low side (lower) switch conduct, or vice-
versa, are active states. During the six active states the phase voltages output by the inverter to a
balanced 3-phase linear load are as detailed in Sec.35.1 of Lesson 35. Accordingly instantaneous
magnitude of two of the phase voltages are 1/3
rd
E
dc
and the third phase voltage is 2/3
rd
E
dc

(where E
dc
is the dc link voltage). The voltage polarities of the two phases getting 1/3
rd
E
dc
are
identical and opposite to the third phase having 2/3
rd
E
dc
. Fig. 38.3 also shows, in a tabular form,
the instantaneous magnitudes of the three load-phase voltages (normalized by the dc link voltage
magnitude) during the six active states of the inverter. The switching states of the inverter have
been indicated by a 3-bit switching word. The 1
st
(MSB) bit for leg A, 2
nd
bit for leg B and 3
rd

bit for leg C. When a particular bit is 1, the high (upper) side switch of that leg is ON and when
the bit is 0, the low side switch is ON. Thus a switching word 101 indicates that high side
switches of legs A and C and low side switch of leg B conduct. The resulting voltage
pattern is identical to the voltage pattern of space voltage vector V
1
of Fig. 38.2 provided 2/3
rd

E
dc
equals the peak magnitude of phase voltage in Fig. 38.2. The table given in Fig. 38.3 shows
how six active states of the inverter produce space voltage vectors V
1
to V
6
that can be identified
on one to one basis with the six voltage vectors of Fig. 38.2. There are some important
differences between the resultant space voltage vectors due to the sinusoidal phase voltages of
Fig. 38.2 and the space voltage vectors formed by the inverter output voltages. These are
described in the next section.

Fig. 38.2: The concept of voltage space-vectors: (a) 3-phase balanced voltages
(b) The voltage space-vectors

A
B
C
V
2
V
1 V
3
V
4
V
5
V
6
n
t in
rad/sec
V
An V
Bn
V
Cn
V
1 V
6
V
5
V
4
V
2
V
3
(a) (b)

Fig. 38.3: Space vectors output by a 3-phase voltage source inverter
Q
AU
A
B
C
Q
AL
Q
BL
Q
BU
Q
CU
Q
CL
E
DC
+
_

Switch
states
v
An
v
Bn
v
Cn
001
101 100 110 010 011
(V
6
) (V
1
) (V
2
) (V
3
) (V
4
) (V
5
)
-1/3
-1/3
2/3
1/3

1/3

-2/3

1/3
-2/3
1/3
2/3
-1/3
-1/3
-1/3
2/3
-1/3
-2/3
1/3
1/3
38.3.1 Smoothly Rotating Space Voltage Vector From Inverter

The continuously varying sinusoidal waveforms, as shown in Fig. 38.2, result in a space voltage
vector of fixed magnitude rotating at fixed (synchronous) speed in the space. If the inverter could
have produced ideal sinusoidal 3-phase voltages, the resultant space voltage vector would have
also moved smoothly in space with constant magnitude and constant angular speed. However by
now the reader would know that the practical power electronic inverter could never produce the
perfectly ideal sinusoidal voltages. In fact when the inverter switches from one active state to
another, the space voltage vector changes its direction abruptly, the abrupt change in direction
being in multiples of 60 electrical degrees. If at a time only one bit of the inverter switching
word changes (i.e., only one leg of the inverter changes the switching state) the abrupt change in
space vector direction is by 60 electrical degrees.
Knowing that the inverter cannot produce ideal sinusoidal voltage waveforms, a good PWM
inverter aims to remove low frequency harmonic components from the output voltage at the cost
of increasing high frequency distortion. The high frequency ripple in the output voltage can
easily be filtered by a small external filter or by the load inductance itself. In terms of voltage
space vectors the above trade-off between low and high frequency ripples means that the
resultant voltage vector will have two components; (i) a slowly moving voltage vector of
constant magnitude and constant speed superimposed with (ii) a high frequency ripple
component whose direction and magnitude changes abruptly.

The space-vector PWM technique aims to realize this slowly rotating voltage space vector
(corresponding to fundamental component of output voltage) from the six active state voltage
vectors and two null state vectors. The active state voltage vectors have a magnitude =E
dc
and
they point along fixed directions whereas null state vectors have zero magnitude. Fig. 38.4 shows
the voltage space-vector plane formed by the active state and null state voltage vectors. The null
state voltage vectors V
7
and V
8
are each represented by a dot at the origin of the voltage space
plane. The switching word for V
7
is 000, meaning all lower side switches are ON and for V
8
is
111, corresponding to all upper side switches ON. The active-state voltage space vectors point
along directions shown previously in Fig. 38.2(b). A regular hexagon is formed after joining the
tips of the six active voltage vectors. The space-plane of Fig. 38.4 can be divided in six identical
zones (I to VI). The output voltage vector from the inverter (barring high frequency
disturbances) should be rotating with fixed magnitude and speed in the voltage plane. Now it is
possible to orient the resultant voltage space-vector along any direction in the space plane using
the six active vectors of the inverter. Suppose one needs to realize a space voltage vector along a
direction that lies exactly in the center of sector-I of the space-plane shown in Fig.38.4. For this
the inverter may be continuously switched (at high frequency) between V
1
and V
2
active states,
with identical dwell time along these two states. The resultant vector so realized will occupy the
mean angular position of V
1
and V2 and the magnitude of the resultant vector can be found to be
0.866 times the magnitude of V
1
or V
2
(being the vector sum of 0.5 V
1
and 0.5 V
2
). Further, the
magnitude of the resultant voltage vector can be controlled by injecting suitable durations of null
state.

Fig. 38.4: The voltage space-vectors output by a 3-phase inverter
(100) V
2
V
1 V
3
V
4
V
5
V
6
(010)
(001)
(101) (110)
(011)
I
II

III
IV
V

VI
V
7
V
8

In general both magnitude and direction control of the resultant voltage vector can be achieved
by properly controlling the dwell times of two adjacent active voltage vectors and null voltage
vectors. The two active state vectors chosen are the ones that define the boundary of the space-
plane sector in which the desired resultant vector lies. The following illustrative example may be
helpful.

Example:

Let us assume that a resultant vector V
X
of magnitude (E
dc
), lying in sector-I and making an
angle from active vector V
1
is to be realized (Fig. 38.5). Let us further assume that T
S
is the
sampling time for which the desired vector V
X
may be assumed to be stationary in space along
the described direction. Now as per the above discussion the desired vector is to be realized
using active vectors V
1
, V
2
and null vectors V
7
, V
8
. Let the respective dwell time along these
vectors be t
1
, t
2
, t
7
and t
8
such that

t
1
+t
2
+t
7
+t
8
=T
S
----------------------------------------------- (38.1)

Fig. 38.5: The voltage space-vectors output by a 3-phase inverter
(100)

Now the resultant space vector V
X
is the vector sum of ( )
1
1
S
t
V
T
and (
2
2
S
t
V
T
) , where V
1
and V
2
are space vectors, each having magnitude E
dc
. Thus, according to vector algebra,
(
1 2
S S
t t
Cos Cos
3
T T

= +
)
-------------------------------- (38.2)

and
(
1 2
S S
t t
Sin Sin
3
T T

=
)
------------------------------- (38.3)

From Eqns. (38.2) and (38.3), one can determine the fraction of sampling time during which the
inverter is along active states V
1
and V
2
.

Sector-I

V
X
V
2
V
1
(101)
Accordingly,
( ) ( )
( )
( )
1
S
Sin
t
3
T
Sin Cos Sin Cot
3 3
= =

+
-------------------- (38.4)

and
( ) ( ) ( )
( )
2
S
t Sin
T
Sin Cos Cot Sin
3 3 3

= =

+
----------- (38.5)

The total null duration is generally equally divided between t
7
and t
8
and hence
( )
( )
1 2
7 8
S S
Sin Sin
t t
3
t t 0.5 1 0.5 0.5
T T
Sin
3

+

= = =

------------ (38.6)
Knowing the magnitude factor and the angular position the inverter switching-pattern is
determined as per the above equations. Along any fixed direction , the magnitude of the
voltage space vector is controlled by controlling the null duration time. For maximum magnitude
along a particular direction the null vector duration must be zero. Thus, from Eqn. (38.6) one can
determine the maximum possible voltage magnitude factor
max
along as
( )
( )
max
Sin
3
Sin Sin
3
+
-------------------------------- (38.7)
As is varied in the range 0
3
, the minimum magnitude of

max
is encountered at
6
= and equals 0.866. Thus to have a rotating space voltage vector (fundamental component)
of uniform magnitude over the whole voltage space-plane, the upper limit on the voltage vector
magnitude will be 0.866 E
dc
. The tip of the corresponding space voltage vector falls on the
interior circle of the hexagon in Fig. 38.4. It may be recalled that the SPWM technique can
output maximum (corresponding to modulation index =1.0) voltage space vector magnitude
=
dc
dc
E
1.5 0.75E
2
= , where
dc
E
2
is the peak magnitude of fundamental phase voltage (Lesson-37)
and the factor 1.5 is due to the resultant of the three phases. Thus space-vector PWM technique
can output 1.1547 (=0.866/0.75) times more voltage, exactly as in Sine+3
rd
harmonic modulation
technique discussed in the beginning of this lesson (section 38.2).

38.3.2 Algorithm For Producing Sinusoidal Output Voltages Using
SV-PWM

As would be clear from the discussions in the above sections, the SV-PWM is concerned with
the control of inverter output voltages in a unified manner. It does not control the individual
phase voltages separately. The instantaneous magnitude and direction of the desired resultant
voltage vector is decided as per the frequency and magnitude of inverters fundamental output
voltage. The SV-PWM is best realized with the help of a digital computing device, like
microprocessor or Digital Signal Processor. The algorithm to be executed is outlined below:
(1) Get the input data like; input dc link voltage (E
dc
), desired output frequency f
OP
(this
will determine the speed of the resultant voltage vector), desired phase sequence of
output voltage (will determine which way, clockwise or anticlockwise, the resultant
voltage vector is moving), desired magnitude of output voltage and the desired switching
frequency. It will be shown later that the switching frequency (f
SW
) and sampling time
period (T
S
) are related. During each sampling time period three switching take place,
where one turn-on and one turn-off is taken as one switching.
(2) Calculate magnitude factor from the knowledge of input dc link voltage and the
desired output voltage ( E
dc
=3/2 times peak of phase voltage). Also, calculate the
sampling time period T
S
=1/(3 f
SW
).
(3) Initialize sector position =I, and angle =0. Assume the rotating space voltage vector
to remain stalled at this position for the sampling time period T
S
. Calculate the time
duration for active and null state vectors as per Eqns. (38.4) to (38.6). Output the inverter
switching pulses as per the calculated time durations so as to realize the space vectors in
the following sequence: V
8
(111), V
1
(101), V
2
(100), V
7
(000).
(4) Calculate the next position angle
S OP old
2T f = + for clockwise rotation in the vector
space-plane of Fig. 38.4. The reader should be able to work out the changes when the
rotation is anti-clock wise. Recalculate the time durations as in step (3) above but this
time the switching sequence will be V
7
(000), V
2
(100), V
1
(101), V
8
(111).
(5) Step (4) is to be repeated but every time the switching sequence alternates between the
sequences given in steps 4 and 5. This helps in reducing the switching losses. The reader
may note that this way there are only 3 switching per sampling period. The switching to
next space vector involves change of only one bit of the switching word (i.e., only one
turn-on and one turn-off). When the space vector enters sector-II (for ), the
vector V
/3
1
is replace by V
2
and V
2
is replaced by V
3
. At the same time, angular position is
reset to a value within by subtracting 60 degrees from the old value. Every
time the voltage vector enters a new sector the angle is readjusted so that it varies
between 0 and 60 degrees. The active state vectors are also reassigned as described
above. The process continues to produce a continuously rotating voltage space vector of
fixed magnitude and fixed speed.
/3 0

38.4 Some Other Popular PWM Techniques

By now the readers must be familiar with sine-PWM (SPWM), sine +3
rd
harmonic PWM and
space vector PWM (SV-PWM) techniques. In the following sections two more PWM techniques
are briefly touched upon. These are (i) selective harmonic elimination technique and (ii) current
controlled PWM (CCPWM) technique.

38.4.1 Selective Harmonic Elimination Technique

In Lesson-36 (sections 36.1 and 36.2) it was shown that some selected harmonics could be
eliminated from the inverter output voltage by introducing notches at suitable time instants
(angles) in the pole voltage waveform. To eliminate more number of unwanted harmonics from
the output one needs to have more notches per output cycle. For the required magnitude of
output voltage and frequency and the inverters dc bus voltage, these notch angles need to be
calculated off-line using digital computer and later used for generating the switching sequence.
The notch angle information for all three phases taken together can be converted into a matrix of
switching word for the inverter. The consecutive switching word information at short and regular
time interval (in time steps of, say, 10 microseconds) is stored for a full output cycle in
consecutive locations of a memory device, like, EPROM. To output the proper switching signal
these stored values are output sequentially by sequentially incrementing the address word of the
EPROM. The time rate at which the address changes should be identical to the time rate at which
the information was stored. The switching word information is then converted into gate control
signals for the inverter switches. As the inverters input and output parameters change, the
switching matrix changes too. For an inverter producing variable voltage, variable frequency
output the total requirement of memory size becomes large. However the cost of memory chips
is coming down and hence the scheme is one of the preferred PWM schemes.

38.4.2 Current Controlled PWM (CCPWM) Technique

In this technique, reference load current (as desired by the user) signals are generated and the
inverter switches are controlled so that the actual inverter phase currents match these within
tolerable error limits. The scheme requires current sensors to sense actual phase currents. For a
three-phase load, sensing two phase-currents suffices as the third phase current can be obtained
by algebraic manipulation of the other two. The actual currents are compared with the
corresponding reference currents to generate the required switching action. Most often hysteresis
type bang-bang controllers are used. To increase the magnitude of current leaving the inverter
pole (and entering the load terminal), the high side switch of the particular pole is turned on.
Conversely the low side switch is turned on to decrease the magnitude of load current. Turning
of high side switch causes input dc voltage to support the load phase current. The load phase
current flows against the input dc voltage when low side switch is ON. The control actions for
individual legs are generally independent of each other but the rate at which current changes in
one leg may get affected by the switching state of the other legs. The control required is simple
and the load current is directly controlled, hence the name CCPWM. The necessity of two
numbers of fast current sensors may be seen as a drawback but current sensor costs are coming
down and most inverter circuits employ current sensors, any way, for protection against over-
current. Another draw back of the scheme may be associated with the hysteresis controller, if
used. The switching frequency of such controllers becomes dependent on load parameters and
may not remain optimum for the given load. There are, however, other control schemes for
CCPWM inverter where the switching frequency can remain fixed in spite of load parameter
changes.

Quiz problems

1. For a dc link voltage of 142 volts, which of the following PWM schemes can produce
good quality line voltage (free from lower order harmonics) of 95 volts (rms) and 50 Hz.
(a) Sine PWM
(b) Sine+3
rd
harmonic PWM
(c) Space vector PWM
(d) all the above

2. The third harmonic component in the pole voltages of a 3-phase inverter, connected to a
balanced 3-phase load, affects:
(a) load-phase voltage
(b) load-line voltage
(c) load-phase current
(d) none of the above

3. An inverter designed to work with fixed input dc voltage is fed with a fluctuating dc
voltage. The basic controller for the following PWM scheme can still be used to output
good quality current of constant magnitude:
(a) Sine
(b) (b) Sine+3
rd
Harmonic
(c) (c) Space Vector
(d) (d) Current Controlled PWM

4. With 283 volts dc link voltage connected to a 3-phase inverter what maximum phase
voltage (rms magnitude) of good quality can be output by Sine PWM and Space Vector
PWM:
(a) 50 and 75 volts
(b) 100 and 115 volts
(c) 141 and 200 volts
(d) 200 and 282 volts

Answers: 1-b & c, 2-d, 3-d, 4-b.
Instructional Objectives
Study of the following:
The circuit for single-phase Current Source Inverter (CSI) using thyristors
Auto-Sequential Commutated mode of operation for 1-ph. Inverter (ASCI), with waveforms
Three-phase Current Source Inverter (CSI) circuit and operation, with waveforms

Introduction
In the previous six (5.1-5.6) lessons in this module, the circuit and operation of single-phase
and three-phase Voltage Source Inverters (VSI), with waveforms, were described in detail. Also,
the presence of harmonics in voltage waveforms, along with its reduction mainly by Pulse Width
Modulation (PWM) techniques, was presented. Presently, mainly self-commutated switching
devices, like say transistors, are used in the above circuits, replacing thyristors, with bulky
commutation circuits needed to turn them OFF, these being force-commutated ones. In the last
two (5.7-5.8) lessons in this module, the circuit and operation of different types of single-phase
and three-phase Current Source Inverters (CSI), with waveforms, will be described in detail. The
device used here is thyristor. In this lesson (5.7), initially, the circuit of single-phase CSI will be
presented. The Auto-Sequential Commutated mode of operation for this Inverter (ASCI), using
thyristors, will be discussed in detail, with waveforms. Then, the circuit and operation of three-
phase CSI, along with relevant waveforms, will be presented. Finally, the advantages and
disadvantages of CSI over VSI, in brief, are described
For the VSI, as the full form denotes, the output voltage is constant, with the output current
changing with the load type, and/or the values of the components. But in the CSI, the current is
nearly constant. The voltage changes here, as the load is changed. In an Induction motor, the
developed torque changes with the change in the load torque, the speed being constant, with no
acceleration/deceleration. The input current in the motor also changes, with the input voltage
being constant. So, the CSI, where current, but not the voltage, is the main point of interest, is
used to drive such motors, with the load torque changing.
Keywords: Single-phase and Three-phase Current Source Inverter (CSI), ASCI mode of
operation, CSI using thyristors
Current Source Inverter
Single-phase Current Source Inverter

a
b
L'
+
V
S
I
a
b
Th
1 Th
2
Th
3
Th
4
+
+
-
-
I
I
I
I
D
1 D
2
D
4
D
3
Load (L)

C
1
= C/2
C
2
= C/2
Fig. 39.1: Single phase current source inverter (CSI) of ASCI type.

The circuit of a Single-phase Current Source Inverter (CSI) is shown in Fig. 39.1. The type
of operation is termed as Auto-Sequential Commutated Inverter (ASCI). A constant current
source is assumed here, which may be realized by using an inductance of suitable value, which
must be high, in series with the current limited dc voltage source. The thyristor pairs, Th
1
& Th
3
,
and Th
2
& Th
4
, are alternatively turned ON to obtain a nearly square wave current waveform.
Two commutating capacitors C
1
in the upper half, and C
2
in the lower half, are used. Four
diodes, D
1
D
4
are connected in series with each thyristor to prevent the commutating capacitors
from discharging into the load. The output frequency of the inverter is controlled in the usual
way, i.e., by varying the half time period, (T/2), at which the thyristors in pair are triggered by
pulses being fed to the respective gates by the control circuit, to turn them ON, as can be
observed from the waveforms (Fig. 39.2). The inductance (L) is taken as the load in this case, the
reason(s) for which need not be stated, being well known. The operation is explained by two
modes.

T/2 T
0
T/2 T
0
T/2 T
0
i
g3
i
g1
,
i
g2
,
i
g4
v
C
0
t
t
2
t
1
I
i
0
-I
I i
C1
i
D1 i
D2
-I
Th
1
& Th
3
triggered
Th
2
& Th
4
triggered
Th
1
& Th
3
triggered
i
01
,
i
D
Fig. 39.2: Voltage and current waveforms
T/2
T/2
T
V
Co
-V
Co
T
0

Mode I: The circuit for this mode is shown in Fig. 39.3. The following are the assumptions.
Starting from the instant, , the thyristor pair, Th
= 0 t
2
& Th
4
, is conducting (ON), and the
current (I) flows through the path, Th
2
, D
2
, load (L), D
4
, Th
4
, and source, I. The commutating
capacitors are initially charged equally with the polarity as given, i.e., . This
mans that both capacitors have right hand plate positive and left hand plate negative. If two
capacitors are not charged initially, they have to pre-charged.
0 2 1 C C C
V v v = =

I
a
b
Th
1 Th
2
Th
3
Th
4
+
+
-
-
I
I
I
I
D
1 D
2
D
4
D
3
L
C
1
=C/2
I
e
f
c d
h g
I
Fig. 39.3: Mode I (1 phase CSI)
C
2
=C/2

At time, t = 0, thyristor pair, Th
1
& Th
3
, is triggered by pulses at the gates. The conducting
thyristor pair, Th
2
& Th
4
, is turned OFF by application of reverse capacitor voltages. Now,
thyristor pair, Th
1
& Th
3
, conducts current (I). The current path is through Th
1
, C
1
, D
2
, L, D
4
,
C
2,
Th
3
, and source, I. Both capacitors will now begin charging linearly from ( ) by the
constant current, I. The diodes, D
0 C
V
2
& D
4
, remain reverse biased initially. The voltage, across
D
1 D
v
1
, when it is forward biased, is obtained by going through the closed path, abcda
as It may be noted the voltage across load inductance, L is zero
(0), as the current, I is constant. So,
( )

= + 0 ) 2 / /( 1
1
dt I C V v
co D
+ = dt I C V v
co D
) / 2 (
1

As the capacitor gets charged, the voltage across D
1 D
v
1
, increases linearly. At some time,
say t
1
, the reverse bias across D
1
becomes zero (0), the diode, D
1
.starts conducting. An identical
equation can be formed for diode, D
3
also. Actually, both diodes, D
1
& D
3
, start conducting at the
same instant, t
1
. The time t
1
for which the diodes, D
1
& D
3
, remain reverse biased is obtained by
equating, ( 0 / ) 2 (
1 1
) = + = C t I V v
co D
. The time is given by, ( )
0 1
) 2 /(
C
V I C t = . The
capacitor voltages , appear as reverse voltage across the thyristors, Th
C C C
v v v = =
2 1
2
& Th
4
,
when the thyristors, Th
1
& Th
3
, are triggered. The value of is
C
v
+ = = = dt I C V v v v
co C C C
) / 2 (
2 1
, which, if computed at
1
t t = , comes out as,
( ) ( ) ( ) 0 ) 2 /( / ) 2 ( / ) 2 ( ) (
0 1 1 2 1
= + = + = = =
C co co C C C
V I C C I V C t I V t v v v ,
using the value of t
1
obtained earlier. This means that the voltages across C
1
& C
2
, varies linearly
from to zero in time, t
0 C
V
1
. Mode I ends, when
1
t t = , and 0 =
C
v . Note that t
1
is the circuit
turn-off time for the thyristors.

I
a
b
Th
1 Th
2
Th
3
Th
4
I
i
0
D
1 D
2
D
4
D
3
L
i
C2

I
e
f
c d
h g
i
C1

Fig. 39.4(a): Mode II (1-phase CSI)
C
1
=C/2
C
2
=C/2
+
-
+
-

I
a
b
i
0
I
e (g)
f (h)
c
d
L
i
e

I C
Fig. 39.4(b): Equivalent circuit for mode II
+ -

Mode II: The circuit for this mode is shown in Fig. 39.4a. Diodes, D
2
& D
4
, are already
conducting, but at , diodes, D
1
t t =
1
& D
3
, get forward biased, and start conducting. Thus, at the
end of time t
1
, all four diodes, D
1
D
4
conduct. As a result, the commutating capacitors now get
connected in parallel with the load (L). For simplicity in analysis, the circuit is redrawn as
shown in Fig. 39.4b, where the equivalent capacitor is , as 2 / C C C C = =
2 1
. The equation for
the current at the node is, ) (
2 1 0 C C C
i i i i I + = = + , where, 2 /
2 1 C C C
i i i = = The voltage balance
equation is,

+ = = = dt i I C dt i C
t d
i d
L
C
) ( ) / 1 ( ) / 1 (
0
0

or,
C
I
C
i
dt
i d
L = +
0
2
0
2
or,
) ( ) (
0
2
0
2
C L
I
C L
i
dt
i d
+
or, I i
dt
i d
C L = +
0
2
0
2
) (
The solution of the equation is, K t B t A i + + = ) ( sin ) ( cos
0 0 0
,
where, A, B & K are constants, natural frequency,
( ) ) ( ) 2 ( / 1
0
C L f = , ) ( / 1 ) 2 (
0 0
C L f = = , and time period,
) ( ) 2 ( / ) 2 ( / 1
0 0
C L f T = = = .
The initial conditions at t = 0 are, I i =
0
and 0 /
0
= dt i d . It should be noted that the time, t is
measured from the instant, the diodes, D
1
& D
3
, start coducting, i.e., from the instant, mode I is
over. Using the initial conditions stated earlier, the current is, ( ) 1 ) ( cos 2
0 0
= t I i . The
capacitor current is ) ( cos 2
0 0
t I i I i
C
= + = .
The voltage across capacitor is, ) ( sin
2 1
0
0
t
C
I
dt i
C
v
C C

= =

.
This expression can also be obtained as,
( ) ) ( sin ) ( ) 2 ( ) / (
0 0 0
t L I dt i d L v v
L C
= = = , where, ) /( 1
0 0
C L = , as can be
derived using ) ( / 1
0
C L = . So, the above expressions are same, and can be written as,
( ) ) ( sin ) / ( ) 2 (
0
t C L I v
C
= , substituting the expression for
0
in any of the above
expressions. So, ) ( cos
0 2 1
t I i i
C C
= = , and
( 1 ) ( cos
0 1 1
= = t I i I i
C D
) , in the interval
2
0 t t < < .
As the current, tends to reverse, diode, D
1 C
i
3
prevents its reversal. Similarly, the diode, D
4

prevents the reversal of the current, . From the initiation of mode II, a time, t
2 C
i
2
must elapse for
the current, to become zero (0). The time, is,
1 C
i
2
t
( ) 4 / ) 4 /( 1 ) ( ) 2 / ( / ) 2 / (
0 0 2
T f C L t = = = = , as ) 2 / ( ) (
2 0
= t , using,
0 ) ( cos
2 0 1
= = t I i
C
. The capacitor voltage at time, is,
2
t ( )
0 0
) /( ) 2 (
C C
V C I v = = . Note
that this is also the maximum value. Now, the load current is, I I i = = ) 1 2 (
0
. This shows that
the load current has reversed from +I to I during mode II, after time, t
2
. It is also seen that the
capacitor voltage changes by (from
0
2
C
V
0 C
V to ) during each commutation interval. The
time , after substituting , comes out as,
0 C
V
1
t
0 C
V
( ) ( ) ( ) ) ( / 1 ) /( ) 2 ( 2 /( 2 /(
0 0 0 1
C L C I I C V I C t
C
= = = = .
The total commutation interval is, ( ) ( ) ) ( ) 2 / ( 1 / ) 2 / ( 1
0 2 1
C L t t t
c
+ = + = + = .
At the end of the process, constant current flows in the path, Th
1
, D
1
, load (L), D
3
, Th
3
, and
source, I. This continues till the next commutation process is initiated by the triggering of the
thyristor pair, Th
2
& Th
4
.
The complete commutation process is summarized here. The process (mode I) starts with the
triggering of the thyristor pair, Th
1
& Th
3.
Earlier, the thyristor pair, Th
2
& Th
4
were conducting.
With the two commutating capacitors charged earlier with the polarity as shown (Fig. 39.3), the
conducting thyristor pair, Th
2
& Th
4
turns off by the application of reverse voltage. Then, the
voltages across the capacitors decrease to zero at time, (end of mode I), as constant (source)
current, I flows in the opposite direction. Mode II now starts (Fig. 39.4a), as the diodes, D
1
t
1
& D
3
,
get forward biased, and start conducting. So, all four diodes D
1
-D
4
, conduct, and the load
inductance, L is now connected in parallel with the two commutating capacitors. The current in
the load reverses to the value I, after time, (end of mode II), and the two capacitors also are
charged to the same voltage in the reverse direction, the magnitude remaining same, as it was
before the start of the process of commutation (t = 0). It may be noted that the constant current, I
flows in the direction as shown, a part of which flows in the two capacitors.
2
t
In the above discussion, one form of load, i.e. inductance L only, has been considered. The
procedure remains nearly same, if the load consists of resistance, R only. The procedure in mode
I, is same, but in mode II, the load resistance, R is connected in parallel with the two
commutating capacitors. The direction of the current, I remains same, a part of which flows in
the two capacitors, charging them in the reverse direction, as shown earlier. The derivation,
being simple, is not included here. It is available in books on this subject.
Three-phase Current Source Inverter

i
A
i
B
i
C
L
L
L
R
R
R
N
Th
6
Th
5 Th
3
Th
1
C
1 C
3
C
5
D
1
D
3
D
5
A
B
C
C
4 C
6
C
2
D
4
D
6
D
2
Th
2 4
Th
V
dc
Fig. 39.5(a): Three-phase current source inverter (CSI)
+
-
X
Y
The circuit of a Three-phase Current Source Inverter (CSI) is shown in Fig. 39.5a. The type
of operation in this case is also same here, i.e. Auto-Sequential Commutated Inverter (ASCI). As
in the circuit of a single-phase CSI, the input is also a constant current source. The output current
(phase) waveforms are shown in Fig. 39.5b. In this circuit, six thyristors, two in each of three
arms, are used, as in a three-phase VSI. Also, six diodes, each one in series with the respective
thyristor, are needed here, as used for single-phase CSI. Six capacitors, three each in two (top
and bottom) halves, are used for commutation. It may be noted that six capacitors are equal, i.e.
. The diodes are needed in CSI, so as to prevent the capacitors from
discharging into the load. The numbering scheme for the thyristors and diodes are same, as used
in a three-phase VSI, with the thyristors being triggered in sequence as per number assigned
(Fig. 39.5b).
C C C C = = = =
6 2 1


120
180 300
360

0
i
A
-I
I
60
0
I
B
-I
I
120
240
360
300
60
0
I
C
-I
I
180
240 360
Th
1
Th
2
Th
3
Th
4
Th
5
Th
6
Th
5
Th
6
Th
1
Th
2
Th
3
Th
4
Th
1
Th
5
Th
1
Th
1
Th
3
Th
3
Th
5
Th
5
Th
6
Th
2
Th
2
Th
4
Th
4
Th
6
Th
1
Th
6
60 120 180 240 300 360
0
on
off
Thyristors conducting
Fig. 39.5(b): Phase current waveforms

The commutation process in a three-phase CSI is described in brief. The circuit, when two
thyristors, Th
1
& Th
2
, and the respective diodes, are conducting, is shown in Fig. 39.6a. The
current is flowing in two phases, A & C. The three capacitors in the top half, are charged
previously, or have to pre-charged as shown. But the capacitors in the bottom half are not shown.

Th
3
C
1
D
1
Th
5 Th
1
C
3
C
5
D
3
D
5
D
2
Th
2
I
I
I
I
A A
C
B
+ +
+ -
-
-
Fig. 39.6(a): Three-phase CSI with two thyristors, Th
1
& Th
2
conducting
L
I (i
C
)
I (i
A
)
X
Y
+
-

Mode I: The commutation process starts, when the thyristor, Th
3
in the top half, is triggered, i.e.
pulse is fed at its gate. Immediately after this, the conducting thyristor, Th
1
turns off by the
application of reverse voltage of the equivalent capacitor. Mode I (Fig. 39.6b) now starts. As the
diode D
1
is still conducting, the current path is via Th
3
, the equivalent capacitor, D
1
, and

the load
in phase A (only in the top half). The other part, i.e. the bottom half and the source, is not
considered here, as the path there remains same. The current, I from the source now flows in the
reverse direction, thus the voltage in the capacitor, C
1
(and also the other two) decreases. It may
be noted the equivalent capacitor is the parallel combination of the capacitor, C
1
and the other
part, being the series combination of the capacitors, C
3
& C
5
( 2 / C C = ). It may be shown the its
value is , parallel combination of C & , as 3 / C C
eq
= 2 / C C C C C = = =
5 3 1
. Also, the current
in the capacitor, C
1
is , and the current in other two capacitors, C I ) 3 / 2 (
3
& C
5

is . When
the voltage across the capacitor, C
3 / I
1
(and also the other two) decreases to zero, the mode I ends.


Th
3
C
1
D
1
Th
5
Th
1
C
3
C
5
D
3
D
5
D
2
Th
2
I
I
I
I
A
C
+ +
+
-
- -
Fig. 39.6(b): Mode I (3-phase CSI)
B
L
2I/3
I/3
I
I/3
X
Y
I (i
A
)
I (i
C
)

Mode II: After the end of mode I, the voltage across the diode, D
3
goes positive, as the voltage
across the equivalent capacitor goes negative, assuming that initially (start of mode I) the voltage
was positive. It may be noted that the current through the equivalent capacitor continues to flow
in the same direction. Mode II (Fig. 39.6c) starts. Earlier, the diode, D
1
was

conducting. The
diode, D
3
now

starts conducting, with the voltage across it being positive as given earlier. A
circulating current path now exists between the equivalent capacitor, two conducting diodes, D
1

& D
3
and the load (assumed to be inductive R & L, per phase) of the two phases, A & B, the
two loads and also the two diodes being now connected in series across the equivalent capacitor.
The current in this path is oscillatory, and goes to zero after some time, when the mode II ends.
The diode, D
1
turns off, as the current goes to zero. So, at the end of mode II, the thyristor, Th
3
&
the diode, D
3
conduct. This process has been described in detail in the earlier section on single-
phase CSI (see mode II). It may be noted that the polarity of the voltage across the equivalent
capacitor (at the end of mode II) has reversed from the initial voltage (at the beginning of mode
I). This is needed to turn off the outgoing (conducting) thyristor, Th
3
, when the incoming
thyristor, Th
5
is triggered. The complete commutation process as described will be repeated. The
diodes in the circuit prevent the voltage across the capacitors discharging through the load.

C
1
D
1
Th
5
Th
1
C
3
D
3
D
5
D
2
Th
2
I
I
I
A
+
+ - -
Fig. 39.6(c): Mode II (3-phase CSI)
B
Th
3
C
I
L
C
5
+
-
X
Y
+
-
i
A
I (i
C
)
i
B

The circuit is shown in Fig. 39.6d, with two thyristors, Th
3
& Th
2
, and the respective diodes
conducting. The current now flows in two phases, B & C, at the end of the commutation process,
instead of phase A at the beginning (Fig. 39.6a). It may be noted the current in the bottom half
(phase C) continues to flow, and also the thyristor, Th
2
& the diode, D
2
remain in conduction
mode. This, in brief, is the commutation process, when the thyristor, Th
3
is triggered and the
current is transferred to the thyristor, Th
3
& the diode, D
3
(phase B),

from the thyristor, Th
1
& the
diode, D
1
(phase A).

Th
3
C
1
D
1
Th
5
Th
1
C
3
C
5
D
3
D
5
D
2
Th
2
I
I
I
I
A
C
+ +
+
-
- -
Fig. 39.6(d): Three-phase CSI with two thyristors, Th
3
& Th
2
conducting
B
I
L
+
-

Comments
In the introductory remarks, one merit of CSI has been stated, i.e. it can be used for the speed
control of ac, specially induction, motors subject to variation in load torque. In recent years,
self-commutated power switching devices, such as power transistors etc., are being used in VSI,
but not costly inverter-grade thyristors (having low turn-off time), along with bulky commutation
circuits. These circuits also need additional diodes for feeding the reactive power back to the
supply, when used with heavily inductive loads. The advantages and disadvantages of CSI vis--
vis VSI are given.
Advantages
1. The circuit for CSI, using only converter grade thyristor, which should have reverse blocking
capability, and also able to withstand high voltage spikes during commutation, is simple.
2. An output short circuit or simultaneous conduction in an inverter arm is controlled by the
controlled current source used here, i.e., a current limited voltage source in series with a
large inductance.
3. The converter-inverter combined configuration has inherent four-quadrant operation
capability without any extra power component.
B
C
I (i
C
)
I (i
B
)
Y
Disadvantages
1. A minimum load at the output is required, and the commutation capability is dependant upon
load current. This limits the operating frequency, and also puts a limitation on its use for UPS
systems.
2. At light loads, and high frequency, these inverters have sluggish performance and stability
problems.
In this lesson the seventh one of this module, the current source inverter (CSI) vis--vis
VSI, is introduced. The commutation process for Auto-Sequential Commutated Inverter (ASCI)
mode of operation in single-phase CSI, is mainly described, along with circuit diagram and
relevant waveforms, in detail. Then, the commutation process for the same mode of operation,
i.e. ASCI, in three-phase CSI, is described, along with various circuit diagrams, in brief. Finally,
the advantages and disadvantages of CSI over VSI, are presented. In the next lesson, eighth and
last one, of this module, the load-commutated CSI, and also the Pulse Width Modulation (PWM)
techniques used in CSI, will be discussed.

Instructional Objectives
Study of the circuit and operation for Load-commutated Current Source Inverter (CSI)

Introduction
In the last lesson (5.7) seventh one in this module, the circuit and operation of single-phase
and three-phase Current Source Inverters (CSI), with relevant waveforms, have been described in
detail. The device used is thyristor. The type is the Auto-Sequential Commutated Inverter
(ASCI). In this lesson (5.8) eighth and final one in this module, the circuit and operation of
load-commuted CSI, including waveforms, will be presented in detail.
Keywords: Load-commutated current source inverter (CSI)
Load-Commutated CSI
In the last lesson, ASCI mode of operation for a single-phase Current Source Inverter (CSI)
was presented. Two commutating capacitors, along with four diodes, are used in the above
circuit for commutation from one pair of thyristors to the second pair. Earlier, also in VSI, if the
load is capacitive, it was shown that forced commutation may not be needed. The operation of a
single-phase CSI with capacitive load (Fig. 40.1) is discussed here. It may be noted that the
capacitor, C is assumed to be in parallel with resistive load (R). The capacitor, C is used for
storing the charge, or voltage, to be used to force-commutate the conducting thyristor pair as will
be shown. As was the case in the last lesson, a constant current source, or a voltage source with
large inductance, is used as the input to the circuit.

I
a
b
Th
1
Th
2
Th
3
Th
4
+ -
V
in
i
Load (R)
C
c
-
+
d
v
0
= v
C
i
C
Fig. 40.1: Load-commuted CSI
i

The power switching devices used here is the same, i.e. four thyristors only in a full- bridge
configuration. The positive direction for load current and voltage, is shown in Fig. 40.1. Before t
=0, the capacitor voltage is , i.e. the capacitor has left plate negative and right plate
positive. At that time, the thyristor pair, Th
1
V v
C
=
2
& Th
4
was conducting. When (at t =0), the thyristor
Load-commutated Current Source Inverter (CSI)
pair, Th
1
& Th
3
is triggered by the pulses fed at the gates, the conducting thyristor pair, Th
2
&
Th
4
is reverse biased by the capacitor voltage
1
V v
C
= , and turns off immediately. The current
path is through Th
1
, load (parallel combination of R & C),

Th
3
, and the source. The current in the
thyristors is , the output current is I i i
Th Th
= =
3 1
I i
ac
= ; the capacitor voltage, changes from
to , as the capacitor gets charged by the current during the time, . The
load voltage is . Thus, the waveform of the current,
C
v
1
V
1
V
C
i 0 ) 2 / ( > > t T
C
v v =
0
) / ( ) / (
0 0
R v R v i
C
= = through load
resistance, R has the same nature as that of (Fig. 40.2). Similarly, when (at ), the
thyristor pair, Th
C
v 2 / T t =
2
& Th
4
is triggered by the pulses fed at the gates, the conducting thyristor pair,
Th
1
& Th
3
is reverse biased by the capacitor voltage
1
V v
C
= , and turns off immediately. The
current path is through Th
2
, load (parallel combination of R & C),

Th
4
, and the source. The
current in the thyristors is I i i
Th Th
= =
4 2
, but the output current is ; the capacitor
voltage, changes from to , as the capacitor gets charged by the current during the
time, .
I i
ac
=
C
v
1
V
1
V
C
i
) 2 / (T t T > >

i
g1,
i
g3
i
g2,
i
g4
0 T/2 T
0 T/2 T t
i
Th3
i
Th1,
I
0
T/2 T
T/2 T
0
I
1,
V
1
-I
1,
-V
1,
v
0,
i
0
T/2 T
0
V
1
-V
1
v
in
I+I
1
T/2 T
0
I-I
1
-(I+I
1
)
-(I-I
1
)
i
C
0 T/2 T
v
Th1,
v
Th3
V
1
-V
1
i
Th2,
i
Th4
I
T/2 T
0
T/2 T
0
i
ac
I
-I
Th
1
, Th
3
Th
2
, Th
4
Th
1
, Th
3
triggered
Th
1
, Th
3
triggered
Th
2
, Th
4
triggered
Fig. 40.2: Voltage and current waveforms.

Various current and voltage waveforms during one cycle , are shown in Fig. 40.2.
At t =0, the capacitor voltage is
0 > > t T
1
V v
C
= , then
1 0
V v v
C
= = , and the load current through R is
. As stated earlier, during the time , the capacitor gets charged,
with its voltage changing from
1 1 0
) / ( I R V i = = 0 ) 2 / ( > > t T
1
V to . So, At
1
V 2 / T t = , the load current is
. The input voltage is
1 1 0 0
) / ( ) / ( ) / ( I R V R v R v i
C
= = = =
0
v v
in
= , during , and
, during .
0 ) 2 / ( > > t T
0
v v
in
= ) 2 / (T t T > >
It may be observed that, when the thyristor pair, Th
1
& Th
3
is conducting for ,
the currents are leaving node A (Fig. 40.1), and the current, I is entering node A.
Therefore, the equivalent circuit for , is shown in Fig. 40.3a. The current in node
A, is or, . At t =0,
0 ) 2 / ( > > t T
0
, i i
C
0 ) 2 / ( > > t T
I i i
C
= +
0 0
i I i
C
=
1 0
I i = , and
1
I I i
C
+ = . The mathematical steps for a
steady solution of the output current, and other parameters, such as input voltage etc., are given
later. J ust after (T/2), when the thyristor pair, Th
2
& Th
4
is conducting, the currents are
entering node B (Fig. 40.1), and so also the current, I. The equivalent circuit for ,
is shown in Fig. 40.3b. The current in node B is
0
, i i
C
) 2 / (T t T > >
0
0
= + + I i i
C
or, ) (
0
i I i
C
+ = . At t =(T/2),
, and . The cycle repeats itself.
1 0
I i = ) (
1
I I i
C
+ =

V
1
d (b)

C
-
+
i
C
v
0
= v
C
R

i
0
I

c (a)

(a)

I

V
1
d (b)

C
-
+
i
C
v
0
= v
C R
i
0
I

c (a)

(b)

I

Fig. 40.3: (a) Equivalent circuit for 0 < t < T/2
(b) Equivalent circuit for T/2 < t < T

The steps to be followed to find the expression of the output current, and other parameters
are described. The voltage balance equation for the equivalent circuit (Fig. 40.3a) is,

= + 0 ) ( ) / 1 (
1 0 0
v dt i I C i R
Differentiating it, we get
C
I
C
i
dt
i d
R = +
0 0

Solving it, with the initial condition for as given earlier,
0
i
( )
) /(
1
) /(
0
1
C R t C R t
e I e I i

=
To arrive at a steady solution only, the following steps are followed. At t =(T/2), the current is
, as shown later. So,
1 0
I i = ( )
) 2 /(
1
) 2 /(
1
1
C R T C R T
e I e I I

=
or, I
e
e
I I
C R T
C R T
=
=

) 2 /(
) 2 /(
1
1
1
, if ( ) 1 ) 2 /( >> C R T or, ) ( C R T >>
So, using the above expression, the output current, or the current in resistance, R comes out as,
( )
=

) 2 /(
) /(
0
1
2
1
C R T
C R t
e
e
I i
The output voltage , or the capacitor voltage is,
0
v
C
v
( )
= = =

) 2 /(
) /(
0 0
1
2
1 ) (
C R T
C R t
C
e
e
I R R i v v
The turn-off time provided by the circuit for each thyristor is obtained from the condition that,
when ,
OFF
t t = 0
0 0
= = = R i v v
C
. So,
( )
/( )
0 0 /(2 )
2
( ) 1
1
OFF
t R C
C T R C
e
v v i R R I
e

= = = =
+

0
2

or,
( )
/( ) /(2 )
1 /
OFF
t R C T R C
e e

= +
or,
( )
/(2 )
/(2 )
2
( ) log ( ) log 1 / 2
1
T R C
OFF e e T R C
t R C R C e
e

= = +

+

The average value of the input voltage, is,
in
V
( )
dt
e
e
T
R I
dt R i
T
V
T
C R T
C R t T
in

=

2 /
0
) 2 /(
) /( 2 /
0
0
1
2
1
2
) (
2 /
1

or,

=

) 2 /(
) 2 /(
1
1 4
1 ) (
C R T
C R T
in
e
e
T
C R
R I V
When the input power ( ) is positive, power is delivered to the load. I V
in

The following points may be noted.
1. It may be observed from the equation given earlier that, as the inverter frequency ( T f / 1 = )
is increased, the turn-off time provided by the circuit decreases. But, the circuit commutation
time, , should be more than the turn-off time of the thyristor, , for reliable operation.
This means that there is an upper limit to the inverter frequency, beyond which the thyristors
in the inverter circuit will fail to commutate.
off
t
q
t
2. When the inverter frequency ( T f / 1 = ) is low, or time period, T is high, the graph of
or as given in Fig. 40.2, becomes flatter as shown by dotted line in Fig. 40.4. As this
graph is nearer to a square wave, it can be inferred that, for low inverter frequencies, the
inverter has square wave output for load current or load voltage ( ).
0
( ) i t
0
( ) v t
0 0
/ i v
When the inverter frequency ( T f / 1 = ) is high, or time period, T is low, the waveform
of or is shown by full line in Fig. 40.4. As this graph is closer to a sine wave, it can be
noted that, for higher frequency, the CSI has sinusoidal wave shape for load (output) current
or voltage.
0
v
0
i

Fig. 40.4: Waveforms for CSI with resistive (R) load
Small T
T
t
v
0
, i
0
Large T
T/2

(a) Square wave output: It has been found that, for obtaining square wave of the load current,
. If is the turn-off time for the thyristors used in CSI, then form the
equation given earlier,
0 . 5 ) 2 /( > C R T
q
t
( ) ) ( 69 . 0 2 log ) ( ) 1 /( 2 log ) (
5
C R C R e C R t
e e q
= + =

or, ) 69 . 0 /( R t C
q
=
For or , the maximum frequency is, 0 . 5 ) 2 /( = C R T C R T 10 =
) 10 /( 1 / 1
max
C R T f = =
Substituting the value of obtained earlier, C
q
t f / 069 . 0
max
=
(b) Sinusoidal wave output: For obtaining sinusoidal wave of the load current, the capacitive
reactance, at three times the minimum frequency, , should be lower than , i.e.,
C
X
min
f 2 / R
at ,
min
3f
min
1
2 3 2
C
R
X
f C
= ,
or
min)
/( 106 . 0 f R C
The inverter should therefore be operated at frequencies higher than in order to obtain
the sinusoidal wave shape.
min
f
In this lesson (5.8) eighth and final one in this (last) module (5), the circuit and operation,
of load-commuted CSI, including waveforms, are discussed in detail. In this module (5), mainly
two types of dc-ac converters, termed as inverters Voltage Source (VSI) and Current Source
(CSI), have been presented. Both single-phase and three-phase inverters have been described,
with relevant waveforms. Starting with the use of Pulse Width Modulation (PWM) techniques,
used for voltage control in VSI, other variations, such as Sine PWM, have been taken up.
Incidentally, this is the last lesson for the course on Power Electronics.

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After completion of this lesson the reader will be able to:

(i) Identify the essential components of a voltage source inverter.

. The two switches of the inverter leg are turned on in a complementary

is the frequency (f) of the square wave. f also

and the nth harmonic voltage (n being odd

, for 0 <t <0.5T ....(34.7)

, for 0.5T <t <T

, for 0.5T <t <T ............... (34.8)

+ respectively. A close look at Eqn. 35.12 will reveal that for a

, the minimum magnitude of

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