ECE 428 Final Project Instruction

1. Design Objective
In this project, a biquad low-pass filter is to be implemented on XILINX FPGA prototpe
board! "he filter#s transfer function and bloc$ dia%ram are shown in below!
&n' ( -)!*+,-./&n-+' 0 )!1-23.&n-*' 4 )!-11,.&n--'
Fi%ure *5 6iquad low-pass filter bloc$ dia%ram
"he filter input, output and coefficients are all 7-bit fi/ed-point two#s complementar
numbers! Also, all the numbers are normali8ed such that each number is within the ran%e
from 4* to *! "he two#s complementar number representation of the filter coefficients are
listed in the followin% table!
"able *5 9oefficient representation
9oefficient :ecimal -#s 9omplement ;e/
a* -)!*+,- <<
b* )!1-23 =*
b- -)!-11, :<
-! Design Considerations
-!*Data truncation
"he first desi%n issue that needs to be addressed in our desi%n is data truncation! For
e/ample, when multiplication is performed for two 7-bit numbers the product is *=-bit!
>hen, the *=-bit product is added with an 7-bit ?or *=-bit@ number, the summation can be
*1-bit! Aou need deBelop a strate% to perform data truncation in our desi%n! Aou also
need state the reason for ou to ta$e our selected truncation approach! A simple truncation
mechanism is %iBen below!
Truncation example5 "wo#s complement ei%ht bit multipliers can be used to implement
the multiplication! ;oweBer, since this produces a number %reater than ei%ht bits roundin%
: : : &n' /&n'
b* b-
a*
or truncation can ta$e place after the multiplication to brin% the result bac$ to ei%ht bits! A
simple wa to truncate is to just drop the least si%nificant bits! "his allows for the use of
ei%ht bit adders!
Another truncation strate% is to $eep all the bit durin% computation and perform truncation
at the final output of the filter ?which is a more reasonable approach in this small filter
circuit@! "he adBanta%e is reduced truncation error with increased hardware comple/it!
Also, durin% truncation, ou can simpl drop the least si%nificant bits as mentioned aboBeC
or ou can appl the same principle as we normall do when we round decimal numbers
?when it is %reater than )!=, we round it to *@!

2.2Overflow and underflow

"he second desi%n issue is how to handle oBerflow ?and underflow@ since the data width is
fi/ed in our desi%n! Aou ma e/pect that all final and intermediate results should with a
certain ran%e! For e/ample, ou ma e/pect that all the numbers produced b our
hardware are within the ran%e from 4* to *! ;oweBer, if a result e/ceeds this ran%e,
oBerflow occurs! In our desi%n, ou must haBe some mechanisms to handle oBerflow! A
simple strate% is described as follows! Assume two numbers A and 6 are added, and the
summation is D! Also, assume the ran%e for the summation is from 4* to *! If DE*, we can
force D(*! Fn the other hand, if DG-*, we let D( 4*! A possible hardware implementation
of the aboBe mechanism and more detail discussion is %iBen below!

Overflow (and underflow) example5 >hen wor$in% with two#s complement numbers the
onl time we mi%ht %et an error output is if both Balues are ne%atiBe and the Balue is
smaller than it is possible to represent with ei%ht bits, or both Balues are positiBe and the
Balue is lar%er than it is possible to represent with ei%ht bits! In these cases the Balue
wanted should be either the most positiBe or most ne%atiBe possible! Hsin% the oBerflow
bit and a si%n bit as the selection to a mu/ the appropriate Balue can be obtained! A bloc$
dia%ram can be seen in fi%ure -!
Fi%ure -5 Adder with FFIHF hardware
. Design !erfor"ance evaluation and function verification
First, after the placement and routine, ou need run static timin% analsis and find out its
critical path dela! Accordin%l, ou can estimate the ma/imum cloc$ frequenc of the
filter! Aou can also tr to use Barious techniques includin% user constraints to improBe the
reali8ed ma/imum cloc$ frequenc! :ocument our efforts on improBin% circuit
performance and hi%hli%ht how much improBement is achieBed b these efforts!
"he circuit function eBaluation is done b circuit simulation! First ou can choose = or 1
Balues ?filter input@ that will be passed throu%h the circuit and calculate b hand what the
output should be! Fne of these Balues needs to be handled as underflow and another needs
to be handled as oBerflow! "hese results should be mar$ed as such in the simulation! >hen
finished the simulation results will need to be submitted alon% with the hand calculations
indicatin% the e/pected outputs!
In addition to the aboBe eBaluation, ou also need to run simulation in which the filter is
used to filter out noise associated with a sinusoidal waBeform! In the simulation, filter input
and filter outputs are stored in separate te/t files! A simple testbench and filter input si%nal
file can be downloaded from the class website! Also, matlab codes can be downloaded to
plot and perform FF" for the filter input and output si%nals! Fi%ure + and 2 show the filter
input and its spectrum plot! If our filter implementation is correct, the e/pected filter
output waBeform and its FF" plots should be similar to Fi%ure = and 1!
Fi%ure + Filter input waBeform! Fi%ure 2 FF" plot of the filter input!
Fi%ure = Filter output waBeform! Fi%ure 1 FF" plot of the filter output!