Instruksi Allen Bradley PLC

Allen-Bradley
PLC-5
Programmable
Controllers
Instruction
Set Reference
Important User Information
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PLC-5 Instruction Set Alphabetical Listing

For this
Instruction:
See Page:
For this
Instruction:
See Page:
For this
Instruction:
For this
Instruction:
See Page:
See Page:
ABL
17-51
CMP
3-3
JSR
13-12
RES
2-25
ACB
17-71
COP
9-20
LBL
13-5
RET
13-12
ACI
17-91
COS
4-211
LEQ
3-9
RTO
2-13
ACN
17-101
CPT
4-5
LES
3-10
SBR
13-12
ACS
4-131
CTD
2-20
LFL
11-51
SDS
18-2
ADD
4-14
CTU
2-18
LFU
11-51
SFR
13-231
AEX
17-111
DDT
10-2
LIM
3-11
SIN
4-271
AFI
13-19
DEG
6-51
LN
4-231
SQI
12-2
SQL
12-2
AHL
17-12
DFA
18-3
LOG
4-241
AIC
17-141
DIV
4-22
MCR
13-3
SQO
12-2
AND
5-2
DTR
10-8
MEQ
3-13
SQR
4-28
ARD
17-151
EOT
13-24
MOV
7-4
SRT
4-291
ARL
17-181
EQU
3-6
MSG
16-2
STD
4-311
ASC
17-211
FAL
9-2
MUL
4-25
SUB
4-34
ASN
4-151
FBC
10-2
MVM
7-5
TAN
4-351
ASR
17-221
FFL
11-5
NEG
4-26
TND
13-19
ATN
4-161
FFU
11-5
NEQ
3-15
TOD
6-3
AVE
4-171
FLL
9-21
NOT
5-4
TOF
2-9
AWA
17-231
FOR
13-8
NXT
13-8
TON
2-5
AWT
17-261
FRD
6-4
ONS
13-20
UID
13-251
BRK
13-8
FSC
9-15
OR
5-6
UIE
13-261
BSL
11-2
GEQ
3-7
OSF
13-221
XIC
1-3
BSR
11-2
GRT
3-8
OSR
13-211
XIO
1-4
BTD
7-2
IDI
1-102
OTE
1-5
XOR
5-8
XPY
4-361
BTR
15-4
IDO
1-11
OTL
1-6
BTW
15-4
IIN
1-8
OTU
1-7
CIO
15-252
IOT
1-9
PID
NO TAG
CLR
4-20
JMP
13-5
RAD
6-61
Enhanced PLC -5 processors

only.
6200 programming software
with ControlNet PLC-5
processors only
1785-6.1 November 1998
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Table A
Choosing an Instruction Category
If You Want to Perform
this Operation:
Use this Instruction Category:
examine, check or control
2-state device or condition

multiple 2-state devices or conditions
bit level
multi-bit
move, copy, change,

compute, compare
analog values, codes

multiple sets of values
element level
file instructions
convert
conversion instructions
time or delay
timer
count
counter
shift or track
bit shift
sequence
sequencer
PID
PID
message sending/receiving
message
transfer data to/from modules
block transfer or ControlNet transfer
diagnostics, fault handling
diagnostics
control the flow of your program program control
Table B
Example Operations
If Your Application Calls for Operations such as:
Use:
detecting when a limit switch closes
bit level
changing the temperature preset
element level
transfer analog data
block transfer
turn on a motor 10 seconds after a pump is activated
timing
move 1 of 3 recipes into a work area
multi-element
keep track of parts as they move from station to station shifting

keep track of total parts in a bin
1785-6.1 November 1998
counting
Summary of Changes
Summary of Changes
New Information Added to
this Manual
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PDQXDO VLQFH WKH ODVW SULQWLQJ
For this Update Information:
See Chapter:
Converting non-decimal numbers with the FRD instruction
How non-existing, indirect addresses affect the COP and

FLL instructions
How the .POS value operates in sequencer instructions
12
Using a RET instruction
13
Using the PID bias term
14
Using the no zero crossing (.NOZC) and no back calculation

(.NOBC) features in the PD control block
14
Clarification to error code 89 for MSG instruction
16
Ethernet PLC-5 processors now support SLC Typed Read and

SLC Typed Write MSG instructions
16
Configuring a multihop MSG instruction over Ethernet or

over ControlNet
16
Monitoring the status of the .EN bit in a continuous

MSG instruction
16
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1785-6.1 November 1998
Summary of Changes
1RWHV
1785-6.1 November 1998
Preface
Preface
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Conventions
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References to:
Include these Allen-Bradley Processors:
Classic PLC-5 processors
PLC-5/10, -5/12, -5/15, -5/25, and -5/VME processors.
Enhanced PLC-5 processors
PLC-5/11, -5/20, -5/30, -5/40, -5/40L, -5/60,

-5/60L, and -5/80 processors.
Note: Unless otherwise specified, Enhanced PLC-5 processors include
Ethernet PLC-5, ControlNet PLC-5, Protected PLC-5 and VME PLC-5
processors.
Ethernet PLC-5 processors
PLC-5/20E, -5/40E, and -5/80E processors.
ControlNet PLC-5 processors
PLC-5/20C, -5/40C, -5/46C, and -5/80C processors.
Protected PLC-5 processors 1
PLC-5/26, -5/46, and -5/86 processors.
VME PLC-5 processors
PLC-5/V30, -5/V40, -5/V40L, and -5/V80 processors. See the

PLC-5/VME VMEbus Programmable Controllers User Manual for more
information.
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1785-6.1 November 1998
Preface
1RWHV
1785-6.1 November 1998
Table of Contents
Relay-Type Instructions
XIC, XIO, OTE, OTL, OTU, IIN, IOT,
IDI, IDO
Timer Instructions TON, TOF,

RTO Counter Instructions CTU,
CTD Reset RES
Chapter 1
Using Relay-Type Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-1
I/O Image Files in Data Storage . . . . . . . . . . . . . . . . . . . . . 1-2
Rung Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Examine On (XIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Examine Off (XIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Energize (OTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Latch (OTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Unlatch (OTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Immediate Input (IIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Immediate Output (IOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Immediate Data Input (IDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Immediate Data Output (IDO) . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Using IDI and IDO Instructions . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Chapter 2
Using Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Using Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Timer Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Timer On Delay (TON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Timer Off Delay (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Retentive Timer On (RTO) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Count Up (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Count Down (CTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timer and Counter Reset (RES). . . . . . . . . . . . . . . . . . . . . . 2-20
1785-6.1 November 1998
toc2
Table of Contents
Compare Instructions
CMP, EQU, GEQ, GRT, LEQ, LES, LIM,
MEQ, NEQ
Compute Instructions
CPT, ACS, ADD, ASN, ATN, AVE,
CLR, COS, DIV, LN, LOG, MUL, NEG,
SIN, SRT, SQR, STD, SUB, TAN, XPY
1785-6.1 November 1998
Chapter 3
Using Compare Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Compare (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Entering the CMP Expression. . . . . . . . . . . . . . . . . . . . . . . 3-2
Determining the Length of an Expression. . . . . . . . . . . . . . 3-3
Equal to (EQU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than or Equal to (GEQ). . . . . . . . . . . . . . . . . . . . . . . . 3-5
Greater than (GRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than or Equal to (LEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Less than (LES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Limit Test (LIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Mask Compare Equal to (MEQ) . . . . . . . . . . . . . . . . . . . . . . . 3-9
Not Equal to (NEQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Chapter 4
Using Compute Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Data Types and the Compute Instruction . . . . . . . . . . . . . . . . 4-3
Using Floating Point Data Types . . . . . . . . . . . . . . . . . . . . . . 4-4
Compute (CPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Entering the CPT Expression . . . . . . . . . . . . . . . . . . . . . . . 4-5
Determining the Length of an Expression. . . . . . . . . . . . . . 4-7
Determining the Order of Operation . . . . . . . . . . . . . . . . . . 4-8
Expression Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Entering the Destination . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Using CPT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Arc Cosine (ACS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Addition (ADD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Arc Sine (ASN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Arc Tangent (ATN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Average File (AVE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Clear (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Cosine (COS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Divide (DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Natural Log (LN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
Log to the Base 10 (LOG). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Multiply (MUL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Negate (NEG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Sine (SIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Square Root (SQR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Table of Contents
toc3
Sort File (SRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

Standard Deviation (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28
Subtract (SUB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Tangent (TAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
X to the Power of Y (XPY). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
Logical Instructions
AND, NOT, OR, XOR
Conversion Instructions
FRD and TOD, DEG and RAD
Bit Modify and Move Instructions

BTD, MOV, MVM
File Instruction Concepts
Chapter 5
Using Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 5-1
AND Operation (AND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
NOT Operation (NOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
OR Operation (OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Exclusive OR Operation (XOR) . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Chapter 6
Using the Conversion Instructions . . . . . . . . . . . . . . . . . . . . . 6-1
Using Arithmetic Status Flags . . . . . . . . . . . . . . . . . . . . . . 6-1
Convert to BCD (TOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Convert from BCD (FRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Degree (DEG)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-3
Radian (RAD)
(Enhanced PLC-5 Processors Only) . . . . . . . . . . . . . . . . . . . . 6-4
Chapter 7
Using Bit Modify and Move Instructions . . . . . . . . . . . . . . . . . 7-1
Bit Distribute (BTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Move (MOV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Masked Move (MVM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Chapter 8
Concepts of File Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Using the Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Manipulating File Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Choosing Modes of Block Operation . . . . . . . . . . . . . . . . . . . 8-5
All Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Numerical Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Incremental Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Special Case, Numerical Mode with Words Per Scan = 1. . 8-8
1785-6.1 November 1998
toc4
Table of Contents
File Instructions
FAL, FSC, COP, FLL
Diagnostic Instructions
FBC, DDT, DTR
Shift Register Instructions

BSL, BSR, FFL, FFU, LFL, LFU
Sequencer Instructions
SQO, SQI, SQL
1785-6.1 November 1998
Chapter 9
Using File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
File Arithmetic and Logic (FAL) . . . . . . . . . . . . . . . . . . . . . . . 9-2
FAL Copy Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
FAL Arithmetic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Upper and Lower Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
FAL Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
FAL Convert Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
File Search and Compare (FSC) . . . . . . . . . . . . . . . . . . . . . . 9-14
FSC Search and Compare Operations . . . . . . . . . . . . . . . . . 9-17
Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Search Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
File Copy (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
File Fill (FLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Chapter 10
Using Diagnostic Instructions . . . . . . . . . . . . . . . . . . . . . . . 10-1
File Bit Comparison (FBC) and Diagnostic Detect (DDT) . . . . 10-2
Selecting the Search Mode . . . . . . . . . . . . . . . . . . . . . . . 10-2
One Mismatch at a Time . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
All Per Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Data Transitional (DTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Chapter 11
Applying Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Using Bit Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Using FIFO and LIFO Instructions . . . . . . . . . . . . . . . . . . . . . 11-5
Chapter 12
Applying Sequencers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Using Sequencer Instructions . . . . . . . . . . . . . . . . . . . . . . . 12-2
Resetting the Position of SQO . . . . . . . . . . . . . . . . . . . . . 12-6
Using SQI Without SQO . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
Table of Contents
Program Control Instructions MCR,

JMP, LBL, FOR, NXT, BRK, JSR,
SBR, RET, TND, AFI, ONS, OSR, OSF,
SFR, EOT, UIE, UID
Process Control Instruction PID
toc5
Chapter 13
Selecting Program Flow Instructions . . . . . . . . . . . . . . . . . . 13-1
Master Control Reset (MCR) . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Jump (JMP) and Label (LBL) . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Using JMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Using LBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
For Next Loop (FOR, NXT), Break (BRK) . . . . . . . . . . . . . . . . 13-5
Using FOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Using BRK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Using NXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
Jump to Subroutine (JSR), Subroutine (SBR),
and Return (RET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Passing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Nesting Subroutine Files . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Using JSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using SBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Using RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Temporary End (TND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Always False (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
One Shot (ONS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
One Shot Rising (OSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
One Shot Falling (OSF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Sequential Function Chart Reset (SFR). . . . . . . . . . . . . . . . 13-17
End of Transition (EOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
User Interrupt Disable (UID) . . . . . . . . . . . . . . . . . . . . . . . . 13-19
User Interrupt Enable (UIE). . . . . . . . . . . . . . . . . . . . . . . . . 13-20
Chapter 14
Using PID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
PID Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Using PID Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Conversion of Gain Constants . . . . . . . . . . . . . . . . . . . . . 14-3
Integral Term Implementation . . . . . . . . . . . . . . . . . . . . . 14-3
Derivative Term . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Setting Input/Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Implementing Scaling to Engineering Units . . . . . . . . . . . . . 14-5
Setting the Dead Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Using No Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Selecting the Derivative Term (Acts on PV or Error) . . . . . . . 14-7
1785-6.1 November 1998
toc6
Table of Contents
Setting Output Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

Using Output Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Anti-Reset Windup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Using a Manual Mode Operation (Bumpless Transfer) . . . 14-8
Set Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Feedforward or Output Biasing . . . . . . . . . . . . . . . . . . . . . . 14-9
Resume Last State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
PID Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Using No Back Calculation. . . . . . . . . . . . . . . . . . . . . . . 14-11
Operational Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Integer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
PD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Using an Integer Data File Type for the Control Block. . . . . 14-14
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-16
Using a PD File Type for the Control Block . . . . . . . . . . . . . 14-18
Using Control Block Values . . . . . . . . . . . . . . . . . . . . . . 14-23
Programming Considerations . . . . . . . . . . . . . . . . . . . . . . 14-25
Run Time Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25
Transferring Data to the PID Instruction . . . . . . . . . . . . . 14-25
Loop Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Number of PID Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Loop Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26
Descaling Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
PID Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Integer Block (N) Examples . . . . . . . . . . . . . . . . . . . . . . . . 14-29
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
PD Block Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
Main Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
STI Program File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34
RTS Program File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36
Ladder Logic Simulation of a Manual Control Station . . . 14-37
Cascading Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Ratio Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38
Process Variable Tracking . . . . . . . . . . . . . . . . . . . . . . . 14-39
PID Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40
1785-6.1 November 1998
Table of Contents
Block-Transfer Instructions
BTR and BTW and ControlNet I/O
Transfer Instruction CIO
toc7
Chapter 15
Using Block Transfer and ControlNet I/O
Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Using Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . 15-1
Block-Transfer Read (BTR) and Block-Transfer Write (BTW). 15-3
Block-Transfer Request Queue . . . . . . . . . . . . . . . . . . . . 15-3
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Requested Word Count (.RLEN) . . . . . . . . . . . . . . . . . . . . 15-8
Transmitted Word Count (.DLEN) . . . . . . . . . . . . . . . . . . . 15-8
File Number (.FILE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Element Number (.ELEM). . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 15-10
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 15-12
Block Transfer Timing Classic PLC-5 Processors . . . . . . 15-13
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Waiting Time in the Queue. . . . . . . . . . . . . . . . . . . . . . . 15-13
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Block Transfer Timing Enhanced PLC-5 Processors . . . . 15-14
Instruction Run Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Waiting Time in the Holding Area . . . . . . . . . . . . . . . . . . 15-14
Transfer Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Example Bidirectional Alternating Block-Transfer. . . . . . 15-16
Example Bidirectional Alternating Repeating
Block-Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Example Bidirectional Continuous Block-Transfer . . . . . 15-18
Example Directional Non-Continuous Block-Transfer . . . 15-19
Example Directional Repeating Block Transfer . . . . . . . . 15-19
Example Directional Continuous Block-Transfer . . . . . . . 15-20
Example Buffering Block Transfer-Data . . . . . . . . . . . . . 15-21
ControlNet I/O Transfer (CIO) Instruction . . . . . . . . . . . . . . 15-22
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Using the CIO Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Using the CT Control Block . . . . . . . . . . . . . . . . . . . . . . 15-25
1785-6.1 November 1998
toc8
Table of Contents
Message Instruction MSG
Chapter 16
Using the Message Instruction. . . . . . . . . . . . . . . . . . . . . . . 16-1
Message (MSG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
Entering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
MSG Data Entry Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Using the Message Instruction for Ethernet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Using the Message Instruction for PLC-5 Ethernet Interface
Module Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Configuring an Ethernet Multihop MSG Instruction. . . . . . . . 16-9
Using the Message Instruction for ControlNet
Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Control Block Address . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
Configuring a ControlNet Multihop MSG Instruction . . . . . . 16-11
Using Status Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Error Code (.ERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Requested Length (.RLEN) . . . . . . . . . . . . . . . . . . . . . . . 16-13
Transmitted Length (.DLEN) . . . . . . . . . . . . . . . . . . . . . . 16-13
Communication Command . . . . . . . . . . . . . . . . . . . . . . 16-14
External Data Table Addresses. . . . . . . . . . . . . . . . . . . . 16-15
PLC-2 to PLC-5 Compatibility Files . . . . . . . . . . . . . . . . 16-15
Sending SLC Typed Logical Read and Typed Logical
Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
Monitoring a Message Instruction . . . . . . . . . . . . . . . . . . . 16-17
Selecting Continuous Operation. . . . . . . . . . . . . . . . . . . . . 16-18
Selecting Non-Continuous Operation . . . . . . . . . . . . . . . . . 16-19
MSG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
1785-6.1 November 1998
Table of Contents
ASCII Instructions
ABL, ACB, ACI, ACN, AEX, AIC, AHL,
ARD, ARL, ASC, ASR, AWA, AWT
Custom Application Routine

Instructions SDS, DFA
toc9
Chapter 17
Using ASCII Instructions
Enhanced PLC-5 Processors Only . . . . . . . . . . . . . . . . . . . . 17-1
Using the Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Length (.LEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Position (.POS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Using Strings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Test Buffer for Line (ABL) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Number of Characters in Buffer (ACB) . . . . . . . . . . . . . . . . . 17-5
ASCII String to Integer (ACI) . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
ASCII String Concatenate (ACN) . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII String Extract (AEX) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
ASCII Set or Reset Handshake Lines (AHL). . . . . . . . . . . . . . 17-8
ASCII Integer to String (AIC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
ASCII Read Characters (ARD). . . . . . . . . . . . . . . . . . . . . . . 17-10
ASCII Read Line (ARL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
ASCII String Search (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
ASCII String Compare (ASR). . . . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write with Append (AWA) . . . . . . . . . . . . . . . . . . . . . 17-15
ASCII Write (AWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
Chapter 18
Chapter Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
Smart Directed Sequencer (SDS) Overview . . . . . . . . . . . . . 18-2
Programming the SDS Instruction . . . . . . . . . . . . . . . . . . 18-2
Diagnostic Fault Annunciator (DFA) Overview . . . . . . . . . . . 18-3
Programming the DFA Instruction . . . . . . . . . . . . . . . . . . 18-3
1785-6.1 November 1998
toc10
Table of Contents
Instruction Timing and

Memory Requirements
SFC Reference
Appendix A-1
Instruction Timing and Memory Requirements. . . . . . . . . . . . A-1
Timing for Enhanced PLC-5 Processors. . . . . . . . . . . . . . . . . A-2
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . A-2
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
Timing for Classic PLC-5 Processors . . . . . . . . . . . . . . . . . . A-10
Bit and Word Instructions. . . . . . . . . . . . . . . . . . . . . . . . . A-10
File Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Program Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
Direct and Indirect Elements: Enhanced PLC-5 Processors . A-17
Direct and Indirect Elements: Classic PLC-5 Processors . . . A-18
Indirect Bit or Elements Addresses: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-19
Additional Timing Considerations: Classic
PLC-5 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
Appendix B-1
Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
SFC Status Information in the Processor Status File. . . . . . . . B-1
Memory Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Dynamic Constraints Classic PLC-5 Processors Only . . . . . B-5
Scanning Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Step and Transition Scanning . . . . . . . . . . . . . . . . . . . . . . B-7
Selected Branch Scanning. . . . . . . . . . . . . . . . . . . . . . . . . B-8
Simultaneous Branch Scanning . . . . . . . . . . . . . . . . . . . . . B-9
SFC Example and Scan Sequence . . . . . . . . . . . . . . . . . . B-11
Run Times Classic PLC-5 Processors . . . . . . . . . . . . . . . . B-12
Using Sequence Diagrams to Determine Run Time . . . . . B-13
Using Equations to Determine Run Time . . . . . . . . . . . . . B-14
Valid Data Types for

Instruction Operands
1785-6.1 November 1998
Appendix C-1
Appendix Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Instruction Operands and Valid Data Types . . . . . . . . . . . . . . C-1
Chapter
Relay-Type Instructions XIC, XIO, OTE,

OTL, OTU, IIN, IOT, IDI, IDO
Using Relay-Type Instructions
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WKH GDWD WDEOH VXFK DV LQSXW ELWV RU WLPHU FRQWUROZRUG ELWV 7KH UHOD\
LQVWUXFWLRQV OHW \RX
If You Want to:
Use this Instruction:
Found on Page:
Examine a bit for an ON condition
XIC
1-3
Examine a bit for an OFF condition
XIO
1-3
Hold a bit ON or OFF (non-retentive)
OTE
1-4
Latch a bit to ON (retentive)
OTL
1-4
Unlatch a bit to OFF (retentive)
OTU
1-5
Immediately update input image bits
IIN
1-6
Immediately update outputs
IOT
1-7
Immediately perform an update of

the ControlNet data input file from
the ControlNet memory buffers.
IDI
1-8
Immediately perform an update of

the ControlNet memory buffers from
the source file before the next
output-image update
IDO
1-8
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VWRUDJH EXW WKH H[DPSOHV LQ WKLV FKDSWHU RQO\ VKRZ KRZ WR DGGUHVV
ELWV LQ WKH ,2 LPDJH ILOHV
)RU PRUH LQIRUPDWLRQ RQ WKH RSHUDQGV DQG YDOLG GDWD W\SHVYDOXHV RI
HDFK RSHUDQG XVHG E\ WKH LQVWUXFWLRQV GLVFXVVHG LQ WKLV FKDSWHU VHH
$SSHQGL[ &
,I \RX XVH UHOD\W\SH LQVWUXFWLRQ 27( 27/ RU 278 ZLWK LQGLUHFW
DGGUHVVHV WR VHW RU UHVHW D ELW LQ WKH FRQWURO ILOH RI D EORFNWUDQVIHU RU
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1785-6.1 November 1998
1-2
Relay-Type Instructions XIC, XIO, OTE, OTL, OTU, IIN, IOT, IDI, IDO
I/O Image Files in Data Storage

7KH LQSXW LPDJH ILOH LQ WKH SURFHVVRU VWRUHV WKH VWDWXV RI LQSXW VHQVRUV
FRQQHFWHG WR LQSXW PRGXOH WHUPLQDOV
If the Input Sensor Is:
Then Its Corresponding Input Image Bit Is:
closed (on)
on (1)
open (off)
off (0)
<RX SURJUDP LQVWUXFWLRQV LQ ODGGHU ORJLF WR PRQLWRU ELWV 8VH D

ORJLFDO DGGUHVV IRU WKH ELW
7KH RXWSXW LPDJH ILOH FRQWUROV WKH VWDWXV RI DFWXDWRUV ZLUHG WR RXWSXW
PRGXOH WHUPLQDOV
If the Output Image Bit Is:
Then Its Corresponding Output Is:
on (1)
energized (on)
off (0)
de-energized (off)
<RX SURJUDP LQVWUXFWLRQV LQ ODGGHU ORJLF WR FRQWURO ELWV
Rung Logic
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H[DPLQHG WR VHH LI LW PDWFKHV D FHUWDLQ FRQGLWLRQ RQ RU RII ,I D
FRPSOHWH SDWK RI WUXH FRQGLWLRQV H[DPLQHG IRU DUH IRXQG WKH UXQJ
LV VHW WR WUXH 7KH UXQJ PXVW FRQWDLQ D FRQWLQXRXV SDWK RI WUXH
LQVWUXFWLRQV IURP WKH VWDUW RI WKH UXQJ WR WKH RXWSXW IRU WKH RXWSXW
WR EH HQDEOHG
1785-6.1 November 1998
1-3
Examine On (XIC)
Description:
Example:
I:012
07
If you find an ON condition at bit I:012/07 in

the input table, set this instruction true.
This bit corresponds to input terminal 7 of a
module in I/O group 2 of I/O rack 1. If the input
circuit is true, the instruction is true.
:KHQ D GHYLFH FORVHV LWV FLUFXLW WKH PRGXOH ZKRVH LQSXW WHUPLQDO LV
ZLUHG WR WKH GHYLFH GHWHFWV WKH FORVHG FLUFXLW 7KH SURFHVVRU UHIOHFWV
WKLV 21 VWDWH LQ WKH GDWD WDEOH :KHQ WKH SURFHVVRU ILQGV DQ ;,&
LQVWUXFWLRQ WKDW DGGUHVVHV WKH ELW WKDW FRUUHVSRQGV WR WKH LQSXW
WHUPLQDO WKH SURFHVVRU GHWHUPLQHV ZKHWKHU WKH GHYLFH LV 21 FORVHG
,I WKH SURFHVVRU ILQGV DQ 21 VWDWH LW VHWV WKH ORJLF IRU WKLV LQVWUXFWLRQ
WUXH LI WKH SURFHVVRU ILQGV DQ 2)) VWDWH LW VHWV WKH ORJLF IRU WKH
LQVWUXFWLRQ QRW WUXH
,I WKH ;,& LQVWUXFWLRQ LV WKH RQO\ FRQGLWLRQLQJ LQVWUXFWLRQ RQ WKH UXQJ
WKH SURFHVVRU HQDEOHV WKH RXWSXW LQVWUXFWLRQ ZKHQ WKH ;,& LQVWUXFWLRQ
LV WUXH LQSXW FORVHG 7KH SURFHVVRU GLVDEOHV DQ RXWSXW LQVWUXFWLRQ
ZKHQ WKH ;,& LQVWUXFWLRQ LV IDOVH LQSXW RSHQ
7KH H[DPLQHRQ LQVWUXFWLRQ LV WUXH RU IDOVH GHSHQGLQJ RQ ZKHWKHU WKH
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If the Bit Is:
Then the Instruction Is:
Bit Logic State:
on
true
off
false
Examine Off (XIO)

Description:
Example:
I:012
07
If you find an OFF condition at bit I:012/07 in

the input table, set this instruction true.
This bit corresponds to input terminal 7 of a
module in I/O group 2 of I/O rack 1. If the input
circuit is false, the instruction is true.
:KHQ D GHYLFH RSHQV LWV FLUFXLW WKH PRGXOH ZKRVH LQSXW WHUPLQDO LV
ZLUHG WR WKH GHYLFH GHWHFWV DQ RSHQ FLUFXLW 7KH SURFHVVRU UHIOHFWV
WKLV 2)) VWDWH LQ WKH GDWD WDEOH :KHQ WKH SURFHVVRU ILQGV DQ ;,2
LQVWUXFWLRQ WKDW DGGUHVVHV WKH ELW WKDW FRUUHVSRQGV WR WKH LQSXW
WHUPLQDO WKH SURFHVVRU GHWHUPLQHV ZKHWKHU WKH GHYLFH LV 2))
RSHQ ,I WKH SURFHVVRU ILQGV DQ 2)) VWDWH LW VHWV WKH ORJLF IRU WKLV
LQVWUXFWLRQ WUXH ,I WKH SURFHVVRU ILQGV DQ 21 VWDWH LW VHWV WKH ;,2
LQVWUXFWLRQ WR IDOVH
,I WKH ;,2 LQVWUXFWLRQ LV WKH RQO\ FRQGLWLRQLQJ LQVWUXFWLRQ RQ WKH UXQJ
WKH SURFHVVRU HQDEOHV WKH RXWSXW LQVWUXFWLRQ ZKHQ WKH ;,2 LQVWUXFWLRQ
LV WUXH LQSXW RSHQ
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SURFHVVRU ILQGV DQ 2)) RU 21 FRQGLWLRQ DW WKH DGGUHVVHG ELW
If the Bit Is:
Then the Instruction Is:
Bit Logic State:
off
true
on
false
1785-6.1 November 1998
1-4
Energize (OTE)
Description:
Example:
O:013
01
Turn ON bit O:013/01 of the output image table if

the rung is true. Turn it OFF if the rung is false.
This bit corresponds to output terminal 01 of a
module in /O group 3 of I/O rack 1.
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FRUUHVSRQGV WR DQ RXWSXW PRGXOH WHUPLQDO WKH GHYLFH ZLUHG WR WKLV
WHUPLQDO LV HQHUJL]HG ZKHQ WKH LQVWUXFWLRQ LV HQDEOHG DQG
GHHQHUJL]HG ZKHQ WKH LQVWUXFWLRQ LV GLVDEOHG ,I WKH LQSXW FRQGLWLRQV
WKDW SUHFHGH WKH 27( LQVWUXFWLRQ DUH WUXH WKH SURFHVVRU HQDEOHV WKH
27( LQVWUXFWLRQ ,I WKH LQSXW FRQGLWLRQV WKDW SUHFHGH WKH 27(
LQVWUXFWLRQ DUH IDOVH WKH SURFHVVRU GLVDEOHV WKH 27( LQVWUXFWLRQ
:KHQ UXQJ FRQGLWLRQV EHFRPH IDOVH WKH FRUUHVSRQGLQJ GHYLFH
GHHQHUJL]HV
$Q 27( LQVWUXFWLRQ LV VLPLODU WR D UHOD\ FRLO 7KH 27( LQVWUXFWLRQ LV
FRQWUROOHG E\ SUHFHGLQJ LQSXW LQVWUXFWLRQV WKH UHOD\ FRLO LV FRQWUROOHG
E\ FRQWDFWV LQ LWV KDUGZLUHG UXQJ
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If the Rung Is:
Then the Processor Turns the Bit:
Bit Logic State:
true
on
false
off
Latch (OTL)
Description:
L
Example:
O:013
L
01
Turn ON bit O:013/01 of the output image table

if the rung is true.
module in I/O group 3 of I/O rack 1.
1785-6.1 November 1998
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LQ SDLUV ZLWK DQ 278 XQODWFK LQVWUXFWLRQ ZLWK ERWK LQVWUXFWLRQV
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WHUPLQDO LV HQHUJL]HG ZKHQ WKH SURFHVVRU VHWV HQDEOHV WKH ELW LQ
SURFHVVRU PHPRU\ ,I WKH LQSXW FRQGLWLRQV WKDW SUHFHGH WKH 27/
LQVWUXFWLRQ DUH WUXH WKH SURFHVVRU HQDEOHV WKH 27/ LQVWUXFWLRQ :KHQ
UXQJ FRQGLWLRQV EHFRPH IDOVH DIWHU EHLQJ WUXH WKH ELW UHPDLQV VHW
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LQVWUXFWLRQ
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:KHQ HQDEOHG WKH ODWFK LQVWUXFWLRQ WHOOV WKH SURFHVVRU WR WXUQ RQ WKH
DGGUHVVHG ELW 7KHUHDIWHU WKH ELW UHPDLQV RQ UHJDUGOHVV RI WKH UXQJ
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LQVWUXFWLRQ LQ DQRWKHU UXQJ
If the Rung Is:
true
on
false
no change
:KHQ WKH SURFHVVRU FKDQJHV IURP 5XQ WR 3URJUDP PRGH RU ZKHQ WKH
SURFHVVRU ORVHV SRZHU DQG WKHUH LV EDWWHU\ EDFNXS WKH ODVW WUXH 27/
LQVWUXFWLRQ FRQWLQXHV WR FRQWURO WKH ELW LQ PHPRU\ 7KH ODWFKHG RXWSXW
GHYLFH LV HQHUJL]HG HYHQ WKRXJK WKH UXQJ FRQGLWLRQV WKDW FRQWURO WKH
LQVWUXFWLRQ PD\ KDYH JRQH IDOVH
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UHVHW
Unlatch (OTU)
Description:
U
Example:
O:013
U
01
Turn OFF bit O:013/01 of the output image table

if the rung is true.
module in I/O group 3 in I/O rack 1.
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SURFHVVRU ORVHV SRZHU DQG WKHUH LV EDWWHU\ EDFNXS WKH ELW LV UHWDLQHG
LQ WKH VWDWH VHW E\ WKH ODVW UXQJ RI WKH ODWFKXQODWFK SDLU WKDW ZDV WUXH
7KH XQODWFK LQVWUXFWLRQ WHOOV WKH SURFHVVRU WR WXUQ RII WKH DGGUHVVHG ELW
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If the Rung is:
true
off
false
no change
1785-6.1 November 1998
1-6
Immediate Input (IIN)

Description:
IIN
Example:
RRG
IIN
Where:
RR = I/O rack number
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20
00-07 PLC-5/25, -5/30
000-177 PLC-5/40, -5/40L
000-277 PLC-5/60, -5/60L, -5/80
G = I/O group number (0 - 7)
001
IIN
When the input conditions are true, update the

input image word corresponding to I/O rack 0,
group 1.
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LQSXWLPDJH XSGDWH
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ZKLOH WKH LQSXWV RI WKH DGGUHVVHG ,2 JURXS DUH H[DPLQHG 7KLV
VHWV WKH LQSXWLPDJH ELWV WR WKH FXUUHQW VWDWHV RI WKH LQSXWV EHIRUH
WKH SURJUDP VFDQ FRQWLQXHV ,I WKH SURJUDP UHDFKHV DQ HQDEOHG
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ILOH QXPEHU VXFK DV , 7KH SURFHVVRU LQWHUSUHWV WKH
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1785-6.1 November 1998
1-7
Immediate Output (IOT)

Description:
IOT
Example:
RRG
IOT
Where:
RR = I/O rack number
00-03 PLC-5/10, -5/11, -5/12, -5/15, -5/20
00-07 PLC-5/25, -5/30
000-177 PLC-5/40, -5/40L
000-277 PLC-5/60, -5/60L, -5/80
G = I/O group number (0 - 7)
001
IOT
When the input conditions are true, update the

output image word corresponding to I/O rack 0,
group 1.
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RXWSXW FLUFXLWV WR WKH FXUUHQW VWDWHV RI WKH RXWSXW ELWV LQ WKH RXWSXW
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UHDFKHV DQ HQDEOHG ,27 LQVWUXFWLRQ ZKLOH D EORFNWUDQVIHU LV LQ
SURJUHVV WKH SURFHVVRU FRPSOHWHV WKH EORFNWUDQVIHU EHIRUH H[HFXWLQJ
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1785-6.1 November 1998
1-8
Immediate Data Input (IDI)

Description:
IDI
IMMEDIATE DATA INPUT
Data file offset
Length
Destination
232
10
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/HQJWK VSHFLILHV WKH QXPEHU RI ZRUGV WR EH WUDQVIHUUHG DQ

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Immediate Data Output (IDO)

Description:
IDO
IMMEDIATE DATA OUTPUT
Data file offset
232
Length
10
Source
N7:232
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1785-6.1 November 1998
Using IDI and IDO Instructions
1-9
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1785-6.1 November 1998
1-10
1RWHV
1785-6.1 November 1998
Chapter
Timer Instructions TON, TOF, RTO

Counter Instructions CTU, CTD
Reset RES
Using Timers and Counters
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Table 2.A
Available Timer and Counter Instructions
If You Want to:
Found on Page:
Delay turning on an output
TON
2-4
Delay turning off an output
TOF
2-7
Time an event retentively
RTO
2-10
Count up
CTU
2-15
Count down
CTD
2-17
Reset a counter, timer, or counter

instruction
RE
2-20

$SSHQGL[ &
Using Timers
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SDUDPHWHUV WKDW \RX HQWHU IRU WLPHU LQVWUXFWLRQV DQG KRZ WLPHU
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1785-6.1 November 1998
2-2
Timer Instructions TON, TOF, RTO Counter Instructions CTU, CTD Reset RES
Entering Parameters
TON
TIMER ON DELAY
EN
Timer
Time base
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IROORZLQJ LQIRUPDWLRQ
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VWRUDJH 8VH WKH IROORZLQJ DGGUHVV IRUPDW
DN
Preset
Accum
timer structure number (0-999)

timer file number (3-999)
timer (file type)
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RWKHU WKDQ WKH GHIDXOW \RX PXVW ILUVW GHOHWH WKH
HQWLUH GHIDXOW ILOH IRU WKDW QXPEHU DQG WKHQ FUHDWH WKH
WLPHU ILOH )RU H[DPSOH LI \RX ZDQW D WLPHU ILOH QXPEHU
DV ILOH \RX PXVW ILUVW GHOHWH WKH HQWLUH GHIDXOW ELQDU\
ILOH DQG WKHQ FUHDWH WKH WLPHU ILOH DV ILOH
7R DFFHVV D WLPHU VWDWXV ELW SUHVHW RU DFFXPXODWHG YDOXH VWRUHG DW WKH
WLPHU FRQWURO DGGUHVV XVH WKH IROORZLQJ DGGUHVV IRUPDW
Status Bit
Preset
Accumulated Value
Tf:s.sb
Tf:s.PRE
Tf:s.ACC
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ELW ZRUGV LQ D WLPHU ILOH 7
15 14 13 12
T4:0
EN TT
11 10 09 08 07 06 05 04 03 02 01 00
DN
internal use only

preset value (16 bits)
Control word
for T4:0
accumulated value (16 bits)

T4:1
internal use only
EN TT DN
preset value (16 bits)

T4:2
1785-6.1 November 1998
.
.
.
Control word
for T4:1
2-3
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SRVVLEOH WLPH EDVHV
Table 1.B
Available Time Base Values
Enter This Time Base:
The Accumulated Value Range Is:
1 second
to 32,767 time-base intervals (to 9.1hours)
0.01 seconds (10ms)
to 32,767 time-base intervals (to 5.5

minutes)
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LQWHJHU
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XVLQJ D 72) LQVWUXFWLRQ 6HH SDJH IRU PRUH
LQIRUPDWLRQ
Timer Accuracy
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WLPH EDVH
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WR VHFRQGV WKH VHFRQG WLPHU PDLQWDLQV DFFXUDF\ ZLWK D SURJUDP
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WR EH OHVV WKDQ WKH SUHVHW ZKHQ WKH GRQH ELW LV VHW
1785-6.1 November 1998
2-4
Timer On Delay (TON)

Description:
TON
TIMER ON DELAY
EN
Timer
Time base
DN
Preset
Accum
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RI WKH IROORZLQJ KDSSHQV
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RXW RU QRW
Using Status Bits

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SURFHVVRU FKDQJHV WKH VWDWHV RI VWDWXV ELWV ZKHQ WKH SURFHVVRU UXQV
WKLV LQVWUXFWLRQ <RX DGGUHVV VWDWXV ELWV E\ PQHPRQLF
This Bit:
Is Set When:
Indicates:
And Remains Set Until One of the

Following Occurs:
Timer Enable.EN (bit 15)
the rung goes true
that the timer is enabled
the rung goes false

a reset instruction resets the timer
the SFC step goes inactive
Timer Timing Bit .TT (bit 14)
the rung goes true
that a timing operation is

in progress
Timer Done Bit .DN (bit 13)
the accumulated value is

equal to the preset value
that a timing operation

is complete
the rung goes false

the associated SFC step goes inactive
1785-6.1 November 1998
the rung goes false

the .DN bit is set (.ACC = .PRE)
2-5
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LV UHVWRUHG WKH IROORZLQJ KDSSHQV
Condition:
Result:
If the rung is true:
.EN bit remains set

.TT bit remains set
.DN bit remains reset
.ACC value is reset and starts counting up
If the rung is false:
.EN bit is reset

.TT bit is reset
.DN bit is reset
.ACC value is reset
Figure 2.1
Example TON Ladder Diagram
TON
I:012
TIMER ON DELAY
10
T4:0
When the input condition is true, the

processor increments the accumulated value
of T4:0 in 1-second increments.
Timer
EN
T4:0
Time base
1.0
Preset
180
Accum
Sets the output while the timer is timing
DN
O:013
TT
01
T4:0
Sets the output when the timer is done timing
O:013
DN
02
When bit I:012/10 is set, the processor starts T4:0. The accumulated value increments in 1-second intervals.
T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE) T4:0.TT is reset (so O:013/01 and the associated output device is
de-energized) and T4:0.DN is set (so O:013/02 is set and the associated output device is energized). When the
accumulated value reaches 180, the .DN bit is set. Or if the rung goes false, the timer is reset.
1785-6.1 November 1998
2-6
Figure 2.2
Example TON Timing Diagram
ON
Rung Condition
OFF
ON
Timer Enable Bit
OFF
ON
Timer Timing Bit
OFF
ON
Timer Done Bit

Output Device
(Controlled by Done Bit)
OFF
ON
OFF
3 minutes
Timer Accumulated Value

(Accumulator)
ON
Delay
2 minutes
180
120
0
Timer Preset = 180
1785-6.1 November 1998
16649
2-7
Timer Off Delay (TOF)

Description:
TOF
TIMER OFF DELAY
EN
Timer
Time base
DN
Preset
Accum
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7KH SURFHVVRU UHVHWV WKH DFFXPXODWHG YDOXH ZKHQ WKH UXQJ FRQGLWLRQV
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Using Status Bits

WKLV LQVWUXFWLRQ <RX DGGUHVV WKH VWDWXV ELWV E\ PQHPRQLF
This Bit:
Is Set When:

Following Occurs:
Timer Enable .EN (bit 15)
the rung goes true
the rung goes false

the SFC step goes inactive
the rung goes false and the

accumulated value is less than
the preset
the rung goes true
the accumulated value is equal to the

preset value
the rung goes true

the .DN bit is set (.ACC = .PRE)
1785-6.1 November 1998
2-8
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Condition:
Result:
.EN bit is set

.TT bit is reset
.DN bit remains set
.ACC value is cleared
.EN bit is reset

.TT bit is reset
.DN bit is reset
.ACC value equals PRE value
(the timer does not start timing)
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2-9
Figure 2.3
Example TOF Ladder Diagram
TOF
I:012
TIMER OFF DELAY

10
T4:0
EN
Timer
When the input goes false, the processor starts

incrementing the accumulated value in T4:0 in
1-second increments until the input goes true.
T4:0
Time base
1.0
Preset
180
Accum
Sets the output while the timer is timing
O:013
01
TT
T4:0
DN
Resets the output when the timer is done timing
O:013
DN
02
When bit I:012/10 is reset, the processor starts timer T4:0. The accumulated value increments by 1-second intervals as long as the
rung remains false. T4:0.TT is set and output bit O:013/01 is set (the associated output device is energized) while the timer is timing.
When the timer is finished (.ACC = .PRE), T4:0.TT is reset (so O:013/01 is reset and the associated output device is de-energized)
and T4:0.DN is reset (so O:013/02 is reset and the associated output device is de-energized). When the accumulated value reaches
180 or when the rung conditions go true, the timer stops.
Figure 2.4
Example TOF Timing Diagram
ON
Rung Condition
Timer Enable Bit
OFF
ON
OFF
ON
Timer Timing Bit
Timer Done Bit
OFF
ON
OFF
Output Device
ON
OFF
OFF Delay
3 minutes
2 minutes
180
Time
120
(Accumulator)
0
Timer Preset = 180
16650
1785-6.1 November 1998
2-10
Retentive Timer On (RTO)

Description:
RTO
RETENTIVE TIMER ON
EN
Timer
Time base
DN
Preset
Accum
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Using Status Bits

This Bit:
Is Set When:
Indicates:

Following Occurs:
Timer Enable Bit .EN (bit 15)
the rung goes true

in progress
the rung goes false

the rung goes true

in progress
the rung goes false

the .DN bit is set
the accumulated value is equal to
the preset value (.ACC=.PRE)
the accumulated value is

that a timing operation

is complete
the .DN bit is reset with the

RES instruction.
1785-6.1 November 1998
2-11
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Condition:
Result:
.EN bit remains set

.TT bit remains set
.ACC value continues timing
.EN bit is reset

.TT bit is reset
.DN bit remains the same
.ACC value remains the same
Figure 2.5
Example RTO Ladder Diagram
RTO
I:012
RETENTIVE TIMER ON
10
I:017
When the input is true, the processor starts incrementing

the accumulated value of T4:10 in 1-second increments.
The timer values remain when the input goes false.
Resets the timer
Timer
Time base
Preset
Accum
EN
T4:10
1.0
180
0
DN
T4:10
RES
12
1785-6.1 November 1998
2-12
Figure 2.6
Retentive Timer Timing Diagram
ON
Rung Condition
Timer Enable Bit
OFF
ON
OFF
Reset Pulse
ON
OFF
Timer Timing Bit
ON
OFF
Timer Done Bit
ON
OFF
ON
Output Device
OFF
180
120
100

(Accumulator)
40
Timer Preset = 180
1785-6.1 November 1998
16651
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Using Counters
CTU
COUNT UP
CU
Counter
Preset
Accum
2-13
DN
Entering Parameters
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GDWD VWRUDJH 8VH WKH IROORZLQJ DGGUHVV IRUPDW
f
s
counter structure number (0-999)
counter file number (3-999)

counter (file type)
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Status Bit
Preset
Accumulated Value
Cf:s.bb
Cf:s.PRE
Cf:s.ACC
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15 14 13 12
C5:0
CU
11 10 09 08 07 06 05 04 03 02 01 00
CD DN OV UN
internal use only

preset (16 bits)
Control word
for C5:0

C5:1
CU
CD DN OV UN
internal use only
Control word
for C5:1
preset (16 bits)

C5:2

..
.
1785-6.1 November 1998
2-14
1785-6.1 November 1998
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2-15
Count Up (CTU)
Description:
CTU
COUNT UP
CU
Counter
Preset
DN
Accum
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Using Status Bits

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This Bit:
Is Set:
And Remains Set Until One of the Following Occurs:
Count Up
Enable Bit .CU (bit 15)
when the rung goes true to indicate the

instruction has increased its count
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.
the rung goes false

a RES instruction resets the .DN bit
Count Up
Done Bit .DN (bit 13)
when the accumulated value is greater than or

the accumulated value counts below the preset, either

by using a CTD instruction to count down or changing
the accumulated value
Count Up
Overflow Bit .OV (bit 12)
when the up counter has exceeded the upper

limit of +32,767 and has wrapped around to
32,768. The CTU counts up from there.

counting back down to 32,767 with a CTD instruction
with the same address
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Figure 2.7
Example CTU Ladder Diagram
CTU
I:012
COUNT UP
Each time the input goes false to true,
the processor increments the counter
by 1.
10
C5:0
CU
Counter
C5:0
Preset
Accum
Tells when the count is reached (ACC > or = PRE)
O:020
01
DN
C5:0
Tells when the counter overflows +32,767
O:021
02
OV
Reset the counter
I:017
C5:0
RES
12
Figure 2.8
Example CTU Timing Diagram
Counter preset = 4 counts
Rung condition that
controls counter
Count-up enable bit
ON
OFF
ON
OFF
Rung condition that

controls reset instruction
Done Bit
ON
OFF
ON
OFF
Output instruction on rung

controlled by counter
ON
OFF
4
3
2
1
Counter Accumulated Value
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Count Down (CTD)

Description:
CTD
COUNT DOWN
CD
Counter
Preset
DN
Accum
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Using Status Bits

This Bit:
Is Set:
And Remains Set Until One of the Following Occurs:
Count Down
Enable Bit .CD (bit 14)
when the rung goes true to indicate that the

counter is enabled as a down-counter.
Note: During prescan, this bit is set to prevent
a false count when the program scan begins.
the rung goes false

Count Down
Done Bit .DN (bit 13)
when the accumulated value is greater than or

equal to the preset value.
the accumulated value counts below the preset

another instruction changes the accumulated value
Count Down
Underflow Bit (.UN) (Bit 11)
by the processor to show that the down

counter went below the lower limit of 32,768
and has wrapped around to +32,767. The CTD
instruction counts down from there.

count back up to -32,768 with a CTU instruction
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Figure 2.9
Example CTD Ladder Diagram
CTD
I:012
CD
COUNT DOWN
10
Each time the input goes from false to true,

the processor decrements the counter by 1.
C5:0
Counter
C5:0
Preset
Accum
O:020
01
DN
C5:0
Tells when the counter underflows -32,768
O:021
02
UN
I:017
Resets the counter
C5:0
RES
12
Figure 2.10
Example CTD Timing Diagram
Rung condition that

controls counter
Counter preset = 4 counts

Counter accumulated = 8
ON
OFF
Count-up enable bit
Rung condition that

controls reset instruction
Done Bit
Output instruction on rung

controlled by counter
8
3
0
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1785-6.1 November 1998
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2-19
Figure 2.11
Example CTU and CTD Logic Diagram
I:012
CTU
Count up pushbutton
COUNT UP
10
I:012
CU
Counter
Preset
Accum
C5:0
4
0
DN
CTD
Count down pushbutton
COUNT DOWN
11
CD
Counter
Preset
Accum
C5:0
C5:0
4
0
DN
O:013
Tells when the counter overflows +32,767
O:013
01
DN
C5:0
02
OV
C5:0
Tells when the counter underflows -32,768
O:013
UN
I:017
Resets the counter
C5:0
03
RES
12
Figure 2.12
Example CTU and CTD Timing Diagram
ON
Count Up Pushbutton
OFF
ON
Count Down Pushbutton
OFF
ON
Reset Pulse
OFF
ON
Done Bit
OFF
1
Count Up Preset = 4
Count Down Preset = 4
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Timer and Counter Reset (RES)

Description:
RES
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When Using a RES Instruction for a:
The Processor Resets the:
Timer
(Do not use a RES instruction for a TOF.)
.ACC value
.EN bit
.TT bit
.DN bit
Counter
.ACC value
.EN bit
.OV or .UN bit
.DN bit
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Figure 2.13
Example RES Ladder Diagram
CTD
I:012
COUNT DOWN
10
C5:0
Each time the input goes from false to true, the

processor decrements the counter by 1.
CD
C5:0
Preset
Accum
O:020
01
DN
I:017
Counter
Resets the counter
C5:0
RES
12
1785-6.1 November 1998
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Chapter
Compare Instructions CMP, EQU, GEQ,

GRT, LEQ, LES, LIM, MEQ, NEQ
Using Compare Instructions
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Table 3.A
Available Compare Instructions
If You Want to:
Use the
Instruction:
On
Page:
Compare values based on an expression
CMP
3-2
Test whether two values are equal
EQU
3-5
Test whether one value is greater than or equal to a

second value
GEQ
3-5
Test whether one value is greater than a second value
GRT
3-6
Test whether one value is less than or equal to a

second value
LEQ
3-6
Test whether one value is less than a second value
LES
3-7
Test whether one value is between two other values
LIM
3-7
Pass two values through a mask and test whether

they are equal
MEQ
3-9
Test whether one value is not equal to a second value
NEQ
3-10
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Compare Instructions CMP, EQU, GEQ, GRT, LEQ, LES, LIM, MEQ, NEQ
Using Arithmetic Status Flags
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Table 3.B
Arithmetic Status Bits
This Bit:
Description:
S:0/0
Carry (C)
S:0/1
Overflow (V)
S:0/2
Zero (Z)
S:0/3
Sign (S)
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Compare (CMP)
Description:
CMP
COMPARE
Expression
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Entering the CMP Expression

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3-3
Table 3.C
Valid Operations for Use in a CMP Expression
Type
Operator
Description
Example Operation
Comparison
equal to
if A = B, then ...
<>
not equal to
if A <> B, then ...
<
less than
if A < B, then ...
<=
less than or equal to
if A <= B, then ...
>
greater than
if A > B, then ...
>=
greater than or equal to
if A >= B, then ...
add
2 + 3 Enhanced PLC-5 processor:

2+3+7
subtract
12 5
multiply
5 * 2 PLC-5/30, -5/40, -5/60,

-5/80: 6 * (5 * 2)
| (vertical bar)
divide
24 | 6
negate
N7:0
SQR
square root
SQR N7:0
**
exponential
(x to the power of y)
10**3
(Enhanced PLC-5 processors only)
FRD
convert from BCD

to binary
FRD N7:0
TOD
convert from binary

to BCD
TOD N7:0
Arithmetic
Conversion
Determining the Length of an Expression

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Table 3.D
Character Lengths for Operators
This Operation:
Using this Operator:
Uses this Number

of Characters:
math binary
+, , *, |
OR, **
AND, XOR
(negate)
LN
FRD, TOD, DEG, RAD, SQR, NOT, LOG, SIN,

COS, TAN, ASN, ACS, ATN
=, <, >
<>, <=, >=
math unary
comparative
Example:
CMP
O:013
COMPARE
01
Expression
(N7:0 + N7:1) > (N7:2 + N7:3)
The CMP instruction tells an Enhanced PLC-5 processor: if the sum of the values in N7:0 and N7:1 is greater than the sum of the
values in N7:2 and N7:3, set output bit O:013/01. (The total number of characters used in this expressions is 3.)
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3-5
Equal to (EQU)
Description:
EQU
EQUAL
Source A
Source B
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Example:
EQU
O:013
EQUAL
Source A
Source B
N7:5
N7:10
01
If the value in N7:5 is equal to the value in N7:10, set output bit O:013/01.
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Greater than or Equal to (GEQ)

Description:
GEQ
GREATER THAN OR EQUAL
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Source A
Source B
Example:
GEQ
O:013

Source A
N7:5
Source B
N7:10
01
If the value in N7:5 is greater than or equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998
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Greater than (GRT)

Description:
GRT
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Source A
Source B
Example:
GRT
O:013
GREATER THAN
Source A
N7:5
Source B
N7:10
01
If the value in N7:5 is greater than the value in N7:10, set output bit O:013/01.
Less than or Equal to (LEQ)

Description:
LEQ
LESS THAN OR EQUAL
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Source A
Source B
Example:
LEQ
O:013
LESS THAN OR EQUAL

Source A
N7:5
Source B
N7:10
If the value in N7:5 is less than or equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998
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3-7
Less than (LES)

Description:
LES
LESS THAN
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Source A
Source B
Example:
LES
O:013
LESS THAN
Source A
N7:5
Source B
N7:10
01
If the value in N7:5 is less than the value in N7:10, set output bit O:013/01.
Limit Test (LIM)

Description:
LIM
LIMIT TEST (CIRC)
Low limit
Test
High limit
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Entering Parameters
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Parameter:
Definition:
Low Limit
a constant or an address from which the instruction reads the

lower range of the specified limit range. The address contains an
integer or floating-point value.
Test Value
the address that contains the integer or floating-point value you

examine to see whether the value is inside or outside the
specified limit range.
High Limit
a constant or an address from which the instruction reads the

upper range of the specified limit range. The address contains an
integer or floating-point value.
1785-6.1 November 1998
3-8
LIM Example Using Integer:
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false
<
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-------true-----A ................C
< value B >
> false
..........
to +32,767
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value B <
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< value B
Example (when the Low Limit is less

than the High Limit):
LIM
O:013
LIMIT TEST (CIRC)

Low lim
N7:10
Test
N7:15
High lim
N7:20
01
If the value in N7:15 is greater than or equal to the value in N7:10 and less than or equal to the value in
N7:20, set output bit O:013/01.
1785-6.1 November 1998
3-9
Mask Compare Equal to (MEQ)

Description:
MEQ
MASKED EQUAL
Source
Mask
Compare
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Entering Parameters
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Example:
Parameter:
Definition:
Source
a program constant or data address from which the instruction reads an

image of the value. The source remains unchanged.
Mask
specifies which bits to pass or block. A mask passes data when the
mask bits are set (1); a mask blocks data when the mask bits are reset
(0). The mask must be the same element size (16-bits) as the source
and compare address. In order for bits to be compared, you must set (1)
mask bits; bits in the compare address that correspond to zeros (0) in
the mask are not compared. If you want the ladder program to change
the mask value, store the mask at a data address. Otherwise, enter a
hexadecimal value for a constant mask value. If you enter a hexadecimal
value that starts with a letter (such a F800), enter the value with a
leading zero. For example, type 0F800
Compare
specifies whether you want the ladder program to vary the compare
value, or a program constant for a fixed reference. Use 16-bit elements,
the same as the source.
Source
Mask
Compare
Result
01010101 01011111
11111111 11110000
01010101 0101xxxx
The instruction is true because
reference bits xxxx are not compared.
MEQ
O:013
MASKED EQUAL
Source
Mask
Compare
N7:5
N7:6
N7:10
01
The processor passes the value in N7:5 through the mask in N7:6. It then passes the value in N7:10 through the mask
in N7:6. If the two masked values are equal, set output bit O:013/01
1785-6.1 November 1998
3-10
Not Equal to (NEQ)

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Description:
NEQ
NOT EQUAL
Source A
Source B
Example:
NEQ
O:013
NOT EQUAL
Source A
N7:5
Source B
N7:10
If the value in N7:5 is not equal to the value in N7:10, set output bit O:013/01.
1785-6.1 November 1998
01
Chapter
Compute Instructions CPT, ACS, ADD,

ASN, ATN, AVE, CLR, COS, DIV, LN, LOG,
MUL, NEG, SIN, SRT, SQR, STD, SUB,
TAN, XPY
Using Compute Instructions
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Table 4.A
Available Compute Instructions
If You Want to:
Use this
Instruction:
Found on
Page:
Evaluate an expression
CPT
4-5
Take the arc cosine of a number
ACS*
4-11
Add two values
ADD
4-12
Take the arc sine of a number
ASN*
4-13
Take the arc tangent of a number
ATN*
4-14
Calculate the average for a set of values
AVE*
4-15
Clear an address word (set all bits to zero)
CLR
4-17
Take the cosine of a number
COS*
4-18
Divide two values
DIV
4-19
Take the natural log of a number
LN*
4-20
Take the log of a number
LOG*
4-21
* Only Enhanced PLC-5 processors support this instruction.
(Continued)
1785-6.1 November 1998
4-2
Compute Instructions CPT, ACS, ADD, ASN, ATN, AVE, CLR, COS, DIV, LN, LOG, MUL, NEG, SIN, SRT, SQR, STD, SUB, TAN, XPY
If You Want to:
Use this
Instruction:
Found on
Page:
Multiply two values
MUL
4-22
Take the opposite sign of a value
NEG
4-23
Take the sine of a number
SIN*
4-24
Take the square root of a value
SQR
4-25
Sort a set of values into ascending order
SRT*
4-26
Calculate the standard deviation for a set of values
STD*
4-28
Subtract two values
SUB
4-31
Take the tangent of a number
TAN*
4-32
Raise a number to a power
XPY*
4-33
* Only Enhanced PLC-5 processors support this instruction.

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Table 4.B
Arithmetic Status Bits
1785-6.1 November 1998
This Bit:
Description:
S:0/0
Carry (C)
S:0/1
Overflow (V)
S:0/2
Zero (Z)
S:0/3
Sign (S)
Data Types and the

Compute Instruction
4-3
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If You are Using this Processor:
The Processor Rounds:
Classic PLC-5
the final value of a mathematical operation before

storing the final result. The processor rounds to
the nearest whole number: The processor rounds
values of 0.5-0.9 up to the next whole number; the
processor rounds values of 0.1- 0.4 down to the
closest whole number. If this value is greater than
32,767 or less than 32,768, the overflow status
bit is set.
Enhanced PLC-5
down if the value is < 0.5, up if the value is > 0.5,

and to the nearest even number if the value is =
0.5. If this value is greater than 32,767 or less
than 32,768, the processor wraps negative
(32,767, 32,768, 32,767, 32,766, etc.). For
example, if you have an ADD instruction with a
result greater than 32,767, the overflow bit is set,
the sign bit is set, and the result is negative:
32,767 + 5 = 32,764.
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4-4
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ADD
I:012
]
]
10
ADD
Add the lower words of value1 and value2.
BITWISE AND
Capture the carry bit.
10
Source A
Source B
Dest
ADD
Add the high word of value1 to the carry bit.
10
S:0
1
N7:4
ADD
I:012
]
Source A
Source B
Dest
I:012
ADD
ADD
]
10
N7:1
N7:3
N7:5
ADD
AND
I:012
]
Source A
Source B
Dest
Add the high word of value2 to this sum.
Using Floating Point Data Types
Source A
Source B
Dest
N7:0
N7:4
N7:4
N7:2
N7:4
N7:4
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4-5
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Compute (CPT)
Description:
CPT
COMPUTE
Destination
Expression
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Entering the CPT Expression

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1785-6.1 November 1998
4-6
Table 4.C
Valid Operations for Use in a CPT Expression
Type
Operator
Description
Example Operation
Copy
none
copy from A to B
enter source address in the expression enter

destination address in destination
Clear
none
set a value to zero
0 (enter 0 for the expression)
Arithmetic
add
2+3
2+3+7
(Enhanced PLC-5 processors)
12 5
(12 5) 7
5*2
6 * (5 * 2)
24 | 6
(24 | 6) *2
| (vertical bar)
Trigonometric
Bitwise
Conversion
subtract
multiply
divide
negate
N7:0
SQR
square root
SQR N7:0
**
exponential *
10**3
LN
natural log *
LN F8:20
LOG
log to the base 10*
LOG F8:3
ACS
arc cosine*
ACS F8:18
ASN
arc sine*
ASN F8:20
ATN
arc tangent *
ATN F8:22
COS
cosine*
COS F8:14
SIN
sine*
SIN F8:12
TAN
tangent*
TAN F8:16
AND
bitwise AND
D9:3 AND D10:4
OR
bitwise OR
D10:4 OR D10:5
XOR
bitwise exclusive OR
D9:5 XOR D10:4
NOT
bitwise complement
NOT D9:3
FRD
convert from BCD

to binary
FRD N7:0
TOD
convert from binary

to BCD
TOD N7:0
DEG
convert radians
to degrees*
DEG F8:8
RAD
convert degrees
to radians*
RAD F8:10
* Available in Enhanced PLC-5 processors only.
1785-6.1 November 1998
4-7
Determining the Length of an Expression

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Table 4.D
Character Lengths for Operators
This Operation:
Using this Operator:
Uses this
Number of
Characters:
math binary
+, , *, |
OR, **
AND, XOR
(negate)
LN *
FRD, TOD, DEG*, RAD*, SQR, NOT, LOG*, SIN*,

COS*, TAN*, ASN*, ACS*, ATN*
=, <, >
<>, <=, >=
math unary
comparative
1785-6.1 November 1998
4-8
Determining the Order of Operation

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Table 4.E
Order of Operation for CPT Expressions
Order
Operation
Description
**
exponential (XY)
Enhanced PLC-5 processors only
negate
NOT
bitwise complement
multiply
divide
add
subtract
AND
bitwise AND
XOR
OR
bitwise OR
Expression Examples
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1785-6.1 November 1998
4-9
Example:
CPT
I:012
]
10
COMPUTE
Destination
N7:20
Expression
(N7:1 * 5) | (N7:2 | 7)
If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7.
If N7:1=5 and N7:2=9, the result is 25. (The result is rounded to the nearest whole number because the constants 5 and 7
were specified as whole numbers.)
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Example:
I:012
CPT
COMPUTE
10
Destination
N7:20
Expression
(N7:1 * 5.0) | (N7:2 | 7.0)
If the input word 12, bit 10 is set, multiply the value of N7:1 by 5. Divide this result by the quotient of N7:2 divided by 7. If N7:1=5 and
N7:2=9, the result is 19. (The result is rounded differently because the constants 5.0 and 7.0 were specified to 1 decimal place.
Entering the Destination

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Using CPT Functions

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Table 4.F
CPT Functions for Number Conversion
Mnemonic
Title
Description
RAD *
radians
Converts from degrees to radians
DEG *
degrees
Converts from radians to degrees
TOD
to BCD
Converts from integer to BCD (supports 4-digit BCD

numbers)
FRD
from BCD
Converts from BCD to integer (supports 4-digit BCD

numbers)
SQR
square root
Takes the square root of the number; accurate to 6

significant digits
LOG *
Log to the base 10; accurate to 6 significant digits
LN *
Natural log; accurate to 6 significant digits
SIN *
sine; manipulated in radians, accurate to 6 significant digits
COS *
cosine; manipulated in radians, accurate to 6 significant digits
TAN *
tangent; manipulated in radians, accurate to 6 significant digits
ASN *
inverse sine; manipulated in radians, accurate to 6 significant digits
ACS *
inverse cosine; manipulated in radians, accurate to 6 significant digits
ATN *
inverse tangent; manipulated in radians, accurate to 6 significant digits

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1785-6.1 November 1998
4-11
Arc Cosine (ACS)

(Enhanced PLC-5 Processors Only)
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Description:
ACS
ARCCOSINE
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Source
Destination
Table 4.G
Updating Arithmetic Status Flags for an ACS Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
sets if overflow generated; otherwise resets
Zero (Z)
sets if result is zero; otherwise resets
Sign (S)
always resets
Example:
I:012
]
]
10
ACS
ARCCOSINE
Source
Destination
F8:19
0.7853982
F8:20
0.6674572
If input word 12, bit 10 is set, take the arc cosine of the value in F8:19 and store the result in F8:20.
1785-6.1 November 1998
4-12
Addition (ADD)
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Description:
ADD
ADD
Source A
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Source B
Destination
Table 4.H
Updating Arithmetic Status Flags for an ADD Instruction
With this Bit:
The Processor:
Carry (C)
sets if carry generated; otherwise resets
Overflow (V)
Zero (Z)
Sign (S)
sets if result is negative; otherwise resets
Example:
I:012
ADD
ADD
]
10
Source A
N7:3
Source B
N7:4
Destination
N7:20
If input word 12, bit 10 is set, add the value in N7:3 to the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998
4-13
Arc Sine (ASN)

8VH WKH $61 LQVWUXFWLRQ WR WDNH WKH DUF VLQH WKH VRXUFH LQ UDGLDQV
DQG VWRUH WKH UHVXOW LQ UDGLDQV LQ WKH 'HVWLQDWLRQ 6HH 7DEOH , IRU
VWDWXV IODJV IRU $61 LQVWUXFWLRQ
Description:
ASN
ARCSINE
Source
7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ RU

HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D !NAN!
UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV
DOZD\V JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ RU HTXDO WR /2
ZKHUH
Destination
Table 4.I
Updating Arithmetic Status Flags for an ASN Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
always resets
Example:
I:012
ASN
ARCSINE
Source
]
10
F8:17
0.7853982
Dest
F8:18
0.9033391
If input word 12, bit 10 is set, take the arc sine of the value in F8:17 and store the result in F8:18.
1785-6.1 November 1998
4-14
Arc Tangent (ATN)

8VH WKH $71 LQVWUXFWLRQ WR WDNH WKH DUF WDQJHQW RI WKH VRXUFH LQ
UDGLDQV DQG VWRUH WKH UHVXOW LQ UDGLDQV LQ WKH 'HVWLQDWLRQ 7KH
UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV DOZD\V JUHDWHU WKDQ RU
HTXDO WR DQG OHVV WKDQ RU HTXDO WR /2 ZKHUH
6HH 7DEOH - IRU VWDWXV IODJV IRU $71 LQVWUXFWLRQ
Description:
ATN
ARCTANGENT
Source
Destination
Table 4.J
Updating Arithmetic Status Flags for an ATN Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
ATN
ARCTANGENT
Source
Destination
F8:21
0.7853982
F8:22
0.6657737
If input word 12, bit 10 is set, take the arc tangent of the value in F8:21 and store the result in F8:22.
1785-6.1 November 1998
4-15
Average File (AVE)

Description:
AVE
AVERAGE FILE
File
Destination
Control
Length
Position
EN
DN
7KH $9( LQVWUXFWLRQ FDOFXODWHV WKH DYHUDJH RI D VHW RI YDOXHV :KHQ

WKH UXQJ JRHV IURP IDOVH WR WUXH WKH YDOXH DW WKH FXUUHQW SRVLWLRQ LV
DGGHG WR WKH QH[W YDOXH ZKLFK LV DGGHG WR WKH QH[W YDOXH DQG VR RQ
6HH 7DEOH . IRU VWDWXV IODJV IRU $9( LQVWUXFWLRQ
(DFK WLPH DQRWKHU YDOXH LV DGGHG WKH SRVLWLRQ ILHOG DQG WKH VWDWXV
ZRUG 6 LV LQFUHPHQWHG 7KH ILQDO VXP LV GLYLGHG E\ WKH QXPEHU
RI YDOXHV DGGHG DQG WKH UHVXOW LV VWRUHG LQ WKH GHVWLQDWLRQ
Table 4.K
Updating Arithmetic Status Flags for an AVE Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
$Q RYHUIORZ FDQ RFFXU LI
WKH LQWHUPHGLDWH VXP H[FHHGV WKH PD[LPXP IORDWLQJ SRLQW YDOXH
WKH GHVWLQDWLRQ LV DQ LQWHJHU DGGUHVV DQG WKH ILQDO YDOXH LV JUHDWHU

WKDQ RU OHVV WKDQ
,I DQ RYHUIORZ RFFXUV WKH SURFHVVRU VWRSV WKH FDOFXODWLRQ VHWV WKH (5
ELW DQG WKH 'HVWLQDWLRQ UHPDLQV XQFKDQJHG 7KH SRVLWLRQ LGHQWLILHV
WKH HOHPHQW WKDW FDXVHG WKH RYHUIORZ :KHQ \RX FOHDU WKH (5 ELW WKH
SRVLWLRQ UHVHWV WR DQG WKH DYHUDJH LV UHFDOFXODWHG
,PSRUWDQW 8VH WKH 5(6 LQVWUXFWLRQ WR FOHDU WKH VWDWXV IODJV
Entering Parameters
7R SURJUDP WKH $9( LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU
ZLWK WKH IROORZLQJ
)LOH LV WKH DGGUHVV WKDW FRQWDLQV WKH ILUVW YDOXH WR EH DGGHG 7KLV
DGGUHVV FDQ EH IORDWLQJ SRLQW RU LQWHJHU
'HVWLQDWLRQ LV WKH DGGUHVV ZKHUH WKH UHVXOW RI WKH LQVWUXFWLRQ LV

VWRUHG 7KLV DGGUHVV FDQ EH IORDWLQJ SRLQW RU LQWHJHU
&RQWURO LV WKH DGGUHVV RI WKH FRQWURO VWUXFWXUH LQ WKH FRQWURO DUHD

5 RI SURFHVVRU PHPRU\ 7KH SURFHVVRU VWRUHV LQIRUPDWLRQ VXFK
DV WKH OHQJWK SRVLWLRQ DQG VWDWXV DQG XVHV WKLV LQIRUPDWLRQ WR
H[HFXWH WKH LQVWUXFWLRQ
/HQJWK LV WKH QXPEHU RI ZRUGV LQ WKH ILOH
3RVLWLRQ SRLQWV WR WKH ZRUG WKDW WKH LQVWUXFWLRQ LV FXUUHQWO\ XVLQJ

1785-6.1 November 1998
4-16
Using Status Bits

7R XVH WKH $9( LQVWUXFWLRQ FRUUHFWO\ H[DPLQH VWDWXV ELWV LQ WKH
FRQWURO VWUXFWXUH $GGUHVV WKHVH ELWV E\ PQHPRQLF
This Bit:
Is Set:
Enable .EN (bit 15)
on a false-to-true rung transition to indicate that the instruction

is enabled. The instruction follows the rung condition.
Done .DN (bit 13)
after the instruction finishes operating. After the rung goes

false, the processor resets the .DN bit on the next false-to-true
rung transition.
Error .ER (bit 11)
when the operation generates an overflow. The instruction

stops until the ladder program resets the .ER bit.
,PSRUWDQW 7KH $9( LQVWUXFWLRQ FDOFXODWHV WKH DYHUDJH XVLQJ

IORDWLQJ SRLQW UHJDUGOHVV RI WKH W\SH VSHFLILHG IRU WKH ILOH
RU GHVWLQDWLRQ SDUDPHWHUV
$77(17,21 7KH $9( LQVWUXFWLRQ LQFUHPHQWV WKH
RIIVHW YDOXH VWRUHG DW 6 0DNH VXUH \RX PRQLWRU RU
ORDG WKH RIIVHW YDOXH \RX ZDQW SULRU WR XVLQJ DQ LQGH[HG
DGGUHVV 2WKHUZLVH XQSUHGLFWDEOH PDFKLQH RSHUDWLRQ
FRXOG RFFXU ZLWK SRVVLEOH GDPDJH WR HTXLSPHQW DQGRU
LQMXU\ WR SHUVRQQHO
Example:
AVE
I:012
]
]
10
File
Dest
R6:0
EN
AVERAGE FILE
#N7:1
N7:0
Control
R6:0
Length
Position
4
0
DN
O:010
]
EN
R6:0
O:010
]
DN
7
R6:0
RES
If input word 12, bit 10 is set, the AVE instruction is enabled. The values in N7:1, N7:2, N7:3, and N7:4 are
added together and divided by 4. The result is stored in N7:0. When the calculation is complete, output
word 10, bit 7 is set. Then the RES instruction resets the status bits of the control file R6:0.
1785-6.1 November 1998
4-17
Clear (CLR)
Description:
CLR
CLEAR
Destination
8VH WKH &/5 LQVWUXFWLRQ WR VHW DOO WKH ELWV RI D ZRUG WR ]HUR 7KH
GHVWLQDWLRQ PXVW EH D ZRUG DGGUHVV 6HH 7DEOH / IRU VWDWXV IODJV IRU
&/5 LQVWUXFWLRQ
Table 4.L
Updating Arithmetic Status Flags for a CLR Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
always sets
Sign (S)
always resets
Example:
I:012
]
]
10
CLR
CLEAR
Destination
N7:3
If input word 12, bit 10 is set, clear all of the bits in N7:3 to zero.
1785-6.1 November 1998
4-18
Cosine (COS)
8VH WKH &26 LQVWUXFWLRQ WR WDNH WKH FRVLQH RI D QXPEHU 6RXUFH LQ
UDGLDQV DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 0 IRU
VWDWXV IODJV IRU &26 LQVWUXFWLRQ
Description:
COS
COSINE
7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ
RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D
!INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH
'HVWLQDWLRQ LV DOZD\V JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ RU
HTXDO WR
Source
Destination
,PSRUWDQW )RU JUHDWHVW DFFXUDF\ WKH VRXUFH GDWD VKRXOG EH JUHDWHU

WKDQ RU HTXDO WR DQG OHVV WKDQ RU HTXDO WR
Table 4.M
Updating Arithmetic Status Flags for an COS Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
COS
COSINE
Source
F8:13
0.7853982
Destination
F8:14
0.7071068
If input word 12, bit 10 is set, take the cosine of the value in F8:13 and store the result in F8:14.
1785-6.1 November 1998
4-19
Divide (DIV)
8VH WKH ',9 LQVWUXFWLRQ WR GLYLGH RQH YDOXH 6RXUFH $ E\ DQRWKHU
YDOXH 6RXUFH % DQG SODFH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH $ DQG
6RXUFH % FDQ HLWKHU EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ YDOXHV 6HH
7DEOH 1 IRU VWDWXV IODJV IRU ',9 LQVWUXFWLRQ
Description:
DIV
DIVIDE
Source A
,PSRUWDQW 7KH FRPSXWH LQVWUXFWLRQV H[HFXWH IRU HDFK VFDQ DV ORQJ

DV WKH UXQJ LV WUXH LI \RX RQO\ ZDQW YDOXHV FRPSXWHG
RQFH LQFOXGH WKH 216 FRPPDQG VHH FKDSWHU
Source B
Destination
Table 4.N
Updating Arithmetic Status Flags for a DIV Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
sets if division by zero or if overflow generated;

otherwise resets
Zero (Z)
sets if result is zero; otherwise resets;

undefined if overflow is set
Sign (S)
sets if result is negative; otherwise resets;

undefined if overflow is set
Example:
I:012
]
]
10
DIV
DIVIDE
Source A
N7:3
Source B
N7:4
Destination
N7:20
If input word 12, bit 10 is set, divide the value in N7:3 by the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998
4-20
Natural Log (LN)

8VH WKH /1 LQVWUXFWLRQ WR WDNH WKH QDWXUDO ORJ RI WKH YDOXH LQ WKH
6RXUFH DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 2 IRU VWDWXV
IODJV IRU /1 LQVWUXFWLRQ
Description:
LN
NATURAL LOG
Source
,I WKH 6RXUFH LV HTXDO WR WKH UHVXOW LQ WKH 'HVWLQDWLRQ ZLOO EH

!-INF! LI WKH YDOXH LQ WKH 6RXUFH LV OHVV WKDQ WKH UHVXOW LQ WKH
'HVWLQDWLRQ ZLOO EH !NAN! 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV

Destination
Table 4.O
Updating Arithmetic Status Flags for an LN Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
LN
NATURAL LOG
Source
N7:0
5
Destination
F8:20
1.609438
If input word 12, bit 10 is set, take the natural log of the value in N7:0 and store the result in F8:20.
1785-6.1 November 1998
4-21
Log to the Base 10 (LOG)

8VH WKH /2* LQVWUXFWLRQ WR WDNH WKH ORJ EDVH RI WKH YDOXH LQ WKH
6RXUFH DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 3 IRU VWDWXV
IODJV IRU /2* LQVWUXFWLRQ
Description:
LOG
LOG BASE 10
,I WKH 6RXUFH LV HTXDO WR WKH UHVXOW LQ WKH 'HVWLQDWLRQ ZLOO EH

!-INF! LI WKH YDOXH LQ WKH 6RXUFH LV OHVV WKDQ WKH UHVXOW LQ WKH
'HVWLQDWLRQ ZLOO EH !NAN! 7KH UHVXOWLQJ YDOXH LQ WKH 'HVWLQDWLRQ LV

Source
Destination
Table 4.P
Updating Arithmetic Status Flags for an LOG Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
LOG
LOG BASE 10
Source
N7:2
5
Destination
F8:3
0.6989700
If input word 12, bit 10 is set, take the log base 10 of the value in N7:2 and store the result in F8:3.
1785-6.1 November 1998
4-22
Multiply (MUL)
Description:
MUL
MULTIPLY
Source A
8VH WKH 08/ LQVWUXFWLRQ WR PXOWLSO\ RQH YDOXH 6RXUFH $ E\ DQRWKHU

YDOXH 6RXUFH % DQG SODFH WKH UHVXOW LQ WKH GHVWLQDWLRQ 6RXUFH $ DQG
6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV 6HH 7DEOH 4 IRU VWDWXV IODJV IRU
08/ LQVWUXFWLRQ
Table 4.Q
Updating Arithmetic Status Flags for a MUL Instruction
Source B
Destination
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
MUL
MULTIPLY
Source A
N7:3
Source B
N7:4
Destination
N7:20
If input word 12, bit 10 is set, multiply the value in N7:3 by the value in N7:4 and store the result in N7:20.
1785-6.1 November 1998
4-23
Negate (NEG)
8VH WKH 1(* LQVWUXFWLRQ WR FKDQJH WKH VLJQ RI D YDOXH ,I \RX QHJDWH D
QHJDWLYH YDOXH WKH UHVXOW LV SRVLWLYH LI \RX QHJDWH D SRVLWLYH YDOXH
WKH UHVXOW LV QHJDWLYH 6HH 7DEOH 5 IRU VWDWXV IODJV IRU 1(*
LQVWUXFWLRQ
Description:
NEG
NEGATE
Source
,PSRUWDQW 7KH FRPSXWH LQVWUXFWLRQV H[HFXWH IRU HDFK VFDQ DV ORQJ

DV WKH UXQJ LV WUXH LI \RX RQO\ ZDQW YDOXHV FRPSXWHG
RQFH LQFOXGH WKH 216 FRPPDQG VHH FKDSWHU
Destination
Table 4.R
Updating Arithmetic Status Flags for a NEG Instruction
With this Bit:
The Processor:
Carry (C)
sets if the operation generates a carry
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
NEG
NEGATE
Source
Destination
N7:3
N7:20
If input word 12, bit 10 is set, take the opposite sign of the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998
4-24
Sine (SIN)
8VH WKH 6,1 LQVWUXFWLRQ WR WDNH WKH VLQH RI D QXPEHU 6RXUFH LQ
UDGLDQV DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH 6 IRU
VWDWXV IODJV IRU 6,1 LQVWUXFWLRQ
Description:
SIN
SINE
7KH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ
RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH SURFHVVRU UHWXUQV D
!INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ YDOXH LQ WKH
'HVWLQDWLRQ LV DOZD\V JUHDWHU WKDQ RU HTXDO WR DQG OHVV WKDQ RU
HTXDO WR
Source
Destination

Table 4.S
Updating Arithmetic Status Flags for an SIN Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
SIN
SINE
Source
Destination
If input word 12, bit 10 is set, take the sine of F8:11 and store the result in F8:12.
1785-6.1 November 1998
F8:11
0.7853982
F8:12
0.7071068
4-25
Square Root (SQR)

8VH WKH 645 LQVWUXFWLRQ WR WDNH WKH VTXDUH URRW RI D YDOXH DQG VWRUH
WKH UHVXOW LQ WKH GHVWLQDWLRQ 7KH VRXUFH FDQ EH D YDOXH RU DQ DGGUHVV
,I WKH VRXUFH YDOXH LV QHJDWLYH WKH SURFHVVRU WDNHV LWV DEVROXWH YDOXH
DQG SHUIRUPV WKH VTXDUH URRW IXQFWLRQ 6HH 7DEOH 7 IRU VWDWXV IODJV
IRU 645 LQVWUXFWLRQ
Description:
SQR
SQUARE ROOT
Source
Destination
,PSRUWDQW 7KH 645 LQVWUXFWLRQ H[HFXWHV RQFH IRU HDFK VFDQ DV

ORQJ DV WKH UXQJ LV WUXH LI \RX RQO\ ZDQW YDOXHV
FRPSXWHG RQFH LQFOXGH WKH 216 FRPPDQG VHH
FKDSWHU
Table 4.T
Updating Arithmetic Status Flags for a SQR Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
sets if overflow generated during floating-point

to integer conversion; otherwise resets
Zero (Z)
Sign (S)
always resets
Example:
I:012
]
]
10
SQR
SQUARE ROOT
Source
Destination
N7:3
N7:20
If input word 12, bit 10 is set, take the square root of the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998
4-26
Sort File (SRT)

Description:
SRT
SORT FILE
File
Control
Length
Position
EN
DN
7KH 657 LQVWUXFWLRQ VRUWV D VHW RI YDOXHV LQWR DVFHQGLQJ RUGHU 7KLV
LQVWUXFWLRQ LV H[HFXWHG RQ D IDOVHWRWUXH WUDQVLWLRQ
,PSRUWDQW 0DNH VXUH WKH ILOH OHQJWK YDOXH \RX VSHFLI\ LQ WKH
LQVWUXFWLRQ GRHV QRW FDXVH WKH LQGH[HG DGGUHVV WR H[FHHG
WKH ILOH ERXQGV 7KH SURFHVVRU GRHV QRW FKHFN WKLV
XQOHVV \RX H[FHHG WKH GDWD ILOH DUHD RI PHPRU\
,I WKH LQGH[HG DGGUHVV H[FHHGV WKH GDWD ILOH DUHD WKH
SURFHVVRU LQLWLDWHV D UXQWLPH HUURU DQG VHWV D PDMRU
IDXOW 7KH SURFHVVRU GRHV QRW FKHFN WR VHH ZKHWKHU WKH
LQGH[HG DGGUHVV FURVVHV ILOH W\SHV VXFK DV 1 WR )
Entering Parameters
7R SURJUDP WKH 657 LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ
1785-6.1 November 1998
Parameter:
Definition:
file
the address that contains the first value to be sorted. This address can be
floating point or integer.
control
the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.
length
the number of words in the file (1-1000).
position
points to the element that the instruction is currently using.
4-27
Using Status Bits

7R XVH WKH 657 LQVWUXFWLRQ FRUUHFWO\ WKH ODGGHU SURJUDP PXVW
H[DPLQH VWDWXV ELWV LQ WKH FRQWURO VWUXFWXUH <RX DGGUHVV WKHVH ELWV
E\ PQHPRQLF
This Bit:
Is Set:
Enable .EN (bit 15)
on a false-to-true rung transition to indicate that the instruction is

enabled. The instruction follows the rung condition.
Done .DN (bit 13)
after the instruction finishes operating. After the rung goes false,
the processor resets the .DN bit on the next false-to-true rung
transition.
Error .ER (bit 11)
when the length value is less than or equal to zero or when the
position value is less than zero.
$77(17,21 7KH 657 LQVWUXFWLRQ PDQLSXODWHV WKH

LQMXU\ WR SHUVRQQHO
Example:
I:012
]
]
10
SRT
SORT FILE
File
Control
Length
Position
EN
#N7:1
R6:0
4
0
DN
R6:0
]
EN
O:010
R6:0
]
DN
O:010
]
5
]
7
If input word 12, bit 10 is set, the SRT instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are sorted into ascending
order. When the sort operation is complete, output word 10, bit 7 is set.
1785-6.1 November 1998
4-28
Standard Deviation (STD)

Description:
STD
STANDARD DEVIATION
File
Destination
Control
Length
Position
EN
DN
7KH 67' LQVWUXFWLRQ FDOFXODWHV WKH VWDQGDUG GHYLDWLRQ RI D VHW RI

YDOXHV DQG VWRUHV WKH UHVXOW LQ WKH GHVWLQDWLRQ 7KLV LQVWUXFWLRQ LV
H[HFXWHG RQ D IDOVHWRWUXH WUDQVLWLRQ 6HH 7DEOH 8 IRU VWDWXV IODJV
IRU 67' LQVWUXFWLRQ
7KH VWDQGDUG GHYLDWLRQ LV FDOFXODWHG DFFRUGLQJ WR WKH IROORZLQJ
IRUPXOD
Standard
Deviation
:KHUH
AVE(xi))
SUM((xi

(N 1)
680 VXPPDWLRQ IXQFWLRQ RI WKH HQFORVHG YDULDEOHV
$9( DYHUDJH IXQFWLRQ RI WKH HQFORVHG YDULDEOHV
[L YDULDEOH HOHPHQWV RI WKH GDWD ILOH
1 QXPEHU RI HOHPHQWV LQ WKH GDWD ILOH
,PSRUWDQW 0DNH VXUH WKH ILOH OHQJWK YDOXH \RX VSHFLI\ LQ WKH
LQVWUXFWLRQ GRHV QRW FDXVH WKH LQGH[HG DGGUHVV WR H[FHHG
WKH ILOH ERXQGV 7KH SURFHVVRU GRHV QRW FKHFN WKLV
XQOHVV \RX XVH DQ LQGH[HG LQGLUHFW DGGUHVV RU H[FHHG WKH
GDWD ILOH DUHD RI PHPRU\ ,I WKH LQGH[HG DGGUHVV H[FHHGV
WKH GDWD ILOH DUHD WKH SURFHVVRU LQLWLDWHV D UXQWLPH HUURU
DQG VHWV D PDMRU IDXOW 7KH SURFHVVRU GRHV QRW FKHFN WR
VHH ZKHWKHU WKH LQGH[HG DGGUHVV FURVVHV ILOH W\SHV VXFK
DV 1 WR )
Table 4.U
Updating Arithmetic Status Flags for an STD Instruction
1785-6.1 November 1998
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
always resets
4-29
7KHUH DUH WZR ZD\V DQ RYHUIORZ FDQ RFFXU
WKH LQWHUPHGLDWH VXP H[FHHGV WKH PD[LPXP IORDWLQJ SRLQW YDOXH

WR

IORDWLQJ SRLQW YDOXHV DUH
WKH GHVWLQDWLRQ LV DQ LQWHJHU DGGUHVV DQG WKH ILQDO YDOXH LV JUHDWHU

WKDQ
r"'
r"'
,I DQ RYHUIORZ RFFXUV WKH SURFHVVRU VWRSV WKH FDOFXODWLRQ VHWV WKH (5
ELW DQG OHDYHV WKH GHVWLQDWLRQ XQFKDQJHG 7KH SRVLWLRQ LGHQWLILHV WKH
HOHPHQW WKDW FDXVHG WKH RYHUIORZ :KHQ \RX FOHDU WKH (5 ELW WKH
SRVLWLRQ UHVHWV WR DQG WKH VWDQGDUG GHYLDWLRQ LV UHFDOFXODWHG
,PSRUWDQW 8VH WKH 5(6 LQVWUXFWLRQ WR FOHDU WKH VWDWXV ELWV
Entering Parameters
7R SURJUDP WKH 67' LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ
Parameter:
Defines:
file
the address that contains the first value to be calculated. This address
can be floating point or integer.
destination
the address where the result of the instruction is stored. This address
can be floating point or integer.
control
the address of the control structure in the control area (R) of processor
memory. The processor stores information such as the length, position
and status, and uses this information to execute the instruction.
length
the number of words in the file (1-1000).
position
points to the element that the instruction is currently using.
Using Status Bits

7R XVH WKH 67' LQVWUXFWLRQ FRUUHFWO\ H[DPLQH VWDWXV ELWV LQ WKH
FRQWURO VWUXFWXUH <RX DGGUHVV WKHVH ELWV E\ PQHPRQLF
This Bit:
Is Set:
Enable .EN (bit 15)
on a false-to-true rung transition to indicate that the instruction

is enabled. The instruction follows the rung condition.
Done .DN (bit 13)
after the instruction finishes operating. After the rung goes

false, the processor resets the .DN bit on the next false-to-true
rung transition.
Error .ER (bit 11)
when the operation generates an overflow. The instruction

stops until the ladder program resets the .ER bit.
1785-6.1 November 1998
4-30
,PSRUWDQW 7KH 67' LQVWUXFWLRQ FDOFXODWHV WKH VWDQGDUG GHYLDWLRQ

XVLQJ IORDWLQJ SRLQW UHJDUGOHVV RI WKH W\SH VSHFLILHG IRU
WKH ILOH RU GHVWLQDWLRQ SDUDPHWHUV
$77(17,21 7KH 67' LQVWUXFWLRQ PDQLSXODWHV WKH
LQMXU\ WR SHUVRQQHO
Example:
I:012
]
]
10
STD
STANDARD DEVIATION
File
Destination
Control
Length
Position
EN
#N7:1
N7:0
R6:0
4
DN
R6:0
]
EN
O:010
R6:0
]
DN
O:010
]
5
]
7
R6:0
RES
If input word 12, bit 10 is set, the STD instruction is enabled. The elements N7:1, N7:2, N7:3, and N7:4 are used to calculate the
standard deviation. When the calculation is complete, output word 10, bit 7 is set. Then the RES instruction resets the status bits of
the control file R6:0.
1785-6.1 November 1998
4-31
Subtract (SUB)
8VH WKH 68% LQVWUXFWLRQ WR VXEWUDFW RQH YDOXH 6RXUFH % IURP
DQRWKHU YDOXH 6RXUFH $ DQG SODFH WKH UHVXOW LQ WKH GHVWLQDWLRQ
6RXUFH $ DQG 6RXUFH % FDQ EH YDOXHV RU DGGUHVVHV WKDW FRQWDLQ
YDOXHV 6HH 7DEOH 9 IRU VWDWXV IODJV IRU 68% LQVWUXFWLRQ
Description:
SUB
SUBTRACT
Source A
Source B
,PSRUWDQW 7KH 68% LQVWUXFWLRQ H[HFXWHV RQFH IRU HDFK VFDQ DV

ORQJ DV WKH UXQJ LV WUXH LI \RX RQO\ ZDQW YDOXHV
VXEWUDFWHG RQFH LQFOXGH WKH 216 FRPPDQG VHH
FKDSWHU
Destination
Table 4.V
Updating Arithmetic Status Flags for a SUB Instruction
With this Bit:
The Processor:
Carry (C)
sets if borrow generated; otherwise resets
Overflow (V)
sets if underflow generated; otherwise resets
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
SUB
SUBTRACT
Source A
N7:3
Source B
N7:4
Destination
N7:20
If input word 12, bit 10 is set, subtract the value in N7:4 from the value in N7:3 and store the result in N7:20.
1785-6.1 November 1998
4-32
Tangent (TAN)
8VH WKH 7$1 LQVWUXFWLRQ WR WDNH WKH WDQJHQW RI D QXPEHU 6RXUFH LQ
UDGLDQV DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6HH 7DEOH : IRU
VWDWXV IODJV IRU 7$1 LQVWUXFWLRQ
Description:
TAN
TANGENT
7KH YDOXH LQ WKH 6RXUFH PXVW EH JUHDWHU WKDQ RU HTXDO WR

DQG OHVV WKDQ RU HTXDO WR ,I LW LV QRW LQ WKLV UDQJH WKH
SURFHVVRU UHWXUQV D !INF! UHVXOW LQ WKH 'HVWLQDWLRQ 7KH UHVXOWLQJ
YDOXH LQ WKH 'HVWLQDWLRQ LV DOZD\V D UHDO QXPEHU
Source
Destination

Table 4.W
Updating Arithmetic Status Flags for an TAN Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
TAN
TANGENT
Source
F8:15
0.7853982
Destination
F8:16
1.000000
If input word 12, bit 10 is set, take the tangent of the value in F8:15 and store the result in F8:16.
1785-6.1 November 1998
4-33
X to the Power of Y (XPY)

Description:
XPY
X TO POWER OF Y
Source A
Source B
Destination
8VH WKH ;3< LQVWUXFWLRQ WR UDLVH D YDOXH 6RXUFH $ WR D SRZHU

6RXUFH % DQG VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ ,I WKH YDOXH LQ
6RXUFH $ LV QHJDWLYH WKH H[SRQHQW 6RXUFH % VKRXOG EH DQ LQWHJHU
YDOXH LI WKH H[SRQHQW LV QRW DQ LQWHJHU IRU H[DPSOH LI LW LV D IORDWLQJ
SRLQW YDOXH WKH RYHUIORZ ELW LV VHW DQG WKH DEVROXWH YDOXH RI WKH EDVH
LV XVHG LQ WKH FDOFXODWLRQ 6HH 7DEOH ; IRU VWDWXV IODJV IRU ;3<
LQVWUXFWLRQ
7KH ;3< LQVWUXFWLRQ XVHV WKH IROORZLQJ DOJRULWKP
;3<
< ORJ ;
,I DQ\ RI WKH LQWHUPHGLDWH RSHUDWLRQV LQ WKLV DOJRULWKP SURGXFH DQ

RYHUIORZ WKH DULWKPHWLF PLQRU IDXOW ELW LV VHW 6 7KH
DULWKPHWLF VWDWXV IODJ ELW LV VHW RQO\ LI WKH ILQDO UHVXOW LV DQ RYHUIORZ
,PSRUWDQW .HHS LQ PLQG WKDW [ LV HTXDO WR [ LV HTXDO WR )RU
IORDWLQJ SRLQW QXPEHUV LV HTXDO WR !NAN! DQ
LQYDOLG PDWKHPDWLFDO YDOXH DQG IRU LQWHJHUV LV HTXDO
WR .
Table 4.X
Updating Arithmetic Status Flags for an XPY Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
XPY
X TO POWER OF Y
Source A
Source B
Destination
N7:4
5
N7:5
2
N7:6
25
If input word 12, bit 10 is set, take the value in N7:4, raise it to the power of the value in N7:5, and stores
the result in N7:6.
1785-6.1 November 1998
4-34
1RWHV
1785-6.1 November 1998
Chapter
Logical Instructions AND, NOT, OR, XOR

Using Logical Instructions
7KHVH LQVWUXFWLRQV 7DEOH $ SHUIRUP ORJLFDO RSHUDWLRQV

Table 5.A
Available Logical Instructions
If You Want to:
Found on Page:
Perform an AND operation
AND
5-2
Perform a NOT operation
NOT
5-3
Perform an OR operation
OR
5-4
Perform an XOR operation
XOR
5-5
7KH SDUDPHWHUV \RX HQWHU DUH SURJUDP FRQVWDQWV RU GLUHFW ORJLFDO

DGGUHVVHV
$SSHQGL[ &

7KH DULWKPHWLF VWDWXV ELWV DUH LQ ZRUG ELWV LQ WKH SURFHVVRU VWDWXV
ILOH 6 7DEOH % OLVWV WKH VWDWXV IODJV
Table 5.B
Arithmetic Status Flags
This Bit:
Description:
S:0/0
Carry (C)
S:0/1
Overflow (V)
S:0/2
Zero (Z)
S:0/3
Sign (S)
1785-6.1 November 1998
5-2
AND Operation (AND)

8VH WKH $1' LQVWUXFWLRQ WR SHUIRUP DQ $1' RSHUDWLRQ XVLQJ WKH ELWV
LQ WKH WZR VRXUFH DGGUHVVHV
Description:
AND
Table 5.C
Truth Table for an AND Operation
BITWISE AND
Source A
Source B
Destination
Source A
Source B
Result
Table 5.D
Updating Arithmetic Status Flags for an AND Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
Sign (S)
sets if most-significant bit is set;

otherwise resets
Example:
I:012
AND
AND
[
10
Source A
Source B
Destination
If input word 12, bit 10 is set, the processor performs an AND

operation on N9:3 and N10:4 and stores the result in N12:3.
1785-6.1 November 1998
Source A
N9:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
N12:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
N9:3
N10:4
N12:3
5-3
NOT Operation (NOT)

8VH WKH 127 LQVWUXFWLRQ WR SHUIRUP D 127 RSHUDWLRQ XVLQJ WKH ELWV LQ
WKH VRXUFH DGGUHVV 7KLV RSHUDWLRQ LV DOVR NQRZ DV D ELW LQYHUVLRQ
Description:
NOT
,PSRUWDQW 7KH 127 LQVWUXFWLRQ LV QRW DYDLODEOH RQ 3/&

VHULHV $ SURFHVVRUV
NOT
Source
Destination
Table 5.E
Truth Table for a NOT Operation
Source
Result
Table 5.F
Updating Arithmetic Status Flags for a NOT Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
Sign (S)

otherwise resets
Example:
NOT
I:012
NOT
[
10
Source
Destination
N9:3
N10:4
If input word 12, bit 10 is set, the processor performs a

NOT operation on N9:3 and stores the result in N10:4
Source
N9:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Destination
N10:4
1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1
1785-6.1 November 1998
5-4
OR Operation (OR)
8VH WKH 25 LQVWUXFWLRQ WR SHUIRUP DQ 25 RSHUDWLRQ XVLQJ WKH ELWV LQ
WKH WZR VRXUFHV FRQVWDQWV RU DGGUHVVHV
Description:
OR
Table 5.G
Truth Table for an OR Operation
BITWISE INCLUSIVE OR
Source A
Source B
Destination
Source A
Source B
Result
Table 5.H
Updating Arithmetic Status Flags for an OR Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
Sign (S)

otherwise resets
Example:
OR
I:012
INCLUSIVE OR
10
Source A
Source B
Destination
If input word 12, bit 10 is set, the processor performs

an OR operation on N9:3 and N10:4 and stores the
result in N12:3.
Source A
N9:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
N12:3
1785-6.1 November 1998
N9:3
N10:4
N12:3
5-5
Exclusive OR Operation (XOR)

8VH WKH ;25 LQVWUXFWLRQ WR SHUIRUP DQ H[FOXVLYH 25 RSHUDWLRQ XVLQJ
WKH ELWV LQ WKH WZR VRXUFHV FRQVWDQWV RU DGGUHVVHV
Description:
XOR
Table 5.I
Truth Table for an XOR Operation
BITWISE EXCLUSIVE OR
Source A
Source B
Destination
Source A
Source B
Result
Table 5.J
Updating Arithmetic Status Bits for an XOR Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
Sign (S)
sets if most-significant bit is set; otherwise resets
Example:
XOR
I:012
EXCLUSIVE OR
[
10
If input word 12, bit 10 is set, the processor performs

an XOR operation on N9:3 and N10:4 and stores the
result in N12:3.
Source A
Source B
N9:3
N10:4
Destination
N12:3
Source A
N9:3
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
Source B
N10:4
0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1
Destination
N12:3
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
1785-6.1 November 1998
5-6
1RWHV
1785-6.1 November 1998
Chapter
Conversion Instructions FRD and TOD,

DEG and RAD
Using the Conversion Instructions
7KH FRQYHUVLRQ LQVWUXFWLRQV FRQYHUW LQWHJHU WR %&' DQG FRQYHUW %&'

WR LQWHJHU XVLQJ 72' DQG )5' )RU H[DPSOH XVH 72' DQG )5' IRU
VLJQDOV WRIURP %&' ,2 GHYLFHV IRU GLVSOD\ SXUSRVHV RU IRU QXPEHU
FRPSDWLELOLW\ ZLWK 3/& IDPLO\ SURFHVVRUV <RX FDQ DOVR FRQYHUW
UDGLDQV WR GHJUHHV DQG GHJUHHV WR UDGLDQV XVLQJ '(* DQG 5$' )RU
H[DPSOH \RX FDQ XVH '(* DQG 5$' ZLWK WKH WULJRQRPHWULF
LQVWUXFWLRQV VHH FKDSWHU
7DEOH $ OLVWV WKH DYDLODEOH FRQYHUVLRQ LQVWUXFWLRQV
Table 6.A
Available Conversion Instructions
If You Want to:
Found on Page:
Convert from integer to BCD
TOD
6-2
Convert from BCD to integer
FRD
6-2
Convert radians to degrees
DEG*
6-3
Convert degrees to radians
RAD*
6-4
* These instructions are only supported by Enhanced PLC-5 processors.

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$SSHQGL[ &

VWDWXV ILOH 6 7DEOH % OLVWV WKH VWDWXV IODJV
Table 6.B
Arithmetic Status Flags
This Bit:
Description:
S:0/0
Carry (C)
S:0/1
Overflow (V)
S:0/2
Zero (Z)
S:0/3
Sign (S)
1785-6.1 November 1998
6-2
Conversion Instructions FRD and TOD, DEG and RAD
Convert to BCD (TOD)

8VH WKH 72' LQVWUXFWLRQ WR FRQYHUW DQ LQWHJHU YDOXH WR D %&' YDOXH
,I WKH LQWHJHU YDOXH LV JUHDWHU WKDQ WKH SURFHVVRU VWRUHV DQG
VHWV WKH RYHUIORZ ELW ,I WKH LQWHJHU YDOXH LV QHJDWLYH WKH SURFHVVRU
VWRUHV LQ WKH GHVWLQDWLRQ DQG VHWV WKH RYHUIORZ DQG ]HUR VWDWXV ELWV
Description:
TOD
TO BCD
Source
Table 6.C
Updating Arithmetic Status Flags for a TOD Instruction
Destination
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
sets if integer value is outside the range

0-9999; otherwise resets
Zero (Z)
sets if destination value is negative or

zero; otherwise resets
Sign (S)
always resets
Example:
TOD
I:012
]
TO BCD
10
Source
N7:3
Destination
D9:3
If input word 12, bit 10 is set, convert the value in N7:3 to a BCD value and store the result in D9:3.
Convert from BCD (FRD)

Description:
FRD
FROM BCD
Source
Destination
1785-6.1 November 1998
8VH WKH )5' LQVWUXFWLRQ WR FRQYHUW D %&' YDOXH WR DQ LQWHJHU YDOXH

&RQYHUW %&' YDOXHV WR LQWHJHU YDOXHV EHIRUH \RX PDQLSXODWH WKRVH
YDOXHV ZLWK ODGGHU ORJLF EHFDXVH WKH SURFHVVRU WUHDWV %&' YDOXHV DV
LQWHJHU YDOXHV 7KH DFWXDO %&' YDOXH PD\ EH ORVW RU GLVWRUWHG
Table 6.D
Updating Arithmetic Status Flags for a TOD Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
sets if destination value is zero; otherwise resets
Sign (S)
always resets
6-3
7KH )5' LQVWUXFWLRQ ZLOO FRQYHUW D QRQGHFLPDO QXPEHU ZLWKRXW DQ\

HUURU FRQGLWLRQ )RU H[DPSOH LI D & LV LQ WKH VRXUFH LW LV FRQYHUWHG
WR HYHQ WKRXJK & LV QRW D YDOLG GHFLPDO QXPEHU
Example:
FRD
I:012
]
FROM BCD
10
Source
D9:3
Destination
N7:3
If input word 12, bit 10 is set, convert the value in D9:3 to an integer value and store the result in N7:3.
Degree (DEG)
8VH WKH '(* LQVWUXFWLRQ WR FRQYHUW UDGLDQV 6RXUFH WR GHJUHHV DQG
VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH WLPHV
Description:
DEG
Table 6.E
Updating Arithmetic Status Flags for an DEG Instruction
RADIANS TO DEGREE
Source
Destination
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
DEG
RADIANS TO DEGREE
Source
F8:7
0.7853982
Destination
F8:8
45
If input word 12, bit 10 is set, convert the value in F8:7 to degrees and store the result on F8:8.
1785-6.1 November 1998
6-4
Radian (RAD)
8VH WKH 5$' LQVWUXFWLRQ WR FRQYHUW GHJUHHV 6RXUFH WR UDGLDQV DQG
VWRUH WKH UHVXOW LQ WKH 'HVWLQDWLRQ 6RXUFH WLPHV
Description:
RAD
DEGREES TO RADIANS
Table 6.F
Updating Arithmetic Status Flags for an RAD Instruction
Source
Destination
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
Zero (Z)
Sign (S)
Example:
I:012
]
]
10
RAD
DEGREES TO RADIANS
Source
N7:9
45
Destination
F8:10
0.7853982
If input word 12, bit 10 is set, convert the value in N7:9 to radians and store the result on F8:10.
1785-6.1 November 1998
Chapter
Bit Modify and Move Instructions

BTD, MOV, MVM
Using Bit Modify and Move
Instructions
7KH ELW PRGLI\ DQG PRYH LQVWUXFWLRQV OHW \RX PRGLI\ DQG PRYH ELWV
7DEOH $ OLVWV WKH DYDLODEOH PRYH LQVWUXFWLRQV
Table 7.A
Available Bit Modify and Move Instructions
If You Want to:
Found on Page:
Move bits within a word or between words
BTD
7-2
Copy the value in one word to another word
MOV
7-3
Copy the desired part of a 16-bit value by

masking the rest of the value with a mask
MVM
7-4
7KHVH LQVWUXFWLRQV RSHUDWH RQ ELW LQWHJHU ELQDU\ RU IORDWLQJ SRLQW

QXPEHUV WR PRYH RU FRS\ ELWV EHWZHHQ ZRUGV 7KH 090 LQVWUXFWLRQ
XVHV D PDVN WR HLWKHU SDVV RU EORFN VRXUFH GDWD ELWV $ PDVN SDVVHV
GDWD ZKHQ WKH PDVN ELWV DUH VHW D PDVN EORFNV GDWD ZKHQ WKH
PDVN ELWV DUH UHVHW 7KH PDVN PXVW EH WKH VDPH ZRUG VL]H DV WKH
VRXUFH DQG GHVWLQDWLRQ
:KHQ URXQGLQJ IORDWLQJ SRLQW QXPEHUV GXULQJ D PRYH WR DQ LQWHJHU
ZRUG WKH SURFHVVRU GRHV QRW FRUUHFWO\ URXQG QXPEHUV OHVV WKDQ
$SSHQGL[ &
1785-6.1 November 1998
7-2
Bit Modify and Move Instructions BTD, MOV, MVM
Bit Distribute (BTD)

Description:
BTD
BIT FIELD DISTRIB
Source
Source bit
Destination
Destination bit
Length
7KH %7' LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW PRYHV XS WR ELWV

RI GDWD ZLWKLQ D ZRUG RU EHWZHHQ ZRUGV 7KH 6RXUFH UHPDLQV
XQFKDQJHG 7KH LQVWUXFWLRQ ZULWHV RYHU WKH 'HVWLQDWLRQ ZLWK WKH
VSHFLILHG ELWV ,I WKH OHQJWK RI WKH ELW ILHOG H[WHQGV EH\RQG WKH
'HVWLQDWLRQ ZRUG WKH SURFHVVRU GRHV QRW VDYH WKH RYHUIORZ ELWV
7KHVH RYHUIORZ ELWV DUH ORVW WKH\ GR QRW ZUDS LQWR WKH QH[W ZRUG
2Q HDFK VFDQ ZKHQ WKH UXQJ WKDW FRQWDLQV WKH %7' LQVWUXFWLRQ LV WUXH
WKH SURFHVVRU PRYHV WKH ELW ILHOG IURP WKH VRXUFH ZRUG WR WKH
GHVWLQDWLRQ ZRUG 7R PRYH GDWD ZLWKLQ D ZRUG HQWHU WKH VDPH DGGUHVV
IRU WKH VRXUFH DQG GHVWLQDWLRQ
Entering Parameters
7R SURJUDP WKH %7' LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU ZLWK
WKH IROORZLQJ
Parameter:
Definition:
Source
the address of the source word in binary or integer. The source

remains unchanged.
Source bit
the number of the bit (lowest bit number) in the source word from
which to start the move.
Destination
the address of the destination word in a binary or integer file. The

instruction writes over any data already stored at the destination.
Destination bit
the number of the bit (lowest bit number) in the destination word
where the processor starts copying the bits from the source word.
Length
the number of bits to be moved.
Example:
Moving Bits Within a Word
BTD
Destination Bit
N70:22/10
BIT FIELD DISTRIB

Source
Source bit
Destination
Destination bit
Length
N70:22
3
N70:22
10
6
15
1 0 1 1 0 1
Source Bit
N70:22/3
08 07
1 0 1 1 0 1
00
N70:22
13384
1785-6.1 November 1998
7-3
Example:
Moving Bits Between Words
Source Bit
N7:020/3
BTD
BIT FIELD DISTRIB
Source
Source bit
Destination
Destination bit
Length
15
08 07
N7:20
3
N7:22
5
10
00
N7:20
0 1 1 1 0 1 1 1 0 1
Destination Bit
N7:022/5
15
08 07
00
N7:22
0 1 1 1 0 1 1 1 0 1
13384
,PSRUWDQW %LWV DUH ORVW LI WKH\ H[WHQG EH\RQG WKH HQG RI WKH
GHVWLQDWLRQ ZRUG WKH ELWV DUH QRW ZUDSSHG WR WKH QH[W
KLJKHU ZRUG
Move (MOV)
Description:
MOV
MOVE
7KH 029 LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRSLHV WKH 6RXUFH

DGGUHVV WR D 'HVWLQDWLRQ $V ORQJ DV WKH UXQJ UHPDLQV WUXH WKH
LQVWUXFWLRQ PRYHV WKH GDWD HDFK VFDQ
7DEOH % GHVFULEHV KRZ WKH SURFHVVRU XSGDWHV WKH DULWKPHWLF VWDWXV
IODJV
Source
Destination
Table 7.B
Updating Arithmetic Status Flags for a MOV Instruction
Example:
MOV
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
sets if overflow generated during floating

point-to-integer conversion; otherwise resets
Zero (Z)
Sign (S)
7R SURJUDP WKLV LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU ZLWK WKH
IROORZLQJ
MOVE
Source
Destination
N7:0
N7:2
Parameter:
Definition:
source
is a program constant or data address from which the instruction

reads an image of the value.
You can also use a symbol, as long as the symbol name is more
than 1 character. The source remains unchanged.
destination
the data address to which the instruction writes the result of

the operation. The instruction writes over any data stored at
the destination.
1785-6.1 November 1998
7-4
Masked Move (MVM)

Description:
MVM
MASKED MOVE
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Source
Mask
Destination
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Table 7.C
Updating Arithmetic Status Flags for a MVM Instruction
With this Bit:
The Processor:
Carry (C)
always resets
Overflow (V)
always resets
Zero (Z)
Sign (S)
Entering Parameters
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Example:
1785-6.1 November 1998
Parameter:
Definition:
Source
a program constant or data address from which the instruction reads an

image of the value. The source remains unchanged.
Mask
an address or hexadecimal value that specifies which bits to pass or

block.
You must set (1) mask bits to move data. Moved data overwrites
destination data. Bits at the destination that correspond to zeros in the
mask are not altered.
If you want the ladder program to change the mask value, store the mask
at a data address. When you enter a value in this field, make sure that
you include the data type, file number and word number. For example,
type B100:0.
Otherwise, enter a hexadecimal value for a constant mask value. For
example, type F800.
Destination
the data address to which the instruction writes the result of the
operation. The instruction writes over any data stored at the destination.
7-5
Destination
N7:2
Before Move
MVM
MASKED MOVE
Source
Mask
Destination
N7:0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1111000011110000
N7:2
Mask
F0F0
Source
N7:0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
Destination
N7:2
After Move
0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1
13360
1785-6.1 November 1998
7-6
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Chapter

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Entering Parameters
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
EN
DN
ER
Parameter:
Definition:
Control
the address of the control structure in a control type (R) file. The
processor uses this information to run the instruction. See Using the
Control Structure on page 8-2.
Length
the number of words in the data block on which the file instruction
operates. Enter any decimal number 1-1000.
Position
the current word within the data block that the processor is accessing.
You generally enter a zero to start at the beginning of a block.
Mode
the number of file words operated on each time the rung is scanned in
the program. The mode lets you distribute operation on the complete
block of words. Specify one of the following:
for All mode, type an A
for Numerical mode, type a decimal number (1-1000)
for Incremental mode, type an I
For more information about the different modes, see Choosing Modes of
Block Operation on page 8-5.
Destination
the address where the processor stores the result of the operation. The
instruction converts to the data type specified by the destination address.
Expression
contains addresses, program constants, and operators that specify the

source of data and the operations to be performed.
If you enter the index prefix (#) for a destination or expression address,
the processor accepts it as the address of the first word of a block to be
operated upon. The processor assigns and uses the offset value in
module status to process the block address. If you omit the # prefix, the
processor accepts this as the address of a single work to be operated
upon.
1785-6.1 November 1998
8-2
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Figure 8.1
Example Control File R6:0
Memory
Control Structure Address
Status
Length
R6:0
Position
Status
Length
R6:1
Position
Status
Length
R6:2
Position
13370
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FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Dest
Expression
EN
R6:5
4
0
ALL
#N28:0
N27:3
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Dest
Expression
ER
The # prefix for the destination address and the

absence of a # prefix for the expression address
establish this as a word-to-block operation.
EN
R6:5
4
0
ALL
N28:0
#N27:3
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Dest
Expression
DN
DN
ER
The absence of a # prefix for the destination

address and the # prefix for the expression address
establish this as a block-to-word operation.
EN
R6:5
4
0
ALL
#N28:0
#N27:3
DN
ER
The # prefix for the destination address and the

# prefix for the expression address establish this
as a block-to-block operation.
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8-4
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Moving Data
E
Word to Block
Block to Block
Block to Word
Operating on Data
E
Block
= Result
Word
E
Word
Word
Word
Block
Block
= Result
Block
= Result
D
Block
Block
= Result
Word
= Result
D
Word
= Result
16617a
Block
1785-6.1 November 1998
Block
= Result
Choosing Modes of Block

Operation
8-5
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Data File
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One Scan
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One
program
scan
Condition of rung that
controls file/block instruction
Enable (bit 15)
Done (bit 13)
The processor turns

off status bits and
zeroes position value.
Execution of the instruction

Operation complete
16640
1785-6.1 November 1998
8-6
Numerical Mode
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File
Word
Scan #1
512
5 words
Scan #1
516
517
Scan #2
521
522
Scan #3
5 words
14-Word Block
Scan #2
Scan #3
Remaining
4 words
525
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Rung is true at completion
Rung is not true at completion
Multiple program
scans
Multiple program
scans

controls file instruction
Enable (bit 15)
Done (bit 13)
Execution of instruction
Operation complete
The processor turns off

enable and done bit and
Operation complete
The processor
turns off done
bit and zeroes
position value.
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1-Word Operation
1-Word Operation
1-Word Operation
File Word
File
Word
Word #0
512
Word #1
513
Word #2
514
Word #3
515
Word #12
524
Word #13 (last word)
525
1st Rung Enable

2nd Rung Enable
3rd Rung Enable
Word File
1-Word Operation
14th Rung Enable
16

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One or more
program
scans
controls file instruction
Enable (bit 15)

Done (bit 13)
Execution of instruction
The processor
turns off enable bit.
Operation complete
The processor turns

off status bits and
16644
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8-8
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Chapter
File Instructions FAL, FSC, COP, FLL

Using File Instructions
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Table 9.A
Available File Instructions
If You Want to:
Use this Operation:
Found on
Page:
Perform arithmetic, logic, shift, and

function operations on file data
FAL
9-2
Perform search and compare operations on

file data
FSC
9-14
Copy the contents of a file into another file
COP
9-19
Fill a file with specific values
FLL
9-20
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File Arithmetic and Logic (FAL)
Description:
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
EN
DN
ER
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1785-6.1 November 1998
9-3
Table 9.B
FAL Operations
Type
Operator
Description
Example Operation
Copy
none
copy from A to B
enter source address in the expression enter

destination address in destination
Clear
none
set a value to zero
0 (enter 0 for the expression)
Arithmetic
add
2+3
2+3+7
12 5
(12 5) 1
5*2
6 * (5 * 2)
24 | 6
(24 | 6) * 2
Bitwise
Conversion
subtract
multiply
divide
negate
N7:0
SQR
square root
SQR N7:0
**
exponential
10**3
AND
bitwise AND
D9:3 AND D10:4
OR
bitwise OR
D9:4 OR D9:5
XOR
D10:10 XOR D10:11
NOT
bitwise complement
NOT D9:4
FRD
convert from BCD

to binary
FRD D14:0
TOD
convert from binary

to BCD
TOD N7:0
1785-6.1 November 1998
9-4
Using Status Bits

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LQ WKH FRQWURO HOHPHQW <RX DGGUHVV WKHVH ELWV E\ PQHPRQLF
This Bit:
Is Set:
Enable .EN (bit 15)
by a false-to-true rung transition and indicates the instruction is

enabled.
In incremental mode, the .EN bit follows the rung condition.
In numerical and ALL modes, the .EN bit remains set until the
instruction completes its operation, regardless of the rung
condition. The .EN bit is reset when the rung goes false and the
instruction completes its operation.
Done .DN (bit 13)
after the instruction has operated on the last set of words.

In numerical mode if the instruction is false at completion, it resets
the .DN bit one program scan after the operation is complete. If
the instruction is true at completion, the .DN bit is reset when the
instruction goes false.
Error .ER (bit 11)
when the operation generates an overflow. The instruction stops

until the ladder program resets the .ER bit.
When the processor detects an error, the position value stores the
number of the word that faulted.
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UXQV SURSHUO\
ILOH DQG PDNH \RXU HGLWV LQ WKH 3& WH[W ILOH 7KHQ LPSRUW WKLV WH[W
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7KH )$/ FRS\ RSHUDWLRQ FRSLHV GDWD
FAL Copy Operations
EHWZHHQ ILOHV
IURP D ZRUG WR D ILOH
IURP D ILOH WR D ZRUG
7R FRS\ GDWD ZLWK WKH )$/ FRS\ RSHUDWLRQ HQWHU WKH VRXUFH DGGUHVV
RU SURJUDP FRQVWDQW LQ WKH H[SUHVVLRQ DQG WKH GHVWLQDWLRQ DGGUHVV LQ
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File-to-File Copy Example:

FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
EN
R6:5
4
0
ALL
#N28:0
#N27:3
Element 3
DN
4
ER
File #N27
File #N28
9732
9732
0 Element
1015
1015
2000
2000
19000
19000
5
6
2
3
13366
This Parameter:
Tells the Processor:
Control (R6:5)
What control structure controls the operation.

This parameter is controlled by the rung condition, the state of
the .EN and .DN bits, and by the mode (incremental, numeric, or
all). It contains the location of the last value written to by the FAL
instruction.
For example, if, in incremental mode, position = 0 and length =
4, the last word written to by the FAL instruction would be word
3 since the instruction starts at location 0.
Length (4)
To move four words
Position (0)
To start at the source address
Mode (ALL)
To execute the length in one program scan
Destination (#N28:0)
Where to write the data (the # indicates that the operation is to

be performed on a file)
Expression (#N27:3)
Where to read the data (the # indicates that the operation is to

be performed on a file)
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ILOH 1 ZRUG E\ ZRUG VWDUWLQJ DW HOHPHQW DQG ZULWHV WKH LPDJH WR
LQWHJHU ILOH 1 VWDUWLQJ DW HOHPHQW ,W ZULWHV RYHU DQ\ GDWD LQ WKH
GHVWLQDWLRQ ILOH
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9-6
File-to-Word Copy Example:

1st move
FAL
FILE ARITH/LOGICAL
EN
Control
Length
Position
Mode
Destination
R6:6
5
0
INC
N29:5
Expression
#N29:0
Word 29:5
2nd move
File # N29:0
Word 0
Word
DN
1
ER
2
5th move
4th move
4
3rd move
13372
This Parameter:
Control (R6:6)
What control structure controls the operation
Length (5)
To copy five words
Position (0)
Mode (incremental)
To copy one word each time the rung goes true
Destination (N29:5)
Where to write the data (word address)
Expression (#N29:0)
Where to read the data (the # indicates that the

operation is to be performed on a file)
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HOHPHQW RI LQWHJHU ILOH 1 VWDUWLQJ DW HOHPHQW DQG ZULWHV WKH LPDJH
LQWR HOHPHQW RI LQWHJHU ILOH 1 7KH LQVWUXFWLRQ ZULWHV RYHU DQ\
GDWD LQ WKH GHVWLQDWLRQ
$ ZRUGWRILOH PRYH LV VLPLODU H[FHSW WKDW WKH LQVWUXFWLRQ FRSLHV GDWD
IURP D ZRUG DGGUHVV LQWR D ILOH 7KH ZRUG DGGUHVV FDQ EH LQ WKH VDPH
RU D GLIIHUHQW ILOH
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FAL Arithmetic Operations
9-7
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RU IORDWLQJ SRLQW ZLWK WKH IROORZLQJ RSHUDWRUV
Operator:
Meaning:
Operator:
Meaning:
add
divide
subtract
negate
multiply
clear
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Upper and Lower Limits

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RQ WKH W\SH RI ILOH LQ ZKLFK WKH GDWD LV VWRUHG 7KH IROORZLQJ
JXLGHOLQHV DSSO\
DOO GDWD H[FHSW IORDWLQJ SRLQW LV VLJQHG LQWHJHU
QHJDWLYH YDOXHV DUH VWRUHG LQ WZRV FRPSOHPHQW
IORDWLQJ SRLQW QXPEHUV DUH IRUPDWWHG DV D VXEVHW RI ,(((

VLQJOHSUHFLVLRQ IORDWLQJ SRLQW
Type of File:
Range Stored in Word:
bit
32,768 to +32,767 for integers
integer
32,768 to +32,767
timer
0 to +32,767
counter
32,768 to +32,767
control
0 to +32,767
floating point
1.1754944e38 to 3.4028237e+38
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:KHQ WKH UXQJ JRHV WUXH WKH SURFHVVRU DGGV YDOXHV LQ ILOH 1
WR WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ WKH QXPHULFDO PRGH
RI ZRUGV SHU VFDQ 7KH RSHUDWLRQ LV SHUIRUPHG LQ VFDQV DQG WKH
LQVWUXFWLRQ VHTXHQWLDOO\ DGGV WKH YDOXHV LQ WKH H[SUHVVLRQ VWRULQJ WKH
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Addition Example:
FAL
FILE ARITH/LOGICAL
R6:0
Control
100
Length
0
Position
10
Mode
Dest
#N13:0
Expression
#N11:0 + #N12:0
EN
DN
ER
File # N11:0
File # N13:0
10
338
32
182
11
147
179
99
99
45
572
617
1579
300
1879
620
42
662
800
19
819
1243
1000
2243
328
150
10
32
First Scan
Second Scan
next 10 words
Third Scan
next 10 words
Fourth Scan
next 10 words
//
99
//
last 10 elements
//
//
//
//
Tenth Scan
File # N12:0
99
99
13386
1785-6.1 November 1998
This Parameter:
Control (R6:0)
What control structure controls operation
Length (100)
To operate on one hundred elements
Position (0)
Mode (10)
To execute the data in 10 words per scan
Where to write the result data
Expression
(#N11:0 + #N12:0)
The operators, program constants, and

source addresses
9-9
Subtraction Example:
File #N14
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Dest
Expression
EN
R6:1
8
0
ALL
#N15:10
-256 =
File #N14
328
72
10
DN
150
-106
11
ER
10
-246
12
32
-224
13
-256
14
45
-211
15
1579
1323
16
620
364
17
One
Scan
Required
#N14:0 - 256
16655a
This Parameter:
Control (R6:1)
Length (8)
To operate on eight words
Position (0)
Mode (ALL)
To execute the data in one program scan
Expression
(#N14:0 256)

source addresses
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LQWHJHU ILOH 1 ZRUG E\ ZRUG VWDUWLQJ DW HOHPHQW VXEWUDFWV D
SURJUDP FRQVWDQW IURP HDFK DQG ZULWHV WKH UHVXOW LQWR
GHVWLQDWLRQ ILOH 1 VWDUWLQJ DW HOHPHQW DOO LQ RQH VFDQ
1785-6.1 November 1998
9-10
Multiplication Example:
FAL
FILE ARITH/LOGICAL
EN
R6:2
16
0
INC
#F8:16
Control
Length
Position
Mode
Dest
Expression
DN
ER
#F8:0 * #N17:0
File #F8:0
File #N17:0
File #F8:16
0.01
314
3.14
16
0.1
315
31.5
17
Third Transition
1.0
316
316
18
Fourth Transition
10.0
317
3170
19
First Transition
Second Transition
20
21
22
23
24
25
//
//
//
//
//
//
15
15
31
15290
This Parameter:
Control (R6:2)
Length (16)
To operate on sixteen words
Position (0)
Mode (incremental)
To execute using incremental mode
Destination (#F8:16)
Expression
(#F8:0 * #N17:0)

source addresses
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) E\ WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ LQFUHPHQWDO
PRGH 2QH PXOWLSOLFDWLRQ LV SHUIRUPHG IRU HDFK IDOVH WR WUXH
WUDQVLWLRQ 7KH RSHUDWLRQ UHTXLUHV WUDQVLWLRQV VWRULQJ WKH UHVXOW LQ
ILOH )
1785-6.1 November 1998
9-11
Division Example:
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
EN
R6:2
16
0
INC
#N13:0
DN
ER
#N11:0 | #N12:0
File N11:0
First Transition
60
File N12:0
Word
0
File N13:0
Word
0
12
Word
0
Second Transition
175
35
Third Transition
1128
141
45
Fourth Transition
15
//
//
//
//
//
//
15
15
17955
This Parameter:
Control (R6:2)
Length (16)
To operate on sixteen words
Position (0)
Mode (incremental)
To execute using incremental mode
Expression
(#N11:0 | #N12:0)
The operators and source addresses
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VWDUWLQJ DW 1 E\ WKH FRUUHVSRQGLQJ YDOXHV LQ ILOH 1 XVLQJ
LQFUHPHQWDO PRGH 2QH GLYLVLRQ LV SHUIRUPHG IRU HDFK WUDQVLWLRQ WR
WUXH 7KH RSHUDWLRQ UHTXLUHV WUDQVLWLRQV VWRULQJ WKH UHVXOW LQ D
ZRUG ILOH VWDUWLQJ DW 1
1785-6.1 November 1998
9-12
File Square Root Example:

FAL
FILE ARITH/LOGICAL
Control
R6:4
Length
64
Position
0
Mode
4
#N23:4
Destination
Expression
SQR #N22:25
EN
DN
ER
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VTXDUH URRW RI WKH YDOXH DW WKH VRXUFH 7KH UDWH LV GHWHUPLQHG E\ WKH
PRGH \RX VHOHFW 7KH UHVXOW RI HDFK VTXDUH URRW RSHUDWLRQ LV VWRUHG LQ
WKH FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ RQH ZRUG DW D WLPH
7KH SURFHVVRU WDNHV WKH VTXDUH URRW RI WKH DEVROXWH YDOXH LI WKH VLJQ
LV QHJDWLYH WKH SURFHVVRU GLVUHJDUGV WKH VLJQ
This Parameter:
Control (R6:4)
Length (64)
To take the square root of 64 words
Position (0)
Mode (4)
To operate on 4 words each scan
Expression (SQR #N22:25)
The operator and source address
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GHVWLQDWLRQ ILOH EHJLQQLQJ DW 1 (YHU\ WLPH WKH UXQJ LV VFDQQHG
WKHUHDIWHU WKH QH[W IRXU ZRUGV DUH FDOFXODWHG DQG WKH UHVXOW ZULWWHQ
WR WKH GHVWLQDWLRQ ILOH 7KH SURFHVVRU UHTXLUHV D WRWDO RI VFDQV
OHQJWK PRGH WR FRPSOHWH WKH LQVWUXFWLRQ
FAL Logic Operations
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IROORZLQJ ELWZLVH ORJLF RSHUDWRUV
$1'
25
;25
127
7R SHUIRUP PXOWLSOH ORJLF RSHUDWLRQV \RX HQWHU WKH RSHUDWRUV VRXUFH

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1785-6.1 November 1998
9-13
Logical OR Example:
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
#I:000 OR #B3:6
EN
R6:4
6
0
2
#B5:24
DN
ER
Word
File I:000
First Scan
Second Scan
or
File B3
Word
Word
File B5
0000000000000000
1010101010101010
1010101010101010
24
1111111111111111
1111111100000000
1111111111111111
25
1111000011110000
0000000000000000
1111000011110000
26
1010101010101010
1100110011001100
1110111011101110
27
Third Scan
10
11
28
29
16618a
This Parameter:
Control (R6:4)
Length (6)
To OR 6 words
Position (0)
Mode (2)
To move 2 words each scan
Destination (#B5:24)
Expression
(#I:000 OR #B3:6)
The operator(s) and source addresses
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WZR ZRUGV EHJLQQLQJ DW , DQG % 7KH UHVXOW LV ZULWWHQ LQ WKH
GHVWLQDWLRQ ILOH EHJLQQLQJ DW % (YHU\ WLPH WKH UXQJ LV VFDQQHG
WKHUHDIWHU WKH QH[W WZR ZRUGV DUH FDOFXODWHG DQG WKH UHVXOW ZULWWHQ WR
WKH GHVWLQDWLRQ ILOH 7KH SURFHVVRU UHTXLUHV D WRWDO RI VFDQV
OHQJWK PRGH WR FRPSOHWH WKH LQVWUXFWLRQ
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PRUH LQIRUPDWLRQ DERXW RUGHU RI RSHUDWLRQV VHH FKDSWHU
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9-14
7KH )$/ LQVWUXFWLRQ FDQ SHUIRUP WKHVH FRQYHUW RSHUDWLRQV
FAL Convert Operations
Example: Convert to BCD

FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
TOD #N7:0
R6:2
12
0
ALL
#N14:0
EN
DN
FRQYHUW IURP LQWHJHU WR %&' 72'
FRQYHUW IURP %&' WR LQWHJHU )5'
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WKH VRXUFH IURP LQWHJHU WR %&' 7KH UDWH LV GHWHUPLQHG E\ WKH PRGH
WKDW \RX VHOHFW 7KH UHVXOW RI WKH RSHUDWLRQ LV VWRUHG LQ WKH
FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ
ER
Example: Convert from BCD
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WKH VRXUFH IURP %&' WR LQWHJHU 7KH UDWH LV GHWHUPLQHG E\ WKH PRGH
WKDW \RX VHOHFW 7KH UHVXOW RI WKH RSHUDWLRQ LV VWRUHG LQ WKH
FRUUHVSRQGLQJ ZRUG LQ WKH GHVWLQDWLRQ
,PSRUWDQW &RQYHUW %&' YDOXHV WR LQWHJHU EHIRUH PDQLSXODWLQJ
WKHP LI \RX GR QRW FRQYHUW WKH YDOXHV WKH SURFHVVRU
PDQLSXODWHV WKHP DV LQWHJHU DQG WKHLU %&' YDOXH LV ORVW
File Search and Compare (FSC)
Description:
FSC
FILE SEARCH/COMPAR
Control
Length
Position
Mode
Expression
EN
DN
ER
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FRPSOH[ H[SUHVVLRQV (QKDQFHG 3/& SURFHVVRUV RQO\ 7KH
GLIIHUHQFH LV WKDW WKH )6& LQVWUXFWLRQ SHUIRUPV ORJLFDO RSHUDWLRQV RQ
ILOHV ZKLOH WKH &03 LQVWUXFWLRQ RSHUDWHV RQ D VLQJOH ZRUG $OVR WKH
)6& LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ ZKLOH WKH &03 LQVWUXFWLRQ LV
DQ LQSXW LQVWUXFWLRQ
7KH )6& LQVWUXFWLRQ LV DQ RXWSXW LQVWUXFWLRQ WKDW FRPSDUHV YDOXHV LQ
VRXUFH ILOHV ZRUG E\ ZRUG IRU WKH ORJLFDO RSHUDWLRQV \RX VSHFLI\ LQ
WKH H[SUHVVLRQ :KHQ WKH SURFHVVRU ILQGV WKH VSHFLILHG FRPSDULVRQ LV
WUXH LW VHWV WKH IRXQG ELW )' DQG UHFRUGV WKH SRVLWLRQ 326 ZKHUH WKH
WUXH FRPSDULVRQ ZDV IRXQG 7KH LQKLELW ELW ,1 LV VHW WR SUHYHQW DQ\
IXUWKHU VHDUFKLQJ RI WKH ILOHV
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326 WR WDNH DSSURSULDWH DFWLRQ 5HVHW WKH LQKLELW ELW ,1 VR WKH
LQVWUXFWLRQ FDQ FRQWLQXH
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SURJUDP VFDQV E\ \RXU VHOHFWLRQ RI LQVWUXFWLRQ PRGH )RU PRUH
LQIRUPDWLRQ DERXW PRGHV RI ILOH RSHUDWLRQ VHH FKDSWHU
8VH WKLV LQVWUXFWLRQ WR SHUIRUP RSHUDWLRQV VXFK DV
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VHW KLJK DQG ORZ SURFHVV DODUPV IRU PXOWLSOH DQDORJ LQSXWV
FRPSDUH EDWFK YDULDEOHV DJDLQVW D UHIHUHQFH ILOH EHIRUH VWDUWLQJ D

EDWFK RSHUDWLRQ
9-15
Using Status Bits

7R XVH WKH )6& LQVWUXFWLRQ FRUUHFWO\ \RXU ODGGHU SURJUDP PXVW
H[DPLQH DQG FRQWURO VWDWXV ELWV LQ WKH FRQWURO VWUXFWXUH <RX PXVW
DGGUHVV WKHVH ELWV E\ PQHPRQLF
This Bit:
Is Set:
Enable .EN (bit 15)
by a false-to-true rung transition and indicates the instruction

is enabled.
In incremental mode this bit follows the rung condition. In
Numerical and All modes, this bit remains set until the instruction
completes its operation, regardless of the rung condition. The .EN
bit is reset when rung conditions go false, but only after the
instruction has set the .DN bit.
Done .DN (bit 13)
after the instruction has operated on the last set of words.

In numerical mode if the instruction is false at completion, it
resets the .DN bit one program scan after the operation is
complete. If the instruction is true at completion, the .DN bit is
reset when the instruction goes false.
Error .ER (bit 11)
when the operation generates an overflow. The instruction stops

until the ladder program resets this bit.
When the processor detects an error, the position value stores
the number of the element that faulted.
Inhibit .IN (bit 9)
when the processor detects a true comparison.

Your ladder program must reset this bit to continue the search
after taking an action initiated by examining the .FD bit. The
ladder program must reset this bit to continue operation.
Found .FD (bit 8)
when the processor detects a true comparison. The processor

stops the search and also sets the inhibit .IN bit. The .FD bit is the
output of the FSC instruction.
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7KH IROORZLQJ WLPLQJ GLDJUDP IRU $OO PRGH VKRZV UHODWLRQVKLSV

EHWZHHQ VWDWXV ELWV DQG LQVWUXFWLRQ H[HFXWLRQ ZKHQ WKH LQVWUXFWLRQ
ILQGV WZR WUXH FRQGLWLRQV
Scan Markers
Only
1 Scan
Rung Condition
Enable Bit (.EN)
Done Bit (.DN)
Instruction Execution
Inhibit (.IN) and Found (.FD) Bit
Comparison Found
Ladder Program
Resets Inhibit (.IN) Bit
16656
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1785-6.1 November 1998
FSC Search and Compare

Operations
9-17
7KH )6& LQVWUXFWLRQ SHUIRUPV WKHVH FRPSDULVRQV RQ ILOH GDWD

DFFRUGLQJ WR KRZ \RX VSHFLI\ WKHP LQ WKH ([SUHVVLRQ &RPSOH[
H[SUHVVLRQV DUH YDOLG LQ (QKDQFHG 3/& SURFHVVRUV RQO\
Comparison:
Example Expression:
Search Equal
#N50:0 = #N51:0
Search Not Equal
#N52:0 <> N52:11
Search Less Than
#B3:100 < #N53:0
Search Less Than or Equal
#F60:0 <= F60:12
Search Greater Than
#N54:0 > 256
Search Greater Than or Equal
F60:10 >= #N61:0
Data Conversion
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FRQYHUWLQJ GDWD LQWR LWV ELQDU\ HTXLYDOHQW EHIRUH SHUIRUPLQJ WKH
FRPSDULVRQ 7KH SURFHVVRU WUHDWV WKH IROORZLQJ GDWD W\SHV DV LQWHJHU
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WKH )6& LQVWUXFWLRQ OLPLW WKH FRPSDULVRQV WR OHVV WKDQ
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6LQFH WKH SURFHVVRU LQWHUSUHWV WKHP DV LQWHJHU WKH\ PD\
ORVH WKHLU PHDQLQJ LI \RX HQWHU WKHP DV YDOXHV
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WKH VHFWLRQ 'HWHUPLQLQJ WKH 2UGHU RI 2SHUDWLRQ LQ FKDSWHU
File Search Operation

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E\ WKH PRGH RI RSHUDWLRQ WKDW \RX VSHFLI\
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9-18
Example of Search Not Equal:

FSC
FILE SEARCH/COMPARE
Control
Length
Position
Mode
Expression
#B4:0 <> #B5:0
EN
R6:0
90
0
10
DN
ER
Word
File B4
First scan
File B5
0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 (1 0 0 )
0000000000000001(1)
0000000000000001(1)
0000000000000010(2)
0000000000000010(2)
0000000000000110(6)
0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 )
0 0 00 0 0 0 0 0 0 0 0 0 1 1 0 (6 )
0000000000000111(7)
10
10
Second scan
Ninth scan
Word
0000000100000000(100)
Next 10 words
Next 10 words
Last 10 words
Processor stops and

sets the found and
inhibit bits. To continue,
the program must reset
the inhibit bit.
Next 10 words
Next 10 words
89
Last 10 words
89
This Parameter:
Control (R6:0)
Length (90)
To search through 90 words
Position (0)
To start at source addresses
Mode (10)
To search 10 words per program scan
Expression
(#B4:0 <> #B5:0)
The comparison to perform and the source addresses
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9-19
File Copy (COP)

Description:
COP
COPY FILE
Source
Destination
Length
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Entering Parameters
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Parameter:
Definition:
Source
the starting address of the source file. The source remains unchanged.
Destination
address of the destination file. The instruction writes over any data
already stored at the destination.
Length
the number of the words/structures to overwrite in the destination file.
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1785-6.1 November 1998
9-20
Example:
COP
I:012
[
COPY FILE
10
Source
Destination
Length
#N7:0
#N12:0
5
If input word 12, bit 10 is on, copy the values

of the first five words starting at N7:0 into the first
five words of N12:0.
File Fill (FLL)

Description:
FLL
FILL FILE
Source
Destination
Length
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1785-6.1 November 1998
Parameter:
Definition:
Source
the address of the source word or a program constant. The source

remains unchanged.
Destination
the starting address of the destination file. The instruction writes over
any data already stored at the destination.
Length
the number of the words/structures to fill in the destination file
9-21
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Example:
FLL
I:012
[
FILL FILE
10
Source
Destination
Length
N7:0
#N12:0
5
If input word 12, bit 10 is on, copy the value

of word N7:0 into the first five words
starting at N12:0
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1785-6.1 November 1998
Chapter
10
Diagnostic Instructions FBC, DDT, DTR

Using Diagnostic Instructions
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Table 10.A
Available Diagnostic Instructions
If You Want to:
Use this Operation:
Found on Page:
Compare I/O data against a known, good

reference and record any mismatches
FBC
10-2
Compare I/O data against a known, good

reference, record any mismatches, and
update the reference file to match the
source file
DDT
10-2
Pass source data through a mask and

compare the result to reference data, and
then write the source word into the
reference address of the next comparison.
DTR
10-8

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10-2
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File Bit Comparison (FBC) and

Diagnostic Detect (DDT)
Table 10.B
Available Diagnostic Instructions
Description:
FBC
FILE BIT COMPARE
EN
Source
Reference
Result
Compare Control
Length
Position
Result control
Length
Position
DN
FD
IN
ER
If You Want to Detect Malfunctions By:
Comparing bits in a file of real-time inputs with a

reference bit file that represents correct operation
FBC
Change-of-state diagnostics
DDT
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Selecting the Search Mode

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SURJUDP VFDQ
One Mismatch at a Time
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All Per Scan

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10-4
Entering Parameters
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Parameter:
Description:
Source
the indexed address of your input file.
Reference
the indexed address of the file that contains the data with which you
compare your input file.
Result
the indexed address of the file where the instruction stores the position
(bit) number of each detected mismatch.
Cmp Control
the address of the comparison control structure (R) that stores status
bits, the length of the source and reference files (both should be the
same), and the current position during operation. Use the compare
control address with mnemonic when you address these parameters:
Length (.LEN) is the decimal number of bits to be compared in the
source and reference files. Remember that bits in I/O files are
numbered in octal 00-17, but that bits in all other files are numbered in
decimal 0-15.
Position (.POS) is the current position of the bit to which the instruction
points. Enter a value only if you want the instruction to start at an
offset concurrent with a control file offset for one scan.
Result Control
the address of the result control structure (R) that stores the bit
position number each time the instruction finds a mismatch between
source and reference files.
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10-5
Using Status Bits

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Bit:
Comparison
Control Bits
Result
Control Bits
Function:
Enable .EN (bit 15)
starts operation on a false-to-true rung transition

If the .IN bit is set for one-at-a-time operation, the ladder program
must toggle the .EN bit after the instruction detects each mismatch.
Done .DN (bit 13)
is set when the processor reaches the end of the source and reference files
Error .ER (bit 11)
is set when the processor detects an error and stops operation of

the instruction
For example, an error occurs if the length (.LEN) is less than or equal to zero
or if the position (.POS) is less than zero. The ladder program must reset the
.ER bit if the instruction detects an error.
Inhibit .IN (bit 09)
determines the mode of operation

When this bit is reset, the processor detects all mismatches in one scan.
When this bit is set, the processor stops the search at each mismatch and
waits for the ladder program to re-enable the instruction before continuing
the search.
Found .FD (bit 08)
is set each time the processor records a mismatch bit number in the result file
(one-at-a-time operation) or after recording all mismatches (all per scan).
Done .DN (bit 13)
is set when the result file fills

The instruction stops and requires another false-to-true rung transition to
reset the result .DN bit and then continue. If the instruction finds another
mismatch, it wraps the new position number around to the beginning of the
file, writing over previous position numbers.
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10-6
Example:
DDT
DIAGNOSTIC DETECT
#I:030
Source
#B3:0
Reference
#N10:0
Result
R6:0
Compare control
Length
48
Position
0
Result control
R6:1
Length
10
Position
0
EN
DN
FD
IN
ER
Input
File
#I:030
17
bit 31
10
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07
Result File 2
(mismatched bit #s)
#N10
Reference
File 1
#B3
bit 3
00
15
08
07
00
1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
bit 40
bit32
31
32
40
The FBC and DDT instructions detect mismatches and record their locations by bit number in a result file.
1
The DDT instruction changes the status of the corresponding bit in the reference file to match the input file
when it detects a mismatch.
2
The length of the result file is the length that you enter for RESULT CONTROL.
16657a
1785-6.1 November 1998
This Parameter:
Source (#I:030)
Where to find input data for comparison
Reference (#B3:0)
Where to find the reference file
Result (#N10:0)
Where to store mismatched bit numbers
CMP Control (R6:0)
What control structure controls the comparison
Length (48)
The number of bits to be compared
Position (0)
To start at the beginning of the file
Result Control (R6:1)
What control structure controls the result
Length (10)
The number of words reserved for mismatches
Position (0)
To start at the beginning of the file
10-7
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CLR
Clear
Destination
S:24
FBC
EN
or
Source
Reference
Result
Compare Control
Length
Position
Result Control
Length
Position
#I0:30
#B3:0
#N10:0
R6:0
48
0
R6:1
10
0
DN
FD
IN
ER
DDT
EN
Source
Reference
Result
Compare Control
Length
Position
Result Control
Length
Position
#I0:30
#B3:0
#N10:0
R6:0
48
0
R6:1
10
0
DN
FD
IN
ER
1785-6.1 November 1998
10-8
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Data Transitional (DTR)
Description:
DTR
DATA TRANSITION
Source
Mask
Reference
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Entering Parameters
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Example:
DTR
DATA TRANSITION
Source
Mask
Reference
1785-6.1 November 1998
I:002
0FFF
N63:11
Parameter:
Definition:
Source
the address of the input word, typically real inputs.
Mask
the hexadecimal value or address that contains the mask value
Reference
the address of the reference word

The reference contains the source data from the last DTR scan
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15
10-9
08 07
15
00
08 07
00
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
15
Source Word
I:002
08 07
Previous
Scan
Rung remains false as long as

input value does not change
08 07
15
Mask Value
0FFF
Reference Word
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00
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00
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15
00
Current
Scan
15
08 07
00
Current
Scan
Previous
Scan
Rung goes true for one scan

when change is detected
13385
1785-6.1 November 1998
10-10
1RWHV
1785-6.1 November 1998
Chapter
11
Shift Register Instructions BSL, BSR, FFL,

FFU, LFL, LFU
Applying Shift Registers
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If You Use a Shift Register for:
Data in the Shift Register Could Represent:
Tracking parts through an assembly line
Part types, quality, size, and status
Controlling machine or process operations The order in which events occur

Inventory control
Identification numbers or locations
System diagnostics
A fault condition that caused a shutdown
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Table 11.A
Available Shift Instructions
If You Want to:
Use these Instructions:
Found on Page:
Load bits into, shift bits through, and unload bits from a bit array one bit at
a time, such as for tracking bottles through a bottling line where each bit
represents a bottle
BSL, BSR
11-2
Load and unload values in the same order, such as for tracking parts
through an assembly line where parts are represented by values that have
a part number and assembly code
FFL, FFU
11-5
Load and unload values in reverse order, such as tracking stacked

inventory in a warehouse, where goods are represented by serial number
and inventory codes
LFL, LFU *
11-8
* These instructions are only supported by Enhanced PLC-5 processors.

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1785-6.1 November 1998
11-2
Shift Register Instructions BSL, BSR, FFL, FFU, LFL, LFU
Using Bit Shift Instructions
EN
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Description:
BSL
BIT SHIFT LEFT
File
Control
Bit address
Length
Entering Parameters
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Parameter:
Definition:
File
the address of the bit array you want to manipulate. You must start the
array at a 16-bit word boundary. For example, use bit 0 of word number
1, 2, 3, etc. You can end the array at any bit number up to 15,999.
However, you cannot use the remaining bits in that particular element
because the instruction invalidates them.
Control
The address of the control structure (48 bits three 16-bit words) in the
control area (R) of memory that stores the instructions status bits, the
size of the array (number of bits), and the bit pointer.
Position
the current position of the bit to which the instruction points. Enter a
value only if you want the instruction to start at an offset concurrent with
a control file offset for one scan. Use the control address with mnemonic
when you address this parameter.
Bit Address
the address of the source bit. The instruction inserts the status of this bit
in either the first (lowest) bit position (for the BSL instruction) or the last
(highest) bit position (for the BSR instruction) in the array.
Length
the decimal number of bits to be shifted. Remember that bits in I/O files
are numbered in octal 00-17, but that bits in all other files are numbered
in decimal 0-15. Use the control address with mnemonic when you
address this parameter.
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11-3
Using Status Bits

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Bit:
Definition:
Enable .EN (bit 15)
is set when the rung makes a false-to-true rung transition to

indicate the instruction is enabled.
Done .DN (bit 13)
is set to indicate that the bit array shifted one bit position
Error .ER (bit 11)
is set to indicate that the instruction detected an error, such as if

you entered a negative file length
Unload .UL (bit 10)
is the instructions output.

The .UL bit stores the status of the bit removed from the array
each time the instruction is enabled. Avoid using the .UL bit when
the .ER bit is set.
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Bit Shift Left (BSL) Example:

BSL
15 14 13 12 11 10
BIT SHIFT LEFT

File
Control
Bit address
Length
Source
I:022/12
EN
#B3:1
R6:53
I:022/12
58
31
16
L
DN
47
32
L
48
63
58-Bit
#B3/16
(B3:1)
L
invalid
Unload Bit
64
73
L
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
16658
This Parameter:
File (#B3:1)
The location of the bit array
Control (R6:53)
The instructions address and control element
Bit Address (I:022/12)
The location of the source bit (bit 12 of input word 22)
Length (58)
The number of bits in the bit array
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11-4
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Bit Shift Right (BSR) Example:

BSR
BIT SHIFT RIGHT
File
Control
Bit address
Length
#B3:2
R6:54
I:023/06
38
EN
15 14 13 12 11 10
DN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Unload Bit
47
32
R
48
Bit
Address
I:023/06
R
invalid
69
38-Bit
Array
#B3/32
(#B3:2)
64
R
95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
16659
This Parameter:
File (#B3:2)
The location of the bit array
Control (R6:54)
The instructions address and control element
Bit Address (I:023/06)
The source bit address (bit 06 in input word 23)
Length (38)
The number of bits in the bit array
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1785-6.1 November 1998
11-5
Using FIFO and LIFO Instructions

Description:
FFL
FIFO LOAD
Source
FIFO
Control
Length
Position
EN
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FFU
FIFO UNLOAD
These Instructions:
Retrieve Data:
FFL and FFU
In the order stored (first in, first out)
LFL and LFU *
In reverse of the order stored (last in, first out)
EU
* Available in Enhanced PLC-5 processors only
FIFO
Destination
Control
Length
Position
DN
EM
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This Instruction:
Unloads the Value from:
FIFOs FFU
Word zero
LIFOs LFU
The last word entered
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Using Status Bits

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1785-6.1 November 1998
This Bit:
Is Set:
Enable Load .EN (bit 15)
when the rung makes a false-to-true rung transition to

indicate the instruction is enabled (used in FFL and LFL
instructions).
Note: During prescan, this bit is set to prevent a false load
when the program scan begins.
Enable Unload .EU (bit 14)
when rung conditions are true to indicate the instruction is

enabled (used in FFU and LFU instructions).
Note: During prescan, this bit is set to prevent a false
unload when the program scan begins.
Done .DN (bit 13)
by the processor to indicate that the stack is full. The .DN

bit inhibits loading the stack until there is room.
Empty .EM (bit 12)
by the processor to indicate that the stack is empty. Do not

enable the FIFO or LIFO unload commands if the .EM bit is
set.
11-7
FIFO Load (FFL) and FIFO Unload (FFU)

Example:
DESTINATION
FFL
FIFO LOAD
Source
FIFO
Control
Length
Position
EN
N60:1
#N60:3
R6:51
64
0
DN
File #N60:3
N60:2
FIFO Unload removes data from stack
EM
FFU
FIFO UNLOAD
FIFO
Destination
Control
Length
Position
SOURCE
EU
N60:1
#N60:3
N60:2
R6:51
64
0
Word
3
4
5
6
7
8
9
10
11
DN
64 words
allocated
for FIFO
stack at
#N60:3
FIFO Load enters data into

stack at next position
EM
66
16660a
FIFO Load Description:
This Parameter:
Source (N60:1)
The location of the next in source word
FIFO (#N60:3)
The location of the stack (FIFO file)
Destination (N60:2)
The location of the exit word
Control (R6:51)
The instructions address and control structure
Length (64)
The maximum number of words you can load
Position (0)
To start at the FIFO file address
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FIFO Unload Description:
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11-8
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LIFO Load (LFL) and LIFO Unload (LFU)

Example:
File #N70:3
LFL
LIFO LOAD
Source
LIFO
Control
Length
Position
EN
N70:1
#N70:3
R6:61
64
0
DN
EM
LFU
LIFO UNLOAD
LIFO
Destination
Control
Length
Position
EU
#N70:3
N70:2
R6:61
64
0
DN
SOURCE N70:1
Word
3
4
5
6
7
8
9
10
11
64 words allocated for

LIFO stack at #N70:3
DESTINATION N70:2
EM
LIFO Load enters

data into stack at
next position
63
LIFO Unload removes

data from stack in
reverse order
16621
This Parameter:
Source (N70:1)
the location of the next in source word
LIFO (#N70:3)
the location of the stack (LIFO file)
Destination (N70:2)
the location of the exit word
Control (R6:61)
the instructions control structure
Length (64)
the maximum number of words you can load
Position (0)
to start at the LIFO file address
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1785-6.1 November 1998
LIFO Load Description:
11-9
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LIFO Unload Description:
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1785-6.1 November 1998
11-10
1RWHV
1785-6.1 November 1998
Chapter
12
Sequencer Instructions SQO, SQI, SQL

Applying Sequencers
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Table 12.A
Available Sequencer Instructions
If You Want to:
Found on Page:
Control sequential machine operations by

transferring 16-bit data through a mask to
output image addresses
SQO
12-5
Monitor machine operating conditions for

diagnostic purposes by comparing 16-bit
image data (through a mask) with data in a
reference file
SQI
12-7
Capture reference conditions by manually

stepping the machine through its operating
sequences and loading I/O or storage data
into destination files
SQL
12-8
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Using Sequencer Instructions

Description:
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SQI
SQO
SEQUENCER INPUT
SEQUENCER OUTPUT
File
Mask
Source
Control
Length
Position
File
Mask
Destination
Control
Length
Position
EN
SQL
SEQUENCER LOAD
DN
File
Source
Control
Length
Position
EN
DN
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Entering Parameters
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In this Instruction:
The Sequencer File Stores Data for:
SQO
Controlling outputs
SQI
Reference to detect completion of a

step or a fault condition
SQL
Creating the SQO or SQI file
12-3
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For this Instruction:
The Control Structure Is Incremented:
SQO and SQL
By the instruction itself
SQI
Externally, either by the paired SQO with the same

control address, or by another instruction
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Using Status Bits

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This Bit:
Is Set:
Enable .EN (bit 15)
(SQO or SQL) is set on a false-to-true rung transition to indicate

that the instruction is enabled. The instruction follows the rung
condition.
Note: During prescan, this bit is set to prevent a false increment of
the table pointer when the program scan begins.
Done .DN (bit 13)
(SQO or SQL) is set after the instruction finishes operating on the

last word in the sequencer file. After the rung goes false, the
processor resets the .DN bit on the next false-to-true rung
transition.
Error .ER (bit 11)
when the length value is less than or equal to zero or when the
position value is less than zero
12-5
Sequencer Output (SQO) Example:

File #N7:1
SQO
SEQUENCER OUTPUT
File
Mask
Destination
Control
EN
#N7:1
0F0F
O:014
R6:20
Length
Position
DN
N7:1
17
N7:2
10 10 00 10 11 11 01 01
0
1
N7:3
11 11 01 01 01 00 10 10
01 01 01 01 01 01 0 0 0 1
3 Current Step
00 10 01 00 10 01 00 10
N7:4
N7:5
17
10
10
07
07
00
00
00 00 11 11 00 00 11 11
17
Destination O:014
10
07
Sequencer
Output File
Mask
Value
0F0F
00
00 00 01 01 00 00 10 10
Output Module (s)

17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0
Rack 1
I/O group 4
= No Change
= Off
= On
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
SQO instruction moves the data of the current step through a mask to an output word for controlling
multiple outputs.
16645a
1785-6.1 November 1998
12-6
This Parameter:
File (#N7:1)
The location of the sequencer file
Mask (0F0F)
The fixed hexadecimal value of the mask
Destination (O:014)
The output image address to be changed
Control (R6:20)
The structure that controls the operation
Length (4)
The number of words to step through
Position (2)
The current position
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Resetting the Position of SQO

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S1
MOV
MOVE
15
The bit S:1/15 is the "first pass" bit. This bit is set when the processor
first scans a program. When this rung goes true, the processor moves
the value of 0 to the position word of the SQO instruction. After the
position is set to 0, the next false to true transition will cause the
processor to run step 1.
1785-6.1 November 1998
Source
Dest
0
R6:20.POS
12-7
Sequencer Input (SQI) Example:

SQI
SEQUENCER INPUT
File
Mask
Source
Control
Length
Position
Sequencer Reference File #N7:11
#N7:11
FFF0
I:031
R6:21
4
2
Word
Input Word (Source)

10 07
00
17
00 10 01 00 10 01 11 01
15
08
N 7 :11
Mask Value FFFO

08 07
15
00
11 11 11 11 11 11 00 00
00 Step
0
12
13 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0
14
15
Mask bits are reset
SQI instruction is true when it detects that an input word matches

(through a mask) its corresponding reference word.
1
07
16646a
These bits are not compared. Therefore, the instruction is true in this example.
This Parameter:
File (#N7:11)
The location of the reference file
Mask (FFF0)
The fixed hexadecimal value of the mask
Source (#I:031)
The input image address to be compared
Control (R6:21)
The element that controls the operation
Length (4)
The number of elements to step through
Position (2)
The current position
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Using SQI Without SQO

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Rung 0
ADD
SEQUENCER INPUT
ADD
#N7:0
F0FF
I:005
R6:0
20
0
File
Mask
Source
Control
Length
Position
Rung 1
Source A
Source B
Destination
GTR
MOV
GREATER THAN
MOVE
Source A
Source B
R6:0.POS
R6:0.LEN
R6:0.POS
1
R6:0.POS
0
Source
Destination
0
R6:0.POS
0
Sequencer Load (SQL) Example:

SQL
SEQUENCER LOAD
EN
File
Source
Control
Length
#N7:20
I:002
R6:22
5
Position
DN
17
00
00 00 10 10 11 00 11 01
Input Module (s)

0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
Source Word I:002

10 0 7
Source I:002
Destination File #N7:20

Word
N70:20
15
08
07
00
0
1 Sequencer
Destination
2 File #N7:20
21
22
23
00 00 10 10 11 00 11 01
24
25
3
4
Current Step
Rack 0 I/O Group 2

SQL instruction loads data from the input word into a destination
file from where it can be moved to other sequencer files.
1785-6.1 November 1998
16661a
12-9
This Parameter:
File (#N7:20)
The location of the destination file
Source (I:002)
The input image address to be read
Control (R6:22)
The structure that controls the operation
Length (5)
The number of words to step through
Position (3)
The current step
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Chapter
13
Program Control Instructions MCR, JMP,

LBL, FOR, NXT, BRK, JSR, SBR, RET, TND,
AFI, ONS, OSR, OSF, SFR, EOT, UIE, UID
Selecting Program Flow
Instructions
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Table 13.A
Available Program Control Instructions
Then Use these
Instructions:
Found on
Page:
Turn off all non-retentive outputs in a section

of ladder program
MCR
13-2
Jump over a section of a program that does

not always need to be executed
JMP, LBL
13-3
Loop through a set of rungs for a preset

number of times
FOR, NXT, BRK
13-5
Jump to a separate subroutine file, pass data

to the subroutine, perform an operation, and
return the results
JSR, SBR, RET
13-8
Mark a temporary end that halts program

execution beyond it
TND
13-13
Disable a rung
AFI
13-13
Trigger a one-shot event based on a change in

rung condition
ONS, OSR,* OSF*
13-14 (ONS),
13-15 (OSR),
13-16 (OSF)
Reset a sequential function chart
SFR*
13-17
End a transition file
EOT
13-18
Enable or disable user interrupts
UIE,* UID*
13-19 (UID),
13-20 (UIE)
If You Want to:
*These instructions are only supported by Enhanced PLC-5 processors.

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1785-6.1 November 1998
13-2
Program Control Instructions MCR, JMP, LBL, FOR, NXT, BRK, JSR, SBR, RET, TND, AFI, ONS, OSR, OSF, SFR, EOT, UIE, UID
Master Control Reset (MCR)

Description:
MCR
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If the MCR Rung
that Starts the
Zone Is:
Then the Processor:
True
Executes the rungs in the MCR zone based on each rungs

individual input conditions (as if the zone did not exist).
False
Resets all non-retentive output instructions in the MCR zone

regardless of each rungs individual input conditions.
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I:012
I:012
MCR
01
02
13-3
Beginning of zone
03
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O:013
04
01
I:012
I:012
O:013
11
12
02
I:012
03
I:012
I:012
O:013
13
10
03
MCR
When the first MCR

instruction is true, the
processor executes
the rungs in the zone.
When the first MCR

instruction is false, the
processor resets all
non-retentive outputs
in the zone.
End of zone
Jump (JMP) and Label (LBL)

Description:
JMP
] LBL [
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If the Jump Rung Is:
Then the Processor:
True
Skips from the JMP rung to the LBL rung and continues
executing the program. You can jump forward or backward.
False
Ignores the JMP instruction
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Using JMP
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Using LBL
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If You Have this Processor:
Valid LBL Numbers:
Valid Amount Per

Program File:
Enhanced PLC-5
000-255
256
Classic PLC-5
0-31
32
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JMP and LBL Example:
13-5
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I:012
I:012
O:013
10
11
01
I:012
20
JMP
13
When input I:012/13 is set, the processor jumps to

label 20 and continues program execution. It does not
execute the rungs between these two points.
TON
T4:0
TIMER ON DELAY
DN
Timer
Time base
Preset
Accum
EN
T4:0
1.0
100
0
I:012
O:013
10
13
20
I:012
O:013
17
02
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For Next Loop (FOR, NXT),

Break (BRK)
Description:
FOR
FOR
Label number
Index
Initial value
Terminal value
Step size
NXT
NEXT
Label Number
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Entering Parameters
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Parameter:
Definition:
Label number
the unique label number that marks the location of the FOR instruction. Enter a unique
number. Classic PLC-5 processors support label numbers 0-31; Enhanced PLC-5
processors support label numbers 0-255.
Index
the logical address where the instruction stores the index value it computes. The index
value is the sum of the initial value plus the accumulating step values. The FOR
instruction uses the index value to determine the number of times the loop is executed.
When you enable the FOR instruction, the processor sets the index value equal to the
initial value. Then, if the index values is less than or equal to the terminal value, the
processor loops through the following instructions. If the index is greater than the
terminal value, the processor jumps to the NXT instruction.
When the processor encounters a NXT instruction, it returns to the corresponding FOR
instruction, then it compares the index with the terminal value. If the index is less than
or equal to the terminal value, the processor jumps back to the FOR instruction.
Otherwise it steps to the following instruction. If the processor encounters a BRK on a
true rung, the processor skips to the instruction following the NXT.
Initial value
(index value) is an integer value or integer address that represents the starting value for
the loop.
Terminal value
(reference value) is an integer value or integer address that represents the ending value
for the loop.
Step size
(constant) is an integer value that specifies the amount to increment the index value.
You can change the step value from the ladder program.
Using FOR
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Using NXT
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FOR, BRK, and NXT Example:

If integer file 7, word 10, bit 5 is false,
skip to the rung following the NXT instruction.
N7:10
If integer file 7, word 10, bit 5 is true, initialize N7:0 to

zero and execute the rungs until the NXT. When the
processor encounters the NXT, increment N7:0 and
jump back to the FOR instruction. As long as N7:0
is less than or equal to 10, keep executing the loop.
When N7:0 is greater than 10, jump to the rung
following the NXT.
5
rung
rung
rung
FOR
FOR
Label number
Index
Initial value
Terminal value
Step size
0
N7:0
0
10
1
N7:10
/
BRK
5
rung
rung
rung
rung
rung
rung
If integer file 7, word 10, bit 5 ever goes true,

break out of the loop and jump to the rung
following the NXT instruction.
NXT
NEXT
Label Number
1785-6.1 November 1998
13-8
Jump to Subroutine (JSR),

Subroutine (SBR), and
Return (RET)
Description:
JSR
JUMP TO SUBROUTINE
Prog file number
Input parameter
Return parameter
SBR
SUBROUTINE
Input parameter
RET
RETURN ( )
Return parameter
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Passing Parameters
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Type:
Example:
Program constant (integer)
256
Program constant (floating point)
23.467
Logical element address
N7:0
Logical structure address
C5:0.ACC
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Main Ladder Program
JSR
JUMP TO SUBROUTINE
Values are
returned
Prog file number

Input parameter
Input parameter
Input parameter
Return parameter
Return parameter
90
N16:23
N16:24
231
N19:11
N19:12
Program constants and values

stored at logical addresses are
passed to the SBR instruction
when execution jumps to the
subroutine file.
Execution resumes
Subroutine File 090

SBR
SUBROUTINE
Values and program constants
are stored at logical addresses
in the subroutine as subroutine
execution begins.
Input parameter
Input parameter
Input parameter
N43:0
N43:1
N10:3
RET
Values stored at logical
addresses are returned to the
addresses that you specified in
the JSR instruction when
execution returns to the main
ladder program.
RETURN ( )
Return parameter
Return parameter
N43:5
N43:4
1785-6.1 November 1998
13-10
Entering Parameters
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Parameter:
Definition:
Program file number
the program file number of the file that contains

the subroutine
Input parameter (JSR)
a program constant or an address of a parameter to

be sent to the subroutine (optional)
Input parameter (SBR)
an address where the subroutine stores the incoming

data (optional)
Return parameter (JSR)
an address that stores the data received from the

subroutine (optional)
Return parameter (RET)
a program constant or an address of a parameter

to be returned to the JSR instruction in the main
program (optional)
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Nesting Subroutine Files

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Level 1
Subroutine File 90
Main Program
90
SBR
Level 2
Subroutine File 91
SBR
Level 3
Subroutine File 92
SBR
JS R
91
92
JS R
JS R
RET
RET
RET
15294
Using JSR
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Using RET
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WKH YDOXH VWRUHG DW 1 LV WUDQVIHUUHG WR 1
JSR
JUMP TO SUBROUTINE
Prog file number
Input par
Input par
Input par
Return par
Return par
Balance of Main Program

Subroutine
90
N16:23
N16:24
231
N19:11
N19:12
SBR
SUBROUTINE
Input par
Input par
Input par
N43:0
N43:1
N43:2
(Enter your own logic operation)
RET
RETURN ( )
Return par
Return par
1785-6.1 November 1998
N43:3
N43:4
13-13
Temporary End (TND)

Description:
TND
Example:
I:012
I:012
04
05
TND
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EHJLQV UXQQLQJ WKH ODGGHU SURJUDP DW WKH ILUVW LQVWUXFWLRQ LQ WKH
PDLQ SURJUDP
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ODGGHU SURJUDP 7KH 71' LQVWUXFWLRQ OHWV \RXU SURJUDP UXQ RQO\ XS
WR WKLV LQVWUXFWLRQ 0RYH LW SURJUHVVLYHO\ WKURXJK \RXU SURJUDP DV
\RX GHEXJ HDFK QHZ VHFWLRQ $OVR XVH WKH 71' LQVWUXFWLRQ DV D
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HQGRISURJUDP V\PERO (23 <RX FDQQRW SODFH
LQVWUXFWLRQV RQ WKH UXQJ WKDW KDV WKH (23 V\PERO
Always False (AFI)

Description:
Example:
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ZKHQ LQVHUWHG LQ WKH FRQGLWLRQ VLGH RI WKH UXQJ <RX FDQ XVH WKH $),
LQVWUXFWLRQ WR WHPSRUDULO\ GLVDEOH D UXQJ ZKHQ \RX GHEXJ D SURJUDP
AFI
1785-6.1 November 1998
13-14
One Shot (ONS)

Description:
[ ONS ]
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SUHFHGLQJ WKH 216 LQVWUXFWLRQ RQ WKH UXQJ
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IRU WKH ELW 8VH HLWKHU D ELQDU\ ILOH RU LQWHJHU ILOH DGGUHVV $ XQLTXH ELW
PXVW EH GHGLFDWHG WR HDFK 216 <RX FDQ SURJUDP DQ RXWSXW DGGUHVV
IRU WKH 216 EXW EH DZDUH RI WKH IROORZLQJ
$77(17,21 2QOLQH SURJUDPPLQJ ZLWK WKLV
LQVWUXFWLRQ FDQ EH GDQJHURXV EHFDXVH WKH RXWSXW PD\
WXUQ RQ LPPHGLDWHO\ ZKHQ WKH UXQJ LV VFDQQHG 6HW WKH
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HQHUJL]LQJ LWV RXWSXW
,PSRUWDQW 'XULQJ SUHVFDQ WKH ELW DGGUHVV LV VHW WR LQKLELW IDOVH
WULJJHULQJ ZKHQ WKH SURJUDP VFDQ EHJLQV
Example:
I:011
N7:10
B3
ONS
04
10
When the input condition goes from false to true, the ONS conditions the rung so that
the output turns on for one scan. The output turns off for successive scans until the
input goes from false to true again.
1785-6.1 November 1998
13-15
One Shot Rising (OSR)

Description:
OSR
ONE SHOT RISING
OB
Storage BIt
Output Bit
Output Word
SB
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This Bit:
Changes State as Follows:
Output .OB
Is set for one program scan when the rung goes from false to true
Note: During prescan, this bit is cleared to inhibit false triggering
Storage .SB
Follows the rung status

Note: During prescan, this bit is cleared to inhibit false triggering
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FKDQJH RI VWDWH RI WKH UXQJ IURP IDOVH WR WUXH QRW FRQWLQXRXVO\ ZKHQ
WKH UXQJ LV WUXH <RX PXVW HQWHU D ELW DGGUHVV IRU WKH RXWSXW ELW DQG
VWRUDJH ELW 8VH HLWKHU D ELQDU\ ILOH RU LQWHJHU ILOH DGGUHVV
Entering Parameters
7R SURJUDP WKHVH LQVWUXFWLRQV \RX PXVW SURYLGH WKH SURFHVVRU ZLWK
Parameter:
Definition:
Storage bit
the address where you want the storage bit status stored. For
example, B3/17
Output bit
the bit position in the output word where you want the output
bit status stored. For example 5
Output word
the word address where you want the output bit status
stored. For example, N7:0
1785-6.1 November 1998
13-16
One Shot Falling (OSF)

Description:
OSF
ONE SHOT FALLING
OB
Storage BIt
Output Bit
Output Word
SB
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LQVWUXFWLRQ VHWV WKH IROORZLQJ ELWV
This Bit:
Changes State as Follows:
Output .OB
Is set for one program scan when the rung goes from true to false
Storage .SB
Follows the rung status
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FKDQJH RI VWDWH RI WKH UXQJ IURP WUXH WR IDOVH QRW RQ WKH UHVXOWLQJ UXQJ
VWDWXV <RX PXVW HQWHU D ELW DGGUHVV IRU WKH RXWSXW ELW DQG VWRUDJH ELW
8VH HLWKHU D ELQDU\ ILOH RU LQWHJHU ILOH DGGUHVV
Entering Parameters
7R SURJUDP WKHVH LQVWUXFWLRQV \RX PXVW SURYLGH WKH SURFHVVRU ZLWK
1785-6.1 November 1998
Parameter:
Definition:
Storage bit
the address where you want the storage bit status stored. For
example, B3/17
Output bit
the bit position of the output word where you want the output
bit status stored. For example 5
Output word
the word address where you want the output bit status
stored. For example, N7:0
13-17
Sequential Function Chart Reset

(SFR)
Description:
SFR
SFC Reset
Prog file number
Restart step at
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ILOH DQG WKHQ UHVHWV WKH ORJLF LQ WKH 6)& RQ WKH QH[W SURJUDP VFDQ
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IDOVH 7KH 6)5 LQVWUXFWLRQ DOVR UHVHWV DOO UHWHQWLYH DFWLRQV WKDW DUH
FXUUHQWO\ DFWLYH
Entering Parameters
7R SURJUDP WKLV LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU ZLWK WKH
Example:
SFR
SFC Reset
Prog file number
Restart step at
2
N7:5
Parameter:
Definition:
Program File Number
a valid SFC program file number
Restart Step at
enter one of the following:

a valid step reference number, 0 to 32767 (entering a 0
defaults to restarting at the initial step)
a valid step name
an integer address (that stores a step reference number)
an address symbol (of an integer address that stores a step
reference number)
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SURFHVVRU ZLOO IDXOW
1785-6.1 November 1998
13-18
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End of Transition (EOT)

Description:
Example:
[ EOT ]
1785-6.1 November 1998
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DOO ODGGHU LQVWUXFWLRQV FDQ EH SUHVFDQQHG
13-19
User Interrupt Disable (UID)

Description:
UID
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,QSXW ,QWHUUXSWV 3,,
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1785-6.1 November 1998
13-20
User Interrupt Enable (UIE)

Description:
7KH 8,( LQVWUXFWLRQ UHHQDEOHV 67, RU 3,, LQWHUUXSW SURJUDPV

:KHQ WKH UXQJ LV WUXH DQG WKH LQWHUQDO LQWHUUXSWGLVDEOH FRXQWHU LV
JUHDWHU WKDQ ]HUR WKH LQWHUUXSWGLVDEOH FRXQWHU LV GHFUHPHQWHG
UIE
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WKHQ DEOH WR EH LQWHUUXSWHG DJDLQ ,I WKHUH DUH DQ\ LQWHUUXSW SURJUDPV
SHQGLQJ WKH\ DUH H[HFXWHG DW WKLV WLPH
Example:
I:012
I:012
I:012
O:013
Program can be interrupted
01
02
03
02
UID
I:012
I:012
O:013
01
04
02
I:012
I:012
O:013
04
02
03
Program cannot
be interrupted
I:012
03
UIE
1785-6.1 November 1998
Program can be interrupted
Chapter
14

Using PID
3,' FORVHGORRS FRQWURO KROGV D SURFHVV YDULDEOH DW D GHVLUHG VHW

SRLQW )LJXUH VKRZV D IORZUDWHIOXLG OHYHO H[DPSOH
Figure 14.1
PID Control Example
FFWD
or
Bias
Set Point
Flow
Rate
Error
R
PID Equation
Process
Variable
Control
Output
Level
Detector
14271
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EHWZHHQ VHWSRLQW DQG SURFHVV YDULDEOH LQSXW WKH JUHDWHU WKH RXWSXW
VLJQDO DQG YLFH YHUVD $Q DGGLWLRQDO YDOXH IHHGIRUZDUG RU ELDV
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FDOFXODWLRQV LV WR PDLQWDLQ WKH SURFHVV YDULDEOH \RX DUH FRQWUROOLQJ DW
WKH VHW SRLQW
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1785-6.1 November 1998
14-2
PID Features
7KH 3,' LQVWUXFWLRQ OHWV WKH SURFHVV PRQLWRU DQG FRQWURO SURFHVV
ORRSV IRU VXFK TXDQWLWLHV DV SUHVVXUH WHPSHUDWXUH IORZ UDWH DQG IOXLG
OHYHO )HDWXUHV RI WKH 3,' LQVWUXFWLRQ LQFOXGH
Using PID Equations
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LQSXW DQG RXWSXW UDQJH IURP ELW DQDORJ
LQSXW VFDOLQJ LQ HQJLQHHULQJ XQLWV
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GLUHFW RU UHYHUVH DFWLQJ FRQWURO
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'HULYDWLYH RI (UURU
1 t
d(E)
CV = K c ( E ) + ( E ) dt + T d + Bias
Ti 0
dt
'HULYDWLYH RI 39
1 t
d(PV)
CV = K c ( E ) + ( E ) dt + T d + Bias ( E = SP PV )
0
Ti
dt
1 t
d(PV)
CV = K c ( E ) + ( E ) dt + T d + Bias ( E = PV SP )
Ti 0
dt
1785-6.1 November 1998
14-3
,QGHSHQGHQW JDLQV HTXDWLRQ

'HULYDWLYH RI (UURU
t
d(E)
CV = K P ( E ) + K i ( E ) dt + K d + Bias
0
dt
'HULYDWLYH RI 39
t
d(PV)
CV = K P ( E ) + K i ( E ) dt K d + Bias ( E = SP PV )
0
dt
t
d(PV)
CV = K P ( E ) + K i ( E ) dt + K d + Bias ( E = PV SP )
0
dt
:KHUH
Kp
= Proportional Gain (Unitless)
SP
= Set Point
Ki
= Integral Gain (Seconds1)
PV
= Process Variable
Kd
= Derivative Gain (Seconds)
Error
= (SP PV) or (PV SP)
1

T1
Bias
= Feed-Forward or External Bias
= Reset Gain (Repeats/Minute)

CV
= Output Control Variable
Td
= Rate Gain (Repeats/Minute)
= Loop Update Time
Conversion of Gain Constants

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FRQWUROOHU JDLQ .F UHVHW 7L DQG UDWH 7G YDOXHV LQ WKH
IROORZLQJ IRUPXODV
Kp = Kc unitless
Kc
Ki = inverse seconds
60Ti
Kd = Kc(Td)60 seconds
Integral Term Implementation
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,Q WKH FDVH RI ,QGHSHQGHQW *DLQV 6N
.L(NW 6N
1
Ti
:LWK 'HSHQGHQW *DLQV VHOHFWHG S k = ( E k ) t + S k 1
1785-6.1 November 1998
14-4
,I WKH ,QWHJUDO RU 5HVHW *DLQ LV ]HUR WKH DFFXPXODWHG VXP FRQWLQXDOO\

VHWV WR ]HUR LQ $XWR PRGH
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DFFXPXODWLQJ ZKHQHYHU WKH RXWSXW &9 UHDFKHV LWV PD[LPXP RU
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k
d(E
= CVManual Bias K p ( E ) K d
dt
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PRGH FKDQJH
Derivative Term
7KH IROORZLQJ DSSUR[LPDWLRQ LV XVHG WR FDOFXODWH WKH GHULYDWLYH WHUP
d
( Q ) Q k Qk 1
=
dt
t
Where Q represents either Error or PV,

depending upon your settings.
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GHULYDWLYH WHUP VSLNHV FDXVHG E\ QRLVH LQ WKH 39
$GGLQJ WKLV ILOWHU WR WKH RYHUDOO GHULYDWLYH WHUP \LHOGV
Qk Qk 1
D k = ( 1 ) K d + D k 1
t
Where:
1785-6.1 November 1998
Kd
Dk
Dk1
Qk
= the derivative gain

= the current derivative term
= the previous derivative term
= (as previously defined)
=
= Loop Update Time
1
t
16 + 1
Kd
Setting Input/Output Ranges
14-5
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Engineering Units
Integer File Type
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Setting the Dead Band
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UHPDLQV ZLWKLQ WKLV UDQJH
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PDWFKHV WKH VHWSRLQW ZLWKRXW FKDQJLQJ WKH RXWSXW
high alarm
+DB
process
variable
error within
dead band range
SP
-DB
low alarm
time
Using Zero-Crossing
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SURFHVV YDULDEOH FURVVHV WKH VHWSRLQW HUURU FURVVHV ]HUR DQG FKDQJHV
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Using No Zero Crossing

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FDXVHV WKH &9 RXWSXW QRW WR FKDQJH YDOXH DV ORQJ DV WKH 39 LV LQVLGH
WKH GHDGEDQG UDQJH LQVWHDG RI RQO\ DIWHU UHDFKLQJ WKH VHWSRLQW YDOXH
:LWK WKH SURSHU WXQLQJ LW LV WKHQ SRVVLEOH WR KDYH WKH 39 GULIW WR WKH
VHWSRLQW YDOXH
Selecting the Derivative Term (Acts

on PV or Error)
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GHULYDWLYH DFWLRQ \RX ZDQW
Setting Output Alarms
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QRW ZDQW DODUPV HQWHU IRU WKH ORZHU DODUP DQG IRU WKH
XSSHU DODUP
Using Output Limiting
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:KHQ WKH LQVWUXFWLRQ GHWHFWV WKDW WKH RXWSXW KDV UHDFKHG D OLPLW LW VHWV
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Anti-Reset Windup
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Figure 14.2
Example Diagram for Moving Analog Inputs to a PID Instruction
Ladder Program
BTR
12-bit
Analog Input Module
Main Control Station

Output
Tracking
(Tieback Input)
PV
Input
1st channel
(word 1)
Block Transfer
BLOCK TRANSFER READ

Rack
Group
Module
Control Block
Data File
Length
Continuous
0
0
0
N7:0
N7:109
6
N
EN
DN
ER
2nd channel
(word 2)
Output
Module located in rack 0,
I/O group 0, module slot 0
PID
PID
Control block
Process Variable
Tieback
Control variable
N7:20
N7:109
N7:110
N7:120
15297
Set Output
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1785-6.1 November 1998
14-9
Table 14.A
Set Output Mode Procedure
Integer Control Block (N7:0)
PD Control Block (PD10:0)
Select Automatic Mode
Mode:0 (0:auto/1:manual)
(bit N7:0/1 = 0)
A/M Station Mode = Auto

(bit PD10:0.MO = 0)
Select Set Output Mode
SET OUTPUT MODE: 1 (0:no/1:yes)

(bit N7:0/4 = 1)
Software A/M Mode = Manual

(bit PD10:0.SWM = 1)
Note: In data monitor, MODE=AUTO changes to
MODE=SW MANUAL.
Enter % in Set Output

Value (0-100%)
SET OUTPUT VALUE %

(word N7:10 = %value)
SET OUTPUT %
(word PD10:0.SO = % value)
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Feedforward or Output Biasing
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PID Instruction
Description:
PID
PID
Control Block
Process variable
Tieback
Control variable
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Using No Back Calculation

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Operational Status Bits

Integer Block
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LWV TXDOLI\LQJ UXQJ FRQGLWLRQV PDGH D IDOVHWRWUXH WUDQVLWLRQ 7KH
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EHFRPH IDOVH
Rung
State
True
False
True
.EN
.DN
False
Actual Execution of
the PID Instruction
True
False
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PD Block
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EORFN GRHV QRW XVH D GRQH ELW
Rung
State
True
False
True
.EN
False
Actual Execution of
the PID Instruction
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Entering Parameters
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FRQWURO EORFN LV QRW DYDLODEOH ,Q WKH (QKDQFHG 3/& SURFHVVRUV
ERWK WKH 1 DQG 3' FRQWURO EORFNV DUH DYDLODEOH 7KH 3' FRQWURO EORFN
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Parameter:
Definition:
Control Block
a file that stores PID status and control bits, constants, variables,
and internally used parameters.
Based on the data type you use, a different configuration screen
appears for you to enter PID information (see the next sections for
more information).
If you have an Enhanced PLC-5 processor, you can use an integer
control block or a PD control block. Using a PD file, words 0, 1 are
the status words; words 2-80 store the PID values.
If you use an Integer control block, the PID calculations are
performed using integer values. If you use a PD control block, the
PID calculations are performed using floating point values.
If you have a Classic PLC-5 processor, you must use an integer file
(N) for your control block. Using an integer file, word 0 is the status
word; words 1-22 store the PID values.
Process Variable
a word address that stores the process input value.
Tieback
a word address used to implement bumpless transfer when using a

manual control station. The tieback is an output of a BTR instruction
from the station.
Control Variable
a word address to which the PID instruction sends its calculated PID
output value.
Note: If a value greater than 4095 is written to the control variable
location of the Integer Type PID instruction, the output of the PID
instruction obtains a permanent offset which can only be removed
by writing to the control variable with a value between 0 and
4095. This happens whether you write to this location via rung logic
or directly to the data table location.
Note: The file PD type PID instruction does not exhibit this behavior.
1785-6.1 November 1998
14-14
Using an Integer Data File Type for

the Control Block
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Table 14.B
PID Parameter Descriptions (Integer Control Block)
Parameter:
Description:
Equation
Enter whether you want to use independent (0) or dependent (1) gains. Displays one of
the following:
INDEPENDENT (0) for independent gains
DEPENDENT (1) for dependent gains (ISA)
Use dependent gains when you want to use standard loop tuning methods. Use
independent gains when you want the three gain constants (P, I, and D) to
operate independently.
Mode
Displays operating mode:

AUTO (0) automatic PID control
MANUAL (1) control from a manual control station
Sets the use of the tieback parameter for manual operation
Error
Displays one of the following error value:

Reverse acting: 0 = SP-PV
Direct acting: 1 = PV-SP
Output Limiting
Displays whether or not the instruction clamps the output at the high and low limiting
values. Displays one of the following:
NO (0) output not clamped
YES (1) output clamped
The PID algorithm has an anti-reset windup feature that prevents the integral term from
becoming too large when the output reaches the high or low alarm limits. If the limits
are reached, the algorithm stops calculating the integral term until the output comes
back into range.
Set output mode
Selects the use of set output value % for manual operation
Setpoint scaling
Selects if the setpoint is to be interpreted as a value in the engineering units or an

unscaled (0 to 4095) value
Derivative input
Selects if derivative term is based on changes in PV or on changes in error
Last state resume
Selects if you want to resume last state or hold last state

(Continued)
1785-6.1 November 1998
14-15
Parameter:
Description:
Deadband status
Set if the PV is inside the selected deadband range; reset if it is not
Upper CV limit alarm
Set if calculated CV is greater than the CV upper limit word %
Lower CV limit alarm
Set if calculated CV is less than the CV lower limit word %
Setpoint out of range
Displays whether or not the setpoint is out of the range of engineering units you
selected on the PID Configuration screen. Displays one of the following:
NO (0) SP within range
YES (1) SP out of range
Note: A major processor fault occurs if the SP is out of range when the instruction is
first enabled.
PID done
Displays whether the PID instruction has completed (1 = done; 0 = not done).
PID enabled
Displays whether the PID instruction is enabled (1 = enabled; 0 = not enabled).
Feed forward
Enter a value between 4095 and 4095 for the amount of feed forward.
The ladder program can enter a feedforward value to bump the output in anticipation of
a disturbance. This value is often used to control a process with transportation lag.
Max scaled input
Enter the integer number (32,768 - 32,767) that is the maximum value available from
the analog module. For example, use 4095 for a module whose range is 0-4095.
Min scaled input
Enter the number that is the minimum value available from the analog module. For
example, use 0 for a module whose range is 0 to 4095.
Dead band
For an unscaled deadband, enter a value in the engineering units you selected on
the PID Configuration screen. Valid range is 0 to 4095 unscaled, 32,768 to
+32,767 scaled.
Note: The deadband is zero crossing.
Set output value %
Enter a percent (0-100%) to use as the CV Output when set output mode is selected.
Upper CV limit %
Enter a percent (0-100) above which the algorithm clamps the output.
Lower CV limit %
Enter a percent (0-100) below which the algorithm clamps the output.
Scaled PV value
Displays data from the analog input module that the instruction scales to the same
engineering units that you selected for the setpoint.
Scaled error
Displays the current error in scaled engineering units
Current CV %
Displays current controlled variable output value as a percent
Setpoint
Enter an integer. Valid range is 0 to 4095 (unscaled) or Smin- Smax (scaled

engineering units).
Proportional gain
(Kc)
Enter an integer. Valid entry range is 0-32,767 (unitless) or Kp 0-32,767. The

processor divides the entry value by 100 for calculations.
Reset time (Ti)

minutes/repeat
Enter an integer. Valid entry range for Ti is 0-32,767 (minutes times 100). The
processor automatically divides the entry value by 100 for calculations.
Valid entry range for Ki is 0-32,767 (inverse seconds times 1000). The processor
automatically divides the entry by 1000 for calculations.
(Continued)
1785-6.1 November 1998
14-16
Parameter:
Description:
Derivative rate (Td)
Enter an integer. Valid entry range is 0-32,767 or KD 0-32,767. The processor divides
the entry value by 100 for calculations.
Loop update time
Enter an update time (greater than or equal to 0.01 seconds) at 1/5 to 1/10 times the
natural period of the load (load time constant). Valid entry range is 1-32,767 seconds.
The processor divides the entry value by 100 for calculations. The load time constant
should be greater than:
1ms(algorithm) + block transfer time (ms)
Periodically enable the PID instruction at a constant interval equal to the update time.
For update times of less than 100 msec, use an STI. When update times are greater
than 100 msec, use a timer or a real-time sampling.
Note: If you omit an update time or enter a negative update time, a major fault occurs
the first time the processor runs the PID instruction.
Using Control Block Values

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Table 14.C
PID Control Block (Integer Control Block)
Word:
Contains:
Bit 15
Enabled (EN)
Bit 13
Done (DN)
Bit 11
Set point out of range
Bit 10
Output alarm, lower limit
Bit 9
Output alarm, upper limit
Bit 8
DB, set when error is in deadband
Bit 7
Resume last state (0=yes; 1=hold last state)
Bit 6
Derivative action (0=PV, 1=error)
Bit 5
Setpoint descaling (0=no, 1=yes)
Bit 4
Set output (0=no, 1=yes)
Bit 3
Output limiting (0=no, 1=yes)
Bit 2
Control (0=reverse, 1=direct)
Bit 1
Mode (0=automatic, 1=manual)
Bit 0
Equation (0=independent, 1=ISA)
Note: During prescan, bits 8, 9, 10, in addition to the Integral
Accumulator and Derivative Error values, are cleared and the
error register value of previous scans is set to 32,767.
reserved
Setpoint
Term:
Entry Range:
SP
0-4095 (unscaled)
SminSmax (scaled)
Note: Terms marked with an asterisk (*) are entered as Yy 100. The term itself is Yy. The term marked with a double
asterisk (**) is entered as Yy 1000. The term itself is Yy.
(Continued)
1785-6.1 November 1998
14-17
Word:
Contains:
Independent:
Term:
Entry Range:
Proportional gain x 100 (unitless)
Kp *
0-32,767
ISA:
Controller gain x 100 (unitless)
Kc*
0-32,767
Independent:
Integral gain x 1000 (1/sec)
Ki**
0-32,767
ISA:
Reset term x 100 (minutes per repeat)
Ti*
0-32,767
Independent:
Derivative gain x 100 (seconds)
Kd*
0-32,767
ISA:
Rate term x100 (minutes)
Td*
0-32,767
Feedforward or bias
FF/Bias
4095-+4095
Maximum scaling
Smax
32,768-+32,767
Minimum scaling
Smin
32,768-+32,767
Dead band
DB
0-4095 (unscaled)
SminSmax (scaled)
10
Set output
SETOUT
0-100%
11
Maximum output limit (% of output)
Lmax
0-100%
12
Minimum output limit (% of output)
Lmin
0-100%
13
Loop update time x 100 (seconds)
dt
0-32,767
14
Scaled PV value (displayed)
SminSmax
15
Scaled error value (displayed)
SminSmax
16
Output (% of 4095)
17-22
internal storage; do not use
CV
0-100%
Note: Terms marked with an asterisk (*) are entered as Yy 100. The term itself is Yy. The term marked with a double
asterisk (**) is entered as Yy 1000. The term itself is Yy.
1785-6.1 November 1998
14-18
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Using a PD File Type for the

Control Block
Table 14.D
PID Parameter Descriptions (PD Control Block)
Parameter
Address
Mnemonic:
Description:
Setpoint
.SP
Enter a floating-point number in the same engineering units that are on the
PID Configuration screen. Valid range is 3.4 E+38 to +3.4 E+38.
Process Variable
.PV
Displays data from the analog input module that the instruction scales to
the same engineering units that you selected for the setpoint.
Error
.ERR
Displays one of the following error values:

Reverse acting: Error = PV-SP
Direct acting: Error = SP-PV
Output %
.OUT
Displays the PID algorithm control output value (0-100%).
Mode
.MO
.MO=0
.MO=1
.SWM=1
Displays operating mode:

AUTO automatic PID control
MANUAL control from a manual control station
SW MANUAL simulated manual control from the data monitor or
ladder program
PV Alarm
.PVHA=1
.PVLA=1
Deviation Alarm
.DVPA=1
.DVNA=1
Output Limiting
.OLH=1
.OLL=1
Displays whether the PV is within or exceeds the high or low alarm limits
you selected on the PID Configuration screen. Displays one of the following:
NONE PV within alarm limits
HIGH PV exceeds high alarm limit (used with deadband)
LOW PV exceeds low alarm limit (used with deadband)
Displays whether the error is within or exceeds the high or low deviation
alarms you selected on the PID Configuration screen. Displays one of the
following:
NONE error within deviation alarm limits
POSITIVE error exceeds high alarm (used with deadband)
NEGATIVE error exceeds low alarm (used with deadband)
Displays whether or not the instruction clamps the output at the high and
low limiting values (.MAXO and .MINO) you selected on the PID Configuration
screen. Displays one of the following:
NONE output not clamped
HIGH output clamped at the high end (.MAXO)
LOW output clamped at the low end (.MINO)
The PID algorithm has a anti-reset-windup feature that prevents the integral
term from becoming too large when the output reaches the high or low
alarm limits. If the limits are reached, the algorithm stops calculating the
integral term until the output comes back into range.
(Continued)
1785-6.1 November 1998
14-19
Parameter
Address
Mnemonic:
Description:
SP Out of Range
.SPOR=0
.SPOR=1
Displays whether or not the setpoint is out of the range of engineering units
you selected on the PID Configuration screen. Displays one of the following:
NO SP within range
YES SP out of range
Note: A major processor fault occurs if the SP is out of range when the
instruction is first enabled.
Error Within DB
.EWD=0
.EWD=1
Displays whether the error is within or exceeds the deadband value

you enter on this screen. The deadband is zero crossing. Displays one
of the following:
RESET Error exits the deadband zone
SET Error crosses the deadband centerline
PID Initialized
.INI=0
.INI=1
Each time you change a value in the control block, the PID instruction takes
over twice as long to execute (until initialized) on the first scan. Displays one
of the following:
NO PID instruction not initialized after you changed control block values
YES PID instruction remains initialized because you did not change any
control block values
Attention: Do not change the range of input or engineering units when
running. If you must do this, then you must reset this bit to re-initialize.
Otherwise, the instruction will malfunction with possible damage to
equipment and injury to personnel.
A/M Station Mode
.MO=0
.MO=1
Enter whether you want automatic (0) or manual (1) PID control. Displays
one of the following:
MANUAL (1) manual PID control
Manual control specified that an output from a manual control station
overrides the calculated output of the PID algorithm.
Note: Manual overrides Set Output Mode.
Software A/M Mode
.SWM=0
.SWM=1
Enter whether you want automatic PID (0) control or Set Output Mode (1), for
software-simulated control. Displays one of the following:
SW MANUAL (1) software-simulated PID control
You can simulate a manual control station with the data monitor when you
program a single loop. To do this, set .SWM to SW MANUAL and enter a
Set Output Percent value.
You can simulate a manual control station with ladder logic, pushwheels,
and pushbutton switches when you program several loops. To do this, set
.SWM to SW MANUAL and move a value into the set output element .SO.
(Continued)
1785-6.1 November 1998
14-20
Parameter
Address
Mnemonic:
Description:
Status Enable
.EN=0
.EN=1
Enter whether to use (1) or inhibit (0) this bit which displays the rung
condition so you can see whether the PID instruction is operating. Displays
one of the following:
0 instruction not executing
1 instruction executing
Proportional Gain
.KP
Enter a floating-point value. Valid range for independent or standard gains is

0 to 3.4 E+38 (unitless).
Integral Gain
.KI
Enter a floating-point value. Valid range for independent gains is 0 to 3.4

E+38 inverse seconds; valid range for standard gains is 0 to 3.4 E+38
minutes per repeat.
Derivative Gain
.KD
Enter a floating-point value. Valid range for independent gains is 0 to 3.4

E+38 seconds; valid range for standard gains is 0 to 3.4E+38 minutes.
Output Bias %
.BIAS
Enter a value (100 to +100) to represent the percentage of output you want
to feed forward or use as a bias to the output. The bias value can
compensate for steady-loss of energy from the system.
The ladder program can enter a feedforward value to bump the output in
anticipation of a disturbance. This value is often used to control a process
with transportation lag.
1785-6.1 November 1998
Tieback %
.TIE
Displays a number (0 to 100) representing the percent of raw tieback (0

4095) from the manual control station. The PID algorithm uses this number
to achieve bumpless transfer when switching from manual to auto mode.
Set Output %
.SO
Enter a percent (0 to 100), from this screen or a ladder program, to

represent the software-manually controlled output.
When you select software-simulated control (.SWM=1), the PID instruction
overrides the algorithm with the set output value (0 - 4095) for transfer to
the output module, and copies it to .OUT for display as a percent. The
transfer to software-simulated control is bumpless because .SO (under your
control) starts with the last automatic algorithm output. Do not vary .SO until
after the transfer.
To achieve bumpless transfer when changing from software-simulated
control to automatic control, the PID algorithm changes the integral term so
that the output is equal to the set output value.
14-21
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Table 14.E
PID Configuration Descriptions (PD Control Block)
Parameter:
Address
Mnemonic:
Description:
PID Equation
.PE=0
.PE=1
Enter whether you want to use independent (0) or dependent (1) gains. Displays one of
the following:
INDEPENDENT (0) for independent gains
DEPENDENT (1) for dependent gains
Use dependent gains when you want to use standard loop tuning methods. Use
independent gains when you want the three gain constants (P, I, and D) to
operate independently.
Derivative of
.DO=0
.DO=1
Enter whether you want the derivative of the PV (0) or the error (1). Displays one of
the following:
PV (0) for PV derivative
ERROR (1) for error derivative
Select the PV derivative for more stable control when you do not change the setpoint often.
Select the error derivative for fast responses to setpoint changes when the algorithm can
tolerate overshoots.
Control Action
.CA=0
.CA=1
Enter whether you want reverse (0) or direct acting (1). Displays one of the following:
REVERSE (0) for reverse acting (E = SP-PV)
DIRECT (1) for direct acting (E = PV-SP)
PV Tracking
.PVT=0
.PVT=1
Enter whether you do not (0) or do (1) want PV tracking. Displays one of the following:
NO (0) for no tracking
YES (1) for PV tracking
Select no tracking if the algorithm can tolerate a bump when switching from manual to
automatic control. Select PV tracking if you want the setpoint to track the PV in manual
control for bumpless transfer to automatic control.
Update Time
.UPD
Enter an update time (greater than or equal to .01 seconds) at 1/5 to 1/10 the natural
period of the load (load time constant). The load time constant should be greater than:
3ms(algorithm) + block transfer time (ms)
Periodically enable the PID instruction at a constant interval equal to the update time.
When the program scan time is close to the required update time, use an STI to ensure a
constant update interval. When the program scan is several times faster than the required
update time, use a timer.
Attention: If you omit an update time or enter a negative update time, a major fault occurs
the first time the processor runs the PID instruction.
(Continued)
1785-6.1 November 1998
14-22
Parameter:
Address
Mnemonic:
Description:
Cascade Loop
.CL=0
.CL=1
Enter whether this loop is not (0) or is (1) used in a cascade of loops. Displays one of the
following:
NO (0) not used in a cascade
YES (1) used in a cascade
Cascade Type
.CT=0
.CT=1
If this loop is part of a cascade of loops, enter whether this loop is the master (1) or a slave
(0). Displays one of the following:
SLAVE (0) for a slave loop
MASTER (1) for a master loop
Master to
this Slave
.ADDR
If this loop is a slave loop in a cascade, enter the control block address of the master.
Tieback is ignored in the master loop of a cascade. When you change cascaded loops to
manual control, the slave forces the master into manual control. When PV tracking is
enabled, the order of events is:
Slave.SP > Master.TIE > Master.OUT > Slave.SP
When you return to automatic control, change the slave first, then the master.
Engineering
Unit Max
.MAXS
Enter the floating-point value in engineering units that corresponds to the analog modules
full scale output. Valid range is 3.4 E+38 to +3.4 E+38.
Attention: Do not change this value during operation because a processor fault
might occur.
Engineering Unit
Min
.MINS
Enter the floating-point value in engineering units that corresponds to the analog modules
zero output. Valid range is 3.4 E+38 to +3.4 E+38 (post-scaled number).
Attention: Do not change the maximum scaled value during operation because a
processor fault might occur.
Input
Range Max
.MAXI
Enter the floating-point number (3.4 E+38 to +3.4 E+38) that is the unscaled maximum
value available from the analog module. For example, use 4095 for a module whose range
is 0-4095.
Input
Range Min
.MINI
Enter the floating-point number (3.4 E+38 to +3.4 E+38) that is the minimum unscaled
value available from the analog module. For example, use 0 for a module whose range is
0-4095.
Output Limit
High %
.MAXO
Enter a percent (0-100) above which the algorithm clamps the output.
Output Limit
Low %
.MINO
Enter a percent (0-100) below which the algorithm clamps the output.
PV Alarm High
.PVH
Enter a floating-point number (3.4 E+38 to +3.4 E+38) that represents the highest
PV value that the system can tolerate.
PV Alarm Low
.PVL
Enter a floating-point number (3.4 E+38 to +3.4 E+388) that represents the lowest
PV value that the system can tolerate.
PV Alarm
Deadband
.PVDB
Enter a floating-point number (0-3.4 E+38) that is sufficient to minimize nuisance alarms.
This is a one-sided deadband. The alarm bit (.PVH or .PVL) is not set until the PV crosses
the deadband and reaches the alarm limit (DB zero point). The alarm bit remains set until
the PV passes back through and exits from the deadband.
(Continued)
1785-6.1 November 1998
14-23
Parameter:
Address
Mnemonic:
Description:
Deviation Alarm
(+)
.DVP
Enter a floating-point number (0-3.4 E+38) that specifies the greatest error deviation above
the setpoint that the system can tolerate.
Deviation Alarm
()
.DVN
Enter a floating-point number (3.4 E+38-0) that specifies the greatest error deviation
below the setpoint that the system can tolerate.
Deviation Alarm
Deadband
.DVDB
Enter a floating-point number (0-3.4 E+38) that is sufficient to minimize nuisance alarms.
This is a one-sided deadband. The alarm bit (.DVP or .DVN) is not set until the error crosses
the deadband and reaches the alarm limit (DB zero point). The alarm bit remains set until
the error passes back through and exits from the deadband.
No Zero Crossing
.NOZC=0
.NOZC=1
Enter whether to use (1) or inhibit (0) the no zero crossing feature:
0 no zero crossing disabled
1 no zero crossing enabled
No Back
Calculation
.NOBC=0
.NOBC=1
Enter whether to use (1) or inhibit (0) the no back calculation feature:
0 no back calculation disabled
1 no back calculation enabled
No Derivative
Filter
.NDF=0
.NDF=1
Enter whether to use (1) or inhibit (0) the filter in the derivative calculation.
0 no filter used in derivative calculation
1 filter used in derivative calculation
Using Control Block Values

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Table 14.F
PID Control Block
Word:
Contains:
Control/Status Bits
Bit 15
Enabled (EN)
Bit 11
No back calculation (0=disabled, 1=enabled)
Bit 10
No zero crossing (0=disabled, 1=enabled)
Bit 9
Cascade selection (master, slave)
Bit 8
Cascade loop (0=no, 1=yes)
Bit 7
Process variable tracking (0=no, 1=yes)
Bit 6
Derivative action (0=PV, 1=error)
Bit 5
No derivative filter (0=disabled, 1=enabled)
Bit 4
Set output (0=no, 1=yes)
Bit 2
Control action (0=SP-PV, 1=PV-SP)
Bit 1
Mode (0=automatic, 1=manual)
Bit 0
Equation (0=independent, 1=ISA)
Range:
(Continued)
1785-6.1 November 1998
14-24
Word:
Contains:
Status Bits
Bit 12
PID initialized (0=no, 1=yes)
Bit 11
Set point out of range
Bit 10
Output alarm, lower limit
Bit 9
Output alarm, upper limit
Bit 8
DB, set when error is in DB
Bit 3
Error is alarmed low
Bit 2
Error is alarmed high
Bit 1
Process variable (PV) is alarmed low
Bit 0
Process variable (PV) is alarmed high
Note: During prescan, bit 12 is cleared.
2, 3
Setpoint
4, 5
Independent:
Proportional gain (unitless)
0 to +3.4 E+38
ISA:
Controller gain (unitless)
0 to +3.4 E+38
Independent:
Integral gain (1/sec)
0 to +3.4 E+38
ISA:
Reset term (minutes per

repeat)
0 to +3.4 E+38
Independent:
Derivative gain (seconds)
0 to +3.4 E+38
ISA:
Rate term (minutes)
0 to +3.4 E+38
6, 7
8, 9
Range:
3.4 E+38 to +3.4 E+38
10, 11
Feedforward or bias
100 to +100%
12, 13
Maximum scaling
3.4E+38 to +3.4 E+38
14, 15
Minimum scaling
3.4 E+38 to +3.4 E+38
16, 17
Dead band
0 to +3.4 E+38
18, 19
Set output
0-100%
20, 21
Maximum output limit (% of output)
0-100%
22, 23
Minimum output limit (% of output)
0-100%
24, 25
Loop update time (seconds)
26, 27
Scaled PV value (displayed)
28, 29
Scaled error value (displayed)
30, 31
Output (% of 4095)
0-100%
32, 33
Process variable high alarm value
3.4 E+38 to +3.4 E+38
34, 35
Process variable low alarm value
3.4 E+38 to +3.4 E+38
36, 37
Error high alarm value
0 to +3.4 E+38
38, 39
Error low alarm value
3.4 E+38 to 0
40, 41
Process variable alarm deadband
0 to +3.4 E+38
42, 43
Error alarm deadband
0 to +3.4 E+38
(Continued)
1785-6.1 November 1998
Programming Considerations
14-25
Word:
Contains:
Range:
44, 45
Maximum input value
3.4 E+38 to +3.4 E+38
46, 47
Minimum input value
3.4 E+38 to +3.4 E+38
48, 49
Tieback value for manual control (0-4095)
0-100%
51
Master PID file number
0-999; 0-9999 for

Enhanced PLC-5
processors only
52
Master PID element number
0-999; 0-9999 for

Enhanced PLC-5
processors only
54-80
internal storage; do not use
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1785-6.1 November 1998
Descaling Inputs
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4095
M 2 = ( M 1 S min1 )
( S max1 S min1 )
Variable
Description
M2
calculated output
M1
measured value from the module in scaled units
Smax1
scaled maximum value from the module
Smin1
scaled minimum value from the module
Smax1 Smin1
scaled range from the module
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4095
M 2 = [ 170 ( 200 ) ]
[ 1200 ( 200 ) ]
M 2 = 1082
unscaled
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Figure 14.3
Descaling PID Values Example
FAL
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1785-6.1 November 1998
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14-29
Table 14.G
Variables for the Descaling PID Values Example
Variable
Description
Smax
maximum scaling value
Smin
minimum scaling value
4095
K =
S max S min
constant for each channel
#N17:0
contains M1 values for each channel
#N18:0
contains Smin constants for each channel
#N19:0
contains the result of M1-Smin for each channel
#N20:0
location where you store K for each channel
#N21:0
contains the resulting unscaled value for each channel
PID Examples
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Integer Block (N) Examples
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Figure 14.4
Example PID Programming Conditioned by a Timer in the Main Program
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Figure 14.5
Example PID Programming in an STI File
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Example PID Programming in an RTS File
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Figure 14.7
Example PID Programming Conditioned by a Timer in the Main Program
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Figure 14.8
Example PID Programming in an STI File
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Figure 14.9
Example PID Programming in an RTS File
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Ladder Logic Simulation of a Manual Control Station

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SURJUDP LQ )LJXUH )LJXUH )LJXUH RU )LJXUH
Figure 14.10
Example Program for Simulating a Manual Control Station
I:001
N7:20
L
00
I:001
N7:20
U
01
MOV
N7:20
I:001
002
MOVE
Source
Destination
I:011
N7:30
MOV
N7:20
MOVE
Source
Destination
N7:36
N7:30
7KH ODVW UXQJ LQ WKH DERYH H[DPSOH LV IRU RXWSXW WUDFNLQJ IRU
EXPSOHVV WUDQVIHU IURP DXWRPDWLF WR PDQXDO PRGH
Address:
Description:
I:001/00
Manual pushbutton switch
I:001/01
Automatic pushbutton switch
I:001/02
Enter pushbutton switch
I:011
Manual output value
N7:20/4
PID set output bit
N7:30
PID set output value
N7:36
Current control output
1785-6.1 November 1998
14-38
Cascading Loops
<RX FDQ FDVFDGH WZR ORRSV E\ DVVLJQLQJ WKH FRQWURO RXWSXW RI WKH
RXWHU ORRS WR WKH VHWSRLQW RI WKH LQQHU ORRS 7KH VHWSRLQW RI WKH LQQHU
ORRS LV WKH WKLUG ZRUG ZRUG RI WKH LQWHJHU FRQWURO EORFN ,I WKH
FRQWURO EORFN RI WKH LQQHU ORRS LV 1 DGGUHVV WKH RXWHU ORRS
FRQWURO RXWSXW DW 1 5HSODFH WKH 3,' UXQJV LQ )LJXUH RU
)LJXUH ZLWK WKRVH LQ )LJXUH
<RX PXVW QRW VFDOH WKH VHWSRLQW RI WKH LQQHU ORRS 6HW WKH VFDOLQJ ELW
ZRUG ELW WR WR LQKLELW VHWSRLQW VFDOLQJ
Figure 14.11
Cascaded Loops
PID
PID
Control Block
Process variable
Tieback
Control variable
N7:20
N7:105
N7:106
N7:52
PID
PID
Control Block
Process variable
Tieback
Control variable
N7:50
N7:107
N7:108
N7:121
Ratio Control
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7KUHH SDUDPHWHUV DUH LQYROYHG
WKH ZLOG RU XQFRQWUROOHG YDOXH
WKH FRQWUROOHG YDOXH
WKH UDWLR EHWZHHQ WKHVH WZR YDOXHV
(QWHU WKH DGGUHVV RI WKH FRQWUROOHG YDOXH DV WKH 'HVWLQDWLRQ (QWHU WKH
DGGUHVV RI WKH ZLOG RU XQFRQWUROOHG YDOXH DV 6RXUFH $ (QWHU HLWKHU
WKH DGGUHVV RI WKH UDWLR YDOXH RU D SURJUDP FRQVWDQW IRU WKH UDWLR DV
6RXUFH % )RU H[DPSOH DGG WKH UXQJV LQ )LJXUH WR WKH 3,'
SURJUDP LQ )LJXUH RU )LJXUH
1785-6.1 November 1998
14-39
Figure 14.12
Ratio Control with a PID Instruction
PID
PID
Control block
Process Variable
Tieback
Control variable
MUL
MUL
Source A
Source B
Destination
PID
PID
Control block
Process Variable
Tieback
Control variable
N7:20
N7:105
N7:106
N7:120
N7:105
0.350000
N7:52
N7:50
N7:107
N7:108
N7:121
Process Variable Tracking

:KHQ LQ PDQXDO FRQWURO \RXU SURJUDP FDQ IRUFH WKH VHWSRLQW WR EH
HTXDO WR WKH SURFHVV YDULDEOH 39 E\ PRYLQJ WKH 39 LQWR WKH VHWSRLQW
ZRUG ZRUG RI WKH LQWHJHU FRQWURO EORFN WR DFKLHYH D VPRRWK
PDQXDOWRDXWRPDWLF WUDQVIHU ,I WKH VHWSRLQW LV VFDOHG PRYH WKH
VFDOHG 39 IURP WKH 3,' FRQWURO EORFN GLUHFWO\ LQWR WKH VHWSRLQW
ZRUG ,I WKH VHWSRLQW LV QRW VFDOHG PRYH WKH XQVFDOHG YDOXH IURP
WKH 39 DGGUHVV LQ WKH 3,' LQVWUXFWLRQ WR WKH VHWSRLQW )RU DQ H[DPSOH
DGG WKH UXQJV LQ )LJXUH WR WKH 3,' SURJUDP LQ )LJXUH RU
)LJXUH
Figure 14.13
PID
PID
Control Block
Process variable
Tieback
Control variable
MOV
MOVE
Source
Destination
N7:20
N7:105
N7:106
N7:120
N7:34
N7:22
1785-6.1 November 1998
14-40
)LJXUH DQG )LJXUH VKRZ WKH 3/& 3,' ,QWHJHU DQG 3'
%ORFN SURFHVV IORZ )LJXUH DQG )LJXUH VKRZ WKH 3'
%ORFN PDVWHUVODYH UHODWLRQVKLS
PID Theory
Figure 14.14
PLC-5 PID (Integer Block)
Error
Displayed
as EUs
Convert
Binary % to EU
Smax - Smin
4095
Error x
SetPoint
Scaling
No
12 Bit
Truncation
Error
FeedForward
Set
Output
Mode
Off
Mode
Output
Limiting
Auto
No
SP-PV
SP
+
Yes
Convert Eng. Units
To Binary
(Error)
-
PID
Calculation
-1
(Out)
PV-SP
SP-Smin
x 4095
Smax-Smin
On
Set
Output %
Yes
Manual
CV
Output
Limiting
Tieback
Convert
Binary to EU
SP
Displayed as
user entry
12 Bit
Truncation
Yes
No
PV
Convert
Binary to % Binary
Smax - Smin
+ Smin
PV x
4095
CV x
SetPoint
Scaling
100
4095
Output (CV)
displayed as
% Binary
PV
Displayed
as EUs
Smin - Minimum Scaled Input
Smax - Maximum Scaled Input
Figure 14.15
PLC-5 PID (PD Block)
Error
Displayed
as EUs
SP
Displayed
as EUs
Software A/M
-orA/M Station Mode
Auto
SP-PV
+
SP
(Error)
-
Man
Output
Bias %
Control
Action
-1
PV-SP
Convert Eng.
Units To %
Error x 100
maxs-mins
Software
A/M Mode
PID
Calculation
(Out%)
Auto
Auto
PVT
Output
Limiting
Manual
Set
Output %
No
PV
Displayed
as EUs
Yes
Manual
Tieback %
Convert Binary
To Eng. Units
(PV-mini)(maxs-mins)
+ mins
maxi-mini
PV
1785-6.1 November 1998
Set
Output %
A/M
Station
Mode
PVT
mini
maxi
mins
maxs

Input Range Minimum
Input Range Maximum
Engineering Unit Minimum
Engineering Unit Maximum
Output (CV)
Displayed as
% of EU Scale
Convert %
To Binary
Out% x 40.95
CV
14-41
Figure 14.16
PLC-5 PID (PD Block) as Master/Slave Loops
Master
Loop
Software A/M
-orA/M Station Mode
Auto
SP-PV
(Error)
+
SP
Output
Bias %
Control
Action
Convert Eng.
Units To %
Error x 100
maxs-mins
-1
Man
PV-SP
PVT
No
Software
A/M Mode
PID
Calculation
(Out%)
Auto
Set
Output %
Convert Binary
To Eng. Units
maxi-mini
SP
+ mins
PV
No
Yes
(Master.Out)
Output
Limiting
Manual
Manual
Software
A/M Mode
PVT
Yes
Set
Output %
A/M
Station
Mode
Auto
Convert Eng.
Units To %
x 100
maxs-mins
Auto
Items referenced in this box
are parameters, units, and
modes as they pertain to the
designated Slave loop.
Manual
Manual
Auto
A/M
Station Mode
PV
(Master.Out)
Output
Bias %
Control
Action
Slave
Loop
Convert %
(SP)
To Eng. Units
+
x (maxs-mins)
+ mins
100
SP-PV
-1
PV-SP
Convert Eng.
Units To %
Error x 100
maxs-mins
Software
A/M Mode
PID
Calculation
Auto
Auto
Output
Limiting
Manual
Set
Output %
Convert Binary
To Eng. Units
maxi-mini
+ mins
Set
Output %
A/M
Station
Mode
Convert %
To Binary
Out% x 40.95
CV
Manual
Tieback %
PV
1785-6.1 November 1998
14-42
Figure 14.17
PD Block Master/Slave Interlocking State Transitions
Slave Loop Transitions
Auto
Auto
Auto
Auto
S-M
an
S-Man
S-Auto
Auto
Man
Man
Man
SWM
SWM
S-Auto
SWM
Man
(on
SWM
S-Auto
M-
f)
(of
)
(on
Auto
S-
M-
SW
M-
SW
SWM
Man
( SWM
)
(of
f)
SW
)
(on
MM
(of
n
Ma
f)
SW
SWM
Man
( SWM
)
is in Manual with SWM also on".
Designates Master Loop Mode

Stable State (Composite Mode)
M
S
Man
Auto
SWM
1785-6.1 November 1998
Slave Loop Mode

Mode transition
Designated Master
Slave
Manual
Automatic
Software Manual
S-Auto
S-Man
Man
Note: ( SWM ) indicates that this loop
Man
( SWM
)
SWM
n
Ma
S-
Man
SWM
Man
( SWM
)
S-SWM (off)
Man
SWM
S-SWM (off)
(on
Man
S-SWM (on)
M-
SW
Man
( SWM
)
Man
( SWM
)
S-
S-Man
Man
S-Auto
Auto
to
Man
( SWM
)
M-Au
Man
SWM
M-Ma
Man
SWM
Auto
(on
S-SWM (on)
Man
S-SWM (off)
M
M
SW
Ma
n
SW
Au
to
MM-
M-
SW
Man
( SWM
)
Man
S-
Auto
(on
SWM
WM
S-S
Auto
Man
S-SWM (on)
Ma
n
to
Au
M-
Man
)
(on
M-
M-
Au
to
SW
M-
Master Loop Transitions
Chapter
15
Block-Transfer Instructions BTR and BTW

ControlNet I/O Transfer Instruction CIO
Using Block Transfer and
ControlNet I/O
Transfer Instructions
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WUDQVIHU PRGXOH &RQWURO1HW ,2 WUDQVIHU LQVWUXFWLRQV OHW \RX SHUIRUP
XQVFKHGXOHG WUDQVIHUV WR ,2 PRGXOHV RQ D &RQWURO1HW QHWZRUN
7DEOH $ OLVWV WKH DYDLODEOH EORFN WUDQVIHU DQG &RQWURO1HW ,2
WUDQVIHU LQVWUXFWLRQV
Table 15.A
Available Block Transfer and ControlNet I/O Transfer Instructions
If You Want to:
Use this
Instruction:
Found on Page:
Transfer words to a block transfer module
BTW
15-3
Transfer words from a block transfer

module
BTR
15-3
Perform unscheduled transfers to I/O

modules on a ControlNet network
CIO
15-22

$SSHQGL[ &
Using Block Transfer Instructions
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WLPH WR RU IURP D EORFN WUDQVIHU PRGXOH LQ D ORFDO RU UHPRWH ,2
FKDVVLV <RX FDQ DOVR WUDQVIHU XS WR ZRUGV DW D WLPH EHWZHHQ D
VXSHUYLVRU\ SURFHVVRU VFDQQHU PRGH DQG D SURFHVVRU FRQILJXUHG IRU
DGDSWHU PRGH
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LOOXVWUDWHV KRZ WKH WUDQVIHU RFFXUV
1785-6.1 November 1998
15-2
Block-Transfer Instructions BTR and BTW ControlNet I/O Transfer Instruction CIO
Table 15.B
Block Transfer Instructions for Local or Remote Racks in Scanner Mode
If You Want to Transfer Data:
Use:
To the BT I/O module
BTW (block-transfer write)
From the BT I/O module
BTR (block-transfer read)
Figure 15.1
Block Transfer Operation in Scanner Mode
One of Several Remote I/O Chassis
w/ 1771-ASB Adapter (processor)
PLC-5 (supervisor)
BTD
File
B
T
1
7
7
1
A
S
B
BTW
BTR
M
o
d
u
l
e
7DEOH & GHVFULEHV KRZ WR EORFN WUDQVIHU GDWD ZKHQ WKH SURFHVVRU
LV FRQILJXUHG IRU DGDSWHU PRGH )LJXUH LOOXVWUDWHV KRZ WKH
WUDQVIHU RFFXUV
Table 15.C
Block Transfer Instructions for Adapter Mode
If You Want to Transfer Data:
Use:
From the supervisory processor
BTR (block-transfer read)
To the supervisory processor
BTW (block-transfer write)
Figure 15.2
Block Transfer Operation in Adapter Mode
Adapter
PLC-5
Supervisor
Processor
Scanner
BTW
BTR
BTR
BTW
BTD
File
Both processors simultaneously execute the opposite block transfer instruction.
1785-6.1 November 1998
15-3
Block-Transfer Read (BTR) and

Block-Transfer Write (BTW)
Description:
BTR
BLOCK TRNSFR READ
Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
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DN
ER
Block-Transfer Request Queue

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For this Processor:
The Queue Holds Up to:
Classic PLC-5
17 block transfer requests per logical rack
PLC-5/11, 5/20, -5/30
64 block transfer requests to remote racks

(maximum 64 per channel pair 1A/1B); no limit for
requests to local racks
PLC-5/40, -5/60, -5/80
128 block transfer requests to remote racks

(maximum 64 per channel pair 1A/1B, 2A/2B); no
limit for requests to local racks
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1785-6.1 November 1998
15-4
Table 15.D
Queue-Full Bits for Block Transfer Requests (Word 7)
Classic PLC-5 Processors
Bit
Description
S:7/8
Block-transfer queue for rack 0 is full
S:7/9
S:7/10
S:7/11
S:7/12
S:7/13
S:7/14
S:7/15
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\RX XVH
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SURFHVVRU XVHV WKHVH YDOXHV WR H[HFXWH WKH WUDQVIHU
7KH (QKDQFHG 3/& SURFHVVRUV DOVR KDYH D EORFN WUDQVIHU ILOH W\SH
%7 <RX FDQ VWLOO XVH H[LVWLQJ SURJUDPV ZLWK LQWHJHU ILOH W\SHV EXW
WKH QHZ %7 ILOH W\SH PDNHV DGGUHVVLQJ HDVLHU )RU H[DPSOH LI \RX
QHHG WZR FRQWURO ILOHV \RX FDQ XVH %7 DQG %7 XVLQJ LQWHJHU
ILOHV \RX ZRXOG KDYH WR XVH IRU H[DPSOH 1 DQG 1
Entering Parameters
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SURFHVVRU ZLWK WKH IROORZLQJ LQIRUPDWLRQ WKDW LW VWRUHV LQ LWV
FRQWURO EORFN
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ZKLFK \RX SODFHG WKH WDUJHW ,2 PRGXOH 7DEOH ( OLVWV WKH YDOLG
UDQJHV IRU UDFN QXPEHUV
Table 15.E
Valid Ranges for Rack Number in Block Transfer Instructions
1785-6.1 November 1998
Processor
Maximum Racks Valid Range for Rack Numbers (octal)
PLC-5/10, -5/11, -5/12,

-5/15, -5/20, -5/VME
00-03
PLC-5/25, -5/30
00-07
PLC-5/40, -5/40L
16
00-17
PLC-5/60, -5/60L, -5/80
24
00-27
15-5
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15 14 13 12
word 0 EN
ST DN ER
11 10 09 08 07 06 05 04 03 02 01 00
CO EW NR TO RW
rack
word 1
requested word count
word 2
transmitted word count
word 3
file-type number
word 4
element number
group
slot
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If You Set the
Length to:
The Processor:
Reserves 64 words for block transfer data. The block transfer

module transfers the maximum words it can handle.
1 to 64
Transfers the number of words specified.
1785-6.1 November 1998
15-6
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Using Status Bits
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If You Specify:
The Instruction Uses This Mode:
Yes
Continuous once the rung goes true, the instruction continues

to transfer data until the continuous (.CO) bit is reset and the
rung is false or you edit the instruction and specify NO for
continuous mode.
No
Non-continuous the instruction is enabled each time the

rung goes true and performs only one data transfer per
rung transition.
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1785-6.1 November 1998
This Bit:
Is Set:
Enable .EN (bit 15)
when the rung goes true. This bit shows that the instruction
is enabled (that the block transfer is in progress).
In non-continuous mode, the .EN bit remains set until the
block transfer finishes or fails and the rung goes false.
In continuous mode, once the .EN bit is set, it remains set
regardless of the rung condition.
Start .ST (bit 14)
when the processor begins transferring data. The .ST bit is

reset at the false-to-true transition after the .DN bit or .ER
bit is set.
Done .DN (bit 13)
at completion of the block transfer, if the data is valid. The

.DN bit is set asynchronous to the program scan so the .DN
bit may go true any time after the block transfer is initiated.
The .DN bit is reset the next time the associated rung goes
from false to true.
15-7
This Bit:
Is Set:
Error .ER (bit 12)
when the processor detects that the block transfer failed.

The .ER bit is reset the next time the associated rung goes
from false to true.
Continue .CO (bit 11)
when you edit the instruction for repeated operation of the

block transfer after the first scan, independent of whether
the processor continues to scan the rung.
Reset the .CO bit if you want the rung condition to initiate
block transfers (return to non-continuous mode). If you are
using continuous block transfers in a sequential function
chart, see Appendix B, SFC Reference, in this manual.
Enable-waiting .EW
(bit 10)
when the block transfer request enters the queue. If the

queue is full, this bit remains reset until there is room in the
queue.
The .EW bit is reset when the associated rung goes from
false to true.
In continuous mode, once the .EW bit it set, it remains set.
Use the .EW bit to verify that a BTW or BTR instruction is
queued before leaving an SFC step.
No Response .NR (bit 09)
if the block transfer module does not respond to the first

local block transfer request. The .NR bit is reset when the
associated rung goes from false to true (not used with
remote block transfer).
Time Out .TO (bit 08)
if you reset the time out bit through ladder logic or data
monitor, the processor repeatedly tries to send a block
transfer request to an unresponsive module for four
seconds before setting the .ER bit.
If you set the .TO bit through ladder logic or data monitor,
the processor disables the four-second timer and requests
a block transfer one more time before setting the .ER bit.
Read-Write .RW (bit 07)
controlled by the instruction. A 0 indicates a write

operation; a 1 indicates a read operation.
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15-8
Using the Control Block
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Table 15.F
Values in the Block Transfer Control Block
Word Integer
Control Bock
BT Control Block
Description
.EN through .RW
Status bits
.RLEN
Requested word count
.DLEN
Transmitted word count / error code

.FILE
File type / number
.ELEM
Element number
Requested Word Count (.RLEN)

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Transmitted Word Count (.DLEN)

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FRQWURO EORFN WKDW WKH SURFHVVRU FDQ VHW GXULQJ WKH WUDQVIHU ,I D EORFN
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LWV QHJDWLYH QXPEHU 2QO\ RQH HUURU FRGH LV VWRUHG DW D WLPH D QHZ
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1785-6.1 November 1998
15-9
Table 15.G
Enhanced PLC-5 Processor Block Transfer Error Codes
Error
Number:
Description:
not used
not used
The size of the block transfer plus the size of the index in the block transfer
data table was greater than the size of the block transfer data table file.
There was an invalid transfer of block transfer write data between the
adapter and the block transfer module.
The checksum of the block transfer read data was wrong.
The block transfer module requested a different length than the associated
block transfer instruction. This could happen if a 64-word block transfer
instruction was executed and the block transfer modules default length
was not 64 words.
Block transfer data was lost due to a bad communication channel. Possible
reasons are noise, bad connections, and loose wires. Check resistors.
Error in block transfer protocol unsolicited block transfer.
The block transfer timeout, set in the instruction, timed out before
completion.
10
No communication channels are configured for remote I/O or rack number

does not appear in rack list.
11
No communication channels are configured for the requested rack or slot.
12
The adapter is faulted or not present for the BT command.
13
Queues for remote block transfers are full.
File Number (.FILE)

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QXPEHU RI 1 LV
Element Number (.ELEM)

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1785-6.1 November 1998
15-10
Selecting Continuous Operation
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1785-6.1 November 1998
15-11
Figure 15.3
Timing Diagram for Status Bits in Continuous BTR and BTW Instructions
stage 3
EN
EW
ST
stage 2
stage 1
CO
DN
ER
Rung true
Request
enters the
queue
Instruction
begins
execution
Instruction
finishes
Rung false
Rung true
Stage 1 - If .CO set, return to stage 2; if .CO reset, go to stage 3

Stage 2 - Return here for continuous operation
Stage 3 - Go here if .CO is reset
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1785-6.1 November 1998
15-12
Selecting Non-Continuous
Operation
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Figure 15.4
Timing Diagram for Status Bits in Non-Continuous BTR and BTW Instructions
EN
EW
ST
CO
DN
ER
Rung true
1785-6.1 November 1998
Request
enters the
queue
Instruction
begins
execution
Instruction
finishes
Rung false
Rung true
Block Transfer Timing Classic

PLC-5 Processors
15-13
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Instruction Run Time

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Write:
Read:
310 + 11.2Q + 5.4W
250 + 11.2Q
Where:
Represents:
number of queued block transfer requests to the same I/O chassis

with the continuous bit set
number of words to transfer
Waiting Time in the Queue

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Transfer Time
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Write:
local
Read:
local
0.9 + 0.1W
remote (57.6K baud)
13 + 30C + 0.3W
0.9 + 0.1W
remote (57.6K baud)
Where:
Represents:
number of full remote logical racks
9 + 21.3C + 0.3W
1785-6.1 November 1998
15-14
Block Transfer Timing Enhanced

PLC-5 Processors
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Instruction Run Time

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Waiting Time in the Holding Area

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Transfer Time
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local
1785-6.1 November 1998
600 sec + x(w)
remote (57.6K baud)
4 + 8C + 0.3W
remote (115K baud)
4 + 4.6C + 0.15W
remote (230K baud)
4 + 3.2C + 0.075W
Where this:
Represents:
8 or less block transfers queued in local rack = 86 sec

more than 8 block transfers queued in local rack = 300 sec
Note: This timing assumes that no other block transfers are queued to
the same slot and that successive block transfers to the same slot are
executed every 1000 sec.
number of full remote logical racks
Programming Examples
15-15
3URJUDP \RXU SURFHVVRU IRU EORFN WUDQVIHU XVLQJ RQH RI WKH IROORZLQJ
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Table 15.H
Block Transfer Programming Methods
If You Want to:
Use this Method:
Program block transfers to and from the same

module when you want the order of execution to
follow the same order scanned in the program
Bidirectional alternating
Continuously repeat bidirectional alternating block

transfers and the step will be scanned
Bidirectional alternating repeating
Program block transfers to and from the same

module when you want the transfers to continue
regardless of which SFC steps are active
Bidirectional continuous*
Program a BTR from, or a BTW to a module when

you want the block transfer to execute based on
an event
Directional non-continuous
Continuously repeat a block transfer and the step

will be scanned
Directional repeating
Program a BTR from or BTW to a module when you

want the transfer to continue regardless of which
SFC steps are active
Directional continuous*
Ensure block integrity
Buffering block transfer data
* Only use continuous mode when you want a block transfer to continue executing even when
the logic which controls it is not being scanned.
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SURFHVVRU VXEVWLWXWH DQ DSSURSULDWH LQWHJHU ILOH
1785-6.1 November 1998
15-16
Example Bidirectional Alternating Block-Transfer

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8VLQJ UXQJV OLNH WKLV H[DPSOH PDNHV VXUH WKH EORFN WUDQVIHU UHTXHVWV
DUH H[HFXWHG LQ WKH RUGHU LQ ZKLFK WKH\ ZHUH VHQW WR WKH TXHXH 7KH
SURFHVVRU DOWHUQDWHV EHWZHHQ WKH %75V DQG %7:V LQ WKH RUGHU LQ
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FRQGLWLRQ SUHYHQWV WKH EORFN WUDQVIHU UHDG DQG EORFN WUDQVIHU ZULWH
IURP TXHXHLQJ VLPXOWDQHRXVO\ 7KH EORFN WUDQVIHU FRQWLQXHV DV ORQJ
DV WKH RSWLRQDO FRQGLWLRQ LV WUXH
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FRQGLWLRQV DV \RX ZLVK WR WKH OHIW RI WKH UHTXLUHG HQDEOH ELW
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Figure 15.5
Example Bidirectional Alternating Block Transfer
BTR
Precondition
BT10:0
EN
BTR
enable bit
BTW
enable bit
Precondition
BT10:1
EN
BT10:1
EN
BTW
enable bit
BTR
enable bit
BT10:0
EN
Block-transfer rungs must be scanned for the transfers to occur.

The preconditions allow time-driven or event-driven transfers.
1785-6.1 November 1998
BLOCK TRANSFER READ

Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
3
2
0
BT10:0
N11:0
10
N0
DN
ER
BTW
Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
3
2
0
BT10:1
N11:10
11
NO
DN
ER
15-17
Example Bidirectional Alternating Repeating Block-Transfer

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H[DPSOH 8VLQJ UXQJV OLNH WKLV H[DPSOH PDNHV VXUH WKH EORFN WUDQVIHU
UHTXHVWV DUH H[HFXWHG LQ WKH RUGHU LQ ZKLFK WKH\ ZHUH VHQW WR WKH
TXHXH 7KH SURFHVVRU DOWHUQDWHV EHWZHHQ WKH %75V DQG %7:V LQ WKH
RUGHU LQ ZKLFK WKH\ DUH VFDQQHG E\ YLUWXH RI WKH ;,2 FRQGLWLRQV 7KH
;,2 FRQGLWLRQV SUHYHQWV WKH EORFN WUDQVIHU UHDG DQG EORFN WUDQVIHU
ZULWH IURP TXHXHLQJ VLPXOWDQHRXVO\ 7KH EORFN WUDQVIHUV FRQWLQXH DV
ORQJ DV WKH VWHS LV VFDQQHG
Figure 15.6
Example Bidirectional Alternating Repeating Block Transfer
BTR
BT10:0
EN
BTR
enable bit
BTW
enable bit
BT10:1
EN
BT10:1
EN
BTW
enable bit
BTR
enable bit
BT10:0
EN
BLOCK TRANSFER READ

Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
3
2
0
BT10:0
N11:0
10
N0
DN
ER
BTW
Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
3
2
0
BT10:1
N11:10
11
NO
DN
ER
Block-transfer rungs must be

scanned for the transfers to occur.
1785-6.1 November 1998
15-18
Example Bidirectional Continuous Block-Transfer

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Figure 15.7
Example Bidirectional Continuous Block Transfer
Preconditions
Preconditions
Scan the rung once to start continuous block transfers. The continuous
operation starts on a false-to-true rung transition and continues,
whether or not the rungs are scanned again. To stop continuous
operation, use the Data Monitor to reset the continuous bit (.CO or
bit 11), or change the Continuous field in the instruction to NO.
BTR
BLOCK TRANSFER READ
Rack
Group
Module
Control Block
Data file
Length
Continuous
3
6
1
BT10:0
N7:100
0
YES
BTW
Rack
Group
Module
Control Block
Data file
Length
Continuous
3
6
1
BT10:1
N7:200
0
YES
BT10:0
BT10:1
BT10:1
U
EN
ER
These rungs will reset block transfers and should be placed in logic where rungs are
being scanned for error recovery. Your logic must rescan the block transfers with
preconditions true in order to restart continuous block transfers.
DN
ER
EN
BT10:0
U
EN
ER
1785-6.1 November 1998
EN
DN
ER
15-19
Example Directional Non-Continuous Block-Transfer

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H[DPSOH 7KH EORFN WUDQVIHU H[HFXWHV RQFH IRU HYHU\ IDOVHWRWUXH
WUDQVLWLRQ RI WKH SUHFRQGLWLRQ
Figure 15.8
Example Directional Non-Continuous Block Transfer
BTR
Precondition
Use the same method for a BTW. The rung

must go from false to true for the transfer
to occur.
BLOCK TRANSFER READ

Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
2
5
1
BT10:0
N7:500
0
NO
DN
ER
Example Directional Repeating Block Transfer

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Figure 15.9
Example Directional Repeating Block Transfer
BTR
BT10:0
EN
Use the same method for a BTW. The block

transfer will continue as long as the step
is scanned.
BLOCK TRANSFER READ

Rack
Group
Module
Control Block
Data file
Length
Continuous
EN
2
5
1
BT10:0
N7:500
0
NO
DN
ER
1785-6.1 November 1998
15-20
Example Directional Continuous Block-Transfer

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Figure 15.10
Example Directional Continuous Block Transfer
Precondition
Use the same method for a BTW. Scan the rung once
to start continuous block transfers. The continuous
operation starts on a false-to-true rung transition and
continues, whether or not the rungs are scanned
again. To stop continuous operation, use the Data
Monitor to reset the continuous bit (.CO or bit 11), or
change the Continuous field in the instruction to NO.
BTR
error bit
BT10:0
BTR
BLOCK TRANSFER READ
Rack
Group
Module
Control Block
Data file
Length
Continuous
2
5
1
BT10:0
N7:500
0
YES
DN
ER
BTR
BT10:0 enable bit
U
ER
This rung will reset block transfers and should be placed in logic where rungs are being
scanned for error recovery. Your logic must rescan the block transfers with preconditions
true in order to restart continuous block transfers.
1785-6.1 November 1998
EN
EN
15-21
Example Buffering Block Transfer-Data

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BTR
enable bit
BT10:0
DN
BTR
done bit
BTR
BLOCK TRANSFER READ
Rack
Group
Module
Control Block
Data File
Length
Continuous
FAL
FILE ARITH/LOGICAL
Control
Length
Position
Mode
Destination
Expression
EN
2
2
1
BT10:0
N7:400
4
NO
DN
ER
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R6:4
4
0
ALL
#N7:500
#N7:400
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ER
1785-6.1 November 1998
15-22
ControlNet I/O Transfer (CIO)

Instruction
CIO
CNET I/O TRANSFER
Control Block CT21:50
EN
DN
ER
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Control Block Address

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Using the CIO Instruction
15-23
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Table 15.I
CIO Instruction Entry Screen Configuration
If You Want to:
Press this Key:
Change the command type. Toggle among the following:

1771 Read selects a block transfer read.
1771 Write selects a block transfer write.
1794 Fault Action selects the action the module takes
when the adapter faults and the connection is terminated.
1794 Idle Action selects the action the module takes when
the connection is idle.
1794 Config Data changes the configuration for the 1794
module.
1794 Safe State Data changes the value of the safe state
data for the 1794 module.
[F1] Command Type
Enter a PLC-5 data table address of the ControlNet processor.
[F2] PLC-5 Address
Enter the size in elements.

Type the number of elements and press [Enter].
1 (1794 Fault Action and 1794 Idle Action)
1-15 (1794 Config Data and 1794 Safe State Data)
0-64 (1771 Read and 1771 Write)
Note: If you enter 0 for 1771 Read and/or 1771 Write, 64
words are reserved for block transfer.
[F3] Size in Elements
Enter the destination network address.

Type a number (1-99) and press [Enter].
[F8] Local Node
Enter the destination slot number.

Type a number and press [Enter].
0-7 (1794 command types)
0-15 (1771 command types)
Note: The slot number represents the physical slot in the
chassis occupied by the module. To find your slot number,
count from the left I/O slot starting with 0.
[F9] Slot Number
1785-6.1 November 1998
15-24
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Table 15.J
CIO Instruction Control Block Parameters
If You Want to:
Press this Key:
Toggle the control bit that the cursor is on. You can toggle
among the TO, EW, CO, ER, DN, ST, and EN bits.
[F2] Toggle Bit
Change the size of the block of data to send or receive.
Change the address for which the data is displayed.
[F5] Specify Address
Display the data table values for the next file.
[F7] Next File
Display the data table values for the previous file.
[F8] Previous File
Display the data table values for the next element.
[F9] Next Element
Display the data table values for the previous element.
[F10] Previous Element
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Using Status Bits

This Bit:
Is Set:
Enable .EN (bit 15)
when the rung goes true. The .EN bit is reset when the .DN bit or .ER bit is set.
This bit shows that the instruction is enabled.
Start .ST (bit 14)
when the processor begins executing the CIO instruction. The .ST bit is reset when the
.DN bit or .ER bit is set.
Done .DN (bit 13)
when the last word of the CIO instruction transferred. The .DN bit is reset the next time
the associated rung goes from false to true.
The .DN bit is only active in non-continuous mode.
Error .ER (bit 12)
when the processor detects that the message transfer failed. The .ER bit is reset the next
time the associated rung goes from false to true.
manually for repeated operation of the CIO instruction after the first scan, independent of
whether the processor continues to scan the rung.
Enable-Waiting .EW (bit 10)
when the processor detects that a message request entered the queue. The processor
resets the .EW bit when the .ST bit is set.
through ladder logic to stop processing the message. The processor sets the .ER bit.
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Using the CT Control Block

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Word:
CT Control Block:
Description:
.EN through .TO
Status bits
See Using Status Bits above.
.ERR
Error code
This is where the processor stores the error code if a problem occurs during
message transmission.
.RLEN
Requested length
This is the requested number of elements you wish to transfer with the
message instruction.
.DLEN
Done length
This is the number of elements the module actually transferred after the instruction
completes execution. This number should match the requested length (unless the
requested length is 0).
.FILE
File number
This number identifies the file number of the file from which the data is written or to
which the data is read. For example, the file number of N12:1 is 12.
.ELEM
Element number
This number identifies the starting word in the data file address. For example, in
N12:1, the word number is 1.
1785-6.1 November 1998
15-26
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1785-6.1 November 1998
Chapter
16

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Message (MSG)
Description:
MSG
SEND/RECEIVE MESSAGE
EN
Control Block
DN
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16-2
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Entering Parameters
Processor
Series/Revision:
Processors:
Series A / revision M
PLC-5/40, -5/40L, -5/60, -5/60L
Series A / revision J
PLC-5/30
Series A / revision H
PLC-5/11, -5/20
Series B / revision J
PLC-5/40, -5/40L, -5/60, -5/60L
Series C / revision G
Enhanced, Ethernet, and VME PLC-5 processors
Series C / revision H
ControlNet PLC-5
Series D / revision A
Enhanced, Ethernet, ControlNet, and VME PLC-5 processors
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If You Have this Processor:
Use this Control Block Address:
Classic PLC-5
an integer file (N) without the # symbol for the message

control block. Example: N7:0
Enhanced PLC-5, Ethernet

PLC-5, or VME PLC-5
an integer file (N) or the message (MG) file type to

access the message control block for DH+ transfers.
Example: MG10:0
Using the MG control block, the control block size is
fixed at 56 words. This size is displayed on the screen
in the BLOCK SIZE field. You must use the MG control
block if you are sending messages to an SLC 500
processor using the SLC read and write commands, or
if you are sending message out any port other than
channel 1A.
Ethernet PLC-5, ControlNet

PLC-5, VME PLC-5
1785-6.1 November 1998
a message (MG) file type to access the VMEbus,

Ethernet, or ControlNet network
16-3
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MSG Data Entry Screen

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This Function Key:
Specifies this Information:
[F1] Command Type
Whether the MSG instruction performs a read or write operation and to what type of
processor the message is going to.
[F2] PLC-5 Address
The data file address of the processor containing the message instruction. If the
MSG operation is write, this address is the starting word of the source file. If the
MSG operation is read, this address is the starting word of the destination file.
The number of elements (1-1000) to be transferred.
1785-6.1 November 1998
16-4
This Function Key:
[F4] Local/Remote
LOCAL: the message is sent to a device on the local DH+ link.

REMOTE: the message is sent through a bridge (DH, DH II, etc.) to another
DH+ link.
If you select REMOTE, the function keys [F5] Remote Station, [F6] Link ID, and
[F7] Remote Link are active.
[F5] Remote Station
The DH or DH II address (1-376 octal) of the target station.

PLC-2 and PLC-3 processors require communication adapter modules (1771-KA2
and 1775-KA, respectively) when they operate as stations on data highway. In these
configurations, the remote station address is the address of the communication
adapter module.
[F6] Link ID
The remote link where the processor you want to communicate with resides. The
default is 0.
[F7] Remote Link
Toggles through DH, DH II, and other choices for what connects the remote link to
the local DH+.
[F8] Local Node
The local station address on the DH+ (0-77 octal).

If you communicate with another processor on the local link, this address is the
address of the target station on the local link.
If you communicate with a target station on a remote link, this address is the station
number of the communication adapter module that bridges the data highway.
[F9] Destination Address
The starting address of the source or destination file in the target processor.
[F10] Port Number
The channel for message communications. Valid options are: 0, 1A (default), 1B, 2A,
2B, and 3A for the ASCII command.
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Using the Message Instruction for

Ethernet Communications
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Entering Parameters
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1785-6.1 November 1998
16-6
This Field:
Command Type
Whether the MSG instruction performs a read or write operation. The software
toggles between:
PLC-5 Typed Read
PLC-5 Typed Write
PLC-5 Typed Write to SLC
PLC-5 Typed Read from SLC
SLC Typed Logical Read
SLC Typed Logical Write
PLC-2 Unprotected Read
PLC-2 Unprotected Write
PLC-3 Word Range Read
PLC-3 Word Range Write
ASCII
PLC-5 Address
The data file address of the processor containing the message instruction. If the
MSG operation is write, this address is the starting word of the source file. If the
MSG operation is read, this address is the starting word of the destination file.
Size in Elements
IP Address
The MSG instructions destination node.

If the destination is another PLC-5/20E, -5/40E, or -5/80E, the destination must be
a full Internet address
If the destination is an INTERCHANGE client program, enter the word CLIENT
as the destination node. Do not enter an IP address.
Note: You must set [F10] Port Number to 2 in order to access this function.
Destination Address
Port Number
The channel for message communications. Ethernet communications use channel 2.
Multihop
Select yes if you want to send the MSG instruction to a ControlLogix device. Then use
the Multihop tab to specify the path of the MSG instruction. For more information, see
Configuring an Ethernet Multihop MSG Instruction on page 16-9.
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1785-6.1 November 1998

PLC-5 Ethernet Interface Module
Communications
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16-8
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This Field:
Command Type
Whether the MSG instruction performs a read or write operation. The software
toggles between:
PLC-5 Typed Read
PLC-5 Typed Write
PLC-5 Typed Write to SLC
PLC-5 Typed Read from SLC
ASCII
PLC-5 Address
The data file address of the processor containing the message instruction. If the MSG
operation is write, this address is the starting word of the source file. If the MSG
operation is read, this address is the starting word of the destination file.
Size in Elements
Host/IP Address
The MSG instructions destination node.

If the destination is an Enhanced PLC-5 processor, the destination must be a full
Internet address
If the destination is an INTERCHANGE client program, enter the word CLIENT
as the destination node. Do not enter an IP address.
Note: You must set [F10] Port Number to 2 in order to access this function.
Destination Address
Port Number
The channel for message communications. The PLC-5 Ethernet Interface Module
communications use channel 3A.
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1785-6.1 November 1998
16-9
Configuring an Ethernet Multihop

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Ethernet PLC-5 processor
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16-10

ControlNet Communications
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1785-6.1 November 1998
This Field:
Command Type
Change the command type. Toggle between the following:

PLC-5 Typed Write selects a write operation to a ControlNet PLC-5 processor
PLC-5 Typed Read selects a read operation from another ControlNet PLC-5
processor
PLC-5 Address
The PLC-5 data table address of the ControlNet processor. If the MSG operation is
write, this address is the starting word of the source file. If the MSG operation is read,
this address is the starting word of the destination file.
Size in Elements
Local Node
The destination node address (1-99).
Destination Address
Port Number
The channel for message communications. The port number must be 2 for ControlNet.
Multihop
Select yes if you want to send the MSG instruction to a ControlLogix device. Then use
the Multihop tab to specify the path of the MSG instruction. For more information, see
Configuring an ControlNet Multihop MSG Instruction on page 16-11.
16-11
Configuring a ControlNet Multihop

MSG Instruction
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SLC 5/05 Processor
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ControlNet

PLC-5 Processor
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16-12
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This Bit:
Is Set:
Enable .EN (bit 15)
when the rung goes true. This bit shows that the instruction is enabled (that the
instruction is being executed). In non-continuous mode, .EN bit remains set until the
message is completed and the rung goes false. In continuous mode, once .EN bit is set, it
remains set regardless of the rung condition.
Start .ST (bit 14)
when the processor begins executing the MSG instruction. The .ST bit is reset when the
.DN bit or .ER bit is set.
Done .DN (bit 13)
when the last packet of the MSG instruction transferred. The .DN bit is reset the next
time the associated rung goes from false to true. The .DN bit is only active in
non-continuous mode.
Error .ER (bit 12)
when the processor detects that the message transfer failed. The .ER bit is reset the next
time the associated rung goes from false to true.
manually for repeated operation of the MSG instruction after the first scan, independent
of whether the processor continues to scan the rung. Reset the .CO bit if you want the
rung condition to initiate messages (return to non-continuous mode).
Enable-Waiting .EW (bit 10)
when the processor detects that a message request entered the queue. The processor
resets the .EW bit when the .ST bit is set.
No Response .NR (bit 09)
if the target processor does not respond to the first MSG request. The .NR bit is reset
when the associated rung goes from false to true.
if you set the .TO bit through ladder logic, the processor stops processing the message
and sets the .ER bit (timeout error 55). A DH+ message time out in 30-60 seconds. A
ControlNet message will time out in 4 seconds
No Cache .NC
(ControlNet processors only)
if you set the .NC bit, the open connection is closed when the MSG is done. If this bit
remains reset, the connection remains open even when the MSG is complete.
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16-13

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Table 16.A
Values in the Control Block
Word Integer
Control Block
Message Control Block
Description
.EN thru .RW
Control bits
0 - low byte
.ERR
Error code
2 - high byte
.RLEN
Requested length
2 - low byte
.DLEN
Done length
Internal data
Error Code (.ERR)

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1785-6.1 November 1998
16-14
Entering Parameters
Communication Command
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If You Want the Instruction to:
Select the Command:
Read data identified by a type code. This command reads data structures without you specifying the
actual word length. For example, if you choose a typed read of the PLC-5 timer data section with a
requested data size of 5 elements, the MSG instruction reads 15 words (5 timer structures of 3
words each).
PLC-5 Typed Read
Write data identified by a type code. This command writes data structures without you specifying the
actual word length.
PLC-5 Typed Write
Read 16-bit words from any area of the PLC-2 data table or PLC-2 compatibility file.
Write 16-bit words to any area of the PLC-2 data table or PLC-2 compatibility file.
Read data identified by a type code. This command reads data structures without specifying the actual
word length. This command provides additional data verification for communications between a PLC-5
and SLC 500 processor.1
PLC-5 Typed Read from SLC2, 3
Write data identified by a type code. This command writes data structures without specifying the actual
word length. This command provides additional data verification for communications between a PLC-5
and SLC 500 processor.1
PLC-5 Typed Write to SLC2, 3
Read a range of words, starting at the address specified for the external address in the MSG control file
and reading sequentially the number of words specified for the requested size field in the MSG control
file. The data that is read is stored, starting at the address specified fro the internal address in the MSG
control file. This is used for communicating between a PLC-5 and SLC 500 processor.1
SLC Typed Logical Read3
Write a range of words, starting at the address specified for the internal address in the MSG control file
and writing sequentially the number of words specified for the requested size field in the MSG control file.
The data from the internal address is written, starting at the address specified for the external address in
the MSG control file. This is used for communicating between a PLC-5 and SLC 500 processor.1
SLC Typed Logical Write3
Read a range of words, starting at the address specified for the external address in the MSG control file
and reading sequentially the number of words specified for the requested size field in the MSG control
file. The data that is read is stored, starting at the address specified for the internal address in the MSG
control file.
Write a range of words, starting at the address specified for the internal address in the MSG control file
and writing sequentially the number of words specified for the requested size field in the MSG control file.
The data from the internal address is written, starting at the address specified for the external address in
the MSG control file.
1The PLC-5 is limited to a maximum message of 103 words (206 bytes). The maximum message size for SLC 5/03 and SLC 5/04 processors is 103 words
(206 bytes). The maximum message size capability of all other SLC 500 processors is 41 words (82 bytes).
2
These commands are valid only with any SLC 5/04 and SLC 5/03 series C and later processors.
3
These commands are only valid with processors listed in the table on page 16-2.
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16-15
External Data Table Addresses

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This Communication Command:
To this Device:
Requires that You Enter:
Example Address:
PLC-5 Typed Read
PLC-5/250
the address in double quotes
1N0:0
PLC-5 Typed Write
PLC-5
the address
N7:0
1775-S5
the address in double quotes,

precede with a $ character
$N7:0
1775-SR5
PLC-2
PLC-2
compatibles
octal number of 16-bit

word offset
025

PLC-5/250
1N7:0
PLC-5

precede with a $ character
$N7:0
1775-S5
1775-SR5

precede with a $ character, or
just the address (which will
be slightly faster)
$N7:0
N7:0
1771-DMC
Control
Coprocessors

00 to 31 to match
C program
01

SLC 500
processors
the address
N7:0
PLC-5 Typed Read to SLC

PLC-5 Typed Write from SLC
SLC 5/03 and

5/04 processors
the address
N7:0
PLC-2 to PLC-5 Compatibility Files

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1785-6.1 November 1998
16-16
Sending SLC Typed Logical Read and Typed Logical

Write Commands
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1785-6.1 November 1998
This PLC-5 Data Type:
Is Interpreted by the SLC 5/03

and 5/04 Processors as:
Binary (B)
Bit
Integer (N)
Integer
Output (O)
Integer
Input (I)
Integer
Status (S)
Integer
ASCII (A)
ASCII
BCD (D)
Integer
SFC status (SC)
Integer
String (ST)
String
BT control (BT)
Integer
ControlNet transfer (CT)
Integer
Timer (T)
Timer
Counter (C)
Counter
Control (R)
Control
Float (F)
Float
MSG control (MG)
Integer
PID control (PD)
Integer
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Monitoring a Message Instruction
16-17
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If You Are Using this File Type:
See:
integer (N)
Table 16.B
message (MG)
Table 16.C
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Table 16.B
Data Monitor Screen for the MSG Instruction N File Type
If You Want to:
Press this Key:
specify the number of elements (1-1000) you

want to read from or write to the network station
[F3} Size in Elements
set and reset status bits
[F9] Toggle Bit
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Table 16.C
Data Monitor Screen for the MSG Instruction MG File Type
If You Want to:
Press this Key:
Toggle the control bit that the cursor is on.

You can toggle among the TO, NR, EW, CO, ER, DN, ST, and
EN bits
[F2] Toggle Bit
Change the size of the block of data to send or receive.
Change the address for which the data is displayed.
[F5] Specify Address
Display the data table values for the next file.
[F7] Next File
Display the data table values for the previous file.
[F8] Previous File
Display the data table values for the next element.
[F9] Next Element
Display the data table values for the previous element.
[F10] Previous Element
1785-6.1 November 1998
16-18
Selecting Continuous Operation
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1785-6.1 November 1998
16-19
Figure 16.1
Timing Diagram for Status Bits in Continuous MSG Instructions
EN
EW
A
ST
CO
DN
ER
Rung true
Data sent by
instruction
and received
in the queue
MSG begins
transmission
on network
MSG
transmission
completes
Rung false
Rung true
these events are asynchronous to ladder program scan

A
When the MSG transmission completes, the cycle starts over here without rung transitions
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Operation
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1785-6.1 November 1998
16-20
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Figure 16.2
Timing Diagram for Status Bits in Non-Continuous MSG Instructions
EN
EW
ST
CO
DN
ER
Rung true
Data sent by
instruction
and received
in the queue
MSG begins
transmission
on network
MSG
transmission
completes
Rung false
Rung true
these events are asynchronous to ladder program scan
MSG Timing
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1785-6.1 November 1998
16-21
Table 16.D
Message Instruction Operation
Receiving MSG
(Station A reading/receiving from Station B)
Sending MSG
(Station A writing/sending to Station B)
station A enables the message instruction in the

ladder program
station A enables the message instruction in the

ladder program
station A obtains the token and transmits the read

command (station B acknowledges immediately)
station A obtains the token and transmits data

(station B acknowledges immediately)
station B obtains the token and transmits

requested data
station B stores the data in memory
station A receives the data and

acknowledges immediately
station B obtains the token to respond that the

write is complete
station A sets the done bit
station A sets the done bit when it receives

a response
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Processor Type:
Formula:
Classic PLC-5
Message time = TP + TT + OH + P + 8 (number of messages)
Enhanced PLC-5
Message time = TP + TT + OH + 8 (number of messages)
ZKHUH
TP =
TT
OH
P
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1785-6.1 November 1998
16-22
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Error Codes
Table 16.E
Errors Detected By the Processor
Code:
Enhanced PLC-51
MG data type
Classic PLC-52
N data type
Ethernet Only
Description (Displayed on the Data Monitor screen):
0037
55
0037
message timed out in local processor
0083
131
0083
processor is disconnected
0089
137
0089
message buffer is full

If the MSG is going out channel 0, there are not enough
internal buffers available. Decrease the number of MSG
instructions to this port.
Otherwise, the destination node sent back a MSG indicating
that its buffers are full. Decrease the number of MSG
instructions going to the destination node.
0092
146
0092
no response (regardless of station type)
00D3
211
00D3
you formatted the control block incorrectly
00D5
213
00D5
incorrect address for the local data table
0200
link layer timed out or received a NAK
0300
duplicate token holder detected by link layer
0400
local port is disconnected
0500
application layer timed out waiting for a response
0600
duplicate node detected
0700
station is off line
0800
hardware fault
1000
129
1000
illegal command from local processor
2000
130
2000
communication module not working
3000
131
4000
132
4000
processor connected but faulted (hardware)
5000
133
5000
you used the wrong station number
6000
134
6000
requested function is not available
7000
135
7000
processor is in program node
1
2
remote node is missing, disconnected, or shut down
Hexadecimal word 1 of the control block

Decimal low byte of word 0 of the control block
1785-6.1 November 1998
16-23
Code:
Enhanced PLC-51
MG data type
Classic PLC-52
N data type
Ethernet Only
Description (Displayed on the Data Monitor screen):
8000
136
8000
processors compatibility file does not exist
9000
137
9000
remote node cannot buffer command
B000
139
B000
processor is downloading so it is inaccessible
F001
231
F001
processor incorrectly converted the address
F002
232
F002
incomplete address
F003
233
F003
incorrect address
F006
236
F006
addressed file does not exist in target processor
F007
237
F007
destination file is too small for number of words requested
F00A
240
F00A
target processor cannot put requested information

in packets
F00B
241
F00B
privilege error, access denied
F00C
242
F00C
requested function is not available
F00D
243
F00D
request is redundant
F011
247
F011
data type requested does not match data available
F012
248
F012
incorrect command parameters
00103
0010
no IP address configured for the network
00113
0011
already at maximum number of connections
00123
0012
invalid Internet address or host name
0013
no such host
00143
0014
cannot communicate with the name server
00153
0015
connection not completed before user-specified timeout
00163
0016
connection timed out by the network
0017
connection refused by destination host
00183
0018
connection was broken
00193
0019
reply not received before user-specified timeout
001A3
001A
no network buffer space available
F01A
file owner active the file is being used
F01B
program owner active someone is downloading, online

editing, or set the program owner with APS in the WHO
Active screen
0013
0017
1Hexadecimal
word 1 of the control block

Decimal low byte of word 0 of the control block
3Errors detected by a Enhanced PLC-5 processor attached to a PLC-5 Ethernet Interface Module only.
2
1785-6.1 November 1998
16-24
Table 16.F
Errors Detected By the VME Processor
1785-6.1 November 1998
PLC-5/40V (hexadecimal
word 1 of the control block)
Description (Displayed on the Data Monitor

screen):
0000
success
0001
invalid ASCII message format
0002
invalid file type
0003
invalid file number
0004
invalid file element
0005
invalid VME address
0006
invalid VME transfer width
0007
invalid number of elements requested for transfer
0008
invalid VME interrupt level
0009
invalid VME interrupt status-id value
000A
VMEbus transfer error (bus error)
000B
unable to assert requested interrupt (already pending)
000C
raw data transfer setup error
000D
raw data transfer crash (PLC switched out of run mode)
000E
unknown message type (message type not ASCII)
Chapter
17
ASCII Instructions ABL, ACB, ACI, ACN,

AEX, AIC, AHL, ARD, ARL, ASC, ASR,
AWA, AWT
Using ASCII Instructions
Enhanced PLC-5 Processors Only
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Table 17.A
Available ASCII Instructions
If You Want to:
On Page:
See how many characters are in the buffer, up to

and including the end of line character
ABL
17-4
See how many total characters are in the buffer
ACB
17-5
Convert a string to an integer value
ACI
17-6
Concatenate two strings into one
ACN
17-7
Extract a portion of a string to create a new string
AEX
17-7
Configure your modem handshake lines
AHL
17-8
Convert an integer value to a string
AIC
17-9
Read characters from the buffer and put into a

string
ARD
17-10
Read one line of characters from the buffer and

put into a string
ARL
17-12
Search a string for another string
ASC
17-14
Compare two strings
ASR
17-15
Write a string with user-configured characters

appended
AWA
17-15
Write a string
AWT
17-17

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1785-6.1 November 1998
17-2
ASCII Instructions ABL, ACB, ACI, ACN, AEX, AIC, AHL, ARD, ARL, ASC, ASR, AWA, AWT
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Type of ASCII Instruction:
Description:
ASCII port control
read, write, set/reset handshake lines,

examine the length of the buffer (ARD,
ARL, AWT, AWA, AHL, ACB, ABL)
ASCII string
manipulate string data, such as

compare, search, extract, concatenate,
convert to/from integer (ASR, ASC, AEX,
ACN, ACI, AIC)
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Using Status Bits

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1785-6.1 November 1998
Description:
Explanation of Status Bit:
Found.FD (08)
Reserved
Unload.UL (10)
This bit may be used by the user to cancel an ASCII read or

write in progress. The time out may occur immediately or up to 6
seconds later.
Error.ER (11)
The instruction did not complete successfully.

Note: If this bit is set, the .EN bit is cleared and the .DN bit is set
during prescan.
Synchronous Done.EM (12)
The bit is set on the first scan of the instruction after it is completed.
Asynchronous Done.DN (13)
The bit is set immediately upon successful completion of the

instruction, asynchronous to program scan.
Note: If this bit is set , the .EN bit is cleared and the .DN bit is set
during prescan.
Queue.EU (14)
The bit is set when the instruction is successfully queued.
Enable.EN (15)
The bit is set when the rung goes true and is reset after completion
of the instruction and the rung goes false.
Note: If this bit is set and the .DN and .ER bits are cleared, the
control word is cleared during prescan.
17-3

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Table 17.B
Values in the Control Word
Word Integer
Control Block
ASCII Control Block
Description
.EN, .DN, etc
Status Bits
.LEN
Word Length
.POS
Character Position
Length (.LEN)
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Using Strings
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1785-6.1 November 1998
17-4
Test Buffer for Line (ABL)

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Description:
ABL
ASCII TEST FOR LINE
Channel
Control
Characters
EN
DN
ER
Entering Parameters
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Parameter:
Definition:
Channel
the number of the RS-232 port. (The only valid value is 0).
Control
the address of a control file element used for the control

status bits.
Characters
the number of characters in the buffer (including the

end-of-line/termination characters) that the processor finds
(0-256). This field is display only.
Example:
ABL
I:012
[
EN
ASCII TEST FOR LINE
10
If input word 12, bit 10 is set, the processor
performs an ABL operation for channel 0.
Channel
Control
Characters
0
R6:32
DN
ER
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SRVLWLRQ ILHOG QR HQGRIOLQHWHUPLQDWLRQ FKDUDFWHUV ZHUH IRXQG 7KH
)' ELW LV VHW LI WKH SRVLWLRQ ILHOG ZDV VHW WR D QRQ]HUR YDOXH
:KHQ WKH SURJUDP VFDQV WKH LQVWUXFWLRQ DQG ILQGV WKH '1 ELW VHW WKH
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WKH LQVWUXFWLRQ LV DERUWHG VHULDO SRUW QRW LQ 8VHU PRGH
WKH LQVWUXFWLRQ LV DERUWHG GXH WR SURFHVVRU PRGH FKDQJH
17-5
Number of Characters in Buffer

(ACB)
Description:
EN
DN
ER
Entering Parameters
7R XVH WKH $&% LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU WKH
Parameter:
Definition:
Channel
the number of the RS-232 port (The only valid value in this field is 0).
Control
the address of a control file element used for control status bits.
Characters
the number of the characters in the buffer that the processor finds
(0-256). This field is display only.
Example:
ACB
I:012
[
ACB
ASCII CHARS IN BUFFER
Channel
Control
Characters
8VH WKH $&% LQVWUXFWLRQ WR VHH KRZ PDQ\ WRWDO FKDUDFWHUV DUH LQ WKH
EXIIHU 2Q D IDOVHWRWUXH WUDQVLWLRQ WKH V\VWHP GHWHUPLQHV WKH WRWDO
QXPEHU RI FKDUDFWHUV DQG UHSRUWV LW LQ WKH &KDUDFWHUV ILHOG 7KH VHULDO
SRUW PXVW EH LQ 8VHU PRGH
EN
ASCII CHARS IN BUFFER
10
If input word 12, bit 10 is set, the processor
performs an ACB operation for channel 0.
Channel
Control
Characters
0
R6:32
DN
ER
(1 LV VHW :KHQ WKH LQVWUXFWLRQ LV SXW LQ WKH $6&,, LQVWUXFWLRQ
TXHXH WKH (8 ELW LV VHW DQG SURJUDP VFDQ FRQWLQXHV 7KH LQVWUXFWLRQ
LV WKHQ H[HFXWHG SDUDOOHO WR SURJUDP VFDQ
7KH SURFHVVRU GHWHUPLQHV WKH QXPEHU RI FKDUDFWHUV LQ WKH EXIIHU DQG
SXWV WKLV YDOXH LQ WKH SRVLWLRQ ILHOG 7KH GRQH ELW LV WKHQ VHW ,I D ]HUR
DSSHDUV LQ WKH SRVLWLRQ ILHOG QR FKDUDFWHUV ZHUH IRXQG 7KH )' ELW LV
VHW LI WKH SRVLWLRQ ILHOG ZDV VHW WR D QRQ]HUR YDOXH
1785-6.1 November 1998
17-6
ASCII String to Integer (ACI)

8VH WKH $&, LQVWUXFWLRQ WR FRQYHUW DQ $6&,, VWULQJ WR DQ LQWHJHU YDOXH
EHWZHHQ DQG
Description:
ACI
7KH SURFHVVRU VHDUFKHV WKH VRXUFH ILOH W\SH 67 IRU WKH ILUVW FKDUDFWHU
WKDW LV EHWZHHQ DQG $OO QXPHULF FKDUDFWHUV DUH H[WUDFWHG XQWLO D
QRQQXPHULF FKDUDFWHU RU WKH HQG RI WKH VWULQJ LV UHDFKHG &RPPDV
DQG VLJQV DUH DOORZHG LQ WKH VWULQJ
STRING TO INTEGER CONVERSION
Source
Destination
7KH H[WUDFWHG QXPHULF VWULQJ LV WKHQ FRQYHUWHG WR DQ LQWHJHU EHWZHHQ

DQG
,I QR QXPHULF FKDUDFWHUV DUH IRXQG QR DFWLRQ LV WDNHQ $OVR LI WKH
VWULQJ KDV DQ LQYDOLG OHQJWK OHVV WKDQ ]HUR RU JUHDWHU WKDQ WKH
IDXOW ELW LV VHW 6 DQG WKH LQVWUXFWLRQ LV QRW H[HFXWHG
7KLV LQVWUXFWLRQ DOVR VHWV WKH DULWKPHWLF IODJV IRXQG LQ ZRUG ELWV
LQ WKH SURFHVVRU VWDWXV ILOH 6
Bit:
Description:
Indicating:
S:0/0
Carry (C)
the carry was generated while converting the

string to an integer
S:0/1
Overflow (V)
the integer value was outside of the valid range
S:0/2
Zero (Z)
the integer value is zero
S:0/3
Sign (S)
the integer value is negative
Example:
ACI
I:012
[
[
10
If input word 12, bit 10 is set, convert the string in

ST38:90 to an integer and store the result in N7:123.
1785-6.1 November 1998
STRING TO INTEGER
Source
Destination
ST38:90
N7:123
75
17-7
ASCII String Concatenate (ACN)

7KH $&1 LQVWUXFWLRQ DSSHQGV 6RXUFH % WR WKH HQG RI 6RXUFH $ DQG
VWRUHV WKH UHVXOW LQ WKH 'HVWLQDWLRQ
Description:
ACN
,I WKH UHVXOW LV ORQJHU WKDQ FKDUDFWHUV RQO\ WKH ILUVW DUH ZULWWHQ
WR WKH GHVWLQDWLRQ ILOH DQG WKH HUURU ELW 6 LV VHW $OVR LI WKH
OHQJWK RI HLWKHU VWULQJ LV LQYDOLG OHVV WKDQ ]HUR RU JUHDWHU WKDQ WKH
IDXOW ELW LV VHW DQG WKH VWULQJ DW WKH GHVWLQDWLRQ DGGUHVV LV QRW FKDQJHG
STRING CONCATENATE
Source A
Source B
Destination
Example:
I:012
ACN
STRING CONCATENATE
[
10
If input word 12, bit 10 is set, concatenate the string
in ST37:42 with the string in ST38:91 and store the
result in ST52:76
Source A
Source B
ST37:42
ST38:91
Destination
ST52:76
ASCII String Extract (AEX)

8VH WKH $(; LQVWUXFWLRQ WR FUHDWH D QHZ VWULQJ E\ WDNLQJ D SRUWLRQ RI
DQ H[LVWLQJ VWULQJ
Description:
AEX
STRING EXTRACT
Entering Parameters
Source
Index
Number
Destination
7R XVH WKH $(; LQVWUXFWLRQ \RX PXVW SURYLGH WKH SURFHVVRU WKH
Parameter:
Definition:
Source
the existing string.
Index
the starting position (from 1 to 82) of the portion of the string you want to
extract. (An index of 1 indicates the left-most character of the string.)
Number
the number of characters (from 0 to 82) you want to extract, starting at

the indexed position. If the Index plus the Number is greater than the total
characters in the source string, the destination string will be the
characters from the index to the end of the source string. If you enter 0
for the number, the destination string length is set to zero.
Destination
the string element (ST) where you want the extracted string stored.
Example:
I:012
[
[
10
If input word 12, bit 10 is set, extract 10 characters

starting at the 42nd character of ST38:40 and store
the result in ST52:75.
AEX
STRING EXTRACT
Source
Index
Number
Destination
ST38:40
42
10
ST52:75
1785-6.1 November 1998
17-8
7KH IROORZLQJ FRQGLWLRQV FDXVH WKH SURFHVVRU WR VHW WKH IDXOW

ELW 6
LQYDOLG VWULQJ OHQJWK RU VWULQJ OHQJWK RI ]HUR
LQGH[ RU QXPEHU YDOXHV RXWVLGH RI UDQJH
LQGH[ YDOXH JUHDWHU WKDQ WKH OHQJWK RI WKH VRXUFH VWULQJ
7KH GHVWLQDWLRQ VWULQJ ZLOO QRW FKDQJH LQ DQ\ RI WKH DERYH LQVWDQFHV
ASCII Set or Reset Handshake

Lines (AHL)
Description:
AHL
ASCII HANDSHAKE LINE
Channel
AND Mask
OR Mask
Control
Channel Status
EN
DN
ER
8VH WKH $+/ LQVWUXFWLRQ WR VHW RU UHVHW WKH 56 '75 DQG 576
KDQGVKDNH FRQWURO OLQHV IRU \RXU PRGHP 2Q D IDOVHWRWUXH WUDQVLWLRQ
WKH V\VWHP XVHV WKH WZR PDVNV WR GHWHUPLQH ZKHWKHU WR VHW RU UHVHW WKH
'75 DQG 576 OLQHV RU OHDYH WKHP XQFKDQJHG
,PSRUWDQW %HIRUH \RX XVH WKLV LQVWUXFWLRQ PDNH VXUH WKDW \RX GR
QRW FRQIOLFW ZLWK WKH DXWRPDWLF FRQWURO OLQHV RQ
\RXU PRGHP
Entering Parameters
7R XVH WKH $+/ LQVWUXFWLRQ \RX PXVW SURYLGH WKLV LQIRUPDWLRQ
1785-6.1 November 1998
Parameter:
Definition:
Channel
the number of the RS-232 port that you want to use. Currently, only
channel 0 can be set or reset.
AND Mask
the mask to reset the DTR and RTS control lines. Bit 0 corresponds
to the DTR line and bit 1 corresponds to the RTS line. A 1 at the
mask bit causes the line to be reset; a 0 leaves the line unchanged.
OR Mask
the mask to set the DTR and RTS control lines. Bit 0 corresponds to
the DTR line and bit 1 corresponds to the RTS line. A 1 at the mask
bit causes the line to be set; a 0 leaves the line unchanged.
Control
the address of the result control structure in the control area of

memory for the result.
Channel Status
displays the current status (0000 to FFFF) of the handshake lines

for the channel specified above. This field is display only; convert
the hexadecimal status to binary and refer to the table below:
Bit
Line
RTS
DTR
17-9
Example: (Reset DTR and RTS Lines)

AHL
I:012
[
[
10
If input word 12, bit 10 is set, bit 0 and bit 1 of the AND
mask is set to RESET (OFF) the DTR and RTS lines.
Channel status will display a 000D.
ASCII HANDSHAKE LINES

Channel
AND Mask
OR Mask
Control
Channel Status
EN
0
0003
0000
R6:23
DN
ER
Example: (Set DTR and RTS Lines)

AHL
I:012
[
[
11
If input word 12, bit 11 is set, bit 0 and bit 1 of the OR

mask is set to SET (ON) the DTR and RTS lines.
Channel status will display a 001F.
ASCII HANDSHAKE LINES

Channel
AND Mask
OR Mask
Control
Channel Status
EN
0
0000
0003
R6:22
DN
ER
7KH HUURU ELW (5 LV VHW GXULQJ WKH H[HFXWLRQ RI WKH LQVWUXFWLRQ LI WKH
LQVWUXFWLRQ LV DERUWHG GXH WR SURFHVVRU PRGH FKDQJH
ASCII Integer to String (AIC)

8VH WKH $,& LQVWUXFWLRQ WR FRQYHUW DQ LQWHJHU YDOXH EHWZHHQ
DQG WR DQ $6&,, VWULQJ 7KH VRXUFH FDQ EH D FRQVWDQW RU DQ
LQWHJHU DGGUHVV
Description:
AIC
INTEGER TO STRING
Source
Destination
Example:
I:012
[
[
10
If input word 12, bit 10 is set, convert the value

867 to a string and store the result in ST38:42.
AIC
INTEGER TO STRING
Source
Destination
867
ST38:42
1785-6.1 November 1998
17-10
ASCII Read Characters (ARD)

Description:
ARD
ASCII READ
Channel
Destination
Control
String Length
Characters Read
EN
DN
ER
8VH WKH $5' LQVWUXFWLRQ WR UHDG FKDUDFWHUV IURP WKH EXIIHU DQG VWRUH
WKHP LQ D VWULQJ 7R UHSHDW WKH RSHUDWLRQ WKH UXQJ PXVW JR IURP IDOVH
WR WUXH 7KH VHULDO SRUW PXVW EH LQ 8VHU PRGH
Entering Parameters
7R XVH WKH $5' LQVWUXFWLRQ SURYLGH WKH IROORZLQJ LQIRUPDWLRQ
Parameter:
Definition:
Channel
Control
the control file element used for the control status bits.
Destination
the string element where you want the characters stored.
String Length
the number of characters you want to read from the buffer. The
maximum is 82 characters. If you specify a length larger than 82,
only 82 characters will be read. (If you specify 0, the string length
defaults to 82.)
Characters Read
the number of characters that the processor moved from the buffer
to the string (0 to 82). This field is display only.
Example:
ARD
ASCII READ
I:012
[
10
If input word 12, bit 10 is set, read 50 characters
from the buffer and move them to ST52:76.
Channel
Destination
Control
String Length
Characters Read
EN
0
ST52:76
R6:23
50
DN
ER
2QFH WKH UHTXHVWHG QXPEHU RI FKDUDFWHUV DUH LQ WKH EXIIHU WKH
FKDUDFWHUV DUH PRYHG WR WKH GHVWLQDWLRQ VWULQJ 7KH QXPEHU RI
FKDUDFWHUV PRYHG LV SXW LQ WKH SRVLWLRQ ZRUG RI WKH FRQWURO HOHPHQW
DQG WKH GRQH ELW LV VHW
<RX FDQ XVH WKH 8/ ELW WR WHUPLQDWH DQ $5' LQVWUXFWLRQ EHIRUH LW
FRPSOHWHV IRU H[DPSOH \RX PD\ ZDQW WR WHUPLQDWH WKH LQVWUXFWLRQ LI
\RX NQRZ WKDW WKH $6&,, GHYLFH FRQQHFWHG WR WKH SRUW LV QRW VHQGLQJ
GDWD RU LI WKH FRQQHFWLRQ EUHDNV DIWHU WKH LQVWUXFWLRQ VWDUWV H[HFXWLQJ
6HW WKH 8/ ELW LQ WKH FRQWURO VWUXFWXUH WKH (5 ELW LV WKHQ VHW
1785-6.1 November 1998
17-11
,PSRUWDQW :KHQ \RX VHW WKH 8/ ELW WKH LQVWUXFWLRQ GRHV QRW
WHUPLQDWH LPPHGLDWHO\ LW PD\ WDNH VHYHUDO VHFRQGV
,I DQ $5' LQVWUXFWLRQ VWDUWV H[HFXWLQJ ZLWK WKH 8/ ELW DOUHDG\ VHW DQG
WKHUH DUH QR FKDUDFWHUV LQ WKH EXIIHU WKH LQVWUXFWLRQ WHUPLQDWHV ,I DQ
$5' LQVWUXFWLRQ VWDUWV H[HFXWLQJ ZLWK WKH 8/ ELW DOUHDG\ VHW DQG
WKHUH DUH FKDUDFWHUV LQ WKH EXIIHU WKH LQVWUXFWLRQ SURFHHGV WR
QRUPDO FRPSOHWLRQ
ZKHQ XVLQJ D PRGHP WKH PRGHP LV GLVFRQQHFWHG
Figure 17.1
Example ARD Timing Diagram
Rung Condition
ON
OFF
Enable Bit (.EN)
ON
OFF
Queue Bit (.EU)
ON
OFF
Done Bit
Error Bit
(.DN or. ER)
Synchronous Done Bit (.EM)
ON
OFF
ON
OFF
1 2
3 4
1 - rung goes true
2 - instruction successfully queued
3 - instruction execution complete
4 - instruction scanned for the first time after execution is complete
5 - rung goes false
1785-6.1 November 1998
17-12
ASCII Read Line (ARL)

Description:
ARL
ASCII READ LINE
Channel
Destination
Control
String Length
Characters Read
EN
DN
ER
8VH WKH $5/ LQVWUXFWLRQ WR UHDG FKDUDFWHUV IURP WKH EXIIHU XS WR DQG
LQFOXGLQJ WKH HQGRIOLQH WHUPLQDWLRQ FKDUDFWHUV DQG VWRUH WKHP LQ D
VWULQJ 7KH HQGRIOLQH FKDUDFWHUV DUH VSHFLILHG RQ WKH &KDQQHO
&RQILJXUDWLRQ VFUHHQ WKH GHIDXOW LV D FDUULDJH UHWXUQ )RU PRUH
LQIRUPDWLRQ RQ FKDQQHO FRQILJXUDWLRQ VHH \RXU VRIWZDUH XVHU PDQXDO
7KH VHULDO SRUW PXVW EH LQ 8VHU PRGH
Entering Parameters
7R XVH WKH $5/ LQVWUXFWLRQ \RX PXVW SURYLGH WKLV LQIRUPDWLRQ
Parameter:
Definition:
Channel
Control
the address of the control file element used for the control status bits.
Destination
the string element where you want the string stored.
String Length
the number of characters (maximum 82) you want to read from the
buffer. If the processor finds the end-of-line characters before
reading the number of characters you specified, only those
characters read and the end-of-line are moved to the destination.
Characters
Read
the number of characters that the processor moved from the buffer
to the string (0 to 82). This field is display only.
Example:
I:012
[
10
If input word 12, bit 10 is set, read 18 characters
(or until end-of-line) from the buffer and move
them to ST52:72.
ARL
ASCII READ LINE
Channel
Destination
Control
String Length
Characters Read
EN
0
ST52:72
R6:23
18
DN
ER
2QFH WKH UHTXHVWHG QXPEHU RI FKDUDFWHUV RU WKH HQGRIOLQH
FKDUDFWHUV DUH LQ WKH EXIIHU DOO FKDUDFWHUV LQFOXGLQJ WKH HQGRIOLQH
FKDUDFWHUV DUH PRYHG WR WKH GHVWLQDWLRQ VWULQJ 7KH QXPEHU RI
FKDUDFWHUV PRYHG LV VWRUHG LQ WKH SRVLWLRQ ZRUG RI WKH FRQWURO HOHPHQW
DQG WKH GRQH ELW LV VHW
1785-6.1 November 1998
17-13
<RX FDQ XVH WKH 8/ ELW WR WHUPLQDWH DQ $5/ LQVWUXFWLRQ EHIRUH LW
\RX NQRZ WKDW WKH $6&,, GHYLFH FRQQHFWHG WR WKH SRUW LV QRW VHQGLQJ
,I DQ $5/ LQVWUXFWLRQ VWDUWV H[HFXWLQJ ZLWK WKH 8/ ELW DOUHDG\ VHW DQG
WKHUH DUH QR FKDUDFWHUV LQ WKH EXIIHU WKH LQVWUXFWLRQ WHUPLQDWHV ,I DQ
$5/ LQVWUXFWLRQ VWDUWV H[HFXWLQJ ZLWK WKH 8/ ELW DOUHDG\ VHW DQG
WKHUH DUH FKDUDFWHUV LQ WKH EXIIHU WKH LQVWUXFWLRQ SURFHHGV WR
QRUPDO FRPSOHWLRQ
FKDQQHO LV LQ V\VWHP PRGH RU VZLWFKHV WR V\VWHP PRGH WKH
SURFHVVRU VZLWFKHV WR SURJUDPWHVW PRGH RU LI WKH PRGHP LV ORVW
ZKHQ XVLQJ PRGHP FRQWURO
Figure 17.2
Example ARL Timing Diagram
Rung Condition
ON
OFF
Enable Bit (.EN)
ON
OFF
Queue Bit (.EU)
ON
OFF
Done Bit
Error Bit
(.DN or. ER)
ON
OFF
Empty Bit (.EM)
ON
OFF
1 2
3 4 5
1 - rung goes true
5 - rung goes false
1785-6.1 November 1998
17-14
ASCII String Search (ASC)

Description:
ASC
8VH WKH $6& LQVWUXFWLRQ WR VHDUFK DQ H[LVWLQJ VWULQJ VHDUFK VWULQJ

IRU DQ RFFXUUHQFH RI WKH VRXUFH VWULQJ
STRING SEARCH
Entering Parameters
Source
Index
Search
Result
7R XVH WKH $6& LQVWUXFWLRQ \RX PXVW SURYLGH WKLV LQIRUPDWLRQ

Parameter:
Definition:
Search
the string you want to examine.
Source
the string you want to find when examining the search string.
Index
the starting position (from 1 to 82) of the portion of the search string you
want to search. An index of 1 indicates the left-most character.
Result
an integer address where the processor stores the position of the search
string where the source string begins. If no match is found, 0 is stored in
the result.
Example:
ASC
I:012
[
STRING SEARCH
[
10
If input word 12, bit 10 is set, search the string in ST52:80

starring at the 35th character, for the string found in
ST38:40. In this example, the result is stored in N10:0.
Source
Index
Search
Result
ST38:40
35
ST52:80
N10:0
7KH IROORZLQJ FRQGLWLRQV FDXVH WKH SURFHVVRU WR VHW WKH IDXOW

ELW 6
LQYDOLG VWULQJ OHQJWK RU VWULQJ OHQJWK RI ]HUR
LQGH[ YDOXHV RXWVLGH RI UDQJH
LQGH[ YDOXH JUHDWHU WKDQ WKH OHQJWK RI WKH VRXUFH VWULQJ
7KH UHVXOW LV VHW WR ]HUR LQ DQ\ RI WKH DERYH LQVWDQFHV
1785-6.1 November 1998
17-15
ASCII String Compare (ASR)

Description:
8VH WKH $65 LQVWUXFWLRQ WR FRPSDUH WZR $6&,, VWULQJV 7KH V\VWHP
ORRNV IRU D PDWFK LQ OHQJWK DQG XSSHUORZHU FDVH ,I WKH WZR VWULQJV
DUH LGHQWLFDO WKH UXQJ LV WUXH LI WKHUH DUH DQ\ GLIIHUHQFHV WKH UXQJ
LV IDOVH
Example:
ASR
O:013
ASCII STRING COMPARE

Source A
Source B
01
ST37:42
ST38:90
If the string in ST37:42 is identical to the
string in ST38:90, set output bit O:013/01.
$Q LQYDOLG VWULQJ OHQJWK FDXVHV WKH SURFHVVRU WR VHW WKH IDXOW ELW
6 DQG WKH UXQJ LV IDOVH
ASCII Write with Append (AWA)

Description:
AWA
ASCII WRITE APPEND
Channel
Source
Control
String Length
Characters Sent
EN
DN
8VH WKH $:$ LQVWUXFWLRQ WR ZULWH FKDUDFWHUV IURP WKH VRXUFH WR D

GLVSOD\ GHYLFH 7KLV DSSHQG LQVWUXFWLRQ DGGV RU FKDUDFWHUV ZKLFK
\RX FRQILJXUH LQ WKH &KDQQHO &RQILJXUDWLRQ 7KH GHIDXOW LV D FDUULDJH
UHWXUQ DQG OLQH IHHG DSSHQGHG WR WKH HQG RI WKH VWULQJ <RX FDQ XVH
WKLV LQVWUXFWLRQ ZLWK WKH VHULDO SRUW LQ 8VHU RU 6\VWHP PRGH
ER
Entering Parameters
7R XVH WKH $:$ LQVWUXFWLRQ \RX PXVW SURYLGH WKLV LQIRUPDWLRQ
Parameter:
Definition:
Channel
Source
the string you want to write.
Control
the address of the control file element used for the control status bits.
String Length
the maximum number of characters you want to write from the

source string (0 to 82). If you enter 0, the entire string will be written.
Characters Sent
the number of characters that the processor sent to the display area
(0 to 82). Only after the entire string is sent is this field updated
(no running total for each character sent is stored). This field is
display only.
1785-6.1 November 1998
17-16
Example:
AWA
ASCII WRITE APPEND
I:012
[
[
10
If input word 12, bit 10 is set, read 25 characters from

ST37:42 and write it to the display device. Then write
a carriage return and line feed (default).
Channel
Source
Control
String Length
Characters Sent
EN
0
ST37:42
R6:23
25
DN
ER
7ZHQW\ILYH FKDUDFWHUV IURP WKH VWDUW RI VWULQJ 67 DUH VHQW WR WKH
GLVSOD\ GHYLFH DQG WKHQ XVHUFRQILJXUHG DSSHQG FKDUDFWHUV DUH VHQW
7KH GRQH ELW LV VHW DQG D YDOXH RI LV VHQW WR WKH SRVLWLRQ ZRUG
SURFHVVRU WKHQ VHWV WKH (0 ELW WR DFW DV D VHFRQGDU\ GRQH ELW
FRUUHVSRQGLQJ WR WKH SURJUDP VFDQ
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\RX NQRZ WKDW WKH $6&,, GHYLFH FRQQHFWHG WR WKH SRUW FDQQRW DFFHSW
,I DQ $:$ LQVWUXFWLRQ VWDUWV H[HFXWLQJ ZLWK WKH 8/ ELW DOUHDG\ VHW
WKH LQVWUXFWLRQ DERUWV LPPHGLDWHO\
LQVWUXFWLRQ LV DERUWHG GXH WR SURFHVVRU PRGH FKDQJH RU LI WKH PRGHP
EHFRPHV ORVW ZKHQ XVLQJ PRGHP FRQWURO ,I WKH PRGHP ZDV DOUHDG\
ORVW WKH LQVWUXFWLRQ VWLOO H[HFXWHV
1785-6.1 November 1998
17-17
Figure 17.3
Example AWA Timing Diagram
Rung Condition
ON
OFF
Enable Bit (.EN)
ON
OFF
Queue Bit (.EU)
ON
OFF
Done Bit
Error Bit
(.DN or. ER)
ON
OFF
Empty Bit (.EM)
ON
OFF
1 2
3 4 5
1 - rung goes true
5 - rung goes false
ASCII Write (AWT)

Description:
AWT
ASCII WRITE
Channel
Source
Control
String Length
Characters Sent
EN
8VH WKH $:7 LQVWUXFWLRQ WR ZULWH FKDUDFWHUV IURP WKH VRXUFH WR D

GLVSOD\ GHYLFH 7R UHSHDW WKH LQVWUXFWLRQ WKH UXQJ PXVW JR IURP
IDOVH WR WUXH <RX FDQ XVH WKLV LQVWUXFWLRQ ZLWK WKH SRUW LQ 6\VWHP RU
8VHU PRGH
DN
ER
Entering Parameters
7R XVH WKH $:7 LQVWUXFWLRQ \RX PXVW SURYLGH WKLV LQIRUPDWLRQ
Parameters:
Definition:
Channel
Source
the string you want to write.
Control
the address of the control file element used for the control status file.
String Length
the maximum number of characters you want to write from the

source string (0 to 82). If you enter 0, the entire string will be written.
Characters Sent
the number of characters that the processor sent to the display area
(0 to 82). Only after the entire string is sent is this field updated
(no running total for each character sent is stored). This field is
display only.
1785-6.1 November 1998
17-18
Example:
AWT
I:012
[
[
10
If input word 12, bit 10 is set, write 40 characters

from ST37:20 and write it to the display device.
ASCII WRITE
Channel
Source
Control
String Length
Characters Sent
EN
0
ST37:20
R6:23
40
DN
ER
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1785-6.1 November 1998
17-19
Figure 17.4
Example AWT Timing Diagram
Rung Condition
ON
OFF
Enable Bit (.EN)
ON
OFF
Queue Bit (.EU)
ON
OFF
Done Bit
Error Bit
(.DN or. ER)
ON
OFF
Empty Bit (.EM)
ON
OFF
1 2
3 4 5
1 - rung goes true
5 - rung goes false
1785-6.1 November 1998
17-20
1RWHV
1785-6.1 November 1998
Chapter
18
Custom Application Routine

Instructions SDS, DFA
Chapter Objectives
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For Information About:
See:
SDS or DFA CAR utilities
Distributed Diagnostic and Machine Control User Manual
AGA3
PLC-5 AGA Mass Flow Custom Application Routine

Programming Manual
AGA7
PLC-5 Volumetric Flow CARs for Turbine and Displacement

Metering User Manual
NX19
PLC-5 Volumetric Flow CARs for Orifice Metering User

Manual
API
PLC-5 Volumetric Flow CARs for Turbine and Displacement

Metering User Manual

$SSHQGL[ &
1785-6.1 November 1998
18-2
Custom Application Routine Instructions SDS, DFA
Smart Directed Sequencer (SDS)

Overview
SDS
SMART DIRECTED SEQUENCER
Control File
Step Desc. File
Length
No. of Steps
Position/Step:
No. of I/O
Prog file number
EN
ST
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This Type of
Logic Equation:
Does this:
Transitional
provides traditional state-based control. This type of SDS instruction

is built around the state transition concept, where each input
transition directs the instruction to a unique next state using a logical
OR structure. One input change directs the instruction to step A,
another to step B, etc.
Combinatorial
provides for the ANDing of inputs in addition to the OR function used

in transition equations. This allows complex combinations to be
accommodated more easily within the SDS framework with a
minimum number of steps.
Programming the SDS Instruction

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,PSRUWDQW :KHQ \RX HQWHU WKH Control File DQG Step Desc.
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1785-6.1 November 1998
Diagnostic Fault Annunciator (DFA)

Overview
DFA
EN
DIAGNOSTIC FAULT ANNUNCIATOR
Control File
No. of I/O
Program file number
ER
18-3
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Programming the DFA Instruction

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1785-6.1 November 1998
18-4
1RWHV
1785-6.1 November 1998
Appendix
Instruction Timing and

Memory Requirements
Instruction Timing and Memory
Requirements
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3/& SURFHVVRUV DGGUHVVHV ZLWKLQ ILUVW ZRUGV IRU
H[HFXWLRQ WLPHV VKRZQ LQ V
0HPRU\ UHTXLUHPHQWV UHIHU WR WKH QXPEHU RI ZRUGV WKH LQVWUXFWLRQ

XVHV ,Q VRPH FDVHV DQ LQVWUXFWLRQ PD\ KDYH D UDQJH RI PHPRU\
UHTXLUHPHQWV 7KH UDQJH RI ZRUGV H[LVWV EHFDXVH WKH LQVWUXFWLRQ FDQ
XVH GLIIHUHQW W\SHV RI GDWD DQG DGGUHVVLQJ PRGHV
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UHTXLUHPHQWV WKDW DUH VSHFLILF WR HDFK SURFHVVRU
If You Are Using this Processor:
See Page:
Enhanced PLC-5, series C

Bit and Word Instructions
File Instructions
A-2
A-5
Classic PLC-5 (all series):

File Instructions
A-10
A-13
1785-6.1 November 1998
A-2
Instruction Timing and Memory Requirements
Timing for Enhanced PLC-5

Processors

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LQVWUXFWLRQV IRU (QKDQFHG 3/& SURFHVVRUV
Table A.A
Timing and Memory Requirements for Bit and Word Instructions
(Enhanced PLC-5 Processors)
Category
Relay
Code
Execution Time (s)

floating point
True
False
True
Words of
Memory1
False
XIC
examine if closed
.32
.16
12
XIO
examine if open
.32
.16
12
OTL
output latch
.48
.16
12
OTU
output unlatch
.48
.16
12
OTE
output energize
.48
.48
12
branch end
.16
.16
next branch
.16
.16
branch start
.16
.16
TON
timer on (0.01 base)

(1.0 base)
3.8
4.1
2.6
2.5
2-3
TOF
timer off (0.01 base)

(1.0 base)
2.6
2.6
3.2
3.2
2-3
RTO
retentive timer on
(0.01 base)
(1.0 base)
3.8
4.1
2.4
2.3
CTU
count up
3.4
3.4
2-3
CTD
count down
3.3
3.4
2-3
RES
reset
2.2
1.0
2-3
Branch
Timer and Counter
Title
Execution Time
(s) integer
2-3
(Continued)
Use the larger number for addresses beyond 2048 words in the processors data table.
)or every bit address above the first 256 words of memory in the data table, add 0.16 ms and 1 word of memory.
1785-6.1 November 1998
Category
Arithmetic
Code
Title
A-3
Execution Time (s)

integer
Execution Time (s)

floating point
True
False
True
False
Words of
Memory1
ADD
add
6.1
1.4
14.9
1.4
4-7
SUB
subtract
6.2
1.4
15.6
1.4
4-7
MUL
multiply
9.9
1.4
18.2
1.4
4-7
DIV
divides
12.2
1.4
23.4
1.4
4-7
SQR
square root
9.9
1.3
35.6
1.3
3-5
NEG
negate
4.8
1.3
6.0
1.3
3-5
CLR
clear
3.4
1.1
3.9
1.1
2-3
AVE
average file
152+E25.8
30
162+E22.9
36
4-7
STD
standard deviation
321+E84.3
34
329+E77.5
34
4-7
TOD
convert to BCD
7.8
1.3
3-5
FRD
convert from BCD
8.1
1.3
3-5
RAD
radian
57.4
1.4
50.1
1.4
3-5
DEG
degree
55.9
1.4
50.7
1.4
3-5
SIN
sine
414
1.4
3-5
COS
cosine
404
1.4
3-5
TAN
tangent
504
1.4
3-5
ASN
inverse sine
426
1.4
3-5
ACS
inverse cosine
436
1.4
3-5
ATN
inverse tangent
375
1.4
3-5
LN
natural log
409
1.4
403
1.4
3-5
LOG
log
411
1.4
403
1.4
3-5
XPY
X to the power of Y
897
1.5
897
1.5
4-7
SRT
sort file
(5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
276 + 12[E**1.34] 227

224 + 25[E**1.34] 189
3-5
278 + 16[E**1.35] 227
230 + 33[E**1.35] 189
(Continued)
1.Use the larger number for addresses beyond 2048 words in the processors data table.
E = number of elements acted on per scan
SRT true is only an approximation. Actual time depends on the randomness of the numbers.
1785-6.1 November 1998
A-4
Category
Logic
Code
Title
Execution Time (s)

integer
Execution Time (s)

floating point
True
False
True
Words of
Memory1
False
AND
and
5.9
1.4
4-7
OR
or
5.9
1.4
4-7
XOR
exclusive or
5.9
1.4
4-7
NOT
not
4.6
1.3
3-5
MOV
move
4.5
1.3
MVM
masked move
6.2
1.4
4-7
BTD
bit distributor
10.0
1.7
6-9
EQU
equal
3.8
1.0
4.6
1.0
3-5
NEQ
not equal
3.8
1.0
4.5
1.0
3-5
LES
less than
4.0
1.0
5.1
1.0
3-5
LEQ
less than or equal
4.0
1.0
5.1
1.0
3-5
GRT
greater than
4.0
1.0
5.1
1.0
3-5
GEQ
greater than or
equal
4.0
1.0
5.1
1.0
3-5
LIM
limit test
6.1
1.1
8.4
1.1
4-7
MEQ
mask compare
if equal
5.1
1.1
Compare
CMP
all
2.48 + ([0.8 + i]) 2.16 + Wi[0.56]
2.48 + ([0.8 + i]) 2.16 + Wi[0.56]
2+Wi
Compute
CPT
all
2.48.+ ([0.8 + i]) 2.16 + Wi[0.56]
2.48.+ ([0.8 + i]) 2.16 + Wi[0.56]
2+Wi
Move
Comparison
5.6
1.3
4-7
i = execution time of each instruction (operation, e.g. ADD, SUB, etc.) used within the CMP or the CPT expression
Wi = number of words of memory used by the instruction (operation, e.g. ADD, SUB, etc) within the CMP or CPT expression
CMP or CPT instructions are calculated with short direct addressing
1785-6.1 November 1998
3-5
A-5
File Instructions
5HIHU WR 7DEOH $% IRU WKH LQVWUXFWLRQ WLPLQJ IRU ILOH LQVWUXFWLRQV
Table A.B
Timing and Memory Requirements for File, Program Control, and ASCII
Instructions (Enhanced PLC-5 Processors)
Category
Code
Title
Time (s)
integer
True
False
Time (s)
floating point
True
Words of
Memory1
False
File
Arithmetic
and Logic
FAL
all
11 + ([2.3 + i])E
6.16 + Wi[0.16]
11 + ([2.3 + i])E
6.16 + Wi[0.16]
3-5 +Wi
File Search
and
Compare
FSC
all
11 + ([2.3 + i])E
6.16 + Wi[0.16]
11 + ([2.3 + i])E
6.16 + Wi[0.16]
3-5 +Wi
File
COP
copy
16.2+E[0.72]
1.4
17.8+E[1.44]
1.4
4-6
counter, timer, and

control
15.7+E[2.16]
1.4
fill
15.7+E[0.64]
1.5
18.1+E[0.80]
1.5
4-6
counter, timer, and

control
15.1+E[1.60]
1.5
BSL
bit shift left
10.6+B[0.025]
5.2
4-7
BSR
bit shift right
11.1 + B[0.025]
5.2
4-7
FFL
FIFO load
8.9
3.8
4-7
FFU
FIFO unload
10.0+E[0.43]
3.8
4-7
LFL
LIFO load
9.1
3.7
4-7
LFU
LIFO unload
10.6
3.8
4-7
FBC
0 mismatch
15.4 + B[0.055]
2.9
6-11
1 mismatch
22.4 + B[0.055]
2.9
2 mismatches
29.9+ B[0.055]
2.9
0 mismatch
15.4 + B[0.055]
2.9
1 mismatch
24.5 + B[0.055]
2.9
2 mismatches
34.2 + B[0.055]
2.9
data transitional
5.3
5.3
FLL
Shift
Register
Diagnostic
DDT
DTR
6-11
4-7
(Continued)
i = execution time of each instruction (operation, e.g. ADD, SUB, etc.) used within the FAL or the FSC expression
E = number of elements acted on per scan
B = number of bits acted on per scan
Wi = number of words of memory used by the instruction (operation, e.g. ADD, SUB, etc.) within the FAL or FSC expression
FAL or FSC instructions are calculated with short direct addressing
1785-6.1 November 1998
A-6
Category
Sequencer
Immediate
I/O2
Code
Title
Time (s)
integer
True
False
Time (s)
floating point
True
False
Words of
Memory1
SQI
sequencer input
7.9
1.3
5-9
SQL
sequencer load
7.9
3.5
4-7
SQO
sequencer output
9.7
3.7
5-9
IIN
immediate input
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
1.1
357
307
immediate output
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
1.1
361
301
1.1
4-7
1.1
4-7
IOT
IDI
IDO
immediate data input

(-5/20C)
(-5/40C, -5/60C, and
-5/80C)
200 + 1.4 (for

each word)
200 + 1.4 (for
each word)
immediate data output

(-5/20C)
(-5/40C, -5/60C, and

-5/80C)
230 + 1.4 (for

each word)
250 + 1.7 (for
each word)
Zone
Control
MCR
master control
0.16
0.16
Program
Control
JMP
jump
8.9 + (file number

2) 0.96
1.4 + (file number

2) 0.96
LBL
label
0.32
0.32
2+position
in label table
JSR3/
RET
jump to subroutine/
return
PLC-5/11, -5/20,
-5/30, -5/40, -5/40L,
-5/60, -5/60L, -5/20E,
-5/40E
0 parameters
1 parameter
increase/parameter
PLC-5/80
0 parameters
1 parameter
increase/parameter
3+
parameters/
JSR
1+
parameters/
RET
12.3
16.1
3.8
1.0
1.0
n/a
n/a
17.3
5.0
n/a
1.0
n/a
315
340
31
1.0
1.0
n/a
349
33
1.0
(Continued)
2.Timing for immediate I/O instructions is the time for the instruction to queue-up for processing
3.Calculate execution times as follows: (time) + (quantity of additional parameters)(time/parameter). For example, if you are passing 3 integer parameters in a JSR
within a PLC-5/11 processor, the execution time =16.1 + (2)(3.8)=23.7s.
B = number of bits acted on per scan
1785-6.1 November 1998
Category
Program
Control
Code
SBR
Title
A-7
Time (s)
integer
True
False
Time (s)
floating point
True
False
Words of
Memory1
0 parameters
12.3
1.0
1 parameter
16.1
1.0
increase/
parameter
3.8
END
end
negligible
TND
temporary end
EOT
end of transition
AFI
always false
0.16
0.16
ONS
one shot
3.0
3.0
2-3
OSR
one shot rising
6.2
6.0
4-6
OSF
one shot falling
6.2
5.8
4-6
FOR/
NXT
for next loop

(PLC-5/80)
8.1+ L[15.9]
(151+L[277])
5.3 + N[0.75]
(152+N[6.1])
FOR 5-9
NXT 2
BRK
break
11.3 + N[0.75]
0.9
UID
user interrupt disable

(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
1.0
175
119
user interrupt enable

(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
1.0
170
100
UIE
1+
parameters
17.3
1.0
5.0
1
(Continued)
L = number of FOR/NXT loops
N = number of words in memory between FOR/NXT or BRK/NXT
1785-6.1 November 1998
A-8
Category
Process
Control
Code
PID
Gains
Time (s)
integer
True
Cascade
ABL2
ACB 2
ACI
False
Time (s)
floating point
True
False
PID loop control

3.0
882
ISA
(-5/11, -5/20, -5/20E, 560
-5/20C)
(-5/30, -5/40, -5/40E, 895
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
1142
Manual
(-5/11, -5/20, -5/20E, 372
-5/20C)
(-5/30, -5/40, -5/40E, 420
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
900
Set Output
(-5/11, -5/20, -5/20E, 380
-5/20C)
(-5/30, -5/40, -5/40E, 440
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
882
Slave
1286
Master
840
test buffer for line

(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
no. of characters in
buffer
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
string to integer
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
Words of
Memory1
5-9
Independent
(-5/11, -5/20, -5/20E, 462
-5/20C)
(-5/30, -5/40, -5/40E, 655
-5/40C, -5/40L, -5/60,
-5/60C, -5/60L, -5/80,
-5/80E, -5/80C)
Modes
ASCII2
Title
58
3-5
316
388
214
150
3-5
316
389
214
150
1.4
3-5
220 + C[11]
140 + C[21.4]
(Continued)
2.Timing for ASCII instructions is the time for the instruction to queue-up for processing in channel 0.
1785-6.1 November 1998
Category
ASCII2
Code
ACN
AEX
AHL2
AIC
ARD2
ARL2
ASC
ASR
AWA2
AWT2
Title
A-9
Time (s)
integer
True
False
Time (s)
floating point
True
False
Words of
Memory1
1.9
4-7
1.9
5-9
string concatenate
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
237 + C[2.6]
179 + C[5.5]
string extract
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
226 + C[1.1]
159 + C[2.2]
set or reset lines

(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
318
526
integer to string
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
260
270
read characters
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
315
380
214
149
read line
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
316
388
214
151
string search
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
222 + C[1.7]
151 + C[3.0]
string compare
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
234 + C[1.3]
169 + C[2.4]
202
119
write with append

(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
319
345
215
154
write
(-5/11, -5/20)
(-5/30, -5/40, -5/60,
-5/80)
318
344
215
151
5-9
213
157
1.4
3-5
4-7
4-7
1.9
5-9
3-5
4-7
4-7
2.Timing for ASCII instructions is the time for the instruction to queue-up for processing in channel 0.
C = number of ASCII characters
1785-6.1 November 1998
A-10
Timing for Classic PLC-5

Processors

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Table A.C
Timing and Memory Requirements for Bit and Word Instructions
(Classic PLC-5 Processors)
Category
Relay
Code
1
2
Execution Time (s)

floating point
True
False
True
Words of Memory1
False
XIC
examine if closed
1.3
0.8
12
XIO
examine if open
1.3
0.8
12
OTL
output latch
1.6
0.8
12
OTU
output unlatch
1.6
0.8
11
OTE
output energize
1.6
1.6
12
branch end
0.8
0.8
next branch
0.8
0.8
branch start
0.8
0.8
TON
timer on
(0.01 base)
(1.0 base)
39
44
27
28
2-3
TOF
timer off
(0.01 base)
(1.0 base)
30
30
43
51
2-3
RTO
retentive timer on
(0.01 base)
(1.0 base)
39
44
24
24
CTU
count up
32
34
2-3
CTD
count down
34
34
2-3
RES
reset
30
14
2-3
Branch
Timer and Counter
Title
Execution Time (s)

integer
2-3
Use the smaller number if all addresses are below word 4096; use the larger number if all addresses are above 4096.
For every bit address above the first 256 words of memory in the data table, add 0.8 s to the execution time and 1 word of memory to the requirements.
(Continued)
1785-6.1 November 1998
Category
Arithmetic
Logic
Move
Comparison
Code
Title
A-11
Execution Time (s)

integer
Execution Time (s)

floating point
True
False
True
False
Words of Memory1
ADD
add
36
14
92
14
4-7
SUB
subtract
36
14
92
14
4-7
MUL
multiply
41
14
98
14
4-7
DIV
divide
49
14
172
14
4-7
SQR
square root
82
14
212
14
3-5
NEG
negate
28
14
36
14
3-5
CLE
clear
18
14
23
14
2-3
TOD
convert to BCD
52
14
3-5
FRD
convert from BCD
44
14
3-5
AND
and
36
14
4-7
OR
or
36
14
4-7
XOR
exclusive or
36
14
4-7
NOT
not
27
14
3-5
MOV
move
26
14
MVM
masked move
55
14
EQU
equal
32
14
42
14
3-5
NEQ
not equal
32
14
42
14
3-5
LES
less than
32
14
42
14
3-5
LEQ
less than or equal
32
14
42
14
3-5
GRT
greater than
32
14
42
14
3-5
GEQ
greater than or equal
32
14
42
14
3-5
LIM
limit test
42
14
60
14
4-7
MEQ
mask compare if equal
41
14
35
14
3-5
6-9
4-7
(Continued)
1785-6.1 November 1998
A-12
Category
Compute
Compare
Code
CPT
CMP
Execution Time (s)

integer
Execution Time (s)

floating point
True
False
True
False
add
67
34
124
34
6-9
subtract
67
34
124
34
6-9
multiply
73
34
130
34
6-9
divide
80
34
204
34
6-9
square root
113
33
244
34
5-7
negate
59
33
68
34
5-7
clear
49
30
55
34
4-5
move
58
33
5-7
convert to BCD
84
33
5-7
convert from BCD
75
33
5-7
AND
68
34
6-9
OR
68
34
6-9
XOR
68
34
6-9
NOT
59
34
5-7
equal
63
34
73
34
5-7
not equal
63
34
73
34
5-7
less than
63
34
73
34
5-7
less than or equal
63
34
73
34
5-7
greater than
63
34
73
34
5-7
greater than or equal
63
34
73
34
5-7
Title
1785-6.1 November 1998
Words of Memory1
A-13
File Instructions
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Table A.D
Timing and Memory Requirements for File Instructions
Category
File Arithmetic and Logic
Code
FAL
Time (s)
integer
Time (s)
floating point
Time (s)
integer or
floating point
True
True
False
add
98 + W[36.7 + N]
98 + W[95.1 + N]
54
7-12
subtract
98 + W[36.7 + N]
98 + W[95.1 + N]
54
7-12
multiply
98 + W[42.5 + N]
98 + W[101.2 + N]
54
7-12
divide
98 + W[51.1 + N]
98 + W[180.3 + N]
54
7-12
square root
98 + W[84.7 + N]
98 + W[220.5 + N]
54
6-10
negate
98 + W[29.2 + N]
98 + W[37.2 + N]
54
6-10
clear
98 + W[18.4 + N]
98 + W[24.0 + N]
54
5-8
move
98 + W[27.3 + N]
98 + W[36.2 + N]
54
6-10
convert to BCD
98 + W[54.3 + N]
54
6-10
convert from BCD
98 + W[45.4 + N]
54
6-10
Title
Words of
Memory1
1
W = number of elements acted on per scan
N = 2 (number of integer file addresses) + 8 (number of floating-point file addresses) + 6 (number of timer, counter, or control file addresses) + (
number of
conversions between integer and floating point formats)
(Continued)
1785-6.1 November 1998
A-14
Category
Code
File Arithmetic and Logic
Title
Time (s)
integer
Time (s)
floating point
Time (s)
integer or
floating point
True
True
False
Words of
Memory1
AND
98 + W[37.2 + N]
54
7-12
OR
98 + W[37.2 + N]
54
7-12
XOR
98 + W[37.2 + N]
54
7-12
NOT
98 + W[28.2 + N]
54
6-10
File Search and Compare
FSC
all comparisons
93 + W[32.7 +N]
93 + W[43.3 +N]
54
6-10
File
COP
copy
88 + 2.7W
104 + 3.8W
20
4-7
counter, timer, and

control
98 + 5.8W
fill
81 + 2/.1 W
100 + 3.1W
15
4-7
counter, timer, and

control
97 + 4.4W
BSL
bit shift left
74 + 3.4W
57
4-7
BSR
bit shift right
78 + 3.0W
57
4-7
FFL
FIFO load
54
44
4-7
FFU
FIFO unload
68 + 3.2W
46
4-7
FBC
file bit compare
FLL
Shift Register
Diagnostic
DDT
6-11
0 mismatch
75 + 6W
31
1 mismatch
130 + 6W
31
2 mismatches
151 + 6W
31
diagnostic detect
6-11
0 mismatch
71 + 6W
31
1 mismatch
150 + 6W
31
2 mismatches
161 + 6W
1
W = number of elements acted on per scan
N = 2 (number of integer file addresses) + 8 (number of floating-point file addresses) + 6 (number of timer, counter, or control file addresses) + (
number of
conversions between integer and floating point formats)
(Continued)
1785-6.1 November 1998
Category
Code
Title
Zone Control
MCR
master control
Immediate I/O
IIN
immediate input
IOT
Sequencer
Jump and Subroutine
Time (s)
integer
Time (s)
floating point
Time (s)
integer or
floating point
True
True
False
12
18
Words of
Memory1
1
2-3
local
196
16
remote
204
16
immediate output
2-3
local
202
16
remote
166
16
SQI
sequencer input
57
14
5-9
SQL
sequencer load
55
42
4-7
SQO
sequencer output
77
42
5-9
JMP
jump
45
15
2-3
JSR
jump to subroutine
SBR
0 parameters
56
15
2-3
1 parameter
91
15
3-5
add per parameter
21
RET
LBL
1
A-15
return from sub.

0 parameters
48
13
1 parameter
70
13
2-3
add per parameter
21
label
12
12
(Continued)
1785-6.1 November 1998
A-16
Category
Code
Miscellaneous
1Use
Title
Time (s)
integer
Time (s)
floating point
Time (s)
integer or
floating point
True
True
False
END
end
negligible
negligible
TND
temporary end
negligible
15
AFI
always false
15
13
ONS
one shot
28
30
2-3
DTR
data transitional
41
41
4-7
BTD
bit distributor
77
14
6-11
PID
PID loop control
608
34
5-9
BTR
block transfer read
BTW
block transfer write
MSG
message
See chapter 15
See chapter 16
the smaller number if all addresses are below word 4096; use the larger number if all addresses are above 4096.
1785-6.1 November 1998
Words of
Memory1
A-17
Program Constants
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Direct and Indirect Elements

Enhanced PLC-5 Processors
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Table A.E
Additional Execution Time (Enhanced PLC-5 Processors)
Addressing Mode
Data Type
Modifier in sec
(add for each
operand)
Direct
Integer
Float
0
0
Index
Integer
Float
Counter-Timer-Control
1.1
1.8
2.4
Immediate
Integer
Float
0.24
1.0
Indirect
6.6 + W[0.09]
Float-to-integer
5.6
Integer-to-float
8.4
1785-6.1 November 1998
A-18
Direct and Indirect Elements

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Table A.F
Additional Execution Time Based on Source and Destination Addresses
Source
(integer to floating point)
Destination
(floating point to integer)
0-2K
2-4K
4K+
0-2K
2-4K
4K+
integer
floating point
data conversion
10
33
34
35
Data Type
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V
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FRQWURO W\SH
,I WKH ILOH DGGUHVV FRQWDLQV WZR LQGLUHFW DGGUHVVHV DGG RQO\ RQH YDOXH
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1785-6.1 November 1998
A-19
0XOWLSO\ WKH DGGLWLRQDO WLPH E\ WKH QXPEHU RI HOHPHQWV LQ WKH ILOH IRU
DQ\ W\SH RI ILOH RU ILOH DGGUHVV )RU H[DPSOH
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DGG IRU FRQYHUWLQJ WR IORDWLQJ SRLQW
DGG IRU LQGLUHFW DGGUHVV
'HVWLQDWLRQ 1
DGG IRU FRQYHUWLQJ WR LQWHJHU
)$/ PXOWLSO\ :> 1 LQGLUHFW DGGUHVVLQJ@
1
:
([HFXWLRQ WLPH LQ $// PRGH
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V
Indirect Bit or Elements Addresses

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Table A.G
Additional Execution Times for Indirectly Addressed Bits and Elements
Data Type
Time (s) for

Variable File or
Element
Time (s) for

Variable File and
Element
Bit in binary file
57
60
Bit in integer file
60
63
Bit in timer, counter, or control file
64
66
Integer (N)
42
42
Timer (T), counter (C), or control

(R) file
43
44
Floating point (F)
61
64
Converting integer to floating point
71
77
Converting timer, counter, or control

to floating point
85
81
1785-6.1 November 1998
A-20
Additional Timing Considerations

1785-6.1 November 1998
7DEOH $+ OLVWV DGGLWLRQDO WLPLQJ FRQVLGHUDWLRQV

Table A.H
Additional Timing Considerations (Classic PLC-5 Processors)
Tasks
Time (milliseconds)
Housekeeping
4.5 max
Resident Local I/O scan
1 per assigned rack number
Remote I/O scan
10 per assigned rack number at 57.6 Kb
Appendix
SFC Reference
Appendix Objectives
SFC Status Information in the

Processor Status File
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Table B.A
SFC Status Words
Word:
Title:
Description:
S:1/15
First pass
Set:
Reset:
S:8
Current program
scan time
Processor began first program scan of

the next active step in the SFC
Processor completed scanning the
currently active step
The time for the processor to scan through all active

steps one time
If you are using multiple main control programs on
a Enhanced PLC-5 processor, this time is the
current total of one scan of all main control
programs.
S:9
Maximum program
scan time
The maximum time for the processor to scan

through all active steps one time (word S:8)
an Enhanced PLC-5 processor, this time is the
maximum of all previous totals. This value is
maintained until user resets it.
S:11/3
SFC fault
Set:
Reset:
S:11/5
Start up fault
Set:
Reset:
Processor detected an SFC fault and

stored a fault code in word 12
No SFC fault
Processor detected a start-up protection
fault (see word 26 bit 1)
No fault, start up allowed
(Continued)
1785-6.1 November 1998
B-2
SFC Reference
Word:
Title:
Description:
S:12
Fault codes
74
75
77
78
79
Fault in SFC file

SFC has more than 24 active steps
Missing file or file of wrong type for step,
action or transition
SFC execution cannot continue after
interruption
Cannot run SFC because PLC-5 is
incompatible
S:13
Faulted File
Number
Contains the file number if an SFC fault occurred
S:14
Faulted Rung
Number
Contains the faulted rung number
S:26/0 *
Restart/continue
Set:
Reset:
S:26/1 *
Start-up protection
after power loss
Set:
Reset:
S:28 *
Program
watchdog setpoint
Processor restarts SFC at the active

steps where it left off due to power loss
or processor mode change
Processor restarts SFC at first step
Protection enabled; processor goes to
fault routine at power up and processor
sets word 11, bit 5
Protection disabled; processor powers
up in run mode
Maximum time (milliseconds) for scanning a single

pass through all active steps
an Enhanced PLC-5 processor this time is the total
of one scan of all main control programs.
S:79 *
(except
for scan
time)
S:127
MCP inhibit, file

number and scan
time
Information on the individual multiple main control

programs.
Enhanced PLC-5 processors only.
* You enter values for these words/bits
1785-6.1 November 1998
SFC Reference
B-3
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Memory Allocation
Table B.B
SFC Memory Usage
Uses this Amount of Memory:
This Structure:
Classic PLC-5 Processor
Enhanced PLC-5 Processor
start and end of program
2 words
19 words
each step /transition pair
8 words
16 + 6a words
a = number of actions in step
6 words
each action
each selection branch
5n + 5 words
n = number of
branches
11 + 6a + 7n
a = number of actions in step
n = number of paths
each simultaneous
branch, diverging
n + 1 word
n = number of
branches
3n + 1
each simultaneous
branch, converging
n2 + 6n + 3 words
n = number of
branches
5 + 11n + 6a
a = number of actions in all
converging
steps for that simultaneous
branch
n = number of paths
each label or
GOTO statement
1 word
1 word
each chart compression
3 words
3 words
n = number of paths
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1785-6.1 November 1998
B-4
SFC Reference
Figure B.1
Sample SFC and Memory Requirements
1785-6.1 November 1998
Enhanced PLC-5 Processors
step/transition pair
8 words
one action/step
a=1
16 + 6a=22 words
simultaneous diverge
n=2
n +1 = 3 words
simultaneous diverge
n=2
3n +1 = 7 words
selection branch
n=3
5n + 5 = 20
selection branch
n=3 a=1
11 + 6a + 7n = 38 words
3 step/transition pairs
3 x 8 = 24 words
3 step/transition pairs a =1
3 (16 + 6a) = 66 words
simultaneous converge
n=2
n2 + 6n + 3 = 19 words
simultaneous converge
n=2 a=2
5 + 11n + 6a = 39 words
step/transition
8 words
one action/step a = 1
16 + 6a = 22 words
82 words (sub total)

+ 2 words (start and end of program)
194 words (sub total)

+ 18 words (start and end of program)
(8 actions * 6 words assumes
1 unique action per step)
84 words total for SFC
260 words total for SFC
SFC Reference
Dynamic Constraints Classic

PLC-5 Processors Only
B-5
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1785-6.1 November 1998
B-6
SFC Reference
Figure B.2
Dynamic Limit of Active Steps Could Be Exceeded
1785-6.1 November 1998
SFC Reference
Scanning Sequences
B-7
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Step and Transition Scanning

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Figure B.3
Scan Sequence for a Step, Transition, and Postscan
A
A
pA postcan of step A
X0
I/O I/O scan

hk housekeeping
Xn transition scan
F false
T true
X1
F
A
I/O
hk
X0
T
scan of step A
hk
pA
I/O
hk
hk
X1
pB
15556
1785-6.1 November 1998
B-8
SFC Reference
Selected Branch Scanning

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Figure B.4
Selected Branch Divergence
//
X0
X1
X2
X7
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1785-6.1 November 1998
SFC Reference
B-9
Figure B.5
Scan Sequence for a Selected Branch - Divergence and Convergence
A
scan of step A
X0
I/O I/O scan

hk housekeeping
X1
oh overhead
X2
Xn transition scan
F false
T true
n transition number
X3
Classic PLC-5 Processors: maximum of 7 selections

Enhanced PLC-5 Processors: maximum of 16 selections
F
F
hk
oh X1
hk
I/O
pA
I/O
hk
hk
X3
pC
X0
hk
pA
I/O
hk
hk
X2
pB
15557
Simultaneous Branch Scanning

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Figure B.6
Simultaneous Branch Divergence
//
B
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1785-6.1 November 1998
B-10
SFC Reference
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Figure B.7
Simultaneous Branch - Convergence
//
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VKRZV WKH VFDQ VHTXHQFH IRU WKH GLYHUJHQFH DQG FRQYHUJHQFH RI D
VHOHFWHG EUDQFK
Figure B.8
Scan Sequence for a Simultaneous Branch Divergence and
Convergence
A
A
X0
scan of step A
I/O I/O scan
hk housekeeping**
Xn transition scan
F false
T true
X1
Classic Processors: maximum of 7 selections
oc convergence overhead
od divergence overhead
Enhanced PLC-5 Processors: maximum of 16 selections
hk
X1
F
F
I/O
hk
T hk
pB
oc
pC
X1
A I/O
X0
T
hk
pA
od
I/O
hk
I/O
T
X1
T
hk
pB
oc
hk
pB
oc
pC
pC
15558
In an Enhanced PLC-5 Processors, these states do not occur if scan

configuration is set to ADVANCED mode.
** Any subcharts tied to this MCP execute now, followed by execution

of subsequent MCPs. If this chart is MCP B and has active subchart
actions while MCP A and C have ladder programs the sequence is:
MCP A, Chart in MCP B, MCP B's subcharts, MCP C
1785-6.1 November 1998
SFC Reference
B-11
SFC Example and Scan Sequence

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VHTXHQFH DV D JXLGH 7KHVH ILJXUHV PD\ QRW DSSO\ WR \RXU V\VWHP
Figure B.9
Example SFC for Scan Sequence Example
start
A
X1
X0
B
C
X3
X2
D
X4
X5
F
E
X6
H
J
X7
X9
I
X8
K
X10
end
1785-6.1 November 1998
B-12
SFC Reference
Figure B.10
Scan Sequence Example for the Example SFC
F hk
F oh
X2
F hk
T h k p A D I /O
F hk
X5
T h k p D J I /O
F oh
X1
X9
T hk pJ
F hk
T hk p A C I/O
F hk
X4
T hk p C
A I /O
K I/O
X 10
T hk pK
X0
F hk
F hk
T h k p A B I/O
X3
T hk pB E
F G I /O
F
F o d G I /O h k E I /O F I /O
od F
X6
T
F h k E I/O
*
X6
A =
pA =
I/O =
XN =
oh
oc
od
hk
step scan (A - K)
post scan (A - K)
I/O scan
transition (1 - 10)
T=true
F=false
= overhead
= convergence overhead
= divergence overhead
= housekeeping
Run Times Classic PLC-5

Processors
1785-6.1 November 1998
T o d G I /O h k E I /O p F H I /O G I /O
H I /O
X7
X7
T
X7
T
X7
F
T hk pE oc pH oc pG
I I /O
hk
X8
T hk pI
* In an Enhanced PLC-5 Processor, these states do not occur if

scan configuration is set to ADVANCED mode.
15303
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SFC Reference
B-13
Using Sequence Diagrams to Determine Run Time

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IRU \RXU 6)&
Table B.C
Run Times for Sequence Diagram Sections Classic PLC-5 Processors
This Event:
Takes this Amount of Time

(in milliseconds):
time to execute logic of step A + 0.1 ms
pA
time to scan logic of step A with rungs false + 0.1 ms
XN
transition N false (F): time to scan logic + 0.1 ms

transition N true (T): time to scan logic + .25 ms
I/O (I/O scan)
0.6 ms
hk (housekeeping)
0.7 ms (increases with increasing DH+ traffic)
oh (overhead)
0.02 ms
od (divergence overhead)
0.3 ms
oc (convergence overhead)
0.2 ms
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1785-6.1 November 1998
B-14
SFC Reference
Figure B.11
Minimum Scan Time for a Step and Transition Pair
A
X0
B
X1
1.6 ms
F
A
I/O
1.6 ms
hk
X0
F
hk
pA
I/O
X1
T
1.9 ms
hk
hk
pB
1.9 ms
14271
Using Equations to Determine Run Time

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Tmilliseconds = 0.8a + 0.7 + Tscan
Table B.D
Variables for Steady-State Scan Time
Where:
Is:
Tmilliseconds
steady-state scan time in milliseconds
number of active steps
Tscan
total time to scan logic in all active steps and associated false transitions
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1785-6.1 November 1998
SFC Reference
B-15
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A
//
X0
X1
B
X2
C
Xn
D
Tmilliseconds = TX + pA + TS + 0.02(n1) + 1.55 + 0.8a + T0

Table B.E
Variables for Selected-Path Divergent Scan Time
Where:
Is:
Tmilliseconds
transition scan time in milliseconds from step A to the first step in

selected path N
TX
sum of scan times of logic of transitions X0, X1, . . . , Xn in the

divergence, up to and including the selected transition
pA
postscan time for the step (step A) preceding the divergence
TS
scan time for logic in the new step (step N)
path number selected (1-7, from left to right)
number of active steps outside the divergence
T0
sum of scan times of logic in all other active steps and transitions
parallel to the divergence, but outside of the divergence
1785-6.1 November 1998
B-16
SFC Reference
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A
X0
//
B
Tmilliseconds = TX0 + pA + TS + 0.3(n1) + 1.97 + 0.8a + T0

Table B.F
Variables for Simultaneous-Path Divergent Scan Time
Where:
Is:
Tmilliseconds
transition time in milliseconds from when transition X0 goes true

until the processor finishes scanning the last simultaneous step
(step N) in the divergence
TX0
scan time of logic in transition X0
pA
time to do a post-scan of step A
TS
sum of scan times of logic in new steps (step B, step C, . . . , step N)
number of simultaneous active steps in the divergence
number of parallel active steps outside the divergence
T0
parallel to the divergence, but outside of the divergence
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1785-6.1 November 1998
SFC Reference
B-17
&RQYHUJHQW 6FDQ 7LPH LV ZKHQ D VLPXOWDQHRXV EUDQFK HQGV 7KH

EHVW FDVH LV ZKHQ WKH WUDQVLWLRQ JRHV WUXH MXVW EHIRUH WKH ,2 VFDQ 8VH
WKLV HTXDWLRQ 7DEOH %*
F
N
//
X1
Z
Tmilliseconds = TX1 + Tp + TZ + 0.2(n1) + 1.5 + 0.8a + T0

Table B.G
Variables for Simultaneous-Path Convergent Scan Time
Where:
Is:
Tmilliseconds
transition time in milliseconds from when transition X1 goes true

until the processor finishes scanning step Z
TX1
scan time of logic in transition X1
Tp
sum of postscan times of steps F, G, . . . , N
TZ
scan time of logic in step Z
number of simultaneous active steps in the convergence
number of parallel active steps outside of the convergence
T0
parallel to the convergence, but outside of the convergence
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1785-6.1 November 1998
B-18
1RWHV
1785-6.1 November 1998
SFC Reference
Appendix
Valid Data Types for

Instruction Operands
Appendix Objectives
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7KH IROORZLQJ WDEOH H[SODLQV HDFK YDOLG GDWD W\SHYDOXH
This Data
Type/Value:
Instruction Operands and Valid

Data Types
Accepts:
immediate
(program constant)
any value between 32,768 and 32,767
integer
any integer data type: integer, timer, counter, status, bit, input,
output, ASCII, BCD, control (e.g., N7:0, C4:0, etc.)
float
any floating point data type with 7-digit precision (valid range is
1.1754944e38 to 3.4028237e+38).
block transfer
any block transfer data type (e.g., BT14:0)
ControlNet transfer
any CT data type (e.g., CT14:0)
message
any message data type (e.g., MG15:0)
PID
any PID data type (e.g., PD16:0) or integer data type

(e.g., N7:0)
string
any string data type (e.g., ST12:0)
SFC status
any SFC status data type (e.g., SC17:0)
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1785-6.1 November 1998
C-2
Valid Data Types for Instruction Operands
Table C.A
Programming Instructions and Operands
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
ABL *
ASCII Test Buffer for Line
channel
immediate, 0-4 integer
yes
control
control
channel
immediate, integer
control
control
source
string
destination
integer
source A
string
source B
string
destination
string
source
immediate, float (in radians),

integer
destination
float (in radians), integer
action number
immediate
file number
0 - 999
destination
string
source A
immediate, integer, float
source B
destination
integer, float
source
string
index
number
destination
string
ACB *
ACI *
ACN *
ACS *
ACT *
ADD
AEX *
ASCII Number of Characters

in Buffer
ASCII String to Integer
ASCII String Concatenate
Arc Cosine
SFC action
(only for ASCII import/export)
ADD
String Extract
yes
no
no
no
N/A
no
no
AFI
Always False
none
AHL *
ASCII Set/Reset
Handshake Lines
channel
yes
handshake AND mask
immediate, Hex integer
yes
handshake OR mask
control
control
source
immediate, integer
destination
string
AIC *
1785-6.1 November 1998
ASCII Integer to String
no
no
C-3
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
AND
Logical AND
source A
integer
no
source B
integer
destination
integer
channel
destination
string
control
control
string length
0 - 82
channel
destination
string
control
control
string length
0 - 82
source
string
index
search
string
result
integer
source
immediate, float (in radians)
destination
float (in radians)
source A
string
source B
string
source
destination
float (in radians)
file
integer, float
destination
integer, float
control
control
length
1 - 1000
position
0 - 999
channel
source
string
control
control
string length
0 - 82
ARD *
ARL *
ASC *
ASN *
ASR *
ATN *
AVE *
AWA *
ASCII Read Characters
ASCII Read Line
ASCII String Search
Arc Sine
ASCII String Compare
Arc Tangent
Average File
ASCII Write with Append
yes
yes
no
no
no
no
yes
yes
1785-6.1 November 1998
C-4
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
AWT *
ASCII Write
channel
immediate, integer
yes
source
string
control
control
length
0 - 82
BRK
Break
none
BSL
Bit Shift Left
file
binary
control
control
bit address
bit
length
1 - 16000 (length in bits)
file
binary
control
control
bit address
bit
length
source
immediate, integer
source bit
immediate, (0 - 15) integer
destination
integer
destination bit
immediate (0 - 15)
length
immediate (1 - 16)
BSR
BTD
1785-6.1 November 1998
Bit Shift Right
Bit Distribute
yes
no
yes
yes
no
C-5
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
BTR1
Block Transfer Read
rack
00-277 octal
yes
group
0-7
module
0-1
control block
block, integer
data file
integer
length
0, 1-64
continuous
YES, NO
rack
00-277 octal
group
0-7
module
0-1
control block
block, integer
data file
integer
length
0, 1-64
continuous
YES, NO
BTW
Block Transfer Write
yes
CIO
ControlNet I/O Transfer
control block
ControlNet transfer (1 - 64)
yes
CIR
Custom Input Routine
program file number
immediate (2 - 999) for all

processors
N/A
input parameter list
return parameter list
integer, float
(for use with CAR

applications only)
CLR
Clear
destination
integer, float
no
CMP
Compare
expression, relative
expression, expression
expression using values or

addresses with evaluators (for
a list, see chapter 3 in
this manual)
no
EXE mnemonic
(end of expression)
EXE
only for ASCII import

COP
File Copy
source
array
destination
array
length
immediate (1 - 1000)
no
1 In non-continuous mode, BTR and BTW ladder functions requires a false-to-true transition to execute. In continuous mode, once the rung goes
true, BTR and BTW functions continue to execute regardless of rung condition. See page 15-8 for more information.
1785-6.1 November 1998
C-6
Instruction
Description
Operand
Valid Value
COR
Custom Output Routine
program file number
immediate (2 - 999) for all

processors
integer, float
(for use with CAR

applications only)
Require
False-to-True
Transition
no
COS *
Cosine
source
no
CPT
Compute
math expression
expression using values or

immediate integer float
addresses with evaluators
(for a list, see chapter 4 in
this manual)
no
EXE mnemonic
EXE
relative expression
addresses with evaluators (for

a list, see chapter 4 in
this manual)
destination
integer, float
counter
counter
PRE
32,768 - +32,767
ACC
32,768 - +32,767
counter
counter
PRE
32,768 - +32,767
ACC
32,768 - +32.767
yes
source array
binary
yes
reference array
binary
result array
integer
compare control
control
length
position
0 - 15999
result control
control
length
1 - 1000
position
0 - 999
source
destination
immediate, float (in degrees)
CTD
CTU
DDT
DEG *
1785-6.1 November 1998
Count Down
Count Up
Diagnostic Detect
Degree (convert radians

to degrees)
yes
yes
no
C-7
Instruction
Description
Operand
Valid Value
DFA
Diagnostic Fault Annunciator
control file
integer
number of I/O
immediate (8, 16, 32)
program file number
immediate (3-999)
source A
source B
destination
integer, float
source
immediate, integer
mask
immediate, integer
reference
integer
DIV
DTR
Divide
Data Transitional
Require
False-to-True
Transition
no
no
EOC
end of SFC compression

(see SOC)
only for ASCII

import/export
N/A
EOR
end of rung
only for ASCII

import/export
N/A
EOT
end of transition
none
no
ESE
end SFC selection branch

(see SEL)
only for ASCII

import/export
N/A
EQU
Equal
source A
source B
no
EOP
end of SFC program
only for ASCII

import/export
N/A
ERI
error on an input instruction
only in ASCII
export files
N/A
ERO
error on an output instruction
only in ASCII
export files
N/A
ESI
end SFC simultaneous branch

(see SIM)
only for ASCII

import/export
N/A
FAL
File Arithmetic/Logical
control
control
length
1 - 1000
position
0 - 999
mode
(INC, 1-1000, ALL)
destination
integer, float
math expression
indexed math instruction
yes
1785-6.1 November 1998
C-8
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
FBC
File Bit Compare
source array
binary
yes
reference array
binary
result array
integer
compare control
control
length
position
0 - 15999
result control
control
length
1 - 1000
position
0 - 999
source operand
immediate, indexed, integer
FIFO array
indexed, integer
FIFO control
control
length
1 - 1000
position
0 - 999
FIFO array
indexed, integer
destination
indexed, integer
FIFO control
control
length
1 - 1000
position
0 - 999
source operand
no
destination array
array
no
length
immediate (1 - 1000)
LBL number
integer
index
integer
initial value
immediate, integer
terminal value
immediate, integer
step size
immediate, integer
source
immediate, integer
destination
integer
FFL
FFU
FLL
FOR
FRD
1785-6.1 November 1998
FIFO Load
FIFO Unload
Fill File
For Loop
From BCD
yes
yes
no
no
C-9
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
FSC
File Search and Compare
control
control
yes
length
1 - 1000
position
0 - 999
mode
immediate, integer (0, INC,

1-1000, ALL)
math expression
indexed math instruction
source A
source B
source A
source B
data file offset
immediate (0-999), integer
length
destination
integer
data file offset
length
source
integer
GEQ
GRT
IDI
IDO
Greater Than or Equal To
Greater Than
Immediate Data Input
Immediate Data Output
no
no
yes
yes
IIN
Immediate Input
I (input) word
immediate, integer
PLC-5/10, 11, 12 15, 20, 25,
30: 000-077
PLC-5/40, 40L: 000-157
PLC-5/60, 60L, 80, :000-237
no
IOT
Immediate Output
O (output) word
immediate, integer
PLC-5/10, 11, 12, 15, 20, 25,
30: 000-077
PLC-5/40, 40L: 000-157
PLC-5/60, 60L, 80: 000-237
no
JMP
Jump
label number
immediate
Classic PLC-5 processors:
0-31
Enhanced PLC-5 processors:
0-255
no
JSR
Jump to Subroutine
ladder program
number
immediate (2 - 999)
no
integer float
no
file number
immediate
0-31
0-255
N/A
LAB
SFC label (import/export only)
1785-6.1 November 1998
C-10
Require
False-to-True
Transition
Instruction
Description
Operand
Valid Value
LBL
LBL (ladder program label)
label number
immediate
0-31
0-255
no
LEQ
Less Than or Equal To
source A
no
source B
source A
source B
source operand
LIFO array
indexed, integer
LIFO control
control
length
1 - 1000
position
0 - 999
LIFO array
indexed, integer
destination
indexed, integer
LIFO control
control
length
1 - 1000
position
0 - 999
low limit
test
high limit
source
destination
float
source
no
destination
float
no
LES
LFL *
LFU *
LIM
LN *
LOG *
Less Than
LIFO Load
LIFO Unload
Limit
Natural Log
Log to the Base 10
MCR
Master Control Relay
MEQ
Mask Compare Equal To
MOV
MSG
1785-6.1 November 1998
Move
Message
no
yes
yes
no
no
no
source operand
immediate, integer
source mask
immediate, integer
compare operand
immediate, integer
source
destination
integer, float
control block
message, integer
no
no
yes
C-11
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
MUL
Multiply
source A
no
source B
destination
integer, float
source operand
immediate, integer
source mask
destination
integer
source
destination
integer, float
source A
source B
source
immediate, integer
destination
integer
MVM
NEG
NEQ
NOT
Masked Move
Negate
Not Equal To
Logical NOT
no
no
no
no
NSE
SFC next selection branch
only for ASCII

import/export
N/A
NSI
SFC next simultaneous branch
only for ASCII

import/export
N/A
NXT
Next (FOR Loop)
for label number
immediate
0-31
0-255
no
OR
Logical OR
source A
immediate, bits integer
yes
source B
destination
integer
storage bit
bit
output bit
immediate (0 - 15)
output word
integer
OSF *
One Shot Falling
yes; requires a
true-to-false
transition to
execute
ONS
One Shot
source bit
bit
yes
OSR *
One Shot Rising
storage bit
bit
yes
output bit
immediate (0 - 15)
output word
integer
OTE
Output Energize
destination bit
bit
no
OTL
Output Latch
destination bit
bit
no
OTU
Output Unlatch
destination bit
bit
no
1785-6.1 November 1998
C-12
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
PID
PID
control block
PD
no
control block
integer
yes
pv value
integer
tieback value
immediate, integer
cv value
integer
source
immediate, float (in degrees)
destination
float (in radians)
label number
immediate (0 - 255)
N/A
timer, counter, control
no
RAD *
Radian (convert degrees

to radians)
no
REF
SFC reference (see LAB)

(ASCII import/export only)
RES
Timer/Counter Reset
RET
Return
no
RTO2
Retentive Timer On
timer
timer
yes
time base
immediate (0.01, 1.0)
PRE
0 - 32767
ACC
0 - 32767
SBR
Subroutine
integer, float
no
SDS
Smart Directed Sequencer
control file
integer
no
number of I/O
immediate (8, 16, 32)
program file number
immediate (3-999)
SDZ
start of delete zone,

unassembled edits
only in ASCII
export files
N/A
SEL
SFC selection branch
only for ASCII

import/export
N/A
SFR*
SFC reset
SFC file number
immediate (1 - 999)
restart at step
immediate, integer
SIM
SFC simultaneous branch

2
no
N/A
This instruction requires periodic scans to be updated. See page 2-13 in this manual or your Structured Text User Manual for more information.
1785-6.1 November 1998
C-13
Instruction
Description
Operand
Valid Value
Require
False-to-True
Transition
SIN *
Sine
source
no
destination
float (in radians)
SIZ
start of insert zone,

unassembled edits
only in ASCII
export files
N/A
SOC
start of compression
only for ASCII

import/export
N/A
SOP
SFC start of program
only for ASCII

import/export
N/A
SOR
start of rung
only for ASCII

import/export
N/A
SQI
Sequencer Input
file
integer, indexed
mask
immediate, Hex indexed,

integer
source
control
control
length
1 - 1000
position
0 - 999
file
integer, indexed
source
control
control
length
1 - 1000
position
0 - 999
file
integer, indexed
destination mask
destination
indexed, integer
control
control
length
1 - 1000
position
0 - 999
source
destination
integer, float
sort file
integer, float
file control
control
length
1 - 1000
position
0 - 999
SQL
SQO
SQR
SRT *
Sequencer Load
Sequencer Output
Square Root
Sort
no
yes
yes
no
yes
1785-6.1 November 1998
C-14
Description
Operand
SRZ
start of replace zone,

unassembled edits
only in ASCII export

files
STP
SFC step (Classic

PLC-5 Processors)
file number
2 - 999
N/A
STP *
SFC step
(Enhanced PLC-5 Processors)
step timer file number
2 - 9999
N/A
time base
qualifier
N, S, R, L, D, P1, P0, SL,

SD, DS
action number
(from ACT)
immediate
timer file number
timer
time base
standard deviation file
integer, float
destination
integer, float
file control
control
length
1 - 1000
position
0 - 999
source A
source B
destination
integer, float
source
destination
float (in radians)
token ID number
(must be unique per
SFC file)
immediate
STD *
SUB
TAN *
Standard Deviation
Subtract
Tangent
TID *
Token ID
TND
Temporary End
TOD
To BCD
1785-6.1 November 1998
Valid Value
Require
False-to-True
Transition
Instruction
N/A
yes
no
no
N/A
no
source
immediate, integer
destination
integer
no
C-15
Require
False-to-True
Transition
Instruction
Description
Operand
Valid Value
TOF 2
Timer Off Delay
timer
timer
yes: requires
true-to-false
transition to
execute
TOF 2
Timer Off Delay
time base
PRE
0 - 32767
yes: requires
true-to-false
transition to
execute
ACC
0 - 32767
timer
timer
time base
PRE
0 - 32767
ACC
0 - 32767
file number
2 - 999 for all processors
TON 3
Timer On Delay
yes
TRC
SFC transition
UID *
User Interrupt Disable
no
UIE *
User Interrupt Enable
no
XIC
Examine On
source bit
bit
no
XIO
Examine Off
source bit
bit
no
XOR
Exclusive Or
source A
no
source B
destination
integer
source A
immediate, integer
source B
immediate, integer
destination
integer
XPY *
X to the Power of Y
N/A
no
2
This instruction requires periodic scans to be updated. See page 2-9 in this manual or page 2-10 in the Structured Text User Manual for more
information.
3
This instruction requires periodic scans to be updated. See page 1-14 in this manual or your Structured Text User Manual for more information.
1785-6.1 November 1998
C-16
1RWHV
1785-6.1 November 1998
Index
A
ABL instruction 17-4
ACB instruction 17-5
ACI instruction 17-6
ACN instruction 17-7
ACS instruction 4-11
ADD instruction 4-12
Addition instruction
ADD 4-12
AEX instruction 17-7
AFI instruction 13-13
AHL instruction 17-8
AIC instruction 17-9
Always False instruction 13-13
AND instruction 5-2
AND Operation instruction
AND 5-2
ASCII
ABL 17-4
ACB 17-5
ACI 17-6
ACN 17-7
AEX 17-7
AHL 17-8
AIC 17-9
ARD 17-10
ARL 17-12
ASC 17-14
ASR 17-15
AWA 17-15
AWT 17-17
ASCII instructions, strings 17-3
ASCII Integer to String instruction 17-9
ASCII Read Characters instruction 17-10
ASCII Read Line instruction 17-12
ASCII Set Handshake Lines instruction 17-8
Arc Cosine instruction

ACS 4-11
ASCII String Compare instruction 17-15
Arc Sine instruction

ASN 4-13
ASCII String Extract instruction 17-7
Arc Tangent instruction

ATN 4-14
ASCII String to Integer instruction 17-6
ARD instruction 17-10

ARL instruction 17-12
ASC instruction 17-14
ASCII String Concatenate instruction 17-7

ASCII String Search instruction 17-14
ASCII Write Append instruction 17-15
ASCII Write instruction 17-17
ASN instruction 4-13
ASR instruction 17-15
ATN instruction 4-14
1785-6.1 November 1998
I2
Index
Attention
32- to 16-bit conversion 4-10
AVE indexed address 4-16
change index value 13-6
control structure addressing 10-4
DTR online programming 10-8
entering input addresses 1-6
entering output addresses 1-7
FAL indexed address 9-2
FOR and NXT with output branches 13-5
FOR and NXT within branches 13-5
indexed addressing 8-2
jumped timers and counters 13-4
MCR zones
overlapping or nesting 13-2
timers and counters 13-2
modify status bits of BTR/BTW 15-6
MSG
status bits .ST and .EW 15-24
online programming with ONS 13-14
pairing stack instructions 11-6
PID
change engineering unit max 14-22
change engineering unit min 14-22
change inputs or units 14-19
changing scaling 14-6
resume last state 14-10
setting temperature limits 14-28
update time 14-21
placement of critical counters 2-15, 2-17
resetting TON and TOF 2-8, 2-20
SRT indexed address 4-27
status of BTR/BTW bits 15-7
STD indexed address 4-30
use of control address 12-3
using control addresses 8-2
using control addresses for instructions 11-2
B
Bit Distribute instruction
BTD 7-2
Bit Shift Left (BSL) instruction 11-2
Bit Shift Right (BSR) instruction 11-2
block transfer
BTR instruction 15-3
BTW instruction 15-3
direct communication mode 15-2
I/O scan mode 15-1
instructions 15-1
programming examples 15-15
timing 15-13, 15-14
Block Transfer Read instruction
BTR 15-3
Block Transfer Write instruction
BTW 15-3
Break (BRK) instruction 13-5
BRK instruction 13-5
BSL instruction 11-2
BSR instruction 11-2
BTD instruction 7-2
BTR instruction 15-3
BTW instruction 15-3
C
CAR utility 18-1
CIO instruction 15-22
monitoring 15-24
status bits 15-24
using 15-23
Classic PLC5 processors 1
AVE instruction 4-15
Clear instruction
CLR 4-17
Average File instruction

AVE 4-15
CLR instruction 4-17
AWA instruction 17-15

AWT instruction 17-17
1785-6.1 November 1998
CMP
instruction 3-2
Index
I3
compare
EQU 3-5
expression 3-2
GEQ 3-5, 3-6
instructions 3-2
length of expressions 3-3
LEQ 3-6
LES 3-7
NEQ 3-10
compute
ACS 4-11
ADD 4-12
ASN 4-13
ATN 4-14
AVE 4-15
CLR 4-17
COS 4-18
CPT 4-5
DEG 6-3
DIV 4-19
EOT 13-18
expression 4-5
FSC 9-14
functions 4-9
IOT 1-7
length of expressions 4-7
LN 4-20
LOG 4-21
MUL 4-22
NEG 4-23
ONS 13-14
order of operation 4-8
RAD 6-4
SIN 4-24
SQR 4-25
SRT 4-26
STD 4-28
SUB 4-31
TAN 4-32
XPY 4-33
Compute instruction
CPT 4-5
connecting to Ethernet PLC5 processors using
hostnames 16-6
control file
example 8-2
ControlNet I/O transfer
instruction 15-22
ControlNet PLC5 processors 1
convergent
scan time B-14
conversion
BCD 6-2
FRD 6-2
Convert from BCD instruction
FRD 6-2
Convert to BCD instruction
TOD 6-2
COP instruction 9-19
COS instruction 4-18
Cosine instruction
COS 4-18
Count Down instruction 2-17
Count Up instruction 2-15
counter
CTD 2-17
CTU 2-15
RES 2-20
counters
instructions 2-13
CPT instruction 4-5
CTD instruction 2-17
CTU instruction 2-15
custom application routine 18-1
D
data files
manipulating 8-3
range of values C-1
data storage
I/O image files 1-2
Data Transitional instruction
DTR 10-8
1785-6.1 November 1998
I4
Index
DDT instruction 10-2
Equal To instruction 3-5
DEG instruction 6-3
Ethernet PLC5 processors 1
Degree instruction
DEG 6-3
Examine Off instruction 1-3
derivative smoothing 14-4
expression
determining the length of 3-3, 4-7
DFA instruction 18-1

diagnostic
DDT 10-2
DTR 10-8
FBC 10-2
parameters 10-4, 10-8
search mode 10-2
status 10-5
Examine On instruction 1-3
F
FAL logical instruction 9-12
FBC instruction 10-2
FFL instruction 11-5
FFU instruction 11-5
Diagnostic Detect instruction

DDT 10-2
FIFO Load (FFL) instruction 11-5
Diagnostic Fault Annunciator Instruction 18-1
file
diagnostic instructions 10-1
FIFO Unload (FFU) instruction 11-5

search and compare operations 9-17
direct communication
block transfer 15-2
File Arithmetic and Logic instruction

FAL 9-2
DIV instruction 4-19
File Bit Comparison instruction

FBC 10-2
divergent
scan time B-14
Divide instruction
DIV 4-19
DTR instruction 10-8
E
element manipulation
LIM 3-7
MEQ 3-9
MOV 7-3
MVM 7-4
End of Transmission instruction
EOT 13-18
engineering units
scaling 14-5
Enhanced PLC5 processors 1
EOT instruction 13-18
EQU instruction 3-5
1785-6.1 November 1998
file concepts
control structure 8-2
manipulating data 8-3
modes of operation 8-5
File Copy instruction
COP 9-19
File Fill instruction
FLL 9-20
file instructions
logical 9-12
File Search and Compare instruction
FSC 9-14
Index
I5
files
arithmetic operations 9-7
copy operations 9-5
functions 9-14
instruction
COP 9-19
FLL 9-20
logical operations 9-12
operation modes 8-5
FLL instruction 9-20
floating point
valid value range C-1
For (FOR) instruction 13-5
FOR instruction 13-5
FRD instruction 6-2
FSC instruction 9-14
G
gain constants 14-3
instruction
ControlNet I/O transfer 15-22
immediate data input 1-8
immediate data output 1-8
instructions
ASCII 17-1
block transfer 15-1
CIO
monitoring 15-24
compare 3-2
diagnostic 10-1
memory requirements A-1
message 16-1
operands C-1
program flow 13-1
relay-type 1-1, 2-1
sequencer 12-1
shift register 11-1
timer 2-1
timing A-1
GEQ instruction 3-5, 3-6
INVALID OPERAND
error message 4-4
Greater Than or Equal To instruction 3-5, 3-6
IOT instruction 1-7
I/O image files 1-2
JMP instruction 13-3
I/O scan mode

block transfer 15-1
JSR instruction 13-8
IDI instruction 1-8

using 1-9
Jump to Subroutine instruction 13-8
IDO instruction 1-8

using 1-9
IIN instruction 1-6
Immediate Data Input
instruction 1-8
Jump instruction 13-3
L
Label (LBL) instruction 13-5
Label instruction 13-3
LBL instruction 13-3, 13-5
Immediate Data Output

instruction 1-8
LEQ instruction 3-6
Immediate Input instruction 1-6
Less Than instruction 3-7
Immediate Output instruction

IOT 1-7
Less Than or Equal To instruction 3-6
incremental mode 8-7
LFU instruction 11-5
LES instruction 3-7
LFL instruction 11-5
1785-6.1 November 1998
I6
Index
LIFO Load (LFL) instruction 11-5
MUL instruction 4-22
LIFO Unload (LFU) instruction 11-5

LIM instruction 3-7
Multiply instruction
MUL 4-22
Limit Test instruction 3-7
MVM instruction 7-4
LN instruction 4-20
LOG
instruction 4-21
Log to the base 10 instruction
LOG 4-21
logical
AND 5-2
NOT 5-3
OR 5-4
XOR 5-5
M
manipulating
file data 8-3
Masked Comparison for Equal instruction 3-9
Masked Move instruction 7-4
Master Control Reset instruction 13-2
MCR instruction 13-2
memory
instruction requirements A-1
SFC requirements B-3
N
Natural Log instruction
LN 4-20
NEG instruction 4-23
Negate instruction
NEG 4-23
NEQ instruction 3-10
Next (NXT) instruction 13-5
Not Equal To instruction 3-10
NOT instruction 5-3
NOT Operation instruction
NOT 5-3
Number of Char in Buffer instruction 17-5
NXT instruction 13-5
O
One Shot Falling (OSF) instruction 13-16
One Shot instruction
ONS 13-14
MEQ instruction 3-9
One Shot Rising (OSR) instruction 13-15
message
instruction 16-1
ONS instruction 13-14
modes
file operation 8-5
operands
instructions C-1
OR instruction 5-4
monitoring
CIO instructions 15-24
OR Operation instruction
OR 5-4
MOV instruction 7-3
order of operation 4-8
Move instruction
MOV 7-3
OSF instruction 13-16
MSG
instruction entry 16-10
OTE instruction 1-4
MSG instruction 16-1

using 16-10
OTU instruction 1-5
1785-6.1 November 1998
OSR instruction 13-15

OTL instruction 1-4
Index
I7
Output Energize instruction 1-4

Output Latch instruction 1-4
Output Unlatch instruction 1-5
P
PID
biasing 14-9
equations 14-2
examples 14-29
instruction 14-10
integer examples 14-29
PD examples 14-33
selecting derivative term 14-7
setting output alarms 14-7
using manual mode 14-8
using output limiting 14-7
PID instruction 14-1
PLC2 compatibility file 16-15
process control
biasing 14-9
derivative smoothing 14-4
equations 14-2
gain constants 14-3
integer PID examples 14-29
PD PID examples 14-33
PID 14-10
PID examples 14-29
PID instruction 14-1
selecting derivative term 14-7
setting output alarms 14-7
using manual mode 14-8
using output limiting 14-7
program constant
valid value range C-1
program constants 3-2, 4-5
program flow instruction

FOR, BRK, LBL, and RET 13-5
OSF 13-16
OSR 13-15
SFR 13-17
program flow instructions 13-1
Programming
SDS instruction 18-2
programming
instructions
operands C-1
Proportional, Integral, and Derivative instruction
14-10
R
RAD instruction 6-4
Radian instruction
RAD 6-4
relay-type
IIN 1-6
OTE 1-4
OTL 1-4
OTU 1-5
XIC 1-3
XIO 1-3
RES instruction 2-20
Reset instruction 2-20
RET instruction 13-8
Retentive Timer On instruction 2-10
Return instruction 13-8
RTO instruction 2-10
run times
determining B-12
program flow
AFI 13-13
JMP and LBL 13-3
JSR, SBR, and RET 13-8
MCR 13-2
UID 13-19
UIE 13-20
1785-6.1 November 1998
I8
Index
S
SBR instruction 13-8
scaling
to engineering units 14-5
scan sequence
SFC B-7
scan time
convergent B-14
divergent B-14
steadystate B-14
scanner mode
configuring 15-13, 15-14
SDS instruction 18-1
selection branch
scanning sequence B-8
sequencer
applying 12-1
instructions 12-1
SQI 12-2
SQL 12-2
SQO 12-2
Sequencer Input instruction 12-2
Sequencer Load instruction 12-2
Sequencer Output instruction 12-2
Sequential Function Chart Reset
instruction 13-17
SFC
constraints B-5
example
memory requirements B-3
scanning sequence
example B-11
selection branch B-8
simultaneous branch B-9
scanning sequences
step/transition B-7
status information B-1
SFR instruction 13-17
1785-6.1 November 1998
shift register instruction

applying 11-1
BSL and BSR 11-2
FFL and FFU 11-5
LFL and LFU 11-5
simultaneous branch
SIN instruction 4-24
Sine instruction
SIN 4-24
Smart Directed Sequencer (SDS) Instruction
overview 18-2
programming 18-2
Smart Directed Sequencer Instruction 18-1
Sort File instruction
SRT 4-26
SQI instruction 12-2
SQL instruction 12-2
SQO instruction 12-2
SQR instruction 4-25
Square Root instruction
SQR 4-25
SRT instruction 4-26
Standard Deviation instruction
STD 4-28
status bits
status information
SFC B-1
STD instruction 4-28
steady-state
scan time B-14
step
SUB instruction 4-31
Subroutine Header instruction 13-8
Subtract instruction
SUB 4-31
Index
I9
T
TAN instruction 4-32
Tangent instruction
TAN 4-32
Temporary End
instruction 13-13
Temporary End instruction 13-20
Test Buffer For Line instruction 17-4
timer
accuracy 2-3
instruction parameters 2-2, 2-13
RES 2-20
RTO 2-10
TOF 2-7
TON instruction 2-4
U
units, engineering
scaling 14-5
User Interrupt Disable
UID 13-19
User Interrupt Enable
UIE 13-20
using
IDI instruction 1-9
IDO instruction 1-9
MSG instruction 16-10
X
Timer Off Delay instruction 2-7
X to the Power of Y instruction

XPY 4-33
Timer On Delay instruction 2-4
XIC instruction 1-3
timers 2-1
XIO instruction 1-3
timing
block transfer 15-13, 15-14
instructions A-1
XOR instruction 5-5
tip
XPY instruction 4-33
XOR Operation instruction

XOR 5-5
connecting to Ethernet PLC5 processors

using hostnames 16-6
TND
instruction 13-13
TND instruction 13-19, 13-20
TOD instruction 6-2
TOF instruction 2-7
TON instruction 2-4
transition
1785-6.1 November 1998
I10
1RWHV
1785-6.1 November 1998
Index
Allen-Bradley
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PLC-5 Programmable Controllers Instruction Set Reference
Cat. No. 1785 series
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Pub. No.
1785-6.1
Pub. Date
November 1998
Part No.
Describe Problem(s):
955133-83
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PN 955107-82
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In the United States and Canada
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Outside of the United States
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Region or Area
Customer Support Center

Telephone Number
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1785-6.1 November 1998
1785-6.1 November 1998

Supersedes 1785-6.1 Feburary 1996
PN 955133-83
1998 Rockwell International Corporation. Printed in USA

Instruksi Allen Bradley PLC

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Instruksi Allen Bradley PLC

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Allen-Bradley

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PLC-5 Instruction Set Alphabetical Listing

PLC-5 Instruction Set Alphabetical Listing

Enhanced PLC -5 processors

1785-6.1 November 1998

PLC-5 Instruction Set Alphabetical Listing

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Use this Instruction Category:

examine, check or control

2-state device or condition

move, copy, change,

analog values, codes

transfer data to/from modules

block transfer or ControlNet transfer

diagnostics, fault handling

control the flow of your program program control

detecting when a limit switch closes

changing the temperature preset

transfer analog data

turn on a motor 10 seconds after a pump is activated

move 1 of 3 recipes into a work area

keep track of parts as they move from station to station shifting

1785-6.1 November 1998

Converting non-decimal numbers with the FRD instruction

How non-existing, indirect addresses affect the COP and

How the .POS value operates in sequencer instructions

Using a RET instruction

Using the PID bias term

Using the no zero crossing (.NOZC) and no back calculation

Clarification to error code 89 for MSG instruction

Ethernet PLC-5 processors now support SLC Typed Read and

Configuring a multihop MSG instruction over Ethernet or

Monitoring the status of the .EN bit in a continuous

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1785-6.1 November 1998

1785-6.1 November 1998

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Include these Allen-Bradley Processors:

Classic PLC-5 processors

PLC-5/10, -5/12, -5/15, -5/25, and -5/VME processors.

Enhanced PLC-5 processors

PLC-5/11, -5/20, -5/30, -5/40, -5/40L, -5/60,

Ethernet PLC-5 processors

PLC-5/20E, -5/40E, and -5/80E processors.

ControlNet PLC-5 processors

PLC-5/20C, -5/40C, -5/46C, and -5/80C processors.

Protected PLC-5 processors 1

PLC-5/26, -5/46, and -5/86 processors.

VME PLC-5 processors

PLC-5/V30, -5/V40, -5/V40L, and -5/V80 processors. See the

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1785-6.1 November 1998

1785-6.1 November 1998

Timer Instructions TON, TOF,

1785-6.1 November 1998

1785-6.1 November 1998

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