840

A New Single-Phase Power Factor Corrector

Based on the SEPIC and Sheppard-Taylor
Topologies
Hadi Y. Kanaan and Alfred Hayek
Saint-Joseph University
Faculty of Engineering ESIB
Campus des Sciences et Technologies
Mar Roukos, Mkalls B.P. 11-0514
Riad El-Solh, Beirut, Lebanon
Phone: +961 3 333179, Fax: +961 4 532645
hadi.kanaan@fi.usj.edu.lb , Alfred.hayek@fi.usj.edu.lb
Kamal Al-Haddad
cole de Technologie Suprieure (ETS)
Canada Research Chair in Energy Conversion and Power
Electronics
1100 Rue Notre-Dame West, Montreal, Quebec
H3C 1K3, Canada
Phone: (514) 396-8874, Fax: (514) 396-8684
kamal@ele.etsmtl.ca
Abstract In this paper, a new single-phase Power Factor Cor-
rector (PFC) based on the Sheppard-Taylor topology is
proposed. Compared to conventional buck, boost or buck-boost
PFCs, this topology allows a better current tracking at the AC
side, with a relatively reduced voltage at the DC side. Con-
sequently, the high frequency AC filters required by the buck
PFCs are avoided, and the voltage stresses on the boost switches
are significantly reduced. Furthermore, the control detuning
phenomenon, from which suffer most of the conventional PFCs,
especially at very low input voltage, is avoided. This yields major
improvements in the source current waveform.
The proposed converter is integrated as a PFC at the DC-end
of a single-phase diode bridge. A Pulse-Width-Modulated
(PWM) control is developed in order to ensure a unity power
factor at the AC-source side and a regulated voltage at the DC-
load side. In order to verify the performance of the proposed
control scheme, simulation experiments are carried out on a
numerical version of the converter with its control circuit. The
implemented model of the converter is obtained by using the
switching function technique. The control system is tested
under both rated and disturbed operating conditions. The sy-
stem performance is evaluated in terms of source current Total
Harmonic Distortion (THD), voltage regulation, robustness and
dynamic time response to a set point offset.
I. INTRODUCTION
High power quality achievement is increasingly required
for the power supply systems in order to comply with the in-
ternational standards [1]. For this purpose, and especially for
single-phase low power applications, switch-mode DCDC
converters, commonly known as Power Factor Correction
(PFC) circuits, are designed in order to ensure a high power
factor at the mains side, and to emulate a purely resistive
operation of the diode-bridge-based frontend rectifier [2].
Among the conventionally used PFCs are the Boost-
Buck DC-DC converters [3]. These PFCs can provide non-
pulsating currents at the input and output stages, with a
reduced level of the output voltage, which make them
highly suitable for such applications. Several single-stage
topologies of Boost-Buck combinations have been
introduced in the literature. The most popular ones are
illustrated in Fig. 1. The cascaded Boost-Buck converter
[4] (Fig. 1.a), the Cuk converter [5] (Fig. 1.b) and the
Single Ended Primary Inductance Converter (SEPIC) [6]
(Fig. 1.c) have similar characteristics in PFC application;
however, they all suffer from the control detuning
phenomenon that appears at very low values of the input
voltage (which would correspond to the zero-crossings of
the AC source voltage). Note also that the Cuk and SEPIC
converters differ from each other at the output stage, where
the free-wheel diode and the output inductor are
permutated, and the polarity of the output voltage is
inverted (which, in practice, may cause some problems if
the output stage is not isolated from the input one). The
detuning problem in these latter PFCs is avoided by the use
of the Sheppard-Taylor topology proposed in [7-11] (see
Fig. 2) and presented in Fig. 1.d., where the single active
switch is replaced by two synchronized ones. However, the
reversed polarity feature between the input and output
stages is still existing (as in the Cuk topology of Fig. 1.b).
In this paper, a new non-inverted-polarity Sheppard-
Taylor-based power factor corrector that achieves perfect
current shaping is proposed. The topology of the converter
is presented in Fig. 3. The pair of synchronized switches is
controlled by a multiple-loop control scheme in order to
ensure both AC source current shaping and DC load
voltage regulation. The performance of the proposed
control scheme is then analysed through numerical
simulations by using the Matlab/Simulink tool. For this
purpose, a switching-function-based state model of the
converter operating in Continuous Current Mode (CCM) in
both inductors is implemented, and the control process is
launched under different operating conditions in order to
test successively the dynamics, the robustness and the
tracking abilities of the controller.
978-1-4244-1628-8/07/$25.00 2007 IEEE
841

D
a
v
0
D
b
D
c
D
d
i
in
v
in
i
0
~
Cascaded Boost-Buck Converter
C
L
2
+
_
Q
L
1
C
0

D
a
v
0
D
b
D
c
D
d
i
in
v
in
i
0
~
Cuk Converter
C L
2
+
_
D Q
L
1
C
0


(a) (b)

D
a
v
0
D
b
D
c
D
d
i
in
v
in
i
0
~
SEPIC Converter
C
L
2
+
_
D
Q
L
1
C
0

D
a
v
0
D
b
D
c
D
d
i
in
v
in
i
0
~
Sheppard-Taylor Converter
C
L
2
+
_
L
1
C
0
Q
1
Q
2
D
1
D
2
D
3
D
4


(c) (d)

Fig. 1: Single-stage Boost-Buck PFCs: (a) cascaded Boost-Buck topology, (b) Cuk topology, (c) SEPIC topology and (d) Sheppard-Taylor topology.


i
L1
*
i
L1
Inevitable current distortion due
to the control detuning problem
in the cascaded Boost-Buck,
Cuk or Sepic PFCs
Control detuning problem avoided
in the Sheppard-Taylor PFC


Fig. 2: Control detuning problem in the conventional PFCs.

v
0
i
L1
v
1
i
0
C
L
2
+
_
L
1
C
0
Q
1
Q
2
D
1
D
2
D
3
D
4
i
C
v
C
+
_
i
L2
i
C0


Fig. 3: Proposed Sheppard-Taylor based PFC.

II. CCM/CVM OPERATION AND MODELLING

OF THE PROPOSED PFC
The operating sequences of the converter of Fig. 3 in the
most common case of a Continuous Current Mode (CCM) in
both inductors L
1
and L
2
, and a Continuous Voltage Mode
(CVM) in the intermediate capacitor C, are illustrated in Fig.
4. The circuit has two configurations, depending on the state
of the main switches Q
1
and Q
2
. The expressions of all si-
gnificant circuit variables in both sequences are summarized
by the steady-state waveforms given in Fig. 5, where it is as-
sumed that all the switches and reactive components are ideal
(zero power losses) and that the voltage v
C
across the
intermediate capacitor is higher than the output voltage v
0
(this
assumption will be
842
justified in section 3). Note that the voltage and current
ripples at the switching frequency, which appear in the
waveforms of Fig. 5, are intentionally magnified in order
to be visible. In practice, these ripples are negligible due to
a suitable choice of the inductors and capacitors. This issue
will be addressed in section 4.
Following these considerations, we may describe
analytically the operation of the converter in the
CCM/CVM case by writing the following equations:
( )
( )

=
+ =
=
+ =
0 2
0
0
2 1 1
0
2
2
1
1
1
2 1
i i s
dt
dv
C
i i s i s
dt
dv
C
v s v s
dt
di
L
v s v
dt
di
L
L Q
L L Q L Q
C
Q C Q
L
C Q
L
(1)
where s
Q
denotes the switching function of the pair of
switches Q
1
and Q
2
, defined as:

=
d-on are turne and Q if Q
d-off are turne and Q if Q
s
Q
2 1
2 1
1
0
(2)
and
Q
s is its logical complement.
Moreover, the switching frequency of switches Q
1
and
Q
2
is either time-varying (if a hysteresis flip-flop controller
is used for the line current shaping) or fixed (if a saw-
tooth-carrier-based pulse-width modulator is used along
with a continuous current controller). However, it will be
assumed in both cases, especially as far as the calculation
of the reactive components L
1
, L
2
, C and C
0
(detailed in
section 4) is concerned, that the lowest switching
frequency is far beyond the bandwidth of the current and
voltage loops. Consequently, a simplified averaged model
of the converter may be adopted in order to analyse the
low-frequency operation of the converter in the steady-
state regime (section 3) and to choose, thus, the required
reactive components (section 4).
III. STEADY-STATE OPERATION FOR A UNITY POWER
FACTOR CONDITION
In a Unity Power Factor (UPF) operating condition, the
converter and its control circuit emulate a purely resistive
load.
The AC source voltage and current both have, in this
case, a sine-wave shape, and are in phase. The DC voltage
v
1
and current i
L1
delivered by the single-phase diode
bridge are rectified sine-wave signals and, thus, have the
following expressions:
( ) t V t v
S 0 1
sin 2 = (3)
and:
( ) t I t i
S L 0
*
1
sin 2 = (4)
where V
S
and I
S
represent respectively the RMS-values of
the main source voltage and current, and
0
the angular
frequency of the source. The asterisk (
*
) denotes that we
are placed in the desired steady-state operating regime.
In addition, by neglecting at this first stage the voltage
ripple at the capacitors (which is justified by choosing high
enough values for C and C
0
), we may also write:
( )
*
0
*
0
V t v (5)
and:
( )
* *
C C
V t v (6)
where V
0
*
and V
C
*
designate respectively the static or DC
values of v
0
*
(t) and v
C
*
(t). Moreover, applying the state-
space averaging technique in CCM/CVM mode yields the
following low-frequency model of the converter:
( )
( )
( )
( )

=
=
=
=
0 2
0
0
2 1
0
2
2
1
1
1
1
2 1
1
2 1
i i d
dt
dv
C
i d i d
dt
dv
C
v d v d
dt
di
L
v d v
dt
di
L
L
L L
C
C
L
C
L
(7)
where d(t) denotes the common duty cycle of switches Q
1
and Q
2
. Here, it is assumed that the conditions i
*
L2
> 0 and
v
*
C
> 0 always stand; these assumptions will be justified
later by a suitable choice of inductor L
2
and capacitor C.
Moreover, the current i
L1
is mainly in continuous mode as
noticed in expression (4), and it would be only locally in
discontinuous mode at the zero-crossings of the AC source
voltage; this latter feature will be neglected as far as
modeling and control are concerned.
Replacing v
1
, i
L1
, v
0
and v
C
by their desired expressions
given respectively in (3), (4), (5) and (6) into system (7)
yields expressions (8) and (9) given at the bottom of the
next page, with:
( )
( ) ( )

+ < < +
+ < < +
=

1 2 1 2 for 1
1 2 2 for 1
0
0
k t k
k t k
, Z k (10)
D
*
and I
L2
*
are the steady-state DC-values of the duty cycle
and the current in inductor L
2
, respectively. It appears
from expression (8) that the duty cycle d
*
lies practically
always inside the range:
[d
*
min
, d
*
max
] = [
*
*
2
2
C
S C
V
V V
,
2
1
] (11)
In order to have d
*
min
> 0, V
C
*
should be greater than the
peak value of the AC source voltage.
843
v
0
i
L1
v
1
i
0
C
L
2
+
_
L
1
C
0
Q
1
Q
2
D
1
D
2
D
3
D
4
i
C
v
C
+
_
i
L2
i
C0
v
0
i
L1
v
1
i
0
C
L
2
+
_
L
1
C
0
Q
1
Q
2
D
1
D
2
D
3
D
4
i
C
v
C
+
_
i
L2
i
C0
(a) (b)
Fig. 4: Operating sequences in CCM/CVM: electrical configuration when Q1 and Q2 are turned-on (a) or turned-off (b).
d.T
S
T
S
T
S
d.T
S
0 0
i
L1
i
L2
v
C
v
0
i
C
i
C0
v
Q1
v
Q2
i
Q1
i
Q2
v
D1
v
D2
i
D1
i
D2
v
D3
v
D4
i
D3
i
D4
t t
(v
1
+v
C
)/L
1
(v
1
-v
C
)/L
1 v
C
/L
2
-v
0
/L
2
V
C
V
0
v
C
v
0
-i
L1
-i
L2
i
L2
-i
0
-i
0
v
C
i
L1
+i
L2
v
C
i
L1
v
C
-v
0
v
C
+v
0
i
L2
i
L2
i
L1
Fig. 5: Steady-state waveforms during one switching period.
Note that, in the derivation of expressions (8) and (9),
the Fourier series development of sin(
0
t) and cos(
0
t)
has been used:
( ) ( )

=
=
1
0 2 0
2 cos
1 4
1 4 2
sin
k
t k
k
t

(12)
( ) ( )

=
=
1
0 2 0
2 sin
1 4
8
cos
k
t k
k
k
t

(13)
Considering that we have in practice L
1

0
I
S
<< V
S
, and
that:
( ) 2 for 3 1 4
2
>> k k k (14)
we may write approximately:
( ) ( ) t
V
V
D t d
C
S
0
*
* *
2 cos
3
2 2

+ (15)
and:
( ) ( ) t
L
V
V
V V
I t i
S
C
C
L L 0
0 2
*
*
0
*
*
2
*
2
2 sin
3
2

+
+ (16)
and it appears clearly that, for an increased value of L
2
, the
validity of the assumption i
*
L2
> 0 also increases, and the
converter tends to operate in CCM.
Furthermore, the low-frequency expressions of v
C
*
and
v
0
*
are given approximately by expressions (17) and (18)
given at the bottom. Note again that the voltage ripple
across capacitor C can be decreased by increasing the
value of C. Thus, a CVM is reachable by a suitable choice
of the capacitor. On the other hand, the DC-components in
the expressions (15) to (18) are related to each other as
follows:
( )
( ) ( )
( ) ( )

= )
`

1
0
2
0 1
0
2 *
*
*
0 0 1 0 *
2 sin
1 4
2
2 cos
1 4
2 2
2
cos 2 sin 2
2
1
k
S S
C C
S S
t k
k
I kL
t k
k
V
V
D
V
t I L t V
t d

(8)
( )
( )
( ) ( )

=
)
`

+
+
1
0
2
2
1
0
0 2
2 *
*
0
*
*
2
*
2
2 cos
1 4
2
2 sin
1 4
2
k
S S
C
C
L L
t k
k
I
L
L
t k
L k k
V
V
V V
I t i

(9)
( ) ( ) ( ) t
I
I
C V
I V
t
V
V
V
V V
C L
V
V t v
S
L
C
S S
C
S
C
C S
C C 0
*
2
0
*
0
* *
*
0
*
2
0 2
* *
2 sin
3
2 2
1
2
2 cos
15
2 32
1
12
2

|
|

\
|
+
|
|

\
|

+
+ (17)
( ) ( ) ( ) t
C V
V I
t
V
V
V
V V
C L
V
V t v
C
S L
C
S
C
C S
0
0 0
*
*
2
0
* *
*
0
*
2
0 0 2
*
0
*
0
2 sin
3
2
2 cos
15
2 32
1
12
2

|
|

\
|
+
+
(18)
844
( ) ( )
*
*
0
*
*
*
2
* *
*
*
*
*
*
0
*
*
1
2 2 2 1
2 2
2 1 1 1
2 2
2 1
1
D
I I
D
D
I
V
D D
D
V
D
D
V
V
D
V
S
L
S
C
S
C

(19)
where I
0
*
denotes the DC load current. It is clear that, for
D
*
< , V
C
*
is greater that V
0
*
, which justify the assumption
made in section 2.
It is on the basis of expressions (16), (17) and (18),
which are established in the low-frequency domain, that
the setting of the inductor L
2
and capacitors C and C
0
is
carried out. Regarding the rating of the DC inductor L
1
, a
knowledge of the high-frequency ripple of current i
L1
is
required.
IV. REACTIVE COMPONENTS SETTINGS
In order to choose the inductors, we have to evaluate
first the current ripple to be compensated in each inductor.
For inductor L
1
, the current ripple on a switching period is
(see Fig. 6):
( ) ( ) [ ]
( )
( ) t f
t d
i
S
HF L
*
, 1
tan tan = (20)
with:
( ) ( )
*
1
tan
L
i
dt
d
= ( )
1
*
1
tan
L
v v
C
+
=
and f
S
(t) is the switching frequency. Combining
expressions (3), (4), (6) and (8) with (20) yields:
( )
( ) ( ) [ ]
( )
*
1
2
0 0 1 0
2 *
, 1
2
cos 2 sin 2
C S
S S C
HF L
V t f L
t I L t V V
t i


(21)
The maximum value of the product [f
S
(t)i
L1,HF
(t)] appears
at
0
t = k + tan
-1
(L
1

0
I
S
/ V
S
), kZ, where it becomes:
( ) ( ) [ ]
1
*
max
, 1
2L
V
t i t f
C
HF L S
= (22)
This value must be lower than [f
S
(t)i
L1,HF
(t)]
admissible
. This
leads to the setting of L
1
:
( ) ( ) [ ]
min , 1
admissible
, 1
*
1
2
L
t i t f
V
L
HF L S
C

=

> (23)
Depending on the adopted control strategy (hysteresis-
based or saw-tooth-carrier-based), the inductor L
1
is
chosen according to (23) in order to limit either the
switching frequency or the high-frequency current ripple.
i
L1
*
i
L1
t

d
*
.T
S
T
S
= 1/f
S
i
L1,HF
Q
1
& Q
2
ON
(1-d
*
).T
S

slope
(v
1
- v
C
*
) /L
1
slope
(v
1
+ v
C
*
) /L
1
Q
1
& Q
2
OFF
Fig. 6: High-frequency waveform of the current in inductor L1 in CCM.
For the setting of inductor L
2
, we refer to expression
(16). The required value of L
2
must guarantee a CCM
operation of the converter, i.e. i
L2
*
(t) > 0, t. It yields:
min , 2
*
2 0
*
*
0
*
2
3
2
L
I
V
V
V V
L
L
S
C
C

=
+
>

(24)
Concerning the ratings of capacitors C and C
0
, their
calculation is based on equations (17) and (18)
respectively. For L
2
L
2,min
, it leads after some
mathematical manipulations to expressions (25) and (26)
given at the bottom.
V. CONTROL SYSTEMDESIGN
The control circuit is depicted in Fig. 7. It consists of
two successive loops: the inner or current one is designed
to ensure the wave-shaping of the DC input current i
L1
and,
consequently, the improvement of the input power factor,
while the outer or voltage loop is aimed to regulate the DC
load voltage and to stabilize it around a desired set-point.
( ) ( )
min
2
* 2
*
*
*
2
admissible 0
*
16 3 8
1 32
8 . 0 1
2 1
3
8
1 C
D
D
D
D
v V
I V
C
C C
S S

=
(

+
|
|

\
|
+

>

(25)
( )
min , 0
2
*
*
*
*
admissible 0 0
* 2
0
20 10
32 31
1
2 1
3
8
C
D
D
D
D
v V
I V
C
C
S S

=
|
|

\
|

>

(26)
845
The inner controller is chosen to be a hysteresis flip-flop
with a 0.4A width, and the outer regulator is a linear
Proportional-Integral (PI) one represented by the transfer
function H
v
(s). K
i
and K
v
are feedback scaling gains. To
ensure high stability of the control system, the outer loop is
designed to be enough slower than the inner one.
In addition, in order to emulate a pure resistor behavior,
the current reference must have the same shape as the
rectified source voltage v
1
, with an adjustable magnitude.
An analog multiplier is used for this purpose. Furthermore,
in order to avoid the distortion of the current reference, the
voltage control signal u
c
should be harmonic-free. This can
be satisfied by inserting a suitable second-order low-pass
filter, represented by the transfer function F
v
(s), in the
voltage feedback path.
VI. NUMERICAL IMPLEMENTATION AND SIMULATION RESULTS
In order to highlight the performance of the proposed
Sheppard-Taylor and SEPIC based converter in PFC
applications, a virtual version of the control system of Fig.
7 has been implemented using Matlab/Simulink. The
numerical values of the structural parameters and operating
conditions are listed in the appendix.
The converter is implemented according to the general
equations given in (1). The simulations are carried out
using a fixed-step ode5 (Dormand-Prince) solver. The step
size is 1s.
Steady-state results are given in Fig. 8 for a 1kW-load.
The line current THD is 6.6% and the power factor is
0.998. The switching frequency lies between 45kHz (at the
zero crossings of the line current i
s
) and 23.5kHz (at the
positive and negative peaks of i
s
). The DC output voltage
v
0
is stabilized at the reference value of 100V, with a 1.5%
ripple at 120Hz (twice the mains frequency). The voltage
of the intermediate capacitor C is also stabilized at 250V,
with a 0.6% ripple at 120Hz. Fig. 8 shows also that i
L1
, i
L2
and v
C
are always positive, and thus justifies the
assumption of a CCM/CVM operation made previously.
Figs. 9 and 10 present the system response to a 50%
decrease and increase of the load power, respectively. The
control system still exhibits a low current THD and a high
power factor. In addition, the output voltage returns to its
desired value in less than 0.7s.
VII. CONCLUSION
In this paper, a new non-inverted-polarity Sheppard-
Taylor based single-phase power factor corrector that
ensures perfect current tracking has been proposed and
analyzed. A CCM/CVM state-space averaged model of the
converter has been developed, and a multiple-loops control
system has been designed accordingly in order to achieve a
unity power factor at the mains and a regulated DC voltage
at the load side. The control scheme employs an inner
hysteresis-based current controller and an outer PI voltage
regulator. The converter and its control circuit were
implemented numerically using the Matlab/Simulink tool,
and the tracking and regulation performances of the control
system were evaluated.
~
K
i
+
_
Hysteresis
current controller
Multiplier
K
v
H
v
(s)
s
Q
u
c
+
V
0
*
F
v
(s)
Second order
low-pass filter
_
PI voltage
regulator
v
s
i
s
D
a
v
0
D
b
D
c
D
d
i
L1
v
1
i
0
C
L
2
+
_
L
1
C
0
Q
1
Q
2
D
1
D
2
D
3
D
4
Fig. 7: Control system.
846
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
-30
-20
-10
0
10
20
30
Time (seconds)
Source voltage and source current
v
s
/10
i
s
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
0
5
10
15
20
25
30
Time (seconds)
Currents in the input and intermediate inductors
i
L1
i
L2
(a) (b)
0 0.5 1 1.5
0
50
100
150
200
250
300
350
Time (seconds)
Voltages across the output and intermediate capacitors
v
0
v
C
(c)
Fig. 8: Steady-state performance at the rated load. Waveforms of (a) the source voltage and source current, (b) the currents in the input and intermediate
inductors, and (c) the voltages across the intermediate and load capacitors following a start-up.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
-15
-10
-5
0
5
10
15
Source current
Time (seconds)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
50
100
150
200
250
300
350
Time (seconds)
Voltages across the output and intermediate capacitors
v
0
v
C
(a) (b)
Fig. 9: Regulation performance to a sudden 50% load decrease applied at 0.05s. Waveforms of (a) the source current and (b) the voltages across the
intermediate and load capacitors.
847

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
-15
-10
-5
0
5
10
15
Source current
Time (seconds)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
0
50
100
150
200
250
300
350
Time (seconds)
Voltages across the output and intermediate capacitors


v
0
v
C


(a) (b)

Fig. 10: Regulation performance to a sudden 50% load increase applied at 0.05s. Waveforms of (a) the source current and (b) the voltages across the
intermediate and load capacitors.

APPENDIX: NUMERICAL VALUES

Mains voltage RMS-value V
S
= 120V
Rated load power P
0
= 1kW
Voltage reference V
0
*
= 100V
Mains frequency f
0
= 60Hz
DC inductors L
1
= 1mH, L
2
= 10mH
Series inductors resistors R
L1
= 0.1, R
L2
= 0.1
DC capacitors C = 10mF, C
0
= 10mF
Scaling gains K
i
= 1, K
v
= 1/108
Hysteresis width h = 1A
DC voltage regulator ( )
s
s
s H
v
15
1
20
+
=
Voltage filter ( )
2
300 300
2
1
05 . 0
|

\
|
+ +
=
s
s
s F
v

ACKNOWLEDGMENTS

The authors gratefully thank the Research Council of
Saint-Joseph University and Canada Research Chair in
Energy Conversion and Power Electronics for their
financial support.

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