Multi-Standard Receiver For BlMulti-Standard Receiver For Bluetooth and WLAN Applicationsuetooth and WLAN Applications

MULTI-STANDARD RECEIVER
FOR BLUETOOTH AND WLAN APPLICATIONS

DISSERTATION

Presented in Partial Fulfillment of the Requirements for
The Degree Doctor of Philosophy in the Graduate
School of The Ohio State University

By
Ho Kwon Yoon, M.S.E.E.
* * * * *

The Ohio State University
2004

Dissertation Committee: Approved by
Professor Mohammed Ismail, Adviser
Professor Patrick Roblin ____________________________________
Professor Oscar Y. Takeshita Adviser
Graduate Program in Electrical Engineering

Copyright by
Ho Kwon Yoon
2004

ii
ABSTRACT

This dissertation presents the multi-standard receiver architecture and the
corresponding RF front-end design supporting Bluetooth and IEEE 802.11a/b WLAN
standards with small form factor, low cost, and low power consumption. To maximize the
level of component share in the proposed multi-standard receiver, the corresponding
standards is analyzed and applied to the proposed multi-standard receiver architecture.
Zero-IF architecture is chosen for IEEE 802.11a/b WLANs, and low-IF architecture for
Bluetooth, respectively. The system specifications and the building block specifications is
derived from the corresponding standards and verified by spreadsheet models taking into
account of major design issues such as dc offset, flicker noise and image-rejection. The
spreadsheet simulation results prove the validity of the system analysis and the proposed
multi-standard receiver architecture.
This dissertation also presents the design of the RF front-end consisting of LNAs,
SDCs and downconversion I/Q mixers for multi-standard receiver mentioned above. To
reduce the current consumption and the die size of the RF front-end, single-ended LNAs
with dual gain are designed. For better even order linearity, the double-balanced mixer
topology is chosen for the downconversion mixer. In order to make these single-ended

iii
LNAs operating along with the double-balanced mixers, the on-chip balun, which is
called SDC in this dissertation, is placed between the LNA and the I/Q mixers.
Additionally, by placing the SDC between the LNA and the mixers, LO-RF isolation
would be much improved. The undesired bondwire and package parasitics is taken into
account during the schematic design and the layout. These undesired parasitic capacitors,
inductors, and resistors may affect the gain response and the input impedance matching
of the LNAs, and the gain and phase mismatch of the SDCs. The proposed RF front-ends
are fabricated with TSMC RF CMOS 0.18m process and experimental data is presented.
Although it shows the degradation of the gain and the input impedance to some extent,
the proposed RF front-end shows high linearity, very low corner frequency of the flicker
noise, negligible gain and phase mismatch, and low power dissipation for 2.4-GHz and
5.2-GHz frequency bands.

iv

I would like to dedicate this work to my family and friends.

v
ACKNOWLEDGMENTS

I would like to express the most sincere appreciation and gratitude to Professor
Mohammed Ismail for providing academic guidance and an opportunity to perform
research work at Analog VLSI Laoratory., the Ohio State University. Without his
commitment and encouragement, this dissertation would not have been possible. He has
helped me concentrate all my efforts on this work and encouraged me to have confidence
in my field of study.
I would like to express my appreciation to the colleagues at Analog VLSI Laboratory
who have spent last four years collaborating together days and nights. I really appreciate
their support and suggestions on my research work. I also would like to thank all old and
current Korean members at Analog VLSI Laboratory.
I would like to thank the Semiconductor Research Corporation for sponsoring my
research at Analog VLSI Laboratory, the Ohio State University as a part of the multi-
standard receiver design project. I would like to thank Waleed Khalil and Malcolm H.
Smith in Intel Corporation for giving me a valuable internship opportunity and
broadening my knowledge with many technical discussions.
I really appreciate Dr. Kyung-Hwan Park in ETRI, Korea and Dr. Chang-Ho Lee in
Georgia Institute of Technology, USA for their kind and valuable discussions though e-

vi
mails and international calls. I would like to express the deepest and saddest appreciation
to my old friend, Dr. Jae-kyung Jang who has been in heaven since August 2000.
Lastly and sincerely, I would like to express the deepest and warmest gratitude to my
parents, my wonderful lovely wife and my kids for their great sacrifices during my study
at the Ohio State University.

vii
VITA

January 26, 1968 .... Born Seoul, Korea
March, 1986 February, 1990 ... Bachelor of Science in Electronic
Communication Engineering,
Hanyang University, Seoul, Korea
March, 1990 July, 1990 .. Engineer, Hyundai Motors, Korea
August, 1990 July, 1992 . Master of Science in Electronic
Communication Engineering,
Hanyang University, Seoul, Korea
July, 1992 August, 2000 . Senior Engineer, DACOM Corp.
Seoul, Korea
September, 2000 present Ph.D., Electrical Engineering,
The Ohio State University,
Columbus, Ohio, USA
April, 2004 August, 2004 .. Intern, Intel Corporation, Phoenix,
Arizona, USA
August, 2004 present . Senior RF System Engineer,
Intel Corporation, Phoenix,
Arizona, USA.

viii
PUBLICATIONS
Ho-Kwon Yoon and Mohammed Ismail, A CMOS Multi-Standard Receiver
Architecture for Bluetooth and Wireless LAN Applications, IEEE International
Symposium on Circuits and Systems 2004, pp. 265-268, May, 2004, Vancouver, Canada
Ho-Kwon Yoon, H.-J. Kim and Mohammed Ismail, A CMOS Radio Receiver
Architecture for ISM/UNII Multi-Standard Wireless Applications, IEEE International
Conference on Electronics, Circuits and Systems 2003, pp. 16-19, December, 2003,
U.A.E.

FIELDS OF STUDY

Major Field: Electrical Engineering
Studies in RF/Analog IC Design: Professor Mohammed Ismail

ix
TABLE OF CONTENTS

Page
Abstract .... ii
Dedication ....... iv
Acknowledgments .. v
Vita . vii
List of Tables . xii
List of Figures ... xiv
Chapters:
1. Introduction . 1
1.1 Motivation 1
1.2 Research Contributions ... 2
1.3 Thesis Organization . 3
2. General Wireless Receiver Architecture ... 5
2.1 Introduction .. 5
2.2 Superheterodyne Receiver Architecture .. 6
2.3 Image Reject Receiver Architecture .. 9
2.3.1 Hartley Architecture .... 10
2.3.2 Weaver Architecture ... 12
2.4 Homodyne Receiver Architecture .. 16
2.5 Low-IF Receiver Architetcure ... 20
3. CMOS Receiver Architecture for Multi-standard Wireless Applications . 23
3.1 Introduction ... 23
3.2 Multi-Standard Receiver Architecture for Bluetooth and WLAN

x
Applications . 24
3.3 Overview of Bluetooth, IEEE 802.11b, and IEEE 802.11a Standards .. 27
3.3.1 Important Air Interfaces 27
3.3.2 Blocking Profiles .... 29
3.3.3 Intermodulation Characteristics .. 31
3.4 Top Level Receiver Specifications ...... 32
3.4.1 Noise Figure ... 33
3.4.2 Input-referred Third-order Intercept Point (IIP3) ...... 35
3.4.3 Input-referred Second-order Intercept Point (IIP2) ....... 38
3.4.4 Phase Noise 40
3.5 Design Specifications in n-cascade Stages ...... 43
3.5.1 Noise Figure in n-cascade Stages .. 44
3.5.2 Input-referred Third-order Intercept Point (IIP3) in n-cascade
Stages 47
3.5.3 Input-referred Second-order Intercept Point (IIP2) in n-cascade
Stages 54
3.6 Receiver Modeling and Building Block Specifications 57
3.7 Other Important Specifications .. 62
4. Fully-Integrated CMOS RF Front-End for Bluetooth and WLAN Applications
.... 66
4.1 Introduction 66
4.2 RF Front-end for Bluetooth and WLAN Applications ..... 67
4.3 Low Noise Amplifier .... 69
4.3.1 Input Impedance Matching .... 70
4.3.2 Noise Model ... 72
4.3.3 Design and Simulation Results .. 76
4.4 Single-Ended to Differential Converter 85
4.4.1 Passive Balun and Active SDCs 85
4.4.2 Common-Source Amplifier with Source Degeneration . 88
4.5 Downconversion Mixer 99
4.5.1 Flicker Noise .. 99
4.5.2 Linearity ...... 102
4.5.3 Phase Mismatch and Gain Reduction 104
4.6 Bondwire and Package Parasitics . 110
4.7 Simulation Results of RF Front-end .... 112
5. Experimental Results of RF Front-end 117
5.1 Introduction 117
5.2 Experimental Results of 2.4-GHz RF Front-end ... 120
5.3 Experimental Results of 5.2-GHz RF Front-end ... 128

xi
6. Conclusion ............ 138
Bibliography 143

xii
LIST OF TABLES

Table Page
3.1 Important air interfaces of three wireless standards .. 28
3.2 Overall system noise figures for Bluetooth and WLANs . 34
3.3 Overall system IIP3 for Bluetooth and WLANs 36
3.4 Overall system IIP2 for Bluetooth and WLANs . 40
3.5 Phase noise of local oscillator for Bluetooth and WLANs ... 42
3.6 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver
for Bluetooth Application .. 59

3.7 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver for IEEE
802.11b WLAN Application . 60
3.8 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver for IEEE
802.11a WLAN Application . 61
3.9 Spreadsheet modeling results and system requirements 62
3.10 Specification of high-pass filter for zero-IF WLANs ... 62
3.11 Specification of poly-phase filter for low-IF Bluetooth 63
3.12 Specification of low-pass filter . 63
3.13 Specification of variable gain amplifier . 63
3.14 Specification of ADC .... 63
4.1 Simulation results of 2.4GHz LNA with respect to corner,
supply voltage, and temperature variation .. 83

xiii
4.2 Simulation results of 5.2GHz LNA with respect to corner,
supply voltage, and temperature variation .. 84
4.3 Simulation results of SDC with respect to corner, supply voltage,
and temperature variation ... 98
4.4 Simulation results of the proposed mixer 109
4.5 Undesired parasitics from bondwire and package . 111
4.6 Summary of the post-layout simulation results of the RF front-ends . 116
5.1 Pin description of the test board 117
5.2 Summary of the measured performance of the proposed 2.4GHz RF front-end
.. 128
5.2 Summary of the measured performance of the proposed 5.2GHz RF front-end
.. 137

xiv
LIST OF FIGURES

Figure Page
2.1 Conventional superheterodyne receiver architecture ... 6
2.2 Rejection of image versus suppression of interferers for (a) high IF
and (b) low IF 8
2.3 Hartley image-reject receiver . 10
2.4 Weaver image-reject receiver . 12
2.5 Secondary image in Weaver architecture .. 13
2.6 IF image rejection mixers . 14
2.7 Homodyne receiver architecture ... 16
2.8 Self-mixing of LO signal in a direct conversion receiver .. 17
2.9 Second-order distortion in homodyne receivers . 20
2.10 Low-IF receiver architecture .. 21
2.11 Poly-phase filter for image rejection and the un-cancelled image 22
3.1 Proposed multi-standard receiver for bluetooth and WLAN applications 25
3.2 Frequency bands of the standards . 27
3.3 Blocking Profiles of (a) Bluetooth (b) IEEE 802.11b and (c) IEEE 802.11a .... 30
3.4 The third-order distortion .. 35
3.5 Cross-modulation due to transmission leakage in full duplex transceiver . 37
3.6 Second-order distortion due to the finite direct feedthrough 38

xv
3.7 Spectrums of an ideal oscillator and an actual oscillator .. 40
3.8 Reciprocal mixing of a nearby interferer with actual local oscillator .. 41
3.9 Noise degradation versus SIR (signal to reciprocal mixing interferer ratio) 43
3.10 A simple 2-stages and input-referred cumulative noise figure (NF
total,2-stages
) .. 45
3.11 A simple 3-stages and input-referred cumulative noise figure (NF
total,3-stages
) .. 46
3.12 Intermodulation in a nonlinear system .. 47
3.13 2-cascaded nonlinear stages . 49
3.14 2-cascaded nonlinear stages .. 55
3.15 Signal levels at each stage in the receiver for Bluetooth .. 64
3.16 Signal levels at each stage in the receiver for IEEE 802.11b .. 65
3.17 Signal levels at each stage in the receiver for IEEE 802.11a ... 65
4.1 Multi-standard transceiver 67
4.2 Block diagram of the proposed CMOS RF front-end 68
4.3 Commonly used CMOS LNAs; (a) common-gate and (b) common-source 71
4.4 Equivalent circuit for LNA noise calculation ... 73
4.5 The proposed LNA schematic .. 77
4.6 S11 and S12 of (a) 2.4GHz LNA and (b) 5.2GHz LNA .. 79
4.7 Noise Figure of (a) 2.4GHz LNA and (b) 5.2GHz LNA .. 80
4.8 Gain of (a) 2.4GHz LNA and (b) 5.2GHz LNA .. 81
4.9 IIP3 of (a) 2.4GHz LNA and (b) 5.2GHz LNA 82
4.10 Ring hybrid coupler . 86
4.11 Active single-ended to differential converters (SDCs) ..... 87
4.12 The proposed SDC schematic ... 89

xvi
4.13 Common-source amplifier with source degeneration (a) small signal circuit
and (b) equivalent circuit .. 90
4.14 Circuit for calculation of the output resistance of common-source amplifier
With source degeneration ..... 91
4.15 Source follower with drain resistor (a) small signal circuit
and (b) equivalent circuit .. 93
4.17 Gain of SDC .. 95
4.18 Noise Figure of SDC . 96
4.19 IIP2 and IIP3 of (a) 2.4GHz SDC and (b) 5.2GHz SDC . 97
4.20 Double-balanced mixer ... 100
4.21 Double-balanced mixer with current injection ... 103
4.22 Direct conversion mixer ... 105
4.23 Conversion gain of mixer (A
v,mixer
) versus phase imbalance ( ) .. 107
4.24 The proposed downconversion mixer . 109
4.25 Bondpad and package parasitics . 110
4.26 The layout of the proposed dual-band RF front-end .. 112
4.27 Gain response of 2.4GHz RF front-end .. 113
4.28 Noise figure (SSB) of 2.4GHz RF front-end .. 113
4.29 Linearity of 2.4GHz RF front-end in low-gain mode .. 114
4.30 Gain response of 5.2GHz RF front-end .. 114
4.31 Noise figure (DSB) of 5.2GHz RF front-end .. 115
4.32 Linearity of 5.2GHz RF front-end in low-gain mode . 115
5.1 Test board of the proposed RF front-end chip ... 118
5.2 Magnified photograph of the RF front-end chip on the test board . 119

xvii
5.3 Die photograph of the RF front-end chip 119
5.4 Measured input reflection coefficient S11 of the 2.4-GHz RF front-end ... 120
5.5 Measure flicker noise of the 2.4-GHz RF front-end .. 121
5.6 Measured down converted signal at 5-MHz IF frequency, RF at 2.44-GHz
and LO at 2.445-GHz .. 122
and LO at 2.441-GHz .. 123
5.8 Measured down converted signal at 200-KHz IF frequency, RF at 2.440-GHz
and LO at 2.4402-GHz 124
5.9 Measured gain response of the 2.4-GHz RF front-end .. 125
5.10 Measured 1-dB compression point of the 2.4-GHz RF front-end .. 126
5.11 Measured two-tone test of the 2.4-GHz RF front-end 127
5.12 Measured input reflection coefficient S11 of the 5.2-GHz RF front-end ... 129
5.13 Measure flicker noise of the 5.2-GHz RF front-end .. 130
and LO at 5.151-GHz .. 131
5.15 Measured down converted signal at 0.5-MHz IF frequency, RF at 5.15-GHz
and LO at 5.1505-GHz .... 132

5.16 Measured down converted signal at 200-KHz IF frequency, RF at 5.15-GHz
and LO at 5.1502-GHz .... 133
5.17 Measured gain response of the 5.2-GHz RF front-end .... 134
5.18 Measured 1-dB compression point of the 5.2-GHz RF front-end .. 135
5.19 Measured two-tone test of the 5.2-GHz RF front-end 136

1
CHAPTER 1

INTRODUCTION

1.1 Motivation

Various wireless communication standards have been introduced into markets during
the past decades and multi-standard wireless devices are now highly demanded to
accommodate different wireless standards in a single-chip, so called SOC (System-On-
Chip). Bluetooth has been introduced to connect any home or office appliances such as
personal computers, printers and TVs by using ISM band [1]. On the other hand, the
explosive growth of internet users has led to the proliferation of wireless local area
networks (WLANs). Wireless local area networks (WLANs) have been introduced in
ISM band (IEEE 802.11b/g) and UNII band (IEEE 802.11a) for high data rate wireless
communication up to 54Mbps [2], [3].
For multi-standard wireless receivers, receiver architectures and circuit topologies
should be explored and analyzed to reduce the development risk and the development
period before the actual receiver design begins. In the 1980s and 1990s, the most
popular receiver architecture for a single-standard wireless receiver was superheterodyne
architecture, which had been considered to provide the good performance and reduce the

2
development risk. However, this superheterodyne receiver architecture is not likely to
meet or satisfy the designers demands such as low cost and small form factor since
external components are needed to guarantee proper performance of the superheterodyne
receiver architecture; the image reject filter and the IF (intermediate frequency) filter.
Thus, recently, the RF designers have been looking for alternatives for the multi-standard
wireless transceiver, and homodyne architecture or low-IF architecture would be an
answer for the question.
In addition, the maximum share of RF and analog building blocks throughout the
entire receiver chain is also extensively demanded for the small form factor and low cost
multi-standard transceiver. In order to meet this requirement, the building blocks should
be shared as much as possible by different wireless standards. The maximum share of the
building blocks is as important as the receiver architecture for multi-standard wireless
receivers.

1.2 Research Contributions

The research motivation described above implies there is a huge need to explore
receiver architectures and circuit topologies for the multi-standard receiver with small
form factor, low cost and low power consumption. Moreover, programmability is also
required to provide the maximum share of the common building blocks and serve the
different wireless standards with less parallel signal paths. This dissertation investigates
the receiver architectures and the circuit topologies to simultaneously achieve these

3
challenging design goals of the multi-standard receiver for Bluetooth and WLAN
applications. Regarding these goals, some key research issues are summarized as below.

1. Investigated receiver architectures and proposed novel receiver architecture for
Bluetooth and WLNA standards.
2. Defined the receiver system specifications and the building block specifications
for Bluetooth and WLNA standards.
3. Proposed and designed the RF front-end for Bluetooth and WLNA standards.
4. Designed a 2.4-GHz LNA (Low Noise Amplifier) with dual gain for Bluetooth
and WLNA standards.
5. Designed a 5.2-GHz LNA (Low Noise Amplifier) with dual gain for WLNA
standard.
6. Designed a 2.4-GHz CMOS SDCs (Single-ended to Differential Converter) for
Bluetooth and WLNA standards.
7. Designed a 5.2-GHz CMOS SDCs (Single-ended to Differential Converter) for
WLNA standard.
8. Designed a low flicker noise CMOS active mixer for zero-IF/low-IF architectures.

1.3 Thesis Organization

Chapter 2 provides the investigation of well-know receiver architectures and the
comparison of one and others, and describes the practical issues of multi-standard
receiver architecture such as low-cost, small form factor and low power consumption. In

4
Chapter 3, novel multi-standard receiver architecture for Bluetooth and WLAN
applications is proposed and the corresponding standards are analyzed to derive the
important system specifications. Based on the proposed receiver architecture, the design
specifications for the building blocks are defined satisfying the system specifications in
terms of gain, noise figure, linearity and so on. Chapter 4 describes the proposed RF
front-ends, which is a part of the proposed multi-standard receiver for Bluetooth and
WLAN applications. Also, in Chapter 4, the design issues of the RF front-end, which
consists of LNA, SDC and mixers, is explored and described in details. Chapter 5
presents the experimental results of the proposed RF front-end. In Chapter 6, the
conclusion is presented

5
CHAPTER 2

GENERAL WIRELESS RECEIVER ARCHITECTURES

2.1 Introduction

The current interest in wireless communication devices is prompting research into
new IC technologies, circuit topologies, and transceiver architectures [4]. Low-power
consumption and small form factor in wireless transceivers have been sought to
communicate data in cellular networks, wireless local area networks, and radio
messaging systems. While transistor technology scaling and improved circuit techniques
will contribute evolutionary advances towards these goals, architectural innovations in
the transceiver may lead to significant improvements [4], [5]. In other words, transistor
technology scaling and transceiver architecture play main roles in wireless
communication transceiver to reduce the production cost and make the transceivers much
smaller, in turns, having the battery life longer.
As can be found in numerous papers, there are several receiver architectures;
superheterodyne architecture, homodyne architecture, image-reject architecture, and low-
IF architecture. In the following sections, these transceiver architectures are briefly
examined and described in terms of advantages and disadvantages.

6
2.2 Superheterodyne Receiver Architecture

The superheterodyne receiver architecture, which Armstrong introduced in 1918 [6],
is the most widely used architecture for wireless receivers during the past decades owing
to its high selectivity and sensitivity. In superheterodyne architecture, shown in Figure
2.1, implementation is achieved with a collection of discrete-component filters and
various technologies such as silicon bipolar and CMOS. As shown in Figure 2.1, there
are three discrete-component filters; RF filter, Image-Rejection filter, and IF filter. The
discrete-component RF filter removes out-of-band interferers or blockers and rejects
image-band signals as well [7]. The image-rejection filter, which usually follows the
LNA, further attenuates the unwanted signals presented at the image frequencies. The IF
filter, which follows the first downconversion mixer, reduces the distortion and dynamic
range requirements of the following stages in the receiver chain.

LO1
LNA
Image-Reject
Fiter
IF Filter LPF/VGA
I Q
ADC
RF Filter
LO2

Figure 2.1: Conventional superheterodyne receiver architecture

In superheterodyne receiver, the incoming RF signal is down-converted to the first
high IF and then to the second IF or zero IF. The main advantage over the homodyne
(zero-IF) receiver architecture is that it does not suffer from the flicker noise problem.

7
Due to the first high LO frequency, the first mixer will certainly suffer from large 1/f
noise at its output, but this will not corrupt the signal of interest, because it lies at an IF
far beyond the flicker noise corner frequency. Then a second LO, whose frequency is
equal to the first IF, downconverts the signal to DC (zero IF). The flicker noise at the
output of the second mixer is significantly lower in proportional to this second LO
frequency.
The superior performance of selectivity and sensitivity of the superheterodyne
architecture have made it the dominant choice in RF systems for many decades [8]. To
understand the relationship between the selectivity and the sensitivity, the fundamentals
of the image rejection should be speculated. The problem of image is a serious one in the
superheterodyne architecture. While each wireless communication standard limits signal
emission by its own users, it may not have any control over the signals in other bands [8].
Thus, the image power can be higher than the desired signal and proper image rejection
would be required. For this purpose, the image reject filter is used and usually placed
before the downconversion mixer.
An important issue may be raised regarding the IF frequency; How large can IF
frequency be? Figure 2.2 shows two cases corresponding to high IF and low IF so as to
illustrate the trade-off. A high IF could provide significant image rejection while a low IF
enables to suppress nearby interferers with great extent and make channel selection by
means of practical filters feasible. Thus, the choice of IF frequency depends on trade-offs
between image rejection and channel selection. Since the image degrades the sensitivity
of the receiver, the choice of the IF frequency entails a trade-off between sensitivity and
selectivity.

8

LO1
LNA
Image Reject
Fiter
Channel Select
Filter
Desired Signal
Interferer
Image Image Reject
Filter
Channel Select
Filter
f
RF
f
im
2f
IF
f
IF
0
f
RF
f
im
2f
IF
0 f
IF
(a)
(b)

Figure 2.2: Rejection of Image versus suppression of interferers for (a) high IF and (b)
low IF

9
However, the high Q associated with the discrete external components, image-reject
filter and IF-filter, found on a superheterodyne receiver is difficult and somewhat
impractical to realize at high frequency as an integrated solution [7]. An outstanding
performance with respect to selectivity, a measure of a receivers ability to separate the
desired band from the unwanted interferers or blockers presented at other frequencies,
and sensitivity, the minimal desired signal at the receivers input such that there is a
sufficient signal-to-noise ratio at the receivers output [9], [10], could only be achieved
with the use of high-Q discrete components in a superheterodyne receiver. Using these
discrete components, however, should not be preferred to the goal of fully-integrated
single-chip solution required by current wireless communication systems. For example,
the image-reject filter is usually realized with a passive, external component. Furthermore,
this requires that the preceding stage, the LNA, drive the 50- input impedance of the
filter, inevitably leading to more severe trade-off between the gain, noise figure, stability,
and power dissipation in the LNA. This trade-offs governing the use of image-reject
filters in the superheterodyne architecture have motivated RF designers to seek other
techniques of suppressing the image, which is known as image reject receiver
architecture [11], [12], [13].

2.3 Image Reject Receiver Architecture

The main idea of image-reject receiver architecture is to process the desired signal
and the image differently, which allows cancellation of the image by its negated replica.
The distinction between the desired signal and the unwanted image is possible since the

10
two lie on different sides on the LO frequency. In this section, two image reject
architectures, Hartley architecture and Weaver architecture, are discussed in detail.

2.3.1 Hartley Architecture

Figure 2.3 shows a commonly used image-reject receiver architecture originating
from a single-sideband modulator introduced by Hartley in 1928 [14]. Hartley circuit
mixes the RF input with the quadrature phases of the local oscillator, sin
LO
t and cos
LO
t,
low-pass filters the resulting signals, and shifts in-phase of the resulting signals by 90.
And then by adding in-phase signal and quadrature-phase signal together, the unwanted
image is finally cancelled.

A
LPF
sinw
LO
t
LPF
cosw
LO
t
R
R
C
C
90
o
Shifter
Image
Desired
Channel
0
0
w
LO
0
0
0
B

Figure 2.3: Hartley image-reject receiver

11
It can be best understood in the interpretation of frequency domain as shown in
Figure 2.3. The spectra at points A and B contain the desired signal with the same
polarity and the unwanted image with opposite polarity. The summed output provides
desired signal free from the unwanted image.
However, the principal drawback of the Hartley architecture is its sensitivity to
mismatch; due to the phase imbalance in LO and the gain imbalance of the 90 shifter,
the image cancellation is incomplete and the image corrupts the downconverted signal.
The effects of the gain mismatch () and the phase imbalance ( ) of the LO signal on
image rejection can be shown by calculating the image rejection ratio (IRR).
For << A
LO
and << 1-rad, IRR can be reduced to

4
) (
2 2
+
=
LO
A
IRR (2.1)

The above analysis includes only the gain and phase mismatch of the LO signal. For
typical matching in integrated circuits, IRR falls in the range of 30 to 40dB [15], [16],
which corresponds to 0.2 to 0.6dB of gain mismatch and 1 to 5 of phase imbalance [8].
Another critical issue of the Hartley architecture is the gain imbalance resulting from
the 90 shifter. In Figure 2.3, the 90 phase shifter produces equal gains only at
IF
=
1/(RC). If the absolute values of R and C vary with process and temperature, a gain
imbalance arises. For example, a variation of 20% of R/R limits IIR to only 20dB. In
most wireless receivers, the overall image suppression must be 60 to 70 dB. Now recall

12
that RF bandpass filter in the receivers provides significant attenuation at the image
frequency if the IF frequency is relatively high. Therefore, with proper choice of IF
frequency, Hartley architecture may achieve the required overall image rejection.
However, in this architecture, the matching requirements are much more stringent than
those in homodyne receiver architecture. Other drawback of the Hartley architecture is
that it suffers from the noise of the adder and the noise of the 90 phase shifter.

2.3.2. Weaver Architecture

C
LPF
sinw
LO1
t
LPF
cosw
LO1
t
Image
Desired
Channel
w
LO1
0
0
0
D
sinw
LO2
t
cosw
LO2
t
0
0
-
+

Figure 2.4: Weaver image-reject receiver

The Weaver architecture is an alternative to the Hartley architecture. Figure 2.4
shows the Weaver architecture [17] recently used as a simplified form in [11] and [12].
The Weaver architecture replaces the 90 shifter by a second quadrature mixing operation
to perform fundamentally the same function as RC-phase shifters do in the Hartley

13
Architecture, which produces the opposite polarities for the desired signal and the same
polarities for the unwanted image. Thus, if the final output is subtracted, the desired
signal is obtained without corruption and the unwanted image is cancelled; if they are
added, the desired signal is cancelled out and the unwanted image is obtained.

w
LO1
2w
LO2
-w
in
+2w
LO1
w
in
0
RF Input
w
LO2
2w
LO2
-w
in
+w
LO1
0
First IF
w
in
-w
LO1
0
Second IF
w
in
-w
LO1
-w
LO2
Interferer
Desired
Signal

Figure 2.5: Secondary Image in Weaver architecture

14
The Weaver architecture, however, has the incomplete image rejection due to the gain
and phase mismatch. Another drawback in the Weaver architecture is the secondary
image problem. If the second downconversion mixer translates the IF signal to nonzero
frequency, the image of the unwanted secondary image (interferer) may not be cancelled
and fall into the desired channel. Figure 2.5 illustrates this secondary image problem in
Weaver architecture. As can be seen in Figure 2.5, suppose that an interferer is at 2
LO2

in
+ 2
LO1
. After the first downconversion, the interferer appears at 2
LO2

in
+
LO1

as the image of the desired signal with respect to
LO2
. In the second downconversion,
the interferer is not canceled since it is originally on the same side of
LO1
as the desired
signal. For this reason, the low-pass filter in Figure 2.4 must be replaced with bandpass
filter to suppress the secondary image [8].
Unlikely 1970s and 1980s, recent wireless standards have been using the digital
modulation/demodulation techniques such as QPSK, OQPSK, GMSK, QAM and so on.
It means that in-phase and quadrature-phase signals are required to transmit and receive
data. Thus, in order to accommodate recent wireless standards, Weaver architecture in
Figure 2.4 should be modified as shown as Figure 2.6 [7], [18].
The graphical representation of the IF image rejection mixers are shown in Figure 2.6.
Basically, the IF image rejection mixers utilize the fundamentals of Weaver architecture.
Only difference between Weaver architecture and this IF image rejection mixers is that IF
image rejection mixers have an ability to accommodate in-phase and quadrature-phase
signals. If the desired signal lies on high side with respect to f
LO1
, the Q-Q signal should
be subtracted from the I-I signal in order to generate I-phase signal, and the I-Q signal
should be added to the Q-I signal in order to generate Q-phase signal.

15
LO1I
LO2I
LO2I
LO1Q
LO2Q
LO2Q
I
Q
I-I
I-Q
Q-I
Q-Q
LNA Output
-fLO1 fLO1
1 2 3 4
-fIF fIF
1&3 4&2
-fIF
fIF
j
4&2
4&3
1&2
j
2&3
4&1
-
j
1&3
1,2,3 & 4
j
1
4
Q-Phase
1 & 4
I-Phase
-
2 & 3
I-Phase
j
3
2
Q-Phase

Figure 2.6: IF image rejection mixers

If, on the contrary, the desired signal lies on low side with respect to f
LO1
, the Q-Q signals
should be added to the I-I signal and the Q-I signal should be subtracted from I-Q signal.
It is noteworthy that the IF image rejection mixers in Figure 2.6 demand 2 pairs of
quadrature mixers for I and Q-phase signals. The performance of image rejection mixers
would depend on the gain mismatch and the phase mismatch. Since there are four mixers
involved in I/Q-phase signals, these four mixers should be as same as possible and the
layout should be done not to have the gain and phase imbalance. Otherwise, the image
rejection would be incomplete due to the gain and phase mismatch. Furthermore, the
configuration of the second downconversion mixers is much more complicated than that
of superheterodyne architecture since it requires addition and subtraction. It may result in
large size and high-cost receiver chip, which is not preferable in the current trend of

16
fully-integrated receiver design. This trade-offs governing the use of four image-rejection
mixers in the image reject receiver architecture have motivated RF designers to seek
homodyne receiver architecture as known as zero-IF architecture [4], [19], [20].

2.4 Homodyne Receiver Architecture

Figure 2.7 shows the homodyne receiver architecture, generally known as direct
conversion receiver architecture or zero-IF architecture, where the LO frequency is equal
to the RF input frequency. The main advantage of homodyne receiver architecture over
the superheterodyne architecture or image reject architecture is that it is very suitable for
a fully-integrated receiver chip design and provides low-cost, low-power consumption,
and small form factor chip solution.

LNA
LPF/VGA
I Q
ADC
RF Filter
LO

Figure 2.7: Homodyne receiver architecture

This is because it has a simple RF front-end circuitry. In other words, it does not
either require an image reject filter and IF filters which the superheterodyne receiver
architecture needs, or a 90-shifter and complicated image rejection mixers which the

17
image reject receiver architecture needs, respectively. Note that channel selection
requires only a low-pass filter with relatively sharp cutoff characteristics, which is
amenable to monolithic integration.
On the other hand, the homodyne receiver architecture has two main drawbacks, dc-
offset and 1/f noise, when compared with superheterodyne receiver architectures or image
reject receiver architectures.
As shown in Figure 2.8, in homodyne receiver architecture, dc offset and 1/f noise in
the RF front-end can hugely degrade sensitivity especially for narrow band channels
which lie at zero frequency (DC). Due to the capacitive and substrate coupling, local
oscillator (LO) signal, which is the same frequency as incoming RF carrier frequency,
could feed through the LNA, the mixer, or even the antenna. The LO leakage signal
appearing at the inputs of the LNA and the mixer is now mixed with the LO signal and
produces a time-varying DC offset. A similar effect occurs if a large interferer leaks from
the LNA or mixer input to the LO port and is multiplied by itself [8]. This DC-offset is a
serious problem since the gain of the baseband chain consisting of LPFs and VGAs is
typically 50 to 70 dB. Thus, if directly amplified by 50 to 70 dB, the DC offset voltage
saturates the following stages and prohibits the amplification of the desired signal.

LPF
coswot
LNA
wo
0

Figure 2.8: Self-mixing of LO signal in a direct conversion receiver

18
It has been shown [21], [22] that the 1/f noise at the mixer output due to commutating
MOS switches is inversely proportional to S x T, where S is the slope of the LO
waveform and T is the LO period.

WL T S
IR
sw n o n
1
where
4
2
sw n, , ,

= (2.2)

In homodyne receivers, the LO is the same frequency as the RF carrier frequency.
Thus, the period T is extremely small and, as a result, output flicker noise is usually large.
It is impractical to lower this 1/f noise by scaling up the area of the mixer switches, since
the power consumption of the LO buffer driving the large mixer parasitic capacitance is
likely to get out of hand. Instead, it will be better that the S x T products of the LO
waveform driving the mixer may be made larger by using the right frequency plan. This
leads most RF front-end designers to turn back to the superheterodyne receiver
architectures. The previous works [21] show that dual conversion to zero IF is an
effective way to alleviate 1/f noise at the mixers output.
However, this 1/f noise could not be problematic if silicon BJTs are used for LO
switching pairs since BJTs are inherently free from the 1/f noise. Even if CMOS devices
are used for LO switching pairs, the 1/f noise problem could be alleviated by using p-
MOS devices instead of n-MOS devices and small DC biasing current flowing through
them. Especially, for wireless standards with wide channel bandwidth, using a high-pass
filter with several tens-KHz cutoff frequency, the 1/f noise can be easily removed without
distortion of the desired signal.

19
Another drawback in the homodyne architecture is even-order distortion, that is,
second-order distortion. While odd-order distortion has been considered a source of the
interferer in any receivers, even-order distortion also could become problematic in
homodyne receiver architecture. As illustrated in Figure 2.9, assume that two strong
interferers are close to the desired signal. If the LNA has a nonlinearity such as

( ) ( ) ( ) t x t x t y
2
2 1
+ = (2.3)

and the two interferers are expressed as

( ) t A t A t x
2 2 1 1
cos cos + = (2.4)

, then output y(t) of the LNA contains a term such as

t A A ) cos(
2 1 2 1 1
(2.5)

Equation (2.5) indicates that two interferers close to the desired channel generate a
low-frequency beat due to the nonlinearity of the LNA. Upon downconversion by
cos
LO
t in a mixer, the term in equation (2.5) is translated to high frequency and does not
seem to be problematic. In fact, however, mixers exhibit a finite RF-IF isolation. Thus, a
fraction of equation (2.5) appears at the output of the mixer without frequency translation
and corrupts the desired signal as illustrated in Figure 2.9.

20

cosw
LO
t
LNA
Desired
Signal
Interferers
0
f
LO
f
LO
0
Feedthrough

Figure 2.9: Second-order distortion in homodyne receivers

2.5 Low-IF Receiver Architecture

The dc-offset and the flicker (1/f) noise problems in the homodyne receiver
architecture have led RF designers to seek low-IF receiver architecture. Instead of
translating the RF signal to zero frequency, the low-IF architecture downconverts the RF
signal to IF frequency, which is close to DC (zero frequency). Figure 2.10 shows the low-
IF receiver architecture generally used as an alternative of homodyne receiver
architecture.
The low-IF receiver architecture also suffers from the image problem as similarly as
the superheterodyne receiver architecture does. However, the image reject filter in the
superheterodyne architecture, which is a discrete off-chip component, is now replaced
with poly-phase filter as shown as figure 2.10. The poly-phase filter is a complex filter

21
which has a considerable attenuation in the negative frequency, that is, the image
frequency band. Owing to the poly-phase filter, the main obstacle toward the monolithic
integration, which is the off-chip image reject filter in superheterodyne architecture, has
been removed. Practically speaking, the image rejection provided by the poly-phase filter
may not be complete due to the gain and phase mismatch inherited from the processing
variation or insufficient attenuation in the image frequency. Figure 2.11 illustrates this
un-cancelled image problem.

LNA
RF Filter LPF/VGA
I Q
ADC
LO1
Poly
Phase
Filter
LO2I
LO2I
LO2Q
LO2Q
I-I
I-Q
Q-I
Q-Q
Analog Digital

Figure 2.10: Low-IF receiver architecture

The IF signal in analog domain is now translated to zero frequency (dc) in digital
domain as shown as in Figure 2.10. It is noteworthy that the quadrature mixers are used

22
for further image rejection when the IF signal is downconverted to zero frequency in the
digital domain [23]. The image rejection provided by the qaudrature mixers are the same
concept as explained in Figure 2.6 IF image rejection mixers.
The low-IF frequencies, which have been chosen for various wireless standards,
could be from several-KHz to several-MHz considering the interferers levels according
to the corresponding standard.

0Hz
LO1
Mixer
RF LO1
Uncancelled
Image
Interfers
Poly-Phase
Filter

Figure 2.11: Poly-phase filter for image rejection and the un-cancelled image

23
CHAPTER 3

CMOS RECEIVER ARCHITECTURE FOR MULTI-STANDARD WIRELESS
APPLICATIONS

3.1 Introduction

As various wireless communication standards have been introduced into the market,
multi-standard transceivers with low cost, small form factor and low power consumption
are highly demanded for customer satisfaction. For multi-standard wireless receivers,
receiver architectures should be explored and analyzed to reduce the development risk
and the development period before the actual receiver design begins.
During the past decades, the most popular receiver architecture for a single-standard
receiver was superheterodyne architecture, which had been considered to provide the
good performance and reduce the development risk. However, superheterodyne receiver
architecture is not likely to meet the designers demands such as low cost and small form
factor since external components are needed to guarantee the proper performance. Thus,
recently, the RF designers have been searching for alternatives for the multi-standard
wireless transceiver, and probably zero-IF (homodyne) architecture or low-IF architecture
would be an answer for this question.

24
3.2 Multi-Standard Receiver Architecture for Bluetooth and Wireless LAN
Applications

Direct conversion (homodyne or zero-IF) receiver architecture is used for IEEE
802.11a/b and low-IF architecture is used for Bluetooth. In IEEE 802.11a, the center
subchannel is unused [24], which means that there is an empty spectrum of 312.5KHz in
the middle of the bandwidth, and the empty center sub-channel can be used for dc-offset
cancellation. Thus, if the corner frequency of the high-pass filter is below 156.25KHz,
the neighboring subchannels carrying the information data are not affected. In IEEE
802.11b, the 22MHz-channel bandwidth is fully used to carry the information. But, if the
corner frequency of the high-pass filter is 0.1% of the data rate, the degradation of the
QPSK signal is negligible [25]. This method is much easier to implement comparing with
the feedback loop [26], [27] for the dc-offset cancellation. This method also alleviates 1/f
noise problem in zero-IF architectures. 1/f noise is primarily generated by the
commutating switches of mixers and the baseband circuits. Since 1/f noise is inversely
proportional to the size of the devices, increasing the size of the devices can reduce the
1/f noise.
For Bluetooth, low-IF architecture is preferred rather than zero-IF architecture. This
is because the modulation scheme of Bluetooth is gaussian frequency shift keying
(GFSK). Since the spectrum of GFSK has considerable energy spectrum at zero
frequency, a high-pass filter cannot be used to remove the dc offset with minimum
distortion of the received signal. In low-IF architectures, image rejection is an important
issue. Thus, poly-phase filters, which are complex filters with considerable attenuation at
the negative frequency, are used for the image rejection in low-IF architectures.

25
Figure 3.1 shows the proposed multi-standard receiver for Bluetooth and wireless
LANs (IEEE 802.11b and IEEE 802.11a). Bluetooth and IEEE 802.11b share exactly the
same frequency band, which is know as ISM (Industrial, Scientific, and Medical) band
from 2.4GHz to 2.4835GHz. IEEE 802.11a uses the frequency band known as UNII
(Unlicensed National Information Infrastructure) band, which is from 5.15GHz to
5.35GHz and from 5.725 to 5.825GHz.

SDC
ADC
ADC
D
S
P
LO
90
o
HPF
PPF
PPF
HPF
LPF/VGA
LPF/VGA
2.4GHz
LNA
5GHz
LNA
RF
Filter
RF
Filter
3-Throw
Switch
Antenna
I
Q

Figure 3.1: Proposed multi-standard receiver for Bluetooth and WLAN applications

Since Bluetooth and IEEE 802.11b share the same frequency band from 2.4GHz to
2.4835GHz, the RF filter and the LNA can be shared for the two standards. Thus, a 3-
throw switch can be used instead of a 4-throw switch for three different standards and
select appropriate receive mode or transmit mode. Two RF filters select corresponding

26
frequency bands and also suppress interferers or blockers far away from the frequency
band of interest.
For less even-order distortion, double-balanced mixers are used as direct conversion
mixers. This is because, in direct conversion receiver architecture, low frequency beat
produced by the non-linearity of the LNA can appear at the output of the mixer and
corrupt the desired signal. Thus, high IIP2 (Input referred 2
nd
order Intercept Point) is
required especially for direct conversion architecture. Since the LNAs are single-ended
and the double-balanced mixers need differential RF inputs, single-ended to differential
converter (SDC) is required between the single-ended LNAs and the I/Q double-balanced
mixers. By placing the SDC between the LNAs and the mixers, the LO leakage to the
LNA or the antenna can be reduced to some extent and, additionally, the conventional
off-chip BALUN is now replaced and integrated into the chip. To maximize the level of
the hardware share, the resistors are used as the loads in the SDC and the mixers. Thus
the SDC and the mixers can be shared for the three standards because of the wideband
characteristics of the transconductance.
The high-pass filters are activated only for dc offset removal for IEEE 802.11a and
IEEE 802.11b whereas the poly-phase filters are operational for the image rejection only
for Bluetooth. The low-pass filters in the LPF/VGA chains should be programmable to
change the cutoff frequency among 1, 10, and 11MHz and select the desired channels. To
adjust the desired signal level at the appropriate level at the input of the ADCs, the
variable gain amplifier is required. The gain range of the VGA is determined considering
the minimum and maximum reception levels for each standard. The ADCs are
programmable for multi-standards. It is noteworthy that the RF band-pass filters and the

27
T/R switch are only the off-chip components, and all the other building blocks are
integrated into a single chip.

3.3 Overview of Bluetooth, IEEE 802.11b, and IEEE 802.11a Standards

In this section, the air interfaces, the blocking profiles, and the intermodulation
characteristics of the three standards are introduced and briefly explained.

3.3.1 Important Air Interfaces

Figure 3.2 shows frequency bands of Bluetooth, IEEE 802.11b and IEEE 802.11a
standards.

Bluetooth
IEEE
802.11b
IEEE 802.1a
(lower band)
IEEE
802.11a
(upper
band)
2
4
0
0

M
H
z
2
4
8
3
.
5

M
H
z
5
1
5
0

M
H
z
5
3
5
0

M
H
z
5
7
2
5

M
H
z
5
8
2
5

M
H
z

Figure 3.2: Frequency bands of the standards

The important air interfaces of the three wireless standards are listed in Table 3.1 [1],
[2], [3]. The bandwidths are 1MHz for Bluetooth, 22MHz for IEEE 802.11b, and 20MHz

28
Bluetooth IEEE 802.11b IEEE 802.11a
Frequency Bands 2.4 ~ 2.4835GHz 2.4 ~ 2.4835 GHz
5.15 ~ 5.25 GHz
5.25 ~ 5.35 GHz
5.725 ~ 5.825 GHz
Bandwidth 1MHz 22 MHz 20 MHz
Channel Spacing 1MHz 5 MHz 20 MHz
NO. of Channels 79* 13**
4***
4****
4*****
Modulation Scheme GFSK
DBPSK (1Mbps)
DQPSK (2 & 5.5
Mbps)
QPSK (11Mbps)
BPSK(6 & 9 Mbps)
QPSK(12 & 18
Mbps)
16QAM(24 & 36
Mbps)
64QAM(48 & 54
Mbps)
Multiple Access FHSS
DSSS
CCK
OFDM
Duplexing TDD TDD TDD
Inband & Out-of-Band
Blocking Profile
Refer to section 3.3.2
Intermodulation
Characteristics
Refer to section 3.3.3
Minimum Sensitivity -70dBm -76dBm
-82 dBm(6Mbps)
-81 dBm(9Mbps)
-79 dBm(12Mbps)
-77 dBm(18Mbps)
-74 dBm(24Mbps)
-70 dBm(36Mbps)
-66 dBm(48Mbps)
-65 dBm(54Mbps)
Maximum Sensitivity -20dBm -10 dBm -30 dBm
QoS BER 10
-4

FER= 8* 10
-2

(BER 10
-3)

PER 10
-1

( BER 10
-3
)
* f
c
= 2402 + k MHz, k = 0, 1, 2, ., 78
** f
c
= 2412 + k *5 MHz, k = 0, 1, 2, ., 12
*** f
c
= 5180 + k * 20 MHz, k = 0, 1, 2, 3
**** f
c
= 5260 + k * 20 MHz, k = 0, 1, 2, 3
***** f
c
= 5745 + k * 20 MHz, k = 0, 1, 2, 3

Table 3.1 Important air interfaces of three wireless standards

for IEEE 802.11a, respectively. For Bluetooth and IEEE 802.11a, the channel spacing is
the same as the channel bandwidth. For IEEE 802.11b, however, the channel spacing is

29
5MHz while the channel bandwidth is 22MHz. The modulation scheme is GFSK
(Gaussian Frequency Shift keying) for Bluetooth, QPSK (Quadrature Phase Shift
Keying) for high data rate IEEE 802.11b, and 16 or 64QAM (Quadrature Amplitude
Modulation) for high data rate IEEE 802.11a, respectively. The multiple access schemes
is FHSS (Frequency Hopping Spread Spectrum) for Bluetooth, CCK (Complementary
Code Keying) for high data rate IEEE 802.11b, and OFDM (Orthogonal Frequency
Division Multiplexing) for high data rate IEEE 802.11a. Duplexing is TDD (Time
Division Duplex) for all three standards. Note that IEEE 802.11a has different minimum
sensitivity requirements according to the data rate and IEEE 802.11b requires -10dBm
maximum sensitivity.

3.3.2 Blocking Profiles

The blocking profiles for the three standards are illustrated in Figure 3.3. Note that
since the blocking profile of IEEE 802.11b is not specified in the corresponding standard,
it is derived from Bluetooth standard because IEEE 802.11b operates at the same
frequency band as Bluetooth does. Similarly, since the blocking profile of IEEE 802.11a
is not specified in the corresponding standard, the blocking profile of IEEE 802.11a is
adopted from HIPERLAN2 standard. This is because that the air-interface of IEEE
802.11a is almost the same as that of HIPERLAN2 [28]. The blocking profile is one of
the most important specifications to define top-level system specifications such as phase
noise requirements of VCO in receivers.

30
In-Band Out-of-Band Out-of-Band
-20dBm -20dBm -20dBm -20dBm
-30dBm -30dBm
-60dBm
F
o
+
1
M
H
z
F
o
-
1
M
H
z
F
o
+
2
M
H
z
F
o
+
3
M
H
z
F
o
-
2
M
H
z
F
o
-
3
M
H
z
Fo 2399MHz 2498MHz

(a)
-20dBm -20dBm
-43dBm -43dBm
-73dBm
F
o
+
2
2
M
H
z
F
o
-
2
2
M
H
z
F
o
+
4
4
M
H
z
F
o
-
4
4
M
H
z
Fo 2378MHz 2510MHz

(b)
-30dBm -30dBm -30dBm -30dBm
-79dBm
F
o
+
5
0
M
H
z
F
o
-
5
0
M
H
z
Fo 5150MHz 5350MHz

(c)
Figure 3.3: Blocking profiles of (a) Bluetooth (b) IEEE 802.11b and (c) IEEE 802.11a

31
3.3.3 Intermodulation Characteristics

The intermodulation characteristics of the standards are used to calculate the linearity
requirements such as IIP2 (Input referred 2
nd
-order Intercept Point) and IIP3 (Input
referred 3
rd
-order Intercept Point), which are the most fundamental and important top-
level system specifications. Since the intermodulation characteristics of IEEE 802.11b are
not given in the corresponding standard, they are derived from Bluetooth standard
because IEEE 802.11b uses the same frequency band as Bluetooth does. Similarly,
another assumption is made for the intermodulation characteristics of IEEE 802.11a.
Since they are not specified in the standard, the intermodulation characteristics of IEEE
802.11a are adopted from HIPERLAN2 standard. This is because that the air- interface of
IEEE 802.11a is almost the same as that of HIPERLAN2 [28].

Bluetooth: The reference sensitivity (-70dBm) performance, BER=0.1%, shall be
met under the following conditions.
The wanted signal at frequency fo with power level 6dB over the reference
sensitivity level
A static sine wave signal at f1 with a power level of -39dBm
A Bluetooth modulated signal at f2 with a power level of -39dBm
such that fo=2f1-f2 and |f2-f1|=n*1MHz, where n can be 3, 4, or 5. The system must
fulfill one of the three alternatives.

32
IEEE 802.11b: The reference sensitivity (-76dBm) performance, FER=8* 10
-2
, shall
be met under the following conditions.
sensitivity level
An IEEE 802.11.b modulated signal at f2 with a power level of -45dBm

IEEE 802.11a: The reference sensitivity performance, PER=10
-1
, shall be met under
the following conditions.
sensitivity level
An IEEE 802.11.a modulated signal at f2 with a power level of -45dBm

3.4 Top-Level Receiver Specifications

There are several top-level receiver specifications such as noise figure, linearities,
phase noise and dynamic range of ADC (Analog-to-Digital Converter). These top-level
receiver specifications can be directly extracted by analyzing the corresponding standards.

33
In the following sub-sections, these top-level receiver specifications are discussed and
obtained by analyzing the corresponding standards.

3.4.1 Noise Figure

Noise figure is a measure of how much the SNR (Signal to Noise Ratio) degrades as
the received signal passes through a receiver [8]. Noise Figure can be defined in several
different ways. The most common definition of noise factor, which becomes noise figure
by taking 10LOG, is

out
in
SNR
SNR
r noisefacto = (3.1)

The relationship between the required SNR, which is required to maintain the required
BER (Bit Error Rate), and the overall system noise figure (NF
system
) is expressed by [29]

) ( 10 / 174
min
BW Log SNR Hz dBm P NF
req system
+ = (3.2)

, where P
min
is minimum sensitivity, SNR
req
is minimum SNR for certain BER, and BW is
channel bandwidth.
Based on the air-interfaces in Table 3.1, the overall system noise figure (NF
system
) is
calculated by using Equation (3.2) and summarized in Table 3.2. Overall system noise

34
figure (NF
system
) is 22dB for Bluetooth, 10.6dB for IEEE 802.11b with 11Mbps data rate,
and 15dB for IEEE 802.11a.

Minimum
Sensitivity
-70dBm -76dBm
-82 dBm(6Mbps)
-81 dBm(9Mbps)
-79 dBm(12Mbps)
-77 dBm(18Mbps)
-74 dBm(24Mbps)
-70 dBm(36Mbps)
-66 dBm(48Mbps)
-65 dBm(54Mbps)
Input Noise -114dBm -100.6dBm -101dBm
Input SNR 44dB 24.6dB
19dB
20dB
22dB
24dB
27dB
31dB
35dB
36dB
Required SNR 23dB
-2dB (1Mbps, PG*
of 10.4dB)
1.6dB(2Mbps, PG*of
7.4dB)
11dB(5.5Mbps)
14dB(11Mbps)
4dB
5dB
7dB
9dB
12dB
16dB
20dB
21dB
Overall System NF
(NF
system
)
21dB
26.6dB(1Mbps)
23dB(2Mbps)
13.6dB(5.5Mbps)
10.6dB(11Mbps)
15dB
*: Processing Gain
Table 3.2 Overall system noise figures for Bluetooth and WLANs

35
3.4.2 Input-referred Third-order Intercept Point (IIP3)

In direct conversion receiver architecture or low-IF architecture, the 3
rd
-order
distortion and the 2
nd
-order distortion should be carefully considered since these
unwanted signals can lie in the downconverted channel and corrupt the desired signal.
If large in-band interferers accompany the desired signal, the nonlinearity of the LNA
and the mixer becomes important. This is because in-band interferers cannot be
attenuated by RF band-pass filter. Among odd-order nonlinearities, third-order distortion
is usually dominant. Figure 3.4 illustrates third-order distortion in the front-end. For the
given interferers at
1
and
2
close to the desired signal, the third-order intermodulation
products (IM3) appear at 2
1
-
2
and 2
2
-
1
. As the magnitude of the interferers gets
large, the magnitude of the third-order intermodulation products also gets large and
distorts the desired signal. The input-referred third-order intercept point (IIP3) is
considered a measure of how linear the system (or circuit) is. Thus, IIP3 of each stage
should be sufficiently high to avoid corruption of the desired signal by the third-order
intermodulation products (IM3).

w
1
w
2
2w
1
-w
2
2w
2
-w
1
w
w
1
w
2
w
BPF
LNA
Desired
Channel
Interferers

Figure 3.4: The third-order distortion

36
The overall system input-referred third-order intercept point, IIP3
system
, can be
calculated by using intermodulation characteristics defined in section 3.3.3. The overall
system input-referred third-order intercept point (IIP3
system
) can be obtained by [29].

2
3
int
int
M SNR P P
P IIP
req sig
system
+ +
+ = (3.3)
, where P
int
is the power of the interferer, P
sig
is the power of the desired signal, SNR
req
is
the required SNR, and M is the system margin, which is usually 6dB.

Table 3.3 summarizes the required IIP3system. The required IIP3
system
is -17.5dBm
for Bluetooth, -22.5dBm for IEEE 802.11b with 11Mbps data rate, and -24.5dBm for
IEEE 802.11a, respectively.

Overall System
IIP3
system

-17.5dBm
-30.5dBm (1Mbps)
-29dBm (2Mbps)
-24dBm (5.5Mbps)
-22.5dBm (11Mbps)
-24.5dBm

Table 3.3 Overall system IIP3 for Bluetooth and WLANs

Another important issue in the transceiver design is the cross-modulation especially
for full duplex systems such as IS-95 and WCDMA systems [30], [31], [32]. Figure 3.5
shows the conventional full duplex systems, which means that transmission and reception
can be operational simultaneously. Generally, the duplexer has a finite Tx-Rx isolation

37
and the sufficiently large transmission signal, so called transmission leakage, can appear
at the input of the LNA. If this transmission leakage is accompanied by a blocker which
is very close to the desired channel, the LNA may experience cross modulation of the
blocker with interfering transmission leakage and eventually the cross modulation may
significantly desensitize the LNA. Thus, to minimize this undesired cross-modulation
effect on the LNA, the LNA is required to have high linearity.

LNA
PA
Desired
Channel
Blocker
TX
Signal
Duplexer

Figure 3.5: Cross-modulation due to transmission leakage in full duplex transceiver

It is noteworthy that the required IIP3 of the LNA experiencing cross-modulation is
much higher than that of the LNA which does not experience cross-modulation. For
example, IIP3
cross-mod
of the LNA in WCDMA UMTS receiver is required to be at least
5dBm while the IIP3 of the LNA is required to be -5dBm if the LNA does not experience

38
cross modulation. The required IIP3 of the LNA experiencing cross-modulation can be
obtained by [31], [32]

2
3
mod ker
mod
c P P
P IIP
cross bloc
leakage TX cross
+
+ =

(3.4)

,where P
TX-leakage
is power of the transmission leakage, P
blocker
is power of the blocker,
P
cross-mod
is the power of the cross-modulation with respect to the thermal noise floor, and
c is the correction factor, which can be varied according to the standard.

3.4.3 Input-referred Second-order Intercept Point (IIP2)

cosw
LO
t
LNA
Desired
Signal
Interferers
0
f
LO
f
LO
0
Feedthrough

Figure 3.6: Second-order distortion due to the finite direct feedthrough

39
Second-order nonlinearity can be problematic in direct conversion architecture or
low-IF architecture. If two strong interferers at
1
and
2
, which are close to the channel
of interest, experience even-order distortion in LNA, low frequency beats at
1
-
2
and
2
-
1
are generated. Due to the finite direct feedthrough of the mixer, the low frequency
beats can appear in the down-converted channel and distort the desired signal. Thus, the
double-balanced mixer should be used in zero-IF architectures since it generates less
even-order distortion and lower the low-frequency beats mentioned above. Figure 3.6
illustrates the second-order distortion due to the finite direct feedthrough of the mixer.
Second-order distortion can be characterized by the input-referred second-order
intercept point, IIP2. The overall system input-referred second-order intercept point
(IIP2
system
) can be calculated by using intermodulation characteristics defined in section
3.3.3. And IIP2
system
can be expressed by [29]

M SNR P P IIP
req sig system
+ + =
int
2 2 (3.5)

, where P
int
is the power of the interferer, P
sig
is the power of the desired signal, SNR
req
is
the required SNR, and M is the system margin, which is usually 10 ~ 15dB.

Table 3.4 summarizes the required IIP2
system
. The required IIP2
system
is 12dBm for
Bluetooth, 10dBm for IEEE 802.11b with 11Mbps data rate, and 15dBm for IEEE
802.11a, respectively.

40
Overall System
IIP2
system

12dBm
1.5dBm (1Mbps)
3dBm (2Mbps)
8dBm (5.5Mbps)
10.5dBm (11Mbps)
14.5dBm

Table 3.4 Overall system IIP2 for Bluetooth and WLANs

3.4.4 Phase Noise

For an ideal local oscillator operating at fc, the spectrum is assumed the shape of an
impulse while for an actual local oscillator, the spectrum exhibits skirt frequency around
the center frequency due to the phase noise as shown as Figure 3.7.

f
c
f
c
f f
f
c
+f
offset

Figure 3.7: Spectrums of an ideal oscillator and an actual oscillator

To understand the importance of phase noise in the wireless transceiver, the
reciprocal mixing should be taken into account when the transceiver is designed or
implemented. Recalling an ideal local oscillator illustrated in Figure 3.7, the desire signal

41
is convolved with an impulse and downconverted to the IF frequency without any change
of its shape of spectrum. And there is no interference from the nearby interferer. However,
for an actual local oscillator, the wanted signal may be corrupted by the skirt spectrum of
the nearby interferer due to the finite phase noise of an actual local oscillator. In other
words, the wanted signal suffers from significant noise due to the tail of the nearby
interferer. This undesired effect is called reciprocal mixing. Figure 3.8 depicts the
reciprocal mixing due to the phase noise of an actual local oscillator.

f
LO
f
LO
Spectrum
Wanted
Signal
Interferer
f
Wanted
Signal
Interferer

Figure 3.8: Reciprocal mixing of a nearby interferer with actual local oscillator

42
To define phase noise of a local oscillator from the system level, we need to consider
in-band and out-of-band blocking profiles specified in section 3.3.2. If the phase noise is
assumed to be constant across the band of interest, the required phase noise, PN(f
c
)of
local oscillator at a frequency offset f
c
from the desired LO frequency is obtained by
[29]

SIR BW P P f PN
bloc sig c
= ) log( 10 ) (
ker
(3.6)

, where P
sig
is the power of the desired signal, P
blocker
is the power of the blocker, BW is
the bandwidth, and SIR is signal to reciprocal mixing interferer ratio, which is 15dB.
Table 3.5 lists the required phase noise of the local oscillator according to the standards.

Offset Phase Noise Offset Phase Noise Offset Phase Noise
1MHz -80dBc/Hz
2MHz -110dBc/Hz 22MHz -93dBc/Hz
3MHz -120dBc/Hz 44MHz -123dBc/Hz 50MHz -142dBc/Hz

Table 3.5 Phase noise of local oscillator for Bluetooth and WLANs

Figure 3.9 shows the noise contribution of the local oscillator due to the phase noise.
If SIR is 15dB, the noise degradation is only 0.2dB. This means that SIR should be at
least 15dB if the noise degradation should be kept less than 0.2dB. Generally, SIR could
be assumed 15 ~ 20 dB.

43
0
0.5
1
1.5
2
2.5
3
3.5
0 3 6 9 12 15 18 21 24
SIR
N
F

D
e
g
r
a
d
a
t
i
o
n

(
d
B
)

Figure 3.9: Noise degradation versus SIR (signal to reciprocal mixing interferer ratio)

3.5 Design Specifications in n-cascade Stages

In this section, design specifications are discussed in terms of noise figure, linearities
(IIP2 and IIP3), and gain distribution for n-stages. Recalling the proposed multi-standard
receiver architecture as shown as Figure 3.1, we have a 9-cascaded stage receiver, that is,
from TR S/W to ADC. Thus, proper distribution of noise figure, linearities (IIP2 and
IIP3), and gain should be done throughout these 9 building blocks to satisfy the overall
system noise figure (NF
system
), linearities (IIP2
system
and IIP3
system
), and gain requirement.
Especially, the variable gain range should be thoroughly considered to reduce the

44
dynamic range of ADC and guarantee the desired signal to be the strongest signal level at
the input of ADC.

3.5.1 Noise Figure in n-cascade Stages

For a cascade of n-stages, the total noise figure (NF
total
) can be obtained in terms of
noise figure and gain of each stage [33], [34]. Generally, this is known as Friis equation.

1 2 1 2 1
3
1
2
1
1 1 1
) 1 ( 1

+ +
+ + =
n
n
total
G G G
NF
G G
NF
G
NF
NF NF (3.7)
, where NF
total
is the cumulative noise figure of n-stages referring to the input of the first
stage, NF
i
is the noise figure of the i-th stage, A
pi
is the gain or attenuation of the i-th
stage.
The overall system noise figure (NF
system
) as specified in Table 3.2 should be met by
the cumulative noise figure (NF
total
) of the receiver chain. In order to make the
cumulative noise figure (NF
total
) be less than the overall system noise figure (NF
system
), we
need to distribute the noise figure and the gain of each stage carefully considering the
possible values which can be obtained by current CMOS technologies, the circuit
topologies, and the operating frequency of interest for each building block. For example,
2 ~ 3dB noise figure and 18-dB gain can be achieved with cascode LNA topology if
0.18um RF CMOS technology is used in 2.4GHz.
However, Equation 3.7 does not seem to be easily used for a cascade of n-stages.
Rather than Friis equation, simple input referred noise figure for 2-stages, as shown in

45
Figure 3.10, is much useful for calculating the input referred cumulative noise figure.
This is because usually the noise figure is the input referred noise figure in the receiver
chain when one says about it.

NF
1
A
2
A
1
NF
2
NF
total,2-stages

Figure 3.10: A simple 2-stages and input-referred cumulative noise figure (NF
total,2-stages
)

Using Friis equation for 2-stages, we can easily calculate the input-referred
cumulative noise figure (NF
total,2-stages
) for 2-stages as

1
2
1 2 ,
1
A
NF
NF NF
stages total

+ =
(3.8)
, where NF
1
is the input-referred noise figure for the 1
st
stage, NF
2
is the input-referred
noise figure for the 2
nd
stage, and A
1
is the gain of the 1
st
stage, respectively.
Similarly, the input-referred cumulative noise figure (NF
total,3-stages
) for 3-stages can
be calculated as an extension of a simple 2-stage. As shown as Figure 3.11, the input-
referred cumulative noise figure (NF
total,3-stages
) for 3-stages can be viewed as a simple 2-
stages with NF
total,2-stages
.

46
NF
2
A
3
A
2
NF
3
NF
total,3-stages
NF
1
A
1
NF
total,2-stages

Figure 3.11: A simple 3-stages and input-referred cumulative noise figure (NF
total,3-stages
)

Thus, the input-referred cumulative noise figure (NF
total,3-stages
) for 3-stages can be
obtained as
2 1
3
1
2
1
2
3
2
1
1
2
3
2
1
1
1
2 ,
1 3 ,
1 1

1
1
1

1
1 1

1
A A
NF
A
NF
NF
A
NF
NF
A
NF
A
NF
NF
A
NF
A
NF
NF NF
stages total
stages total
+ =
|
|
.
|
\
|
+ + =
|
|
.
|
\
|
+ + =
+ =

(3.9)

As can be noticed, Friis equation is only the extended version of Equation 3.8 and 3.9.
In actual spreadsheet modeling of the input referred noise figure, Equation 3.8 is used
iteratively to calculate the input referred noise figure for n-stages. And it is noteworthy
that the input-referred cumulative noise figure (NF
total,n-stages
) for n-stages can be achieved
as low as possible if the gains of the proceeding stages are relatively large and the noise

47
figures of them are small comparing with those in the following stages. Thus, for the
optimization of the noise figure performance, smaller noise figure and larger gain should
be assigned to the proceeding stages.

3.5.2 Input-referred Third-order Intercept Point (IIP3) in n-cascade Stages

The intermodulation distortion in a two-tone test is commonly used to describe
nonlinearities of RF/analog circuits. When two signals, which are located closer to each
other in the frequency domain, are applied to a nonlinear circuit, the output in general
exhibits some components that are not harmonics of the input frequencies. Called
intermodulation (IM), this phenomenon arises from mixing (multiplication) of the two
signals when their sum is raised to a power greater than unity.

w
1
w
2
2w
1
-w
2
2w
2
-w
1
w
w
1
w
2
w

Figure 3.12: Intermodulation in a nonlinear system

Nonlinearities of RF/analog circuits in Figure 3.12 can be represented as

) ( ) ( ) ( ) (
3
3
2
2 1
t x t x t x t y + + (3.10)

48
, assuming x(t) = V
1
cos
1
t + V
2
cos
2
t.
The n-th order intermodulation occurs because the product is a result of the
interfering signal voltages being raised to the n-th power. With equal voltages, as in the
test, the resultant output level of the product increases as

n
n dn
V c V = (3.11)
, where c
n
is a proportionality constant and V (= V
1
= V
2
) is the common level of the two
signals.
Since a single output resulting from an input V at the operating frequency would
increase proportionately to V, there is a theoretical level at which the two outputs, the
fundamental signal and the nth order intermodulation product, would be equal. This value,
V
IPn
, is the n-th order intercept point, IP
n
. In Equation 3.11, we note that at the IP
n
, [35],

n
IP n dn
n
V c V = (3.12)

This leads to
1
1
and
|
|
.
|
\
|
= =
n
IP
dn
n
IP n
n
n
V
V
V V V c (3.13)

Figure 3.13 shows 2-cascaded stages with their voltage gains G
v
and the third-order
intercept point V
I3
.

49
V
I31
V
I32
G
v1
G
v2
A
1
A
2

Figure 3.13: 2-Cascaded nonlinear stages

Before we go further to calculate a cumulative IIP3, we should speculate the
conditions (characteristics) of the third-order intermodulation signals. Depending on
whether the third-order intermodulation signals are assumed to add in phase or not, the
procedures to derive the cumulative IIP3 should be different: case (1), correlated
condition and case (2), uncorrelated condition.

Case (1): correlated condition: the IM3 signals are assumed to add in phase
If we assume that a signal traversing the cascaded stages encounters no phase-shift,
we can calculate the cumulative IIP3 by assuming in-phase addition of the individual
contributions. When the third-order intermodulation signals are added in phase, the
voltages of the third-order intermodulation signals are added before squaring them to get
the power.
The third-order IM product generated in the first stage, A
1
, is V
d31
, and that in A
2
is
V
32
. Since V
d31
is applied to the input of A
2
, the overall intermodulation product obtained

50
at the output of A
2
is (G
v2
V
d31
+ V
d32
). The effect is the same as if an interfering signal of
the value were at the input.

2 1
32
1
31
2 1
32 31 2
v v
d
v
d
v v
d d v
d
G G
V
G
V
G G
V V G
V + =
+
= (3.14)

As it can be seen in Equation 3.13, V
d3
= V
3
/ V
I3
2
, referred to the output of a stage.
Thus V
d3j
= V
3
/ V
I3j
2
is at the output of the j-th stage. To place things on a common
footing, we can refer the signal level to the input, V
d3j
= (VG
vj
)
3
/ V
I3j
2

and note that V
d

can be expressed as V
3
/ V
I3,2-stages
2
.
Collecting terms and applying them into Equation 3.14, we have

2 1
2
32
3
2 1
3
1
2
31
3
1
3
2 1
32
1
31
2
2 , 3
3
) (
v v
I
v v
v
I
v
v v
d
v
d
stages I
G G
V
G G V
G
V
G V
G G
V
G
V
V
V
+ = + =
(3.15)

Note that
2
32
3
2 1
3
32
) (
I
v v
d
V
G G V
V = since the third-order intermodulation signals are
assumed to add in phase. Arranging Equation 3.15, we have

2
32
2 1
2
31
1
2
2 , 3
1
|
|
.
|
\
|
+
|
|
.
|
\
|
=
I
v v
I
v
stages I
V
G G
V
G
V
(3.16)

51
The above IM products originate in the active devices of the receiver, so that the voltages
or power levels are measured at the device output. Thus, the IP is naturally referred to the
device output.
It is possible to refer the point to the input of the device, modified, by its gain.
Dividing the first term in Equation 3.16 by G
v1
2
and the second term by G
v2
2
, respectively,
we can obtain the Input-referred IP3 as

2
2
1
2
1
2
2
3 3
1
3
1
|
|
.
|
\
|
+
|
|
.
|
\
|
=
IIP
G
IIP IIP
v
stages
(3.17)

The cumulative IIP3 of the 3-cascaded stages is obtained as

2
3
2
2
2
1
2
2
2
1
2
1
2
3
2
2
2
1
2
2
2
3
3 3 3
1
3 3
1

3
1
IIP
G G
IIP
G
IIP IIP
G G
IIP IIP
v v v v v
stages stages
+ + = + =

(3.18)

Equation 3.17 and 3.18 readily give the general formula of a cumulative IIP3 for the
n-cascaded stages.

2
2
) 1 (
2
2
2
1
2
3
2
2
2
1
2
2
2
1
2
1
2
3 3 3 3
1

3
1
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP

+ + + + = (3.19)

Case (2): uncorrelated condition: the IM3 signals are assumed to add out of phase

52
When the intermodulation signals are assumed to add out of phase, the powers of
each third-order intermodulation components are directly added in parallel. Thus,
Equation 3.15 is modified as

2 1
2
32
3
2
3 2
1
1
2
31
3
1
3
2 1
32
1
31
2
2 , 3
3
) (
v v
I
v v
v
I
v
v v
d
v
d
stages I
G G
V
G V G
G
V
G V
G G
V
G
V
V
V

+ = + =
(3.20)

This is because all third-order intercept points are independent and uncorrelated, which
enable us to apply
2
32
3
2
3 2
1
32
) (
I
v v
d
V
G V G
V

= into Equation 3.15 instead of
2
32
3
2 1
3
32
) (
I
v v
d
V
G G V
V = . After manipulating the variables, we find

2
32
2
2 1
2
31
2
1
2
2 , 3
1
I
v v
I
v
stages I
V
G G
V
G
V
+ =
(3.21)

As similarly as in case (1), we can obtain the Input-referred IP3 dividing the first
term in Equation 3.21 by G
v1
2
v2
2
, respectively. Then, we obtain

2
2
1
2
1
2
2
3 3
1
3
1
IIP
G
IIP IIP
v
stages
+ =
(3.22)

The cumulative IIP3 of the 3-cascaded stages is obtained as

53

2
3
2 1
2
2
1
2
1
2
3
2 1
2
2
2
3
3 3 3
1
3 3
1

3
1
IIP
G G
IIP
G
IIP IIP
G G
IIP IIP
v v v v v
stages stages
+ + = + =

(3.23)

Equation 3.22 and 3.23 readily give the general formula of a cumulative IIP3 for the n-
cascaded stages.

2
) 1 ( 2 1
2
3
2 1
2
2
1
2
1
2
3 3 3 3
1

3
1
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP

+ + + + = (3.24)

Consequently, the general formulas of the cumulative IIP3 of n-cascaded stages are as
follows.

Case (1): correlated condition: the IM3s are assumed to add in phase: the worst case

2
2
) 1 (
2
2
2
1
2
3
2
2
2
1
2
2
2
1
2
1
2
3 3 3 3
1

3
1
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP

+ + + + = (3.25)

Case (2): uncorrelated condition: the IM3s are assumed to add out of phase: the best
case
2
) 1 ( 2 1
2
3
2 1
2
2
1
2
1
2
3 3 3 3
1

3
1
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP

+ + + + = (3.26)

54
It is noteworthy that IIP3
n-stage
in Equation 3.25, which is under the correlated
condition, is generally used to calculate the overall cumulative IIP3 for n-stages. The
overall system IIP3 (IIP3
system
) as specified in Table 3.3 should be met by the cumulative
IIP3 (IIP3
n-stage
) of the receiver chain. In order to make the cumulative IIP3 (IIP3
n-stage
)
larger than the overall system noise figure (IIP3
system
), we need to distribute the IIP3 and
the gain of each stage carefully considering the possible values which can be obtained by
current CMOS technologies, the circuit topologies, and the operating frequency of
interest for each building block.
The cumulative IIP3 (IIP3
n-stage
) for n-stages can be achieved as high as possible if
the gains of the proceeding stages are relatively low and the IIP3 of the latter stages are
relatively high comparing with those in the proceeding stages. Thus, for the optimization
of the input-referred third-order intercept point (IIP3) performance, smaller gain and
higher linearity should be assigned to the proceeding stages and the latter stages,
respectively.

3.5.3 Input-referred Second-order Intercept Point (IIP2) in n-cascade Stages

While third-order distortion has been considered a source of the interferer in any
receivers, second-order distortion also could become problematic in homodyne receiver
architecture. The Second-order distortion can be characterized by the input-referred
second-order intercept point, IIP2.
As similarly as done for third-order intercept point (IIP3) in section 3.5.3, second
order intercept point (IIP2) of n-cascaded stages can be derived. In this section, however,

55
second order intercept point (IIP2) of n-cascaded stages is derived with respect to the
correlated condition since the correlated condition is the worst case estimation.
Figure 3.14 shows 2-cascaded stages with their voltage gains G
v
and the second-order
intercept point V
I2
.

V
I21
V
I22
G
v1
G
v2
A
1
A
2

Figure 3.14: 2-cascaded nonlinear stages

The second-order IM product generated in the first stage, A
1
, is V
d21
, and that in A
2
is
V
22
. Since V
d21
is applied to the input of A
2
, the overall intermodulation product obtained
at the output of A
2
is (G
v2
V
d21
+ V
d22
). The effect is the same as if an interfering signal of
the value were at the input.

2 1
22
1
21
2 1
22 21 2
v v
d
v
d
v v
d d v
d
G G
V
G
V
G G
V V G
V + =
+
= (3.27)

As it can be seen in Equation 3.13, V
d2
= V
2
/ V
I2
, referred to the output of a stage.
Thus V
d2j
= V
2
/ V
I2j
is at the output of the j-th stage. To place things on a common

56
footing, we can refer the signal level to the input, V
d2j
= (VG
vj
)
2
/ V
I2j
and note that V
d
can
be expressed as V
2
/ V
I2,2-stages
. Collecting terms and applying them into Equation 3.27, we
have

2 1
22
2
2 1
2
1
21
2
1
2
2 1
22
1
21
2 , 2
2
) (
v v
I
v v
v
I
v
v v
d
v
d
stages I
G G
V
G G V
G
V
G V
G G
V
G
V
V
V
+ = + =
(3.28)

Note that
22
2
2 1
2
22
) (
I
v v
d
V
G G V
V = since the second-order intermodulation signals are
assumed to add in phase. Arranging Equation 3.28, we have

|
|
.
|
\
|
+
|
|
.
|
\
|
=
22
2 1
21
1
2 , 2
1
I
v v
I
v
stages I
V
G G
V
G
V
(3.29)

The above IM products originate in the active devices of the receiver, so that the
voltages or power levels are measured at the device output. Thus, the IP is naturally
referred to the device output.
It is possible to refer the point to the input of the device, modified, by its gain.
Dividing the first term in Equation 3.29 by G
v1
v2
, respectively,
we can obtain the Input-referred IP2 as

|
|
.
|
\
|
+
|
|
.
|
\
|
=
2
1
1 2
2 2
1
2
1
IIP
G
IIP IIP
v
stages
(3.30)

57
Similarly, the cumulative IIP2 of the 3-cascaded stages is obtained as

3
2 1
2
1
1 3
2 1
2 3
2 2 2
1
2 2
1

2
1
IIP
G G
IIP
G
IIP IIP
G G
IIP IIP
v v v v v
stages stages
+ + = + =

(3.31)

Equation 3.30 and 3.31 readily give the general formula of a cumulative IIP2 for the
n-cascaded stages [36].

n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP 2 2 2 2
1

2
1
) 1 ( 2 1
3
2 1
2
1
1

+ + + + = (3.32)

3.6 Receiver Modeling and Building Block Specifications

The building blocks in the proposed multi-standard receiver architecture shown in
Figure 3.1 are modeled in excel spreadsheet by using Equation 3.7, 3.25, and 3.32. The
overall system NF
system
, IIP3
system
, and IIP2
system
, which have been extracted from the
corresponding standards, should be at least met by the NF
total
, IIP3
total
, and IIP2
total
,
respectively. Recalling the NF
total
, IIP3
total
, and IIP2
total
, the formulas are as

1 2 1 2 1
3
1
2
1
1 1 1
) 1 ( 1

+ +
+ + =
n
n
total
G G G
NF
G G
NF
G
NF
NF NF (3.33)
2
2
) 1 (
2
2
2
1
2
3
2
2
2
1
2
2
2
1
2
1
2
3 3 3 3
1

3
1
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP

+ + + + = (3.34)

58
n
n v v v
v v v
stages n
IIP
G G G
IIP
G G
IIP
G
IIP IIP 2 2 2 2
1

2
1
) 1 ( 2 1
3
2 1
2
1
1

+ + + + = (3.35)

The specifications of each building block are carefully determined considering
possible circuit topologies, CMOS technology, and achievable performance. Once the
receiver modeling is implemented in spreadsheet and the proper values for NF, IIP3, IIP2,
and gain for each building block are chosen, the NF
total
, IIP3
total
, IIP2
total
, and cumulative
gain are calculated by Equation 3.33, 3.34, and 3.35.
In fact, the final specification for each building block could be decided by iteration of
spreadsheet calculation until the NF
total
, IIP3
total
, and IIP2
total
are equal or better than the
overall system NF
system
, IIP3
system
, and IIP2
system
.
Table 3.6, 3.7, and 3.8 show the spreadsheets containing the final values for each
building block from TR switch to ADC according to three standards, Bluetooth, IEEE
802.11b, and IEEE 802.11a, respectively.

Table 3.6 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver for Bluetooth Application
TR S/W RF Filter LNA SDC Mixer PPF LPF VGA ADC
Power Gain (dB) -1 -2
Voltage Gain (dB) -1 -2 8 3 2 0 0 14 0
18 54
Cumulative Gain (dB), Min. Gain -3 5 8 10 10 10 24 24
Cumulative Gain (dB), Max. Gain 15 18 20 20 20 74 74
Noise Figure (dB) 1 2 5 10 18 25 25 30 30
3 15
Cumulative NF (dB), Min. Gain 22.69 21.69 19.69 27.55 30.48 32.23 31.32 30.17
Cumulative NF (dB), Max. Gain 10.74 9.74 7.74 23.98 26.81 28.21 25.40 15.00
IIP3 (dBm) 50 50 0 5 8 12 12 12 25
-5 -30
IIP3 (mVrms) 70710.7 70710.7 223.6 397.6 561.7 890.2 890.2 890.2 3976.4
125.7 7.1
Cumult. IIP3 (mVrms), Min. Gain 115.27 102.73 81.60 220.16 373.45 629.43 890.09 592.29
Cumult. IIP3 (mVrms), Max. Gain 30.96 27.60 21.92 176.84 278.88 404.47 454.05 5.28
Cumulative IIP3 (dBm), Min. Gain -5.76 -6.76 -8.76 -0.13 4.45 8.99 12.00 8.46
Cumult. IIP3 (dBm), Max. Gain -17.17 -18.17 -20.17 -2.04 1.92 5.15 6.15 -32.54
IIP2 (dBm) 80.00 80.00 30.00 40.00 50.00 60.00 60.00 60.00 70.00
25.00 20.00
IIP2 (mVrms) 2236067 2236067 7071 22360 70710 223606 223606 223606 707106
3976 2236
Cumulative IIP2 (dBm), Min. Gain 25.24 24.25 22.27 34.86 44.86 53.87 59.78 51.75
Cumulative IIP2 (dBm), Max. Gain 15.54 14.54 12.55 32.91 40.98 46.77 48.91 11.75
5
9

TR S/W RF Filter LNA SDC Mixer HPF LPF VGA ADC
Voltage Gain (dB) -1 -2 8 3 2 0 0 4 0
18 60
Noise Figure (dB) 1 2 5 10 18 25 25 35 30
3 12
IIP3 (dBm) 50 50 0 7 10 15 15 15 25
-5 -35
IIP3 (mVrms) 70710.7 70710.7 223.6 500.6 707.1 1257.4 1257.4 1257.4 3976.4
125.7 4.0
Cumulative IIP3 (dBm), Min. Gain -3.79 -4.79 -6.79 2.23 6.98 11.99 15.00 14.03
Cumult. IIP3 (dBm), Max. Gain -19.23 -20.23 -22.23 -4.15 -0.80 1.58 1.78 -38.01
IIP2 (dBm) 80.00 80.00 30.00 40.00 50.00 65.00 65.00 65.00 75.00
25.00 15.00
IIP2 (mVrms) 2236067 2236067 7071 22360 70710 397635 397635 397635 1257433
3976 1257
Cumulat. IIP2 (mVrms), Min. Gain 4309 3848 3062 13566 48728 197336 391754 264880
Cumulat. IIP2 (mVrms), Max. Gain 1329 1185 942 9811 24692 47766 54287 628.72

Table 3.7 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver for IEEE 802.11b WLAN Application
6
0

TR S/W RF Filter LNA SDC Mixer HPF LPF VGA ADC
Voltage Gain (dB) -1 -2 8 3 2 0 0 24 0
18 66
Noise Figure (dB) 1 2 5 10 20 25 25 25 30
3.5 10
IIP3 (dBm) 50 50 0 5 8 8 8 8 25
-5 -40
IIP3 (mVrms) 70710.7 70710.7 223.6 397.6 561.7 561.7 561.7 561.7 3976.4
125.7 2.2
Cumulative IIP3 (dBm), Min. Gain -7.54 -8.54 -10.54 -2.13 1.80 4.99 8.00 0.21
Cumult. IIP3 (dBm), Max. Gain -20.96 -21.96 -23.96 -5.90 -2.54 -0.13 0.59 -43.54
IIP2 (dBm) 80.00 80.00 30.00 45.00 55.00 65.00 65.00 65.00 80.00
25.00 10.00
IIP2 (mVrms) 2236067 2236067 7071 39763 125743 397635 397635 397635 2236067
3976 707
Cumulat. IIP2 (mVrms), Min. Gain 5498 4912 3910 21979 69417 195092 383010 104137
Cumulat. IIP2 (mVrms), Max. Gain 1505 1342 1066 11581 23082 35593 39092 433
Table 3.8 Total NF, IIP3, and IIP2 in the proposed multi-standard receiver for IEEE 802.11a WLAN Application
6
1

62
In Table 3.9, the spreadsheet results are summarized and compared with the overall
system specifications. As can be seen, the performance of the multi-standard receiver
satisfies all the overall system specifications.

Bluetooth IEEE 802.11b IEEE 802.11b
Parameters
Result Requirement Result Requirement Result Requiremnt
NF (dB) 10.7 21 10.1 10.6 11.1 15
IIP3 (dBm) -17.1 -17.5 -19.2 -22.5 -20.9 -24.5
IIP2 (dBm) 15.5 12 15.4 10 16.6 15

Table 3.9 Spreadsheet modeling results and system requirements

3.7 Other Important Specifications

Besides noise figure, linearity, and gain specifications, there are several important
specifications to be considered from the viewpoint of top-level system specifications.
Tables 3.10 to 3.14 list other important specifications according to specific building
blocks.

3dB Bandwidth N/A <55KHz* <150KHz**
Attenuation at DC >30dB
*: The values are calculated based on 0.5% of the chip rate.
**: The center subchannel is unused, so it can be used to remove the DC offset.
Table 3.10 Specification of high-pass filter for zero-IF WLANs

63
3dB Bandwidth 1MHz N/A N/A
Attenuation at f
image
(-0.5MHz)

>30dB

Table 3.11 Specification of poly-phase filter for low-IF Bluetooth

3dB Bandwidth 1MHz 11MHz 10MHz
Adjacent Channel
Rejection
N/A
35dB
(25MHz offset)
16dB
(20MHz offset)
Non-Adjacent
Channel Rejection
N/A N/A
32dB
(40MHz offset)
Order Programmable 6
th
order LPF

Table 3.12 Specification of low-pass filter

Variable Gain Range 14~54dB 4~60dB 24~66dB
Overall Variable
Gain Range
4~66dB

Table 3.13 Specification of variable gain amplifier

Dynamic Range 51dB 24.6dB 20dB
Resolution 9bit 4bit 3bit

Table 3.14 Specification of ADC

64
Figure 3.15, 3.16, and 3.17 illustrate all possible signal levels including the wanted
signal, the co-channel interferer, the adjacent channel blockers, and the out-of-band
blocker as they pass through the proposed multi-standard receiver.

Figure 3.15: Signal levels at each stage in the receiver for Bluetooth
-120
-100
-80
-60
-40
-20
0
20
Minimum Desired Signal
Maximum Desired Signal
Co-Channel
Adjacent CH. 1MHz away
Out-of_band Blocker 45MHz away
Noise Floor
Required
ADC
Dynamic
Range
(51dB)
A
n
t
e
n
n
a
T
R

S
/
W
L
N
A
B
a
l
u
n
M
i
x
e
r
R
F

F
i
l
t
e
r
P
P
F
L
P
F
V
G
A
A
D
C
S
i
g
n
a
l

L
e
v
e
l

(
d
B
m
)

65
-120
-100
-80
-60
-40
-20
0
20
Noise Floor
Required
ADC
Dynamic
Range
(25dB)
A
n
t
e
n
n
a
T
R

S
/
W
L
N
A
B
a
l
u
n
M
i
x
e
r
R
F

F
i
l
t
e
r
H
P
F
L
P
F
V
G
A
A
D
C
S
i
g
n
a
l

L
e
v
e
l

(
d
B
m
)

Figure 3.16: Signal levels at each stage in the receiver for IEEE 802.11b

Figure 3.17: Signal levels at each stage in the receiver for IEEE 802.11a
-120
-100
-80
-60
-40
-20
0
20
Noise Floor
Required
ADC
Dynamic
Range
(20dB)
A
n
t
e
n
n
a
T
R

S
/
W
L
N
A
B
a
l
u
n
M
i
x
e
r
R
F

F
i
l
t
e
r
H
P
F
L
P
F
V
G
A
A
D
C
S
i
g
n
a
l

L
e
v
e
l

(
d
B
m
)

66
CHAPTER 4

FULLY-INTEGRATED CMOS RF FRONT-END FOR BLUETOOTH AND
WLAN APPLICATIONS

4.1 Introduction

Figure 4.1 illustrates the diagram of the transceiver including the proposed multi-
standard receiver architecture mentioned in section 3.2. The shaded part in Figure 4.1
indicates the fully-integrated CMOS RF front-end, which is composed of LNA, SDC, and
I/Q mixers. The LNA is a single-ended LNA, which can save the power consumption
significantly and also die area when compared with a differential LNA. There is SDC
(Single-ended to Differential Converter) between the LNA and I/Q mixers. Since the
proposed receiver architecture uses homodyne architecture, known as direct conversion
architecture, for wireless LAN and low-IF architecture for Bluetooth, the second-order
distortion may be problematic. Thus, the double-balanced mixer topology is highly
demanded since it produces less second-order distortion comparing with single-balanced
mixer counterpart. In order to use the double-balanced mixers following the single-ended
LNA, the SDC should be placed between these two building blocks. Furthermore, by
placing the SDC between the LNA and the mixers, better reverse isolation between the

67
LNA and the mixers could be achieved [37], and , in turn, dc-offset can be reduced as
well. Furthermore, a conventional BALUN, generally realized with a passive, external
component, is now integrated into the RF front-end and there is no need to use a
differential LNA, resulting in low power consumption and small chip area.

Figure 4.1: Multi-standard transceiver

4.2 RF Front-End for Bluetooth and WLAN Applications

The previous work [11], which provides the ability to support the dual band
applications for GSM/DCS1800, employed the superheterodyne receiver architecture. It
means that the previous work requires much more power consumption, more chip area,
T/R Switch
SDC
0
90
A/D
A/D
LNA
Mixer LPF VGA
D/A
D/A
0
90
PA
BPF
LPF
D
i
g
i
t
a
l

S
i
g
n
a
l

P
r
o
c
e
s
s
o
r
Frequency
Synthesizer
Frequency
Synthesizer
HPF
PPF

68
and also discrete off-chip image reject filter, which is not preferable to the recent trend of
low power consumption and high-integration design.
A block diagram of the proposed CMOS RF front-end is shown in Figure 4.2. It has
two separate single-ended LNAs; one for Bluetooth/IEEE 802.11.b and the other for
IEEE 802.11.a. Two separate LNAs are required since there is a need to optimize each
LNA for each operating frequency band, 2.4GHz or 5.2GHz. Recently, a concurrent dual-
band LNA has been introduced [38], [39], but it may have a difficulty to provide proper
gain and good input impedance matching at the frequency bands of interest. This is
because gain and input matching should be achieved with only one LNA at two different
frequency bands, which are far away from each other.

LNA
BB I
BB Q
LO I
LO Q
Bluetooth
IEEE 802.11b
(2.4GHz)
LNA
Band-Select
Gain-Control
Band-Select
IEEE 802.11a
(5.2GHz)
SDC
SDC
I-Mixer
Q-Mixer

Figure 4.2: Block diagram of the proposed CMOS RF front-end

The single-input to differential-output conversion in Figure 4.2 is performed before
the direct conversion mixer in order to make it possible to use a double-balanced mixer

69
topology after the single-ended LNAs. Additionally, better LO-RF isolation can be
achieved by placing the single-input to differential-output converter (SDC) between the
LNA and the direct conversion RF mixer. As known well, the double-balanced mixers
generate less even-order distortion, thus lowering the beat components in homodyne
architectures. And the two differential input pairs in the double-balanced mixer add the
amplified LO with opposite phases, thereby providing a first-order cancellation. This
eliminates the potential for the LO-IF feedthrough problem, which plagues a direct
conversion system and results in time-varying dc offset [8].
The signal paths between the different blocks are ac-coupled with several-pF on chip
capacitors. Hence, the low frequency distortion components generated by the second-
order nonlinearities in the LNA and the SDC are filtered before direct conversion. If the
SDC is placed before the LNA, a fully differential signal path could be employed
throughout the RF front-end to reduce the effect of common-mode distortion and noise.
However, it consumes twice power dissipation and chip area, which is not preferable to
the recent trend of low power consumption and high-integration design.

4.3 Low Noise Amplifier (LNA)

Being the first active element in the receiver chain, an LNA should provide good
input impedance matching with 50-termination. Since most of the RF band-pass filters
is usually terminated with 50, the input of LNAs should be matched with 50.
Otherwise, most of the received signal, which is very weak, would be reflected and, thus,
proper amplification of the desired received signal may be impossible.

70
The noise figure of an LNA plays a major role in the overall noise figure performance
of a receiver since low noise amplifier (LNA) is the very first active building block in
wireless receiver chain. Thus, the noise figure of a LNA significantly influences
receivers sensitivity and signal-to-noise ratio (SNR). In the following sections, the input
matching and the noise model of LNAs are explored in details.

4.3.1 Input Impedance Matching

LNAs should provide a stable 50 input impedance to terminate the preceding stage
which delivers signal from the antenna to the LNA. A good input impedance match is
even more important if a RF band-pass filter precedes the LNA since RF filters are
sensitive to the terminating impedance.
Several different topologies have been proposed for LNAs to implement 50 input
impedance; resistive termination, shunt-series feedback, common-gate, and common
source with inductive degeneration. Resistive termination is used in its differential form
by Chang et al. [40], but using real resistors in this fashion may degrade the amplifiers
noise figure. Shunt-series feedback has been used in [41] and [42], however, this
approach often requires high power dissipation compared to others with similar noise
performance [43]. Thus, two most common LNAs, namely, the common-gate topology
[44] and common-source with inductive degeneration [43], will be discussed.
Figure 4.3 9 (a) depicts a common-gate stage design to exhibits an input impedance
of 50; that is, 1 / (g
m
+ g
mb
) = 50, where g
m
and g
mb
are transconductances of the top-
gate and back-gate transistors, respectively. The principal drawback of this common-gate

71
topology is that the transconductance of the input transistor cannot be arbitrarily high for
a proper input matching [44]. Thus, the NF is lower bounded to about 2.2 dB for long-
channel CMOS transistor [45].

( )
( )
mb
mb m O mb
O mb m
O D
in
g
g g r g
r g g
r R
Z
+
+
+
+
+ +
+
=
m
m
D
g
1

1
g
R

1
(4.1)

, where we assume that R
D
<< r
O
and 1 << (g
m
+ g
mb
)r
O
.

L
g
L
s
C
gs
i
x
v
x
+
-
Z
in
v
out
v
in
v
dd
R
d
(a) (b)
Z
in

Figure 4.3: Commonly used CMOS LNAs; (a) common-gate and (b) common-source

72
Figure 4.3 (b) shows a common source with inductive degeneration. As can be seen,
v
x
can be expressed as
( )
s gs m x
gs
x g x x
sL v g i
sC
i sL i v + + + =
1
(4.2)
, where
gs
x
gs
sC
i
v = .
Thus, input impedance, Z
in
, can be expressed as [45]

( )
gs
s m
gs
s g
x
x
in
C
L g
sC
L L s
i
v
Z

+ + + = =
1
(4.3)
At resonance, that is, if ( ) 0
1
= + +
ga
s g
sC
L L s , then Z
in
can be reduced as

( ) =
= 50
gs
s m
in
C
L g
Z (4.4)
4.3.2 Noise Model

The noise factor is defined as

source input to due noise output
power noise output total
F (4.5)

The noise factor is a measure of the degradation in signal-to-noise ratio that a system
introduces. Generally, the noise figure can be obtained by applying 10*LOG to Equation

73
4.5. If a system adds no noise, then the noise factor is unity and, thus, the noise figure is
zero.
L
s
V
rg
2
R
g
i
d
2
I
out
Vdd
M1
R
s
V
s
2
L
g R
l
V
l
2
-
-
- -

Figure 4.4: Equivalent circuit for LNA noise calculation

The equivalent circuit for noise model of LNA is shown in Figure 4.4. The dominant
noise source of CMOS devices is drain channel thermal noise. The noise source due to
drain current is commonly modelled as a shunt current noise source at the output circuit
of the device. The drain current channel noise,
2
d
i , is given by

f g kT i
d d
=
0
2
4 (4.6)
, where g
d0
is the zero-bias drain conductance of the device and is the coefficient of
channel thermal noise [45]. For long channel devices, is 2/3. For short-channel devices,
however, is not 2/3 any longer. In fact, is much greater than 2/3 for short-channel

74
devices operating in saturation [46], [47]. The substitution has been made for Equation
4.6 with
0 d
m
g
g
(4.6)
Since is unity for long-channel devices and progressively decreases as channel lengths
shrinks, it is a measure of the departure from the long-channel regime.
The equivalent input noise voltage accounts for the output noise observed when the
input port is short-circuited. To determine its value, refer the drain current noise source
back to the input as a noise voltage source and recognize that the ratio of this quantity is
g
m
. Thus, we have

2
0
2
2
2
4
m
d
m
d
n
g
f g kT
g
i
v

= =

(4.7)

It is noteworthy that this equivalent input-referred noise voltage source by itself does
not fully account for the drain current noise source, because a noisy drain current also
flows even when the input is open-circuited and induced gate current is ignored [45].
Under this open-circuit condition, multiplying the equivalent input-referred noise voltage,
v
n
2
by the input admittance, C
gs
, yields an equivalent input current noise source, i
n
,
completing the modelling of i
d
.

( )
( )
2
2
0 2 2 2
4
m
gs d
gs n d
g
C f g kT
C v i

= = (4.8)

75
Using the equation,
2 2 2 2 2 2
s d rg l s in
R i v v v v + + + = , the equivalent total input noise voltage,
2
in
v , observed at the output is given by

|
|
.
|
\
|
+ + + =
|
|
.
|
\
|
+ + + =
2
2 2
0
2
2 2 2
0
2
4
4
T
s d
g l s
m
gs s d
g l s in
R g
R R R f kT
g
C R g
R R R f kT v

(4.9)
, where
gs m T
C g is assumed.
By substituting Equation 4.9 and f kTR v
s s
= 4
2
into Equation 4.5, we have
2
0
1
|
|
.
|
\
|
+ + + =
T
s d
s
g
s
l
R g
R
R
R
R
F
(4.10)

Note that the effect of the gate-induced current noise has been ignored in Equation
4.10. This is because, for most of current noise model in MOS devices, the effect of the
gate-induced current noise have not been modelled accurately [43], [48], [49].
Now we can make a few observations in this common source configuration. First, the
dominant term in Equation 4.10 is the last term, which arises from channel thermal noise.
As can be seen in Equation 4.10, the drain current noise contribution is proportional to
g
d0
but inversely proportional to the square of g
m
. For small values of V
od
= V
gs
V
th
, g
d0

and g
m
increase linearly with V
od
until velocity saturation occurs and then gm becomes
constant. Meanwhile, g
d0
and consequently the drain current noise keep increasing with
V
od
. Thus, noise figure drops with V
od
in the beginning but increases with significantly

76
abundant V
od
. This means that there is an optimum current for the minimum noise
performance.
Second observation to note is that there are extra degrees of freedom such as the
width, W, and the length, L, of MOS input device. It is clear that the width of MOS input
device should be large and the length should be short for minimizing the gate resistance,
R
g
. A larger W results in a smaller gate resistance, R
g,,
and a small gate-resistance noise
contribution. However, a larger W also increases the drain current beyond the optimum
drain current consumption and has a negative overall effect on noise performance of
LNAs. It means that there is also an optimum width, W
opt
, resulting in the lowest noise
figure in this topology.
In common-gate topology, there is no extra freedom to change the width of MOS
input device, which results in the change of g
m
, since the input impedance matching is
realized by 1/(g
m
+g
mb
). Although it is easy to implement the input impedance matching
with common-gate topology, it is very difficult to optimize noise performance with
common-gate topology. This is the main drawback of common-gate topology and leads
RF circuit designers towards the common-source topology.

4.3.3 Design and Simulation Results

General requirements of the LNA are low noise figure, moderate gain, input matching,
low power consumption and high linearity. To achieve these goals, the LNA employs a
common-source cascode topology with inductive degeneration, which can also provide
good reverse isolation [37]. Since the linearity performance is rather dominated by the

77
stages following the LNA, the primary goal in LNA design is to minimize the noise
figure and the power consumption.
Figure 4.5 depicts the proposed LNA providing dual gain mode, that is, high gain and
low gain. For IEEE 802.11.b, since the maximum received signal strength is -10dBm, the
LNA needs to have dual gain mode; the low gain mode is required to alleviate the
linearity requirements of the following stages, SDC and mixers, in the presence of the
maximum received signal.

Vdd
L
g
M1
M2
L
s
R
d1
L
d
R
d2
V
out
V
in
I
b
M3 V
ctrl

Figure 4.5: The proposed LNA schematic

As mentioned above, the LNA provides dual gain mode, high gain or low gain. From
the system view as described in section 2, the LNA is required to provide 18-dB in high

78
gain mode and 8dB in low gain mode. In high gain mode, the LNA uses the damped
resonator, L
d
and R
d1
. The damping resistor R
d1
produces a sufficient bandwidth for 2.4-
GHz (or 5.2-GHz) frequency band. The resonant frequency is 2.44-GHz (or 5.25GHz)
and the 1-dB bandwidth is 300MHz. Low gain is realized by connecting load resistor R
d2

in parallel with the resonator, L
d
and R
d1,
and reducing the Q of the resonator by closing
PMOS switch M3. The size of the PMOS switch M3 should be carefully determined by
considering on-resistance and parasitic capacitance since it affects the resonant frequency
and the gain.
Figure 4.6 to 4.10 shows simulation results of 2.4 and 5.2GHz LNAs. And Table 4.1
and 4.2 summarize the simulation results according to corner, supply voltage and
temperature variation.

79

(a)

(b)
Figure 4.6: S11 and S12 of (a) 2.4GHz LNA and (b) 5.2GHz LNA

80

(a)

(b)
Figure 4.7: Noise Figure of (a) 2.4GHz LNA and (b) 5.2GHz LNA

81

(a)

(b)
Figure 4.8: Gain of (a) 2.4GHz LNA and (b) 5.2GHz LNA

82

(a)

(b)
Figure 4.9: IIP3 of (a) 2.4GHz LNA and (b) 5.2GHz LNA

83

2.4GHz LNA Achievements Requirements
SS -15.2 TT -17.4 FF -17.5
1.6V -17.2 1.8V -17.4 2V -18.2 S11 (dB)
-40 -16.1 27 -17.4 80 -18.1
< -10dB
SS -44.1 TT -46.2 FF -46.9
1.6V -45.9 1.8V -46.2 2V -47.3 S12 (dB)
-40 -44.8 27 -46.2 80 -47.4
< -30dB
SS 2.24 TT 2.05 FF 1.9
1.6V 2.1 1.8V 2.05 2V 1.95
High
Gain
-40 1.7 27 2.05 80 2.36
< 3dB
SS 2.47 TT 2.2 FF 2.05
1.6V 2.31 1.8V 2.2 2V 2.12
NF (dB)
Low
Gain
-40 1.9 27 2.2 80 2.53
< 5dB
SS 20.7 TT 22 FF 22.6
1.6V 21.6 1.8V 22 2V 22.2
High
Gain
-40 20.8 27 22 80 23
18dB
SS 9.4 TT 10.2 FF 10.7
1.6V 9.9 1.8V 10.2 2V 10.4
Gain (dB)
Low
Gain
-40 8.6 27 10.2 80 10.5
8dB
IIP3 (dBm) 0.95 0dBm
IIP2 (dBm) 20.8 N/A
Supply Voltage (V) 1.8 N/A
DC Current (mA) 3.18 N/A

Table 4.1 Simulation results of 2.4GHz LNA with respect to corner, supply voltage, and
temperature variation

84

5.2GHz LNA Achievements Requirements
SS -17.2 TT -20.5 FF -21
1.6V -16.7 1.8V -20.5 2V -20.7 S11 (dB)
-40 -17 27 -20.5 80 -20.4
< -10dB
SS -30 TT -31.6 FF -33.1
1.6V -31.5 1.8V -31.6 2V -31.7 S12 (dB)
-40 -32.1 27 -31.6 80 -31.3
< -30dB
SS 2.83 TT 2.75 FF 3.0
1.6V 3.12 1.8V 2.75 2V 2.57
High
Gain
-40 2.05 27 2.75 80 3.35
< 3dB
SS 3.14 TT 3.06 FF 3.5
1.6V 3.57 1.8V 3.06 2V 2.88
NF (dB)
Low
Gain
-40 2.4 27 3.06 80 3.69
< 5dB
SS 18.6 TT 20.2 FF 20.1
1.6V 19.3 1.8V 20.2 2V 20.4
High
Gain
-40 19.4 27 20.2 80 21
18dB
SS 8.6 TT 10.2 FF 10.6
1.6V 9.4 1.8V 10.2 2V 10.6
Gain (dB)
Low
Gain
-40 10 27 10.2 80 10.3
8dB
IIP3 (dBm) 2.4 0dBm
IIP2 (dBm) 22.4 N/A

Table 4.2: Simulation results of 5.2GHz LNA with respect to corner, supply voltage, and

85
4.4 Single-ended to Differential Converter (SDC)

The single-ended to differential converter (SDC), generally known as balun, enables
to use double-balanced mixer topology following the single-ended LNA. Generally, in
the homodyne receiver, the even-order distortion could corrupt the signal of interest since
the second order intermodulation product (IM2) due to the non-linearity of LNA can
appear at the output of the mixer with no frequency translation. For less second-order
distortion in homodyne receiver architecture, double-balanced mixers are much desirable
than single-balanced mixers since the double-balanced mixers produce less second-order
nonlinearity than the single-balanced mixers.
By placing the single-input to differential-output converter, double-balanced mixers
can be used after the single-ended LNA and, as a result, the even-order distortion can be
minimized. Furthermore, the LO-RF isolation can be improved by placing the SDC
between the LNA and the direct conversion mixer.

4.4.1 Passive Balun and Active SDCs

The commonly used passive balun is ring hybrid coupler (Rat-Race coupler) [50],
[51]. Figure 4.10 shows the ring hybrid coupler, which is implemented using the micro
strip-line. The ring hybrid coupler is a four-port network with a 180 phase shift between
the two output ports. When the signal is applied to port 4, it will be equally split into two
components with a 180 phase difference at port 2 and 3, and port 1 will be isolated. It
can also be operated so that the outputs are in phase. When the signal is applied to port 1,

86
it will be evenly split into two in-phase components at ports 2 and 3, and port 4 will be
isolated. When operated as a combiner, with input signals applied at ports 2 and 3, the
sum of inputs will be formed at port 1, while the difference will be formed at port 4.
Hence, ports 1 and 4 are referred to as the sum and difference ports, respectively.

4 / 3
4 /
4 /
4 /
Z
0
Z
0
Z
0
Z
0
0
2Z
4
3 1
2

Figure 4.10: Ring hybrid coupler

A ring hybrid coupler has an advantage over active SDCs. It can provide better S11
than active SDCs with less noise figure. However, a ring hybrid coupler has critical
drawback; practically it is impossible to be integrated into chip because it requires a large
area. This drawback of passive baluns has led RF designers to look for active SDCs for
on-chip integration.
Active SDCs are shown in Figure 4.11. The commonly used active SDCs are a
differential pair and a common-source amplifier with source degeneration.

87
M1 M2 Vin
Vdd
Vout+ Vout-
Vbias
R R
Vdd
Vin M1
Rd
Rs
Vout+
Vout-
P
I
dc

(a) Differential pair (b) Common-source amplifier
with source degeneration
Figure 4.11: Active single-ended to differential converters (SDCs)

A CMOS differential pair in Figure 4.11 (a) can be used as a single-ended to
differential converter (SDC) [52]. The principle of a CMOS differential pair in Figure
4.11 is as follows. The input signal v
in
is only connected to input device M1 whereas
device M2 is dc-biased. The variation of input signal, v
in
, should be cancelled at node P
due to the constant DC current I
dc
. In order to cancel the variation, the same amount of
variation with opposite phase is induced in device M2. The variation of input signal v
in

and the opposite variation of device M2 are happened as a form of current variation. Thus,
output nodes v
out+
and v
out-
are out of phase (180 phase shift).
A common-source amplifier with source degeneration in Figure 4.11 (b) can also act
as a single-input to differential-output converter. The principle of a common-source
amplifier with source degeneration in Figure 4.11 (b) is as follows. From the viewpoint of

88
v
out-
, the circuit is a simple common-source amplifier with source degeneration. The
voltage gain is approximately
d
s m
m
R
R g
g

(
) 1 (
assuming R
out
>> R
d
. On the other
hand, from the viewpoint of v
out+
, the circuit is a source follower with drain resistor. The
voltage gain is approximately ) //
1
(
) 1 (
s
m
s m
m
R
g
R g
g

(
+
. As it can be seen, the two
voltage gains have opposite sign, which means 180 phase shift. Adjusting the values of
R
d
and R
s
produces the same voltage gains with 180 phase shift.
The active SDCs have main advantages over passive baluns. Active SDCs can be
integrated with other building blocks such as LNA and mixer, which is much preferable
to the current trend of fully-integrated transceiver chip design. Second, they can provide
some voltage gain whereas passive baluns have some amount of loss.
However, there are also some disadvantages over passive baluns. First, the active
SDCs suffer from the gain and phase imbalance. This is because the active device
inherently has parasitic capacitances, which can produce undesired effects on the gain
and phase balance, especially at high frequencies. Thus, the compensation technique for
the gain and phase imbalance may be required. Second, they need power consumption
since they are active devices.

4.4.2 Common-Source Amplifier with Source Degeneration

Figure 4.12 shows the schematic of the proposed SDC. The proposed SDC uses the
common-source amplifier with source degeneration to produce the differential output.

89
This topology has an advantage over a differential pair converter. Since it has the source
degeneration resistor, it can give higher linearity with low biasing current [37]. A dummy
transistor M2 is added to compensate for the effect of the gate-source capacitance, C
gs
, of
M1 on the phase of the differential output.

Vdd
M1
Rd
Vout-
Vout+
Rs
Vin
M2
I
b

Figure 4.12: The proposed SDC schematic

Looking into the output of v
out-
, the circuit is a simple common-source amplifier with
source degeneration. On the other hand, Looking into the output of v
out+
, the circuit is a
source follower with drain resistor. Apparently, these two outputs are exactly 180 out of
phase. However, there is a need to derive voltage gains of these two outputs, v
out-
and v
out+
,
to show how to achieve same voltage gain with opposite polarity.

90
Figure 4.13 shows the small signal circuit and the corresponding equivalent circuit
when looking into the output of v
out-
. In order to derive the voltage gain, we need to
calculate equivalent transconductance, G
m
, and output resistance, R
out
.

G
m
v
i
+
-
v
i
R
o
g
m
v
gs
g
mb
v
bs
R
s
R
d
i
d
+
-
v
i
+
-
+
-
v
gs
+
-
v
i

(a) (b)
Figure 4.13: Common-source amplifier with source degeneration (a) small signal circuit
and (b) equivalent circuit

From Figure 4.13 (a), we know that
bs mb gs m d
v g v g i + = (4.11)
, and
s d bs
R i v v = =
1
(4.12)

Substituting Equation 4.12 into Equation 4.11 and rearranging it, we have
s mb
gs m
d
R g
v g
i
+

=
1
(4.13)

Applying KVL to the left loop, we have

91
gs
s mb
s m s mb
s mb
gs s m
gs i
v
R g
R g R g
R g
v R g
v v
+
+ +
=
+

+ =
1
1
1
(4.14)

Defining the equivalent transconductance, G
m
, and using Equation 4.13 and 4.14, we
obtain
s m mb
m
i
d
m
R g g
g
v
i
G
) ( 1 + +
= (4.15)

Now we calculate the output resistance by removing the load resistance, R
d
, and find
the Thevenin equivalent resistance seen looking into the output terminal as shown as
Figure 4.14.

g
m
v
gs
g
mb
v
bs
R
s
r
o
+
-
v
1
+
-
+
-
v
gs
v
x
i
x

Figure 4.14: Circuit for calculation of the output resistance of common-source amplifier
with source degeneration

We know that
s x bs gs
R i v v v = = =
1
(4.16)
, and

92
( )
bs mb gs m x o s x x
v g v g i r R i v + = (4.17)


( ) | |
s s mb m o
x
x
o
R R g g r
i
v
R + + + = = 1 (4.18)
If we assume 0 =
mb
g , r
o
>> R
s
and r
o
>> R
d
, then
s m
m
m
R g
g
G
+
=
1
(4.19)
and
( )
d d s m o d o o
R R R g r R R R + = // 1 //
'
(4.20)

Thus, voltage gain of common-source amplifier with source degeneration, A
v,CS
, is
d
s m
m
o m CS v
R
R g
g
R G A
+
= =

1
'
,
(4.21)

Similarly, Figure 4.15 shows the small signal circuit and the corresponding equivalent
circuit when looking into the output of v
out+
. In order to derive the voltage gain, we need
to calculate equivalent transconductance, G
m
, and output resistance, R
out
.
If we assume 0 =
mb
g , r
o
>> R
s
and r
o
>> R
d
, then

s m
m
m
R g
g
G
+
=
1
(4.22)

93
G
m
v
i
+
-
v
i
R
o
g
m
v
gs
g
mb
v
bs
R
s
R
d
i
d
+
-
v
i
+
-
+
-
v
gs
+
-
v
i

(a) (b)

Figure 4.15: Source follower with drain resistor (a) small signal circuit and (b) equivalent
circuit

Now we calculate the output resistance by removing the load resistance, R
s
, and find
the Thevenin equivalent resistance seen looking into the output terminal as shown as
Figure 4.16.

g
m
v
gs
g
mb
v
bs
R
d
r
o
+
-
+
-
v
gs
v
x i
x
i
x

Figure 4.16: Circuit for calculation of the output resistance of source-follower with drain
resistor

We know that

94
( )
d x bs mb gs m x o x
R i v g v g i r v + + + = (4.23)
and
x bs gs
v v v = = (4.24)


( )
o mb m
d o
x
x
o
r g g
R r
i
v
R
+ +
+
= =
1
(4.25)
If we assume r
o
>> R
d
> 1, then
mb m
o
g g
R
+
=
1
(4.26)
Assuming g
mb
= 0, we have
s m
m
m
R g
g
G
+
=
1
(4.27)
and
s
m
s o o
R
g
R R R //
1
//
'
= (4.28)

Thus, voltage gain of source-follower with drain resistor, A
v,SF
, is
|
|
.
|
\
|
+
= =
s
m s m
m
o m SF v
R
g R g
g
R G A //
1
1
'
,
(4.29)
Consequently, we now have two different voltage gains from differential output, v
out-
and v
out+
as following.

95
d
s m
m
o m CS v
R
R g
g
R G A
+
= =

1
'
,
(4.30)
|
|
.
|
\
|
+
= =
s
m s m
m
o m SF v
R
g R g
g
R G A //
1
1
'
,
(4.31)
As can be seen from Equation 4.30 and 4.31, we can make the two voltage gains be the
same by adjusting properly R
d
and R
s
.


Figure 4.17 to 4.19 show simulation results of the proposed SDC as shown in Figure
4.12. And table 4.3 summarizes the simulation results of SDC according to corner, supply
voltage and temperature variation.

Figure 4.17: Gain of SDC

96

Figure 4.18: Noise Figure of SDC

(a)

97

(b)

Figure 4.19: IIP2 and IIP3 of (a) 2.4GHz SDC and (b) 5.2GHz SDC

98

SDC Achievements Requirements
SS 10 TT 9.2 FF 8.8
1.6V 9.7 1.8V 9.2 2V 9 2.4GHz
-40 7.8 27 9.2 80 10.3
< 10dB
SS 11 TT 10.3 FF 9.5
1.6V 10.8 1.8V 10.3 2V 10.1
NF (dB)
5.2GHz
-40 8.8 27 10.3 80 11.3
< 10dB
SS 4.3 TT 4.8 FF 5.6
1.6V 3.8 1.8V 4.8 2V 5.2 2.4GHz
-40 4.2 27 4.8 80 5.7
> 3dB
SS 3.8 TT 4.6 FF 5.3
1.6V 3.6 1.8V 4.6 2V 4.9
Gain (dB)
5.2GHz
-40 3.5 27 4.6 80 6
> 3dB
Gain Error (dB) 2.4GHz 0.2 5.2GHz 0.17 < 0.3dB
Phase Error () 2.4GHz 2.8 5.2GHz 1.6 < 4
IIP3 (dBm) 2.4GHz 9.9 5.2GHz 9.7 10dBm
IIP2 (dBm) 2.4GHz 57 5.2GHz 48 N/A

Table 4.3: Simulation results of SDC with respect to corner, supply voltage, and

99
4.5 Direct Conversion Mixer

Superheterodyne receiver architecture has been chosen for wireless transceiver during
the past decades. However, due to the number of off-chip components, most RF designers
have been looking for a better alternative, and finally homodyne receiver architecture has
been an alternative. As mentioned in section 2.4, homodyne architecture can reduce the
power consumption and minimize the off-chip components.
The homodyne architecture, however, is well known to suffer from two main
drawbacks; dc offset and flicker noise. For bipolar transceiver design, the flicker noise is
not a main issue any longer, since, at least in principle, bipolar transistors do not produce
the flicker noise significantly [53], [54], and [55]. On the other hand, for CMOS
transceiver design, the flicker noise would be a critical problem, since the CMOS
transistors substantially produce flicker noise and the corner frequency of the flicker
noise could significantly corrupt the down-converted desired signal. For less flicker noise,
CMOS mixers have been reported in [56], [57], and [58].

4.5.1 Flicker Noise

Mixer is the key block of a direct conversion receiver since the flicker noise of the
mixers tends to limit signal to noise ratio (SNR). A passive CMOS mixer, consisting of
four CMOS devices, may be considered the best choice for direct conversion receivers,
since they are essentially free from flicker noise. However, due to the loss of the passive
mixer, a very high gain of LNA is required to minimize the effect of noise degradation on

100
the over receiver chain. This high gain at LNA is hard to handle and the LNA can easily
be unstable [58]. Figure 4.20 shows a conventional double-balanced mixer.

R R
M1 M2
LO+
RF+
LO-
RF-
+ IF -
M3 M4 M5 M6
Vdd
I
b

Figure 4.20: Double-balanced mixer

The input-referred flicker noise of active CMOS mixers in Figure 4.20 is inversely
proportional to the gate area of switching CMOS devices M3 ~ M6, [59], [60], [61].

f C L W
k
V
ox eff eff
f
f

=
2
/ 1
(4.32)
, where W
eff
is effective width, L
eff
is effective length of the switching devices
It has been shown [60], [62] that the flicker noise at the output of the mixer due to the
switching CMOS devices is inversely proportional to S x T, but proportional to I
b
.

101
T S
R I
V
b
f
4
/ 1
(4.33)

, where S is the slope of the LO waveform, T is the LO period, and I
b
is the biasing
current.
As can be expected from Equation 4.32 and 4.33, minimizing the flicker noise leads
to large area switching CMOS devices and a low biasing current. And the finite slope of
the LO signal may significantly contributes the flicker noise in first order. Making the
switching devices operate more abruptly with low biasing current can produce less flicker
noise. It is noteworthy that typically p-MOS devices produce less flicker noise than n-
MOS counterparts since major carriers, i.e. holes, are less likely to be trapped [63].
The noise figure (white noise) of a mixer is also dominated by the LO switching stage.
A small gate overdrive voltage of the LO switching devices require small LO power,
which can turn the switches on and off effectively and abruptly. Thus, the switching
devices, M3 M6, are on simultaneously for a smaller fraction of the LO period, as a
result, injecting less noise to the output of the mixer.
The low biasing current for LO switching devices is exactly opposite phenomenon to
the condition of the biasing currents for RF input devices of the mixer [58]. This is
because that sufficient biasing current for RF input devices is required to achieve higher
linearity [64], [65], [66]. Therefore, independent biasing currents for them, LO switching
devices and RF input devices, are highly demanded for less flicker noise and higher
linearity of mixers [58].

102
4.5.2 Linearity

The down conversion mixer usually follows the LNA in the wireless receiver
architecture. Since the LNA has a significant gain, the down conversion mixer needs to
have sufficient linearity, IIP3 or IIP2, in the presence of the desired signal with
maximum strength. If, in other words, the mixer does not have sufficient linearity, the
desired signal, which is significantly strong and amplified by the LNA, may be distorted
when processed through the mixer.
While the flicker noise is mainly determined by the LO switching devices, M3 to M6
in Figure 4.20, the gain and the linearity are primarily determined by the RF input
devices, M1 and M2, [64], [65], [66]. The conversion gain and the IIP3 of the
conventional double-balanced mixer shown in Figure 4.20 are given by the following
expression [67]
R I
L
W
K G
b
RF
RF
v
= 2
2
(4.34)
RF
RF
b
L
W
K
I
IIP
= 2 3 (4.35)
, where K=C
ox
/2, and W
RF
and L
RF
represent the gate width and gate length of RF input
devices, M1 and M2, respectively. I
b
is the biasing current of RF input devices.
Equation 4.34 and 4.35 imply that there is a trade-off between the conversion gain
and the linearity. High linearity (IIP3) could be achieved by low ratio of W
RF
/L
RF

whereas adequate conversion gain would be achieved by high ratio of W
RF
/L
RF
. It is

103
obvious that adequate conversion gain and high IIP3 are required simultaneously.
Adequate conversion gain is needed to reduce the noise contribution of the following
stages such as filters and variable gain amplifiers. On the other hand, high linearity is
demanded not to limit the input swing range at the RF input of the mixer. A possible
remedy to simultaneously achieve these two goals, which are in the relationship of trade-
off, is to add the current sources in the middle of each LO switching pair, which makes it
possible to allow a high gate overdrive voltage for RF input devices, M1 and M2, and,
moreover, increase the load resistance, R, by a factor of 4 or 5. Furthermore, this current
injection method enables us to use independent biasing currents for the LO switching
devices and, thus, achieve low flicker noise as well [58], [67]. Figure 4.21 depicts the
double-balanced mixer with current injection method.

R R
M1 M2
LO+
RF+
LO-
RF-
+ IF -
M3 M4 M5 M6
Vdd
I
b
I
s
I
s

Figure 4.21: Double-balanced mixer with current injection

104
It is important to note that the input-referred third-order intercept point, IIP3, can be
expressed in terms of the gate overdrive voltage of the RF input devices, M1 and M2 [68].
As can be seen Equation 4.36, linearity can be improved by increasing the gate overdrive
voltage.

2
1 1
1
2
1
4
1
3
8
3
|
|
.
|
\
|
+
|
|
.
|
\
|
=
L v
V
L v
V
V
L v
IIP
sat
od
sat
od
od
sat

(4.36)

4.5.3 Phase Mismatch and Gain Reduction

It is important to examine the effect of the phase imbalance on the performance of the
RF front-end receiver. Since the active SDC is placed between the LNA and the direct-
conversion RF mixer, the phase imbalance of the SDC can influence negatively the
conversion gain of the mixer. Figure 4.22 shows the direct-conversion mixer which is a
typical double-balanced Gilbert cell mixer. The RF input devices M1 and M2 convert the
differential RF input signals, RF+ and RF-, to currents g
m1
V
RF
and -g
m2
V
RF
,
respectively, where g
m1
= g
m2
and V
RF
is the voltage of the RF signal. M3 and M6 turn on
during the positive half cycle of LO signal whereas M4 and M5 turn on during the
negative half cycle of LO signal. Such a switching operation results in the down-
converted RF signal being doubled in amplitude. And the current switching by M3 to M6
is equal to the multiplication of the current by a square-wave toggling between -1 and +1.

105
Rd Rd
M1 M2
LO+
RF+
LO-
RF-
IF+ IF-
Vbias
M3 M4 M5 M6
Vdd

Figure 4.22: Direct conversion mixer

Equation 4.37 shows the result of the down-converted RF signal, i.e. IF signal.

t t
R V V g
t IF
LO RF
d LO RF m

cos cos
4
) ( = (4.37)

Now assume that the phase imbalance caused by the active SDC is . Applying phase
imbalance into Equation 4.37 results in Equation 4.38.

| |
(
+ + + + +
+ +
=
+ + =
) ) cos(( ) ) cos((
) cos( ) cos(

cos ) cos( cos cos
2
) (

t t
t
R V V g
t t t t
R V V g
t IF
LO RF LO RF
LO RF LO RF
d LO RF m
LO RF LO RF
d LO RF m
(4.38)

106

In order to obtain the desired IF signal, the above IF signal is processed with a low-pass
filter. And the desired IF signal after the low-pass filter is obtained as Equation 4.39.

| | ) ) cos(( ) ) cos( ) (
+ + = t t
R V V g
t IF
LO RF LO RF
d LO RF m
(4.39)

Since the receiver architecture in the proposal employs the zero-IF architecture,
RF
is
equal to
IF
. Applying
RF
=
IF
in Equation 4.39, we have

| |
cos 1 ) ( + =
d LO RF m
R V V g
t IF (4.40)

Now we can define the voltage gain of the mixer as follows.

| |
|
.
|
\
|
+ =
|
|
.
|
\
|
=
cos 1 log 20
) (
log 20
,
d LO m
RF
mixer v
R V g
V
t IF
A (4.41)

As it can be seen in Equation 4.41, the conversion gain of the mixer A
v,mixer
varies
according to the phase imbalance . As the phase imbalance increases, the gain of the
mixer, A
v,mixer
, deceases. Figure 4.23 shows the variation of A
v,mixer
versus , where the
gain of the mixer A
v,mixer
at =0 is normalized to 0dB.

107
0 10 20 30 40 50 60 70 80 90
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
Phase Imbalance [degree]
G
a
i
n

o
f

M
i
x
e
r

[
d
B
]

Figure 4.23: Conversion gain of mixer (A
v,mixer
) versus phase imbalance ( )


In direct conversion receivers or low-IF receivers, the down conversion mixer plays
an important role in terms of linearity and noise performance as mentioned in the
previous sections. If the gain is very low, the noise degradation, due to the following
stages such as filters and variable gain amplifiers, would be seriously problematic. If the
flicker noise of the mixer is so high, the downconverted desired signal may be corrupted
by the flicker noise. On the other hand, if the linearity is not high enough, the wanted
signal may be saturated when processed through the mixer. Thus, for an adequate gain,

108
low flicker noise, and high linearity, some remedies should be considered into the design
of the typical double-balanced mixer.
For less flicker noise and the low corner frequency of it, p-MOS LO switching
devices and current injection method are us7ed. As mentioned in section 4.5.1, large area
p-MOS devices produce less flicker noise and current injection method, so called current
boosting, guarantees an independent low biasing current for p-MOS LO switching
devices. This current injection method also provides an adequate gain enabling to
increase the load resistance by factor of 4 or 5. In fact, the biasing current of the LO
switching devices is about one fifth of the biasing current of the RF input devices. It is
noteworthy that low biasing current for LO switching devices also helps reduce the noise
figure of the mixer since the on-off switching operation would be much better with a
proper LO signal.
For high linearity, besides the current injection method, the inductive source
degeneration is used. The inductive source degeneration can provide high linearity by
reducing transconductance of the RF input devices. The gain, however, could be kept
unchanged by increasing the load resistance. This is one of the advantages of the current
injection method. Furthermore, the current injection method guarantees sufficiently high
biasing current for high linearity of the mixer as discussed in section 4.5.2.
Note that the optimum biasing currents for the LO switching devices and the RF input
devices are different; A relatively low biasing current is used for the LO switching
devices to reduce the flicker noise whereas large biasing current is used for the RF input
devices to improve the linearity. The proposed direct downconversion mixer is shown in
Figure 4.24 and the simulation results are summarized in Table 4.4.

109
Vdd
RF+ RF-
LO-
LO+
Vout-
Vout+
Rd Rd
Ls
Ib
Is
M1 M2
M3 M4 M5 M6
Ls

Figure 4.24: The proposed direct conversion mixer

Parameters 2.4GHz Mixer 5.2GHz Mixer Requirements
Gain (dB) 5.3 5.6 > 2, >2
NF (dB) 17.7 19.3 < 18, <20
IIP3 (dBm) 10.4 8.9 > 10, >8
IIP2 (dBm) 90.1 88 > 50, >55
Corner Freq. of 1/f Noise 60KHz 75KHz <100KHz

Table 4.4 Simulation results of the proposed mixer

110
4.6 Bondwire and Package Parasitics

Figure 4.25 shows the undesired parasitics from the bondwire and the plastic package.
As can be seen in Figure 4.25, there are several parasitic resistors, capacitors and
inductors. The critical and important elements, which eventually affect the performance
of the RF front-end, are the parasitic bondwire inductance, L
B
, and the parasitic bondpad
capacitance, C
P
. Generally, depending on the package used, the parasitic bondwire
inductance, L
B
can be between 1~4nH, and the parasitic bondpad capacitance, C
P
, can be
between 80~300fF. Based on the datasheet of the package used, the estimated length of
the bondwire, and the relative position of the bondpad, the parasitic bondwire inductance,
L
B
can be set between 1nH and 1.6nH, and the parasitic bondpad capacitance, C
P
, is set to
80fF. It is noteworthy that the input impedance matching and resonant frequency of the
LNA and the phase and gain error of the SDC are significantly influenced by these
parasitic inductance and capacitance.

Figure 4.25: Bondpad and package parasitics

The package used for the proposed RF front-end is QFN 40A, which is non-lead type
and has 40 pins. According to the manufacturers data sheet, Table 4.5 summarizes the
L
L
R
L
L
B
R
B
C
P
C
B
Lead
Bond Pad

111
values for undesired parasitic inductors, capacitors, and resistors. The actual size of the
bondpad is 100 x 100 m
2
.

Parameters Symbols Values Units
Bond Pad Capacitance C
p
75 fF
Bondwire Resistance R
B
1 m
Bondwire Inductance L
B
1.0 ~ 1.6 nH
Bondwire Capacitance C
B
150 fF
Lead Resistance R
L
5 m
Lead Inductance L
L
0.1 nH

Table 4.5 Undesired parasitics from bondwire and package

112
4.7 Simulation Results of RF Front-End

The RF Front-end, which consists of the LNA, the SDC, and the I/Q mixers described
in the previous sections, have been laid out and simulated together with undesired
parasitic model mentioned in section 4.6. Figure 4.26 shows the actual layout. In Figure
4.26, the upper half is 2.4-GHz RF front-end and the lower half is 5.2-GHz RF front-end,
respectively.

Figure 4.26: The layout of the proposed dual-band RF front-end

113

Figure 4.27: Gain response of 2.4GHz RF front-end

Figure 4.28: Noise figure (SSB) of 2.4GHz RF front-end

114

Figure 4.29: Linearity of 2.4GHz RF front-end in low-gain mode

Figure 4.30: Gain response of 5.2GHz RF front-end

115

Figure 4.31: Noise figure (DSB) of 5.2GHz RF front-end

Figure 4.32: Linearity of 5.2GHz RF front-end in low-gain mode

116
Figure 4.27 to 4.29 show the gain response, the noise figure, and the linearity of the
proposed 2.4GHz RF front-end. And Figure 4.30 to 4.32 show the gain response, the
noise figure, and the linearity of the proposed 5.2GHz RF front-end.
Table 4.6 lists the post-layout simulation results. It is noteworthy that the propose RF
front-ends present sufficient gain and low noise figure. It also provides very low corner
frequencies of the flicker noise; 45-KHz for 2.4-GHz RF front-end and 55-KHz for
5.2GHz RF front-end, respectively.

2.4-GHz RF Front-end 5.2-GHz RF Front-end

High Gain Low-Gain High Gain Low-Gain
Gain (dB) 25.1 15.3 25.4 15.5
NF (DSB, dB) 4.1 10.1 4.9 10.8
IIP3 (dBm) -11.6 -3.5 -14 -3.2
IIP2 (dBm) 43.2 55.2 34.6 45.4
1/f noise corner (KHz) 22 46 34 60
LO-RF Isolation (dB) > 97.9 > 103.7 > 78.4 > 83.5
S11 (dB) < -24.5 < -19
Power Dissipation (mW) 22.7 22.8
Supply Voltage (V) 1.8 1.8

Table 4.6 Summary of the post-layout simulation results of the RF front-ends

117
CHAPTER 5

EXPERIMENTAL RESULTS OF THE RF FRONT-END

5.1 Introduction

Figure 5.1 shows the test board on which the proposed RF front-end chip is soldered.
The proposed RF front-end chip has been fabricated by TSMC RF CMOS 0.18m
process and packaged by QFN 40 pins. The upper half of the test board is for 2.4GHz RF
front-end and the lower half is for 5.2GHz RF front-end, respectively, Table 5.1
summarizes the pin description of the test board.

Pin No. Description Pin No. Description
1 2G I-Mixer Positive Diff. Output 8 5G Q-Mixer Negative Diff. Output
2 2G LNA Input 9 5G LNA Input
3 2G Q-Mixer Positive Diff. Output 10 5G I-Mixer Negative Diff. Output
4 2G Q-Mixer Negative Diff. Output 11 5G I-Mixer LO Input
5 2G Q-Mixer LO input 12 5G I-Mixer Positive Diff. Output
6 5G Q-Mixer LO input 13 2G I-Mixer LO Input
7 5G Q-Mixer Positive Diff. Output 14 2G I-Mixer negative Input

Table 5.1 Pin description of the test board

118

Figure 5.1: Test board of the proposed RF front-end chip

Figure 5.2 shows the magnified photographs of the RF front-end chip on the test
board. For the test purpose, the differential LO inputs of the 2.4GHz and 5.2GHz I/Q
mixers are 50 impedance matched by using off-chip inductors and capacitors. The LO
signal from the signal generator is single-ended whereas the mixers require the
differential inputs. Thus, the off-chip balun has been placed between the corresponding
SMA RF connector and the input matching network. As can be seen in the figure 5.2, the
white-colored components are the baluns and the silver-colored components are the input
matching networks composed of inductors and capacitors.
#1 #2 #3
#4
#5
#6
#7
#8 #9 #10
#11
#12
#13
#14

119

Figure 5.2: Magnified photograph of the RF front-end chip on the test board

Figure 5.3: Die photograph of the RF front-end chip
2.4GHz LNA
2.4GHz
I- Mixer
2.4GHz
Q- Mixer
2.4GHz
SDC
5.2GHz LNA
5.2GHz
I- Mixer
5.2GHz
Q- Mixer
5.2GHz
SDC

120
5.2 Experimental Results of 2.4GHz RF Front-end

Figure 5.4 is the experimental result of S11 of the 2.4GHz LNA. As can be seen, it
shows the very good input impedance matching and S11 is less than -15dB around at
2.4GHz frequency band.

Figure 5.4: Measured input reflection coefficient S11 of the 2.4-GHz RF front-end

Figure 5.5 is the measured flicker noise at the output of the direct downconversion
mixer. The corner frequency of the flicker noise is less than 10-KHz in Figure 5.5. This

121
flicker noise with low corner frequency can be easily removed by using the high-pass
filter with the cutoff frequency of 10-KHz with negligible degradation of the desired
signal.

Figure 5.5: Measure flicker noise of the 2.4-GHz RF front-end
Figure 5.6, 5.7, and 5.8 show the measured down converted signals. In Figure 5.6, the
RF signal at 2.44-GHz is down converted to 5-MHz IF frequency. And the RF signal is
down converted to 1-MHz in Figure 5.7 and 0.2MHz in Figure 5.8, respectively.
R e f

L v l
- 1 0

d B m
R e f

L v l
- 1 0

d B m
R F

A t t

20

dB

A

U n i t dBm
PRN
S t a r t 0

H z S t o p 1 0 0

kHz 10

kHz/
RBW

1

kHz
VBW

1

kHz
SWT

250

ms
1 V I E W 1MI

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 1 0

- 1 0
1
M a r k e r

1

[T1]

-95.24

dBm

1 0 0.00000000

kHz
1

[T1]

- 9 5 . 2 4

dBm

1 0 0 . 0 0 0 0 0 0 0 0

kHz
D a t e :

2 9 . S E P . 2 0 0 4

2 2:37:36

122

Figure 5.6: Measured down converted signal at 5-MHz IF frequency, RF at 2.44-GHz and
LO at 2.445-GHz

1 A V G
R e f

L v l
- 2 0

d B m
R e f

L v l
- 2 0

d B m
R F

A t t

0

dB

A

1SA
U n i t dBm SWT

25

ms
S t a r t 0

H z S t o p 1 0

MHz 1

MHz/
RBW

50

kHz
VBW

50

kHz
PRN

- 1 1 0

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 1 2 0

- 2 0
1
2
1
M a r k e r

1

[T1]

-40.28

dBm

4.98997996

MHz
1

[T1]

- 4 0 . 2 8

dBm

4 . 9 8 9 9 7 9 9 6

MHz
2

[T1]

- 8 2 . 4 2

dBm

2 . 0 0 0 0 0 0 0 0

MHz
1

[T1]

1 3 . 6 8

dB

- 4 . 9 8 9 9 7 9 9 4

MHz
D a t e :

1 2 . A U G . 2 0 0 4

1 8:05:43

123

Figure 5.7: Measured down converted signal at 1-MHz IF frequency, RF at 2.44-GHz and
LO at 2.441-GHz

1 A V G
R e f

L v l
- 2 0

d B m
R e f

L v l
- 2 0

d B m
R F

A t t

0

dB

A

1SA
U n i t dBm SWT

25

ms
PRN
S t a r t 0

H z S t o p 2

MHz 200

kHz/
RBW

50

kHz
VBW

50

kHz

- 1 1 0

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 1 2 0

- 2 0
1
2
1
M a r k e r

1

[T1]

-37.09

dBm

9 9 7.99599198

kHz
1

[T1]

- 3 7 . 0 9

dBm

9 9 7 . 9 9 5 9 9 1 9 8

kHz
2

[T1]

- 8 0 . 9 1

dBm

2 . 0 0 0 0 0 0 0 0

MHz
1

[T1]

1 1 . 7 1

dB

- 9 9 7 . 9 9 5 9 7 6 9 8

kHz
D a t e :

1 2 . A U G . 2 0 0 4

1 7:40:28

124

Figure 5.8: Measured down converted signal at 200-KHz IF frequency, RF at 2.440-GHz
and LO at 2.4402-GHz

1 A V G
R e f

L v l
- 2 0

d B m
R e f

L v l
- 2 0

d B m
R F

A t t

0

dB

A

1SA
U n i t dBm SWT

25

ms
S t a r t 0

H z S t o p 2

MHz 200

kHz/
RBW

50

kHz
VBW

50

kHz
PRN

- 1 1 0

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 1 2 0

- 2 0
1
2
1
M a r k e r

1

[T1]

-37.27

dBm

2 0 0.40080160

kHz
1

[T1]

- 3 7 . 2 7

dBm

2 0 0 . 4 0 0 8 0 1 6 0

kHz
2

[T1]

- 8 1 . 3 0

dBm

2 . 0 0 0 0 0 0 0 0

MHz
1

[T1]

1 1 . 8 9

dB

- 2 0 0 . 4 0 0 7 8 6 6 0

kHz
D a t e :

1 2 . A U G . 2 0 0 4

1 7:44:09

125
Figure 5.9 shows the measured gain response in low gain mode. The peak frequency
of the gain is shifted 250-MHz from the point where it has been found in the post-layout
simulation. This is probably due to the unwanted effect of the bondwire and package
parasitics mentioned in section 4.6. Even though the undesired bondwire and package
models have been considered in the post-layout simulation, the shift of the peak
frequency occurred as shown in Figure 5.9.

Figure 5.9: Measured gain response of the 2.4-GHz RF front-end

Figure 5.10 shows the measure 1-dB compression point of the 2.4-GHz RF front-end
in high gain mode. The P
-1
dB is about -15dBm as shown in Figure 5.10.
0.5 1 1.5 2 2.5 3 3.5
-5
0
5
10
15
20
Low Gain Mode
Frequency (GHz)
Gain (dB)

126

Figure 5.10: Measured 1-dB compression point of the 2.4-GHz RF front-end

Figure 5.11 is the measured two-tone test, in which the two-tones are at 2.240-GHz
and 2.245-GHz, and the LO signal is at 2.260-GHz. This figure shows the down-
converted fundamantal signals and the third-order intermodulation products (IM3) at the
output of the mixer. Based on the measured data, the IIP3 in high gain mode is -7.6dBm.
Table 5.2 summarizes the measured performance of the proposed 2.4-GHz RF front-end.
It is noteworthy that the 2.4GHz RF front-end presents very low corner frequency of the
flicker noise and high linearity. And it has very small gain mismatch in I/Q mixers and
differential outputs. It consumes only 12.1-mA including biasing currents.
-60 -50 -40 -30 -20 -10 0
-50
-40
-30
-20
-10
0
10
P1dB
Input Power (dBm)
Output
Power
(dBm)

127

Figure 5.11: Measured two-tone test of the 2.4-GHz RF front-end

R e f

L v l
- 1 0

d B m
R e f

L v l
- 1 0

d B m
R F

A t t

20

dB

A

U n i t dBm
1.6

MHz/ C e n t e r 1 8

M H z S p a n 1 6

MHz
RBW

50

kHz
VBW

50

kHz
SWT

16

ms
1 V I E W 1MI
PRN

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 1 0

- 1 0
1
2
3
4
M a r k e r

1

[T1]

-35.24

dBm

1 5.99599198

MHz
1

[T1]

- 3 5 . 2 4

dBm

1 5 . 9 9 5 9 9 1 9 8

MHz
2

[T1]

- 3 3 . 9 1

dBm

2 0 . 0 0 4 0 0 8 0 2

MHz
3

[T1]

- 8 3 . 4 6

dBm

1 2 . 0 2 0 0 4 0 0 8

MHz
4

[T1]

- 9 3 . 6 0

dBm

2 4 . 0 1 2 0 2 4 0 5

MHz
D a t e :

2 9 . S E P . 2 0 0 4

2 2:12:56

128

2.4-GHz RF Front-end
High Gain Low-Gain
Gain (dB) 16.4 10.9
IIP3 (dBm) -7.6 -1.5
P1dB (dBm) -15.1 -10.8
1/f noise corner (KHz) < 10 < 10
Gain Mismatch in I/Q Mixers (dB) 0.7
Gain Mismatch in Differential Output 0.3
S11 (dB) < -15
Power Dissipation (mW) 21.9
Supply Voltage (V) 1.8

Table 5.2 Summary of the measured performance of the proposed 2.4GHz RF front-end

5.3 Experimental Results of 5.2GHz RF Front-end

Figure 5.12 is the experimental result of S11 of the 5.2GHz LNA. As can be seen, it
shows good input impedance matching and S11 is less than -7.5dB around at 5.2GHz
frequency band.
Figure 5.13 is the measured flicker noise at the output of the direct downconversion
mixer. The corner frequency of the flicker noise is less than 10-KHz as shown in Figure
5.13. This flicker noise with low corner frequency can be easily removed by using the
high-pass filter with the cutoff frequency of 10-KHz without any degradation of the
desired signal since the center sub-channel of 156.25KHz is empty.

129

Figure 5.12: Measured input reflection coefficient S11 of the 5.2-GHz RF front-end

130

Figure 5.13: Measure flicker noise of the 5.2-GHz RF front-end

A

U n i t dBm
R e f

L v l

0

d B m
R e f

L v l

0

d B m
R F

A t t

30

dB
PRN
S t a r t 0

H z S t o p 1 0 0

kHz 10

kHz/
RBW

1

kHz
VBW

1

kHz
SWT

250

ms
1 V I E W 1SA

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 0

- 1 0 0

0
1
M a r k e r

1

[T1]

-82.51

dBm

1 0 0.00000000

kHz
1

[T1]

- 8 2 . 5 1

dBm

1 0 0 . 0 0 0 0 0 0 0 0

kHz
D a t e :

2 9 . S E P . 2 0 0 4

2 3:30:20

131
Figure 5.14, 5.15, and 5.16 show the measured down converted signals. In Figure
5.14, the RF signal at 5.2-GHz is down converted to 1-MHz IF frequency. And the RF
signal is down converted to 0.5-MHz in Figure 5.15 and 0.2MHz in Figure 5.16,
respectively.

Figure 5.14: Measured down converted signal at 1-MHz IF frequency, RF at 5.15-GHz
and LO at 5.151-GHz

A

U n i t dBm
1 A V G 1SA
R e f

L v l

0

d B m
R e f

L v l

0

d B m
R F

A t t

30

dB
PRN
S t a r t 0

H z S t o p 2

MHz 200

kHz/
RBW

30

kHz
VBW

30

kHz
SWT

6

ms

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 0

- 1 0 0

0
1
M a r k e r

1

[T1]

-26.70

dBm

1.00000000

MHz
1

[T1]

- 2 6 . 7 0

dBm

1 . 0 0 0 0 0 0 0 0

MHz
D a t e :

2 9 . S E P . 2 0 0 4

2 3:07:13

132

Figure 5.15: Measured down converted signal at 0.5-MHz IF frequency, RF at 5.15-GHz

A

U n i t dBm
1 A V G 1SA
R e f

L v l

0

d B m
R e f

L v l

0

d B m
R F

A t t

30

dB
PRN
S t a r t 0

H z S t o p 1

MHz 100

kHz/
RBW

10

kHz
VBW

10

kHz
SWT

25

ms

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 0

- 1 0 0

0
1
M a r k e r

1

[T1]

-26.05

dBm

5 0 0.00000000

kHz
1

[T1]

- 2 6 . 0 5

dBm

5 0 0 . 0 0 0 0 0 0 0 0

kHz
D a t e :

2 9 . S E P . 2 0 0 4

2 3:05:50

133

Figure 5.16: Measured down converted signal at 200-KHz IF frequency, RF at 5.15-GHz

Figure 5.17 shows the measured gain response in low gain mode. The peak frequency
of the gain is shifted 800-MHz from the point where it has been found in the post-layout
simulation. This is probably due to the unwanted effect of the bondwire and package
parasitics mentioned in section 4.6. Even though the undesired bondwire and package
models have been considered in the post-layout simulation, the shift of the peak
frequency occurred as shown in Figure 5.17.

A

U n i t dBm
1 A V G 1SA
R e f

L v l

0

d B m
R e f

L v l

0

d B m
R F

A t t

30

dB
PRN
S t a r t 0

H z S t o p 5 0 0

kHz 50

kHz/
RBW

10

kHz
VBW

10

kHz
SWT

15

ms

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 0

- 1 0 0

0
1
M a r k e r

1

[T1]

-26.09

dBm

2 0 0.00000000

kHz
1

[T1]

- 2 6 . 0 9

dBm

2 0 0 . 0 0 0 0 0 0 0 0

kHz
D a t e :

2 9 . S E P . 2 0 0 4

2 3:08:14

134

Figure 5.17: Measured gain response of the 5.2-GHz RF front-end

Figure 5.18 shows the measured 1-dB compression point of the 5.2-GHz RF front-end
in low gain mode. The P
-1
dB is about -8dBm as shown in Figure 5.18. Figure 5.19 is the
measured two-tone test, in which the two-tone are at 5.150-GHz and 5.155-GHz, and the
LO signal is at 5.170-GHz. This figure shows down-converted IF signal at the output of
the mixer. Based on the measured data, the IIP3 in high gain mode is -10.9dBm.
Table 5.3 summarizes the measured performance of the proposed 5.2-GHz RF front-
end. Note that the 5.2-GHz RF front-end presents very low corner frequency of the
2.5 3 3.5 4 4.5 5 5.5 6
-5
0
5
10
15
Low Gain Mode
Frequency (GHz)
Gain (dB)

135
flicker noise and high linearity. And it has very small gain mismatch in I/Q mixers and
differential outputs. It consumes only 12-mA including biasing currents.

Figure 5.18: Measured 1-dB compression point of the 5.2-GHz RF front-end

-60 -50 -40 -30 -20 -10 0
-50
-40
-30
-20
-10
0
10
P1dB
Input Power (dBm)
Output Power

136

Figure 5.19: Measured two-tone test of the 5.2-GHz RF front-end

R e f

L v l
- 1 0

d B m
R e f

L v l
- 1 0

d B m
R F

A t t

20

dB

A

U n i t dBm
1.6

MHz/ C e n t e r 1 8

M H z S p a n 1 6

MHz
RBW

50

kHz
VBW

50

kHz
SWT

16

ms
PRN
1 V I E W 1MI

- 1 0 0

- 9 0

- 8 0

- 7 0

- 6 0

- 5 0

- 4 0

- 3 0

- 2 0

- 1 1 0

- 1 0
1 2
3
4
M a r k e r

1

[T1]

-34.27

dBm

1 5.99599198

MHz
1

[T1]

- 3 4 . 2 7

dBm

1 5 . 9 9 5 9 9 1 9 8

MHz
2

[T1]

- 3 4 . 1 4

dBm

2 0 . 0 0 4 0 0 8 0 2

MHz
3

[T1]

- 8 0 . 1 8

dBm

1 2 . 0 2 0 0 4 0 0 8

MHz
4

[T1]

- 8 1 . 4 2

dBm

2 4 . 0 1 2 0 2 4 0 5

MHz
D a t e :

2 9 . S E P . 2 0 0 4

2 2:25:32

137

5.2-GHz RF Front-end
High Gain Low-Gain
Gain (dB) 15.5 10.3
IIP3 (dBm) -10.9 -0.2
P1dB (dBm) -19.8 -8
1/f noise corner (KHz) < 10 < 10
Gain Mismatch in I/Q Mixers (dB) 0.8
Gain Mismatch in Differential Output 0.4
S11 (dB) < -7.5
Power Dissipation (mW) 21.7
Supply Voltage (V) 1.8

Table 5.3 Summary of the measured performance of the proposed 5.2-GHz RF front-end

138
CHAPTER 6

CONCLUSION

In this dissertation, various receiver architectures have been examined and analyzed
for the multi-standard receiver supporting Bluetooth and IEEE 802.11a/b WLAN
applications. Zero-IF architecture has been chosen for IEEE 802.11a/b/g WLANs, and
low-IF architecture for Bluetooth, respectively. To maximize the level of component
share in the proposed multi-standard receiver, the corresponding standards have been
analyzed and applied to the proposed multi-standard receiver architecture. The analysis
suggests the maximum share of the analog baseband blocks in the receiver chain for both
Bluetooth and WLANs, and, in turn, results in the programmability to be implemented in
some building blocks such as filter and ADC. The system specifications and the building
block specifications have been derived from the corresponding standards and verified by
using spreadsheet models taking into account of major design issues such as dc offset,
flicker noise and image-rejection, which are the main design issues in zero-IF or low-IF
architecture. The spreadsheet simulation results proved the validity of the system analysis
and the proposed multi-standard receiver architecture.
This dissertation also presented the design of the RF front-ends consisting of LNAs,
SDCs (Single-ended to Differential Converter), and downconversion I/Q mixers. The

139
design specifications of the RF front-ends have been derived during the procedure of
system analysis of the proposed multi-standard receiver architecture. In order to reduce
the current consumption and the size of the LNAs, a single-ended LNA with dual gain
has been proposed. For better even order linearity of the RF front-end, the double-
balanced mixer has been chosen for the downconversion mixer. In order to make these
single-ended LNAs operating along with the double-balanced mixer, the on-chip balun,
which is called SDC in this dissertation, is placed between the LNA and the I/Q mixers.
Additionally, by placing the SDC between them, LO-RF isolation would be much
improved.
The single-ended LNAs with dual gain for 2.4GHz and 5.2GHz frequency bands have
been designed by using TSMC RF CMOS 0.18m process. The common source with
cascode transistor is much preferable for better isolation, adequate gain, and input
impedance matching. The proposed LNAs can provide high gain and low gain by
adjusting the load impedance with help of MOS switch, and the low gain is required to
alleviate the linearity requirement of the following stages in the presence of the strong
signals. To reduce the size of the LNAs further, the bondwire parasitic inductors have
been used as parts of the gate inductor and the load inductor. It could save about 20% of
the overall size of each LNA. Although the multi-band concurrent LNAs have been
reported in recent publications, it seems that the gain of the concurrent LNAs would not
be easy to control since the multiple frequencies of interest are realized together by using
a single LC resonator only.
The single-ended to differential converters for 2.4GHz and 5.2GHz frequency bands
have been designed and placed between the LNAs and the downconversion I/Q mixers.

140
This makes it possible to use the double-balanced mixer for less even order distortion,
especially for less second order distortion, which could be critical in zero-IF and low-IF
receiver architectures. The gain and phase mismatches between the differential outputs of
the SDC should be cared carefully because these mismatches could make the potential
problems such dc-offset and the gain degradation in the downconversion I/Q mixers.
Ideally, since the loads of the SDC have been implemented by resistors instead of
inductors, the SDC would be able to provide constant gain response from 2G to 6GHz.
However, as the operating frequency goes up to 6GHz, the phase imbalance between the
differential outputs of the SDC has been found to increase. This could be due to the
unequal size of the parasitic gate and drain capacitors. It actually led to design two
separate SDCs for each frequency band, 2.4GHz or 5.2GHz.
The I/Q mixers are able to downconvert the RF signal to zero-IF or low-IF depending
on the LO frequency. The LO frequency is assume to be the same as the RF frequency in
case of WLAN mode, and 1-MHz higher or lower than the RF frequency in case of
Bluetooth mode. Inherently, CMOS devices suffer from the flicker noise whereas bipolar
devices does not. This flicker noise presented at the output of the mixers would distort the
desired downconverted signal. Thus, the lower corner frequency of the flicker noise is,
the less distortion generated. For less flicker noise of the mixers, PMOS devices and less
biasing current have been used for LO switching devices. However, for better linearity,
an adequate amount of biasing current should be provided for RF input devices. In I/Q
mixer design, two independent current sources have been used for the LO switching
devices and the RF input devices for these goals. The biasing current of the LO
switching devices is about 20% of that of the RF input devices. As can be seen in the

141
experimental results of the mixers, the corner frequencies of the flicker noise of 2.4-GHz
and 5.2-GHz downconversion mixers are less than 10-KHz, which is even much less than
the schematic results of the mixers.
The undesired bondwire and package parasitics have been taken into account during
the schematic design and the layout. These undesired parasitic capacitors, inductors, and
resistors could affect the gain response and the input impedance matching of the LNAs,
and the gain and phase mismatch of the SDCs. Using these bondwire inductance as parts
of the load and the input matching network of the LNA, the gate inductor and the load
inductor of the LNAs have been reduced and results in smaller size of the LNA layout.
The proposed RF front-ends for 2.4-GHz and 5.2-GHz frequency bands have been
fabricated with TSMC RF CMOS 0.18m process and measurement data is presented.
The proposed RF front-ends show high linearity, very low corner frequency of the flicker
noise, negligible gain and phase mismatch, and low power dissipation for both frequency
bands of interest, 2.4-GHz and 5.2-GHz frequency bands. While all the efforts have been
taken for the accurate estimation of the undesired parasitics of the bondwire and the
package models, the measurement data show that the peak of the gain response and the
input matching of the LNAs have been shifted toward lower frequency bands than the
frequency bands they should be in. Thus, more accurate bondwire and package models
should be considered in the schematic design and the post layout simulation to minimize
the negative effects mentioned above.
Recently, most RF/analog designers have been looking for low cost transceiver
design with high integration level, and zero-IF (direct conversion) or low-IF architecture
has been thought as a competitive solution especially for multi-standard wireless

142
applications. Since it describes the detailed procedures to extract receiver system
specifications from wireless standards considering zero-IF/low-IF architectures and
define the building block specifications satisfying the receiver system specifications, this
dissertation could be a valuable guide or reference for the zero-IF/low-IF multi-standard
receiver design for other wireless standards.

143
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